xref: /linux/drivers/crypto/intel/qat/qat_common/adf_pfvf_utils.c (revision c532de5a67a70f8533d495f8f2aaa9a0491c3ad0)
1 // SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only)
2 /* Copyright(c) 2021 Intel Corporation */
3 #include <linux/crc8.h>
4 #include <linux/pci.h>
5 #include <linux/types.h>
6 #include "adf_accel_devices.h"
7 #include "adf_pfvf_msg.h"
8 #include "adf_pfvf_utils.h"
9 
10 /* CRC Calculation */
11 DECLARE_CRC8_TABLE(pfvf_crc8_table);
12 #define ADF_PFVF_CRC8_POLYNOMIAL 0x97
13 
14 void adf_pfvf_crc_init(void)
15 {
16 	crc8_populate_msb(pfvf_crc8_table, ADF_PFVF_CRC8_POLYNOMIAL);
17 }
18 
19 u8 adf_pfvf_calc_blkmsg_crc(u8 const *buf, u8 buf_len)
20 {
21 	return crc8(pfvf_crc8_table, buf, buf_len, CRC8_INIT_VALUE);
22 }
23 
24 static bool set_value_on_csr_msg(struct adf_accel_dev *accel_dev, u32 *csr_msg,
25 				 u32 value, const struct pfvf_field_format *fmt)
26 {
27 	if (unlikely((value & fmt->mask) != value)) {
28 		dev_err(&GET_DEV(accel_dev),
29 			"PFVF message value 0x%X out of range, %u max allowed\n",
30 			value, fmt->mask);
31 		return false;
32 	}
33 
34 	*csr_msg |= value << fmt->offset;
35 
36 	return true;
37 }
38 
39 u32 adf_pfvf_csr_msg_of(struct adf_accel_dev *accel_dev,
40 			struct pfvf_message msg,
41 			const struct pfvf_csr_format *fmt)
42 {
43 	u32 csr_msg = 0;
44 
45 	if (!set_value_on_csr_msg(accel_dev, &csr_msg, msg.type, &fmt->type) ||
46 	    !set_value_on_csr_msg(accel_dev, &csr_msg, msg.data, &fmt->data))
47 		return 0;
48 
49 	return csr_msg | ADF_PFVF_MSGORIGIN_SYSTEM;
50 }
51 
52 struct pfvf_message adf_pfvf_message_of(struct adf_accel_dev *accel_dev, u32 csr_msg,
53 					const struct pfvf_csr_format *fmt)
54 {
55 	struct pfvf_message msg = { 0 };
56 
57 	msg.type = (csr_msg >> fmt->type.offset) & fmt->type.mask;
58 	msg.data = (csr_msg >> fmt->data.offset) & fmt->data.mask;
59 
60 	if (unlikely(!msg.type))
61 		dev_err(&GET_DEV(accel_dev),
62 			"Invalid PFVF msg with no type received\n");
63 
64 	return msg;
65 }
66