1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (c) 2025 Intel Corporation. */ 3 #include <linux/export.h> 4 5 #include "adf_gen6_tl.h" 6 #include "adf_telemetry.h" 7 #include "adf_tl_debugfs.h" 8 #include "icp_qat_fw_init_admin.h" 9 10 #define ADF_GEN6_TL_DEV_REG_OFF(reg) ADF_TL_DEV_REG_OFF(reg, gen6) 11 12 #define ADF_GEN6_TL_RP_REG_OFF(reg) ADF_TL_RP_REG_OFF(reg, gen6) 13 14 #define ADF_GEN6_TL_SL_UTIL_COUNTER(_name) \ 15 ADF_TL_COUNTER("util_" #_name, ADF_TL_SIMPLE_COUNT, \ 16 ADF_TL_SLICE_REG_OFF(_name, reg_tm_slice_util, gen6)) 17 18 #define ADF_GEN6_TL_SL_EXEC_COUNTER(_name) \ 19 ADF_TL_COUNTER("exec_" #_name, ADF_TL_SIMPLE_COUNT, \ 20 ADF_TL_SLICE_REG_OFF(_name, reg_tm_slice_exec_cnt, gen6)) 21 22 #define SLICE_IDX(sl) offsetof(struct icp_qat_fw_init_admin_slice_cnt, sl##_cnt) 23 24 #define ADF_GEN6_TL_CMDQ_WAIT_COUNTER(_name) \ 25 ADF_TL_COUNTER("cmdq_wait_" #_name, ADF_TL_SIMPLE_COUNT, \ 26 ADF_TL_CMDQ_REG_OFF(_name, reg_tm_cmdq_wait_cnt, gen6)) 27 #define ADF_GEN6_TL_CMDQ_EXEC_COUNTER(_name) \ 28 ADF_TL_COUNTER("cmdq_exec_" #_name, ADF_TL_SIMPLE_COUNT, \ 29 ADF_TL_CMDQ_REG_OFF(_name, reg_tm_cmdq_exec_cnt, gen6)) 30 #define ADF_GEN6_TL_CMDQ_DRAIN_COUNTER(_name) \ 31 ADF_TL_COUNTER("cmdq_drain_" #_name, ADF_TL_SIMPLE_COUNT, \ 32 ADF_TL_CMDQ_REG_OFF(_name, reg_tm_cmdq_drain_cnt, \ 33 gen6)) 34 35 #define CPR_QUEUE_COUNT 5 36 #define DCPR_QUEUE_COUNT 3 37 #define PKE_QUEUE_COUNT 1 38 #define WAT_QUEUE_COUNT 7 39 #define WCP_QUEUE_COUNT 7 40 #define USC_QUEUE_COUNT 3 41 #define ATH_QUEUE_COUNT 2 42 43 /* Device level counters. */ 44 static const struct adf_tl_dbg_counter dev_counters[] = { 45 /* PCIe partial transactions. */ 46 ADF_TL_COUNTER(PCI_TRANS_CNT_NAME, ADF_TL_SIMPLE_COUNT, 47 ADF_GEN6_TL_DEV_REG_OFF(reg_tl_prt_trans_cnt)), 48 /* Max read latency[ns]. */ 49 ADF_TL_COUNTER(MAX_RD_LAT_NAME, ADF_TL_COUNTER_NS, 50 ADF_GEN6_TL_DEV_REG_OFF(reg_tl_rd_lat_max)), 51 /* Read latency average[ns]. */ 52 ADF_TL_COUNTER_LATENCY(RD_LAT_ACC_NAME, ADF_TL_COUNTER_NS_AVG, 53 ADF_GEN6_TL_DEV_REG_OFF(reg_tl_rd_lat_acc), 54 ADF_GEN6_TL_DEV_REG_OFF(reg_tl_rd_cmpl_cnt)), 55 /* Max "get to put" latency[ns]. */ 56 ADF_TL_COUNTER(MAX_LAT_NAME, ADF_TL_COUNTER_NS, 57 ADF_GEN6_TL_DEV_REG_OFF(reg_tl_gp_lat_max)), 58 /* "Get to put" latency average[ns]. */ 59 ADF_TL_COUNTER_LATENCY(LAT_ACC_NAME, ADF_TL_COUNTER_NS_AVG, 60 ADF_GEN6_TL_DEV_REG_OFF(reg_tl_gp_lat_acc), 61 ADF_GEN6_TL_DEV_REG_OFF(reg_tl_ae_put_cnt)), 62 /* PCIe write bandwidth[Mbps]. */ 63 ADF_TL_COUNTER(BW_IN_NAME, ADF_TL_COUNTER_MBPS, 64 ADF_GEN6_TL_DEV_REG_OFF(reg_tl_bw_in)), 65 /* PCIe read bandwidth[Mbps]. */ 66 ADF_TL_COUNTER(BW_OUT_NAME, ADF_TL_COUNTER_MBPS, 67 ADF_GEN6_TL_DEV_REG_OFF(reg_tl_bw_out)), 68 /* Page request latency average[ns]. */ 69 ADF_TL_COUNTER_LATENCY(PAGE_REQ_LAT_NAME, ADF_TL_COUNTER_NS_AVG, 70 ADF_GEN6_TL_DEV_REG_OFF(reg_tl_at_page_req_lat_acc), 71 ADF_GEN6_TL_DEV_REG_OFF(reg_tl_at_page_req_cnt)), 72 /* Page translation latency average[ns]. */ 73 ADF_TL_COUNTER_LATENCY(AT_TRANS_LAT_NAME, ADF_TL_COUNTER_NS_AVG, 74 ADF_GEN6_TL_DEV_REG_OFF(reg_tl_at_trans_lat_acc), 75 ADF_GEN6_TL_DEV_REG_OFF(reg_tl_at_trans_lat_cnt)), 76 /* Maximum uTLB used. */ 77 ADF_TL_COUNTER(AT_MAX_UTLB_USED_NAME, ADF_TL_SIMPLE_COUNT, 78 ADF_GEN6_TL_DEV_REG_OFF(reg_tl_at_max_utlb_used)), 79 /* Ring Empty average[ns] across all rings */ 80 ADF_TL_COUNTER_LATENCY(RE_ACC_NAME, ADF_TL_COUNTER_NS_AVG, 81 ADF_GEN6_TL_DEV_REG_OFF(reg_tl_re_acc), 82 ADF_GEN6_TL_DEV_REG_OFF(reg_tl_re_cnt)), 83 }; 84 85 /* Accelerator utilization counters */ 86 static const struct adf_tl_dbg_counter sl_util_counters[ADF_TL_SL_CNT_COUNT] = { 87 /* Compression accelerator utilization. */ 88 [SLICE_IDX(cpr)] = ADF_GEN6_TL_SL_UTIL_COUNTER(cnv), 89 /* Decompression accelerator utilization. */ 90 [SLICE_IDX(dcpr)] = ADF_GEN6_TL_SL_UTIL_COUNTER(dcprz), 91 /* PKE accelerator utilization. */ 92 [SLICE_IDX(pke)] = ADF_GEN6_TL_SL_UTIL_COUNTER(pke), 93 /* Wireless Authentication accelerator utilization. */ 94 [SLICE_IDX(wat)] = ADF_GEN6_TL_SL_UTIL_COUNTER(wat), 95 /* Wireless Cipher accelerator utilization. */ 96 [SLICE_IDX(wcp)] = ADF_GEN6_TL_SL_UTIL_COUNTER(wcp), 97 /* UCS accelerator utilization. */ 98 [SLICE_IDX(ucs)] = ADF_GEN6_TL_SL_UTIL_COUNTER(ucs), 99 /* Authentication accelerator utilization. */ 100 [SLICE_IDX(ath)] = ADF_GEN6_TL_SL_UTIL_COUNTER(ath), 101 }; 102 103 /* Accelerator execution counters */ 104 static const struct adf_tl_dbg_counter sl_exec_counters[ADF_TL_SL_CNT_COUNT] = { 105 /* Compression accelerator execution count. */ 106 [SLICE_IDX(cpr)] = ADF_GEN6_TL_SL_EXEC_COUNTER(cnv), 107 /* Decompression accelerator execution count. */ 108 [SLICE_IDX(dcpr)] = ADF_GEN6_TL_SL_EXEC_COUNTER(dcprz), 109 /* PKE execution count. */ 110 [SLICE_IDX(pke)] = ADF_GEN6_TL_SL_EXEC_COUNTER(pke), 111 /* Wireless Authentication accelerator execution count. */ 112 [SLICE_IDX(wat)] = ADF_GEN6_TL_SL_EXEC_COUNTER(wat), 113 /* Wireless Cipher accelerator execution count. */ 114 [SLICE_IDX(wcp)] = ADF_GEN6_TL_SL_EXEC_COUNTER(wcp), 115 /* UCS accelerator execution count. */ 116 [SLICE_IDX(ucs)] = ADF_GEN6_TL_SL_EXEC_COUNTER(ucs), 117 /* Authentication accelerator execution count. */ 118 [SLICE_IDX(ath)] = ADF_GEN6_TL_SL_EXEC_COUNTER(ath), 119 }; 120 121 static const struct adf_tl_dbg_counter cnv_cmdq_counters[] = { 122 ADF_GEN6_TL_CMDQ_WAIT_COUNTER(cnv), 123 ADF_GEN6_TL_CMDQ_EXEC_COUNTER(cnv), 124 ADF_GEN6_TL_CMDQ_DRAIN_COUNTER(cnv) 125 }; 126 127 #define NUM_CMDQ_COUNTERS ARRAY_SIZE(cnv_cmdq_counters) 128 129 static const struct adf_tl_dbg_counter dcprz_cmdq_counters[] = { 130 ADF_GEN6_TL_CMDQ_WAIT_COUNTER(dcprz), 131 ADF_GEN6_TL_CMDQ_EXEC_COUNTER(dcprz), 132 ADF_GEN6_TL_CMDQ_DRAIN_COUNTER(dcprz) 133 }; 134 135 static_assert(ARRAY_SIZE(dcprz_cmdq_counters) == NUM_CMDQ_COUNTERS); 136 137 static const struct adf_tl_dbg_counter pke_cmdq_counters[] = { 138 ADF_GEN6_TL_CMDQ_WAIT_COUNTER(pke), 139 ADF_GEN6_TL_CMDQ_EXEC_COUNTER(pke), 140 ADF_GEN6_TL_CMDQ_DRAIN_COUNTER(pke) 141 }; 142 143 static_assert(ARRAY_SIZE(pke_cmdq_counters) == NUM_CMDQ_COUNTERS); 144 145 static const struct adf_tl_dbg_counter wat_cmdq_counters[] = { 146 ADF_GEN6_TL_CMDQ_WAIT_COUNTER(wat), 147 ADF_GEN6_TL_CMDQ_EXEC_COUNTER(wat), 148 ADF_GEN6_TL_CMDQ_DRAIN_COUNTER(wat) 149 }; 150 151 static_assert(ARRAY_SIZE(wat_cmdq_counters) == NUM_CMDQ_COUNTERS); 152 153 static const struct adf_tl_dbg_counter wcp_cmdq_counters[] = { 154 ADF_GEN6_TL_CMDQ_WAIT_COUNTER(wcp), 155 ADF_GEN6_TL_CMDQ_EXEC_COUNTER(wcp), 156 ADF_GEN6_TL_CMDQ_DRAIN_COUNTER(wcp) 157 }; 158 159 static_assert(ARRAY_SIZE(wcp_cmdq_counters) == NUM_CMDQ_COUNTERS); 160 161 static const struct adf_tl_dbg_counter ucs_cmdq_counters[] = { 162 ADF_GEN6_TL_CMDQ_WAIT_COUNTER(ucs), 163 ADF_GEN6_TL_CMDQ_EXEC_COUNTER(ucs), 164 ADF_GEN6_TL_CMDQ_DRAIN_COUNTER(ucs) 165 }; 166 167 static_assert(ARRAY_SIZE(ucs_cmdq_counters) == NUM_CMDQ_COUNTERS); 168 169 static const struct adf_tl_dbg_counter ath_cmdq_counters[] = { 170 ADF_GEN6_TL_CMDQ_WAIT_COUNTER(ath), 171 ADF_GEN6_TL_CMDQ_EXEC_COUNTER(ath), 172 ADF_GEN6_TL_CMDQ_DRAIN_COUNTER(ath) 173 }; 174 175 static_assert(ARRAY_SIZE(ath_cmdq_counters) == NUM_CMDQ_COUNTERS); 176 177 /* CMDQ drain counters. */ 178 static const struct adf_tl_dbg_counter *cmdq_counters[ADF_TL_SL_CNT_COUNT] = { 179 /* Compression accelerator execution count. */ 180 [SLICE_IDX(cpr)] = cnv_cmdq_counters, 181 /* Decompression accelerator execution count. */ 182 [SLICE_IDX(dcpr)] = dcprz_cmdq_counters, 183 /* PKE execution count. */ 184 [SLICE_IDX(pke)] = pke_cmdq_counters, 185 /* Wireless Authentication accelerator execution count. */ 186 [SLICE_IDX(wat)] = wat_cmdq_counters, 187 /* Wireless Cipher accelerator execution count. */ 188 [SLICE_IDX(wcp)] = wcp_cmdq_counters, 189 /* UCS accelerator execution count. */ 190 [SLICE_IDX(ucs)] = ucs_cmdq_counters, 191 /* Authentication accelerator execution count. */ 192 [SLICE_IDX(ath)] = ath_cmdq_counters, 193 }; 194 195 /* Ring pair counters. */ 196 static const struct adf_tl_dbg_counter rp_counters[] = { 197 /* PCIe partial transactions. */ 198 ADF_TL_COUNTER(PCI_TRANS_CNT_NAME, ADF_TL_SIMPLE_COUNT, 199 ADF_GEN6_TL_RP_REG_OFF(reg_tl_prt_trans_cnt)), 200 /* "Get to put" latency average[ns]. */ 201 ADF_TL_COUNTER_LATENCY(LAT_ACC_NAME, ADF_TL_COUNTER_NS_AVG, 202 ADF_GEN6_TL_RP_REG_OFF(reg_tl_gp_lat_acc), 203 ADF_GEN6_TL_RP_REG_OFF(reg_tl_ae_put_cnt)), 204 /* PCIe write bandwidth[Mbps]. */ 205 ADF_TL_COUNTER(BW_IN_NAME, ADF_TL_COUNTER_MBPS, 206 ADF_GEN6_TL_RP_REG_OFF(reg_tl_bw_in)), 207 /* PCIe read bandwidth[Mbps]. */ 208 ADF_TL_COUNTER(BW_OUT_NAME, ADF_TL_COUNTER_MBPS, 209 ADF_GEN6_TL_RP_REG_OFF(reg_tl_bw_out)), 210 /* Message descriptor DevTLB hit rate. */ 211 ADF_TL_COUNTER(AT_GLOB_DTLB_HIT_NAME, ADF_TL_SIMPLE_COUNT, 212 ADF_GEN6_TL_RP_REG_OFF(reg_tl_at_glob_devtlb_hit)), 213 /* Message descriptor DevTLB miss rate. */ 214 ADF_TL_COUNTER(AT_GLOB_DTLB_MISS_NAME, ADF_TL_SIMPLE_COUNT, 215 ADF_GEN6_TL_RP_REG_OFF(reg_tl_at_glob_devtlb_miss)), 216 /* Payload DevTLB hit rate. */ 217 ADF_TL_COUNTER(AT_PAYLD_DTLB_HIT_NAME, ADF_TL_SIMPLE_COUNT, 218 ADF_GEN6_TL_RP_REG_OFF(reg_tl_at_payld_devtlb_hit)), 219 /* Payload DevTLB miss rate. */ 220 ADF_TL_COUNTER(AT_PAYLD_DTLB_MISS_NAME, ADF_TL_SIMPLE_COUNT, 221 ADF_GEN6_TL_RP_REG_OFF(reg_tl_at_payld_devtlb_miss)), 222 /* Ring Empty average[ns]. */ 223 ADF_TL_COUNTER_LATENCY(RE_ACC_NAME, ADF_TL_COUNTER_NS_AVG, 224 ADF_GEN6_TL_RP_REG_OFF(reg_tl_re_acc), 225 ADF_GEN6_TL_RP_REG_OFF(reg_tl_re_cnt)), 226 }; 227 228 void adf_gen6_init_tl_data(struct adf_tl_hw_data *tl_data) 229 { 230 tl_data->layout_sz = ADF_GEN6_TL_LAYOUT_SZ; 231 tl_data->slice_reg_sz = ADF_GEN6_TL_SLICE_REG_SZ; 232 tl_data->cmdq_reg_sz = ADF_GEN6_TL_CMDQ_REG_SZ; 233 tl_data->rp_reg_sz = ADF_GEN6_TL_RP_REG_SZ; 234 tl_data->num_hbuff = ADF_GEN6_TL_NUM_HIST_BUFFS; 235 tl_data->max_rp = ADF_GEN6_TL_MAX_RP_NUM; 236 tl_data->msg_cnt_off = ADF_GEN6_TL_MSG_CNT_OFF; 237 tl_data->cpp_ns_per_cycle = ADF_GEN6_CPP_NS_PER_CYCLE; 238 tl_data->bw_units_to_bytes = ADF_GEN6_TL_BW_HW_UNITS_TO_BYTES; 239 240 tl_data->dev_counters = dev_counters; 241 tl_data->num_dev_counters = ARRAY_SIZE(dev_counters); 242 tl_data->sl_util_counters = sl_util_counters; 243 tl_data->sl_exec_counters = sl_exec_counters; 244 tl_data->cmdq_counters = cmdq_counters; 245 tl_data->num_cmdq_counters = NUM_CMDQ_COUNTERS; 246 tl_data->rp_counters = rp_counters; 247 tl_data->num_rp_counters = ARRAY_SIZE(rp_counters); 248 tl_data->max_sl_cnt = ADF_GEN6_TL_MAX_SLICES_PER_TYPE; 249 250 tl_data->multiplier.cpr_cnt = CPR_QUEUE_COUNT; 251 tl_data->multiplier.dcpr_cnt = DCPR_QUEUE_COUNT; 252 tl_data->multiplier.pke_cnt = PKE_QUEUE_COUNT; 253 tl_data->multiplier.wat_cnt = WAT_QUEUE_COUNT; 254 tl_data->multiplier.wcp_cnt = WCP_QUEUE_COUNT; 255 tl_data->multiplier.ucs_cnt = USC_QUEUE_COUNT; 256 tl_data->multiplier.ath_cnt = ATH_QUEUE_COUNT; 257 } 258 EXPORT_SYMBOL_GPL(adf_gen6_init_tl_data); 259