xref: /linux/drivers/crypto/intel/qat/qat_common/adf_gen6_tl.c (revision b4ada0618eed0fbd1b1630f73deb048c592b06a1)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2025 Intel Corporation. */
3 #include <linux/export.h>
4 
5 #include "adf_gen6_tl.h"
6 #include "adf_telemetry.h"
7 #include "adf_tl_debugfs.h"
8 #include "icp_qat_fw_init_admin.h"
9 
10 #define ADF_GEN6_TL_DEV_REG_OFF(reg) ADF_TL_DEV_REG_OFF(reg, gen6)
11 
12 #define ADF_GEN6_TL_RP_REG_OFF(reg) ADF_TL_RP_REG_OFF(reg, gen6)
13 
14 #define ADF_GEN6_TL_SL_UTIL_COUNTER(_name)			\
15 	ADF_TL_COUNTER("util_" #_name, ADF_TL_SIMPLE_COUNT,	\
16 			ADF_TL_SLICE_REG_OFF(_name, reg_tm_slice_util, gen6))
17 
18 #define ADF_GEN6_TL_SL_EXEC_COUNTER(_name)			\
19 	ADF_TL_COUNTER("exec_" #_name, ADF_TL_SIMPLE_COUNT,	\
20 			ADF_TL_SLICE_REG_OFF(_name, reg_tm_slice_exec_cnt, gen6))
21 
22 #define SLICE_IDX(sl) offsetof(struct icp_qat_fw_init_admin_slice_cnt, sl##_cnt)
23 
24 /* Device level counters. */
25 static const struct adf_tl_dbg_counter dev_counters[] = {
26 	/* PCIe partial transactions. */
27 	ADF_TL_COUNTER(PCI_TRANS_CNT_NAME, ADF_TL_SIMPLE_COUNT,
28 		       ADF_GEN6_TL_DEV_REG_OFF(reg_tl_prt_trans_cnt)),
29 	/* Max read latency[ns]. */
30 	ADF_TL_COUNTER(MAX_RD_LAT_NAME, ADF_TL_COUNTER_NS,
31 		       ADF_GEN6_TL_DEV_REG_OFF(reg_tl_rd_lat_max)),
32 	/* Read latency average[ns]. */
33 	ADF_TL_COUNTER_LATENCY(RD_LAT_ACC_NAME, ADF_TL_COUNTER_NS_AVG,
34 			       ADF_GEN6_TL_DEV_REG_OFF(reg_tl_rd_lat_acc),
35 			       ADF_GEN6_TL_DEV_REG_OFF(reg_tl_rd_cmpl_cnt)),
36 	/* Max "get to put" latency[ns]. */
37 	ADF_TL_COUNTER(MAX_LAT_NAME, ADF_TL_COUNTER_NS,
38 		       ADF_GEN6_TL_DEV_REG_OFF(reg_tl_gp_lat_max)),
39 	/* "Get to put" latency average[ns]. */
40 	ADF_TL_COUNTER_LATENCY(LAT_ACC_NAME, ADF_TL_COUNTER_NS_AVG,
41 			       ADF_GEN6_TL_DEV_REG_OFF(reg_tl_gp_lat_acc),
42 			       ADF_GEN6_TL_DEV_REG_OFF(reg_tl_ae_put_cnt)),
43 	/* PCIe write bandwidth[Mbps]. */
44 	ADF_TL_COUNTER(BW_IN_NAME, ADF_TL_COUNTER_MBPS,
45 		       ADF_GEN6_TL_DEV_REG_OFF(reg_tl_bw_in)),
46 	/* PCIe read bandwidth[Mbps]. */
47 	ADF_TL_COUNTER(BW_OUT_NAME, ADF_TL_COUNTER_MBPS,
48 		       ADF_GEN6_TL_DEV_REG_OFF(reg_tl_bw_out)),
49 	/* Page request latency average[ns]. */
50 	ADF_TL_COUNTER_LATENCY(PAGE_REQ_LAT_NAME, ADF_TL_COUNTER_NS_AVG,
51 			       ADF_GEN6_TL_DEV_REG_OFF(reg_tl_at_page_req_lat_acc),
52 			       ADF_GEN6_TL_DEV_REG_OFF(reg_tl_at_page_req_cnt)),
53 	/* Page translation latency average[ns]. */
54 	ADF_TL_COUNTER_LATENCY(AT_TRANS_LAT_NAME, ADF_TL_COUNTER_NS_AVG,
55 			       ADF_GEN6_TL_DEV_REG_OFF(reg_tl_at_trans_lat_acc),
56 			       ADF_GEN6_TL_DEV_REG_OFF(reg_tl_at_trans_lat_cnt)),
57 	/* Maximum uTLB used. */
58 	ADF_TL_COUNTER(AT_MAX_UTLB_USED_NAME, ADF_TL_SIMPLE_COUNT,
59 		       ADF_GEN6_TL_DEV_REG_OFF(reg_tl_at_max_utlb_used)),
60 };
61 
62 /* Accelerator utilization counters */
63 static const struct adf_tl_dbg_counter sl_util_counters[ADF_TL_SL_CNT_COUNT] = {
64 	/* Compression accelerator utilization. */
65 	[SLICE_IDX(cpr)] = ADF_GEN6_TL_SL_UTIL_COUNTER(cnv),
66 	/* Decompression accelerator utilization. */
67 	[SLICE_IDX(dcpr)] = ADF_GEN6_TL_SL_UTIL_COUNTER(dcprz),
68 	/* PKE accelerator utilization. */
69 	[SLICE_IDX(pke)] = ADF_GEN6_TL_SL_UTIL_COUNTER(pke),
70 	/* Wireless Authentication accelerator utilization. */
71 	[SLICE_IDX(wat)] = ADF_GEN6_TL_SL_UTIL_COUNTER(wat),
72 	/* Wireless Cipher accelerator utilization. */
73 	[SLICE_IDX(wcp)] = ADF_GEN6_TL_SL_UTIL_COUNTER(wcp),
74 	/* UCS accelerator utilization. */
75 	[SLICE_IDX(ucs)] = ADF_GEN6_TL_SL_UTIL_COUNTER(ucs),
76 	/* Authentication accelerator utilization. */
77 	[SLICE_IDX(ath)] = ADF_GEN6_TL_SL_UTIL_COUNTER(ath),
78 };
79 
80 /* Accelerator execution counters */
81 static const struct adf_tl_dbg_counter sl_exec_counters[ADF_TL_SL_CNT_COUNT] = {
82 	/* Compression accelerator execution count. */
83 	[SLICE_IDX(cpr)] = ADF_GEN6_TL_SL_EXEC_COUNTER(cnv),
84 	/* Decompression accelerator execution count. */
85 	[SLICE_IDX(dcpr)] = ADF_GEN6_TL_SL_EXEC_COUNTER(dcprz),
86 	/* PKE execution count. */
87 	[SLICE_IDX(pke)] = ADF_GEN6_TL_SL_EXEC_COUNTER(pke),
88 	/* Wireless Authentication accelerator execution count. */
89 	[SLICE_IDX(wat)] = ADF_GEN6_TL_SL_EXEC_COUNTER(wat),
90 	/* Wireless Cipher accelerator execution count. */
91 	[SLICE_IDX(wcp)] = ADF_GEN6_TL_SL_EXEC_COUNTER(wcp),
92 	/* UCS accelerator execution count. */
93 	[SLICE_IDX(ucs)] = ADF_GEN6_TL_SL_EXEC_COUNTER(ucs),
94 	/* Authentication accelerator execution count. */
95 	[SLICE_IDX(ath)] = ADF_GEN6_TL_SL_EXEC_COUNTER(ath),
96 };
97 
98 /* Ring pair counters. */
99 static const struct adf_tl_dbg_counter rp_counters[] = {
100 	/* PCIe partial transactions. */
101 	ADF_TL_COUNTER(PCI_TRANS_CNT_NAME, ADF_TL_SIMPLE_COUNT,
102 		       ADF_GEN6_TL_RP_REG_OFF(reg_tl_prt_trans_cnt)),
103 	/* "Get to put" latency average[ns]. */
104 	ADF_TL_COUNTER_LATENCY(LAT_ACC_NAME, ADF_TL_COUNTER_NS_AVG,
105 			       ADF_GEN6_TL_RP_REG_OFF(reg_tl_gp_lat_acc),
106 			       ADF_GEN6_TL_RP_REG_OFF(reg_tl_ae_put_cnt)),
107 	/* PCIe write bandwidth[Mbps]. */
108 	ADF_TL_COUNTER(BW_IN_NAME, ADF_TL_COUNTER_MBPS,
109 		       ADF_GEN6_TL_RP_REG_OFF(reg_tl_bw_in)),
110 	/* PCIe read bandwidth[Mbps]. */
111 	ADF_TL_COUNTER(BW_OUT_NAME, ADF_TL_COUNTER_MBPS,
112 		       ADF_GEN6_TL_RP_REG_OFF(reg_tl_bw_out)),
113 	/* Message descriptor DevTLB hit rate. */
114 	ADF_TL_COUNTER(AT_GLOB_DTLB_HIT_NAME, ADF_TL_SIMPLE_COUNT,
115 		       ADF_GEN6_TL_RP_REG_OFF(reg_tl_at_glob_devtlb_hit)),
116 	/* Message descriptor DevTLB miss rate. */
117 	ADF_TL_COUNTER(AT_GLOB_DTLB_MISS_NAME, ADF_TL_SIMPLE_COUNT,
118 		       ADF_GEN6_TL_RP_REG_OFF(reg_tl_at_glob_devtlb_miss)),
119 	/* Payload DevTLB hit rate. */
120 	ADF_TL_COUNTER(AT_PAYLD_DTLB_HIT_NAME, ADF_TL_SIMPLE_COUNT,
121 		       ADF_GEN6_TL_RP_REG_OFF(reg_tl_at_payld_devtlb_hit)),
122 	/* Payload DevTLB miss rate. */
123 	ADF_TL_COUNTER(AT_PAYLD_DTLB_MISS_NAME, ADF_TL_SIMPLE_COUNT,
124 		       ADF_GEN6_TL_RP_REG_OFF(reg_tl_at_payld_devtlb_miss)),
125 };
126 
127 void adf_gen6_init_tl_data(struct adf_tl_hw_data *tl_data)
128 {
129 	tl_data->layout_sz = ADF_GEN6_TL_LAYOUT_SZ;
130 	tl_data->slice_reg_sz = ADF_GEN6_TL_SLICE_REG_SZ;
131 	tl_data->rp_reg_sz = ADF_GEN6_TL_RP_REG_SZ;
132 	tl_data->num_hbuff = ADF_GEN6_TL_NUM_HIST_BUFFS;
133 	tl_data->max_rp = ADF_GEN6_TL_MAX_RP_NUM;
134 	tl_data->msg_cnt_off = ADF_GEN6_TL_MSG_CNT_OFF;
135 	tl_data->cpp_ns_per_cycle = ADF_GEN6_CPP_NS_PER_CYCLE;
136 	tl_data->bw_units_to_bytes = ADF_GEN6_TL_BW_HW_UNITS_TO_BYTES;
137 
138 	tl_data->dev_counters = dev_counters;
139 	tl_data->num_dev_counters = ARRAY_SIZE(dev_counters);
140 	tl_data->sl_util_counters = sl_util_counters;
141 	tl_data->sl_exec_counters = sl_exec_counters;
142 	tl_data->rp_counters = rp_counters;
143 	tl_data->num_rp_counters = ARRAY_SIZE(rp_counters);
144 	tl_data->max_sl_cnt = ADF_GEN6_TL_MAX_SLICES_PER_TYPE;
145 }
146 EXPORT_SYMBOL_GPL(adf_gen6_init_tl_data);
147