1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */ 2 /* Copyright(c) 2014 - 2020 Intel Corporation */ 3 #ifndef ADF_ACCEL_DEVICES_H_ 4 #define ADF_ACCEL_DEVICES_H_ 5 #include <linux/interrupt.h> 6 #include <linux/module.h> 7 #include <linux/list.h> 8 #include <linux/io.h> 9 #include <linux/ratelimit.h> 10 #include <linux/types.h> 11 #include "adf_cfg_common.h" 12 #include "adf_rl.h" 13 #include "adf_pfvf_msg.h" 14 15 #define ADF_DH895XCC_DEVICE_NAME "dh895xcc" 16 #define ADF_DH895XCCVF_DEVICE_NAME "dh895xccvf" 17 #define ADF_C62X_DEVICE_NAME "c6xx" 18 #define ADF_C62XVF_DEVICE_NAME "c6xxvf" 19 #define ADF_C3XXX_DEVICE_NAME "c3xxx" 20 #define ADF_C3XXXVF_DEVICE_NAME "c3xxxvf" 21 #define ADF_4XXX_DEVICE_NAME "4xxx" 22 #define ADF_4XXX_PCI_DEVICE_ID 0x4940 23 #define ADF_4XXXIOV_PCI_DEVICE_ID 0x4941 24 #define ADF_401XX_PCI_DEVICE_ID 0x4942 25 #define ADF_401XXIOV_PCI_DEVICE_ID 0x4943 26 #define ADF_402XX_PCI_DEVICE_ID 0x4944 27 #define ADF_402XXIOV_PCI_DEVICE_ID 0x4945 28 #define ADF_DEVICE_FUSECTL_OFFSET 0x40 29 #define ADF_DEVICE_LEGFUSE_OFFSET 0x4C 30 #define ADF_DEVICE_FUSECTL_MASK 0x80000000 31 #define ADF_PCI_MAX_BARS 3 32 #define ADF_DEVICE_NAME_LENGTH 32 33 #define ADF_ETR_MAX_RINGS_PER_BANK 16 34 #define ADF_MAX_MSIX_VECTOR_NAME 48 35 #define ADF_DEVICE_NAME_PREFIX "qat_" 36 37 enum adf_accel_capabilities { 38 ADF_ACCEL_CAPABILITIES_NULL = 0, 39 ADF_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC = 1, 40 ADF_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC = 2, 41 ADF_ACCEL_CAPABILITIES_CIPHER = 4, 42 ADF_ACCEL_CAPABILITIES_AUTHENTICATION = 8, 43 ADF_ACCEL_CAPABILITIES_COMPRESSION = 32, 44 ADF_ACCEL_CAPABILITIES_LZS_COMPRESSION = 64, 45 ADF_ACCEL_CAPABILITIES_RANDOM_NUMBER = 128 46 }; 47 48 struct adf_bar { 49 resource_size_t base_addr; 50 void __iomem *virt_addr; 51 resource_size_t size; 52 }; 53 54 struct adf_irq { 55 bool enabled; 56 char name[ADF_MAX_MSIX_VECTOR_NAME]; 57 }; 58 59 struct adf_accel_msix { 60 struct adf_irq *irqs; 61 u32 num_entries; 62 }; 63 64 struct adf_accel_pci { 65 struct pci_dev *pci_dev; 66 struct adf_accel_msix msix_entries; 67 struct adf_bar pci_bars[ADF_PCI_MAX_BARS]; 68 u8 revid; 69 u8 sku; 70 }; 71 72 enum dev_state { 73 DEV_DOWN = 0, 74 DEV_UP 75 }; 76 77 enum dev_sku_info { 78 DEV_SKU_1 = 0, 79 DEV_SKU_2, 80 DEV_SKU_3, 81 DEV_SKU_4, 82 DEV_SKU_VF, 83 DEV_SKU_UNKNOWN, 84 }; 85 86 enum ras_errors { 87 ADF_RAS_CORR, 88 ADF_RAS_UNCORR, 89 ADF_RAS_FATAL, 90 ADF_RAS_ERRORS, 91 }; 92 93 struct adf_error_counters { 94 atomic_t counter[ADF_RAS_ERRORS]; 95 bool enabled; 96 }; 97 98 static inline const char *get_sku_info(enum dev_sku_info info) 99 { 100 switch (info) { 101 case DEV_SKU_1: 102 return "SKU1"; 103 case DEV_SKU_2: 104 return "SKU2"; 105 case DEV_SKU_3: 106 return "SKU3"; 107 case DEV_SKU_4: 108 return "SKU4"; 109 case DEV_SKU_VF: 110 return "SKUVF"; 111 case DEV_SKU_UNKNOWN: 112 default: 113 break; 114 } 115 return "Unknown SKU"; 116 } 117 118 struct adf_hw_device_class { 119 const char *name; 120 const enum adf_device_type type; 121 u32 instances; 122 }; 123 124 struct arb_info { 125 u32 arb_cfg; 126 u32 arb_offset; 127 u32 wt2sam_offset; 128 }; 129 130 struct admin_info { 131 u32 admin_msg_ur; 132 u32 admin_msg_lr; 133 u32 mailbox_offset; 134 }; 135 136 struct adf_hw_csr_ops { 137 u64 (*build_csr_ring_base_addr)(dma_addr_t addr, u32 size); 138 u32 (*read_csr_ring_head)(void __iomem *csr_base_addr, u32 bank, 139 u32 ring); 140 void (*write_csr_ring_head)(void __iomem *csr_base_addr, u32 bank, 141 u32 ring, u32 value); 142 u32 (*read_csr_ring_tail)(void __iomem *csr_base_addr, u32 bank, 143 u32 ring); 144 void (*write_csr_ring_tail)(void __iomem *csr_base_addr, u32 bank, 145 u32 ring, u32 value); 146 u32 (*read_csr_e_stat)(void __iomem *csr_base_addr, u32 bank); 147 void (*write_csr_ring_config)(void __iomem *csr_base_addr, u32 bank, 148 u32 ring, u32 value); 149 void (*write_csr_ring_base)(void __iomem *csr_base_addr, u32 bank, 150 u32 ring, dma_addr_t addr); 151 void (*write_csr_int_flag)(void __iomem *csr_base_addr, u32 bank, 152 u32 value); 153 void (*write_csr_int_srcsel)(void __iomem *csr_base_addr, u32 bank); 154 void (*write_csr_int_col_en)(void __iomem *csr_base_addr, u32 bank, 155 u32 value); 156 void (*write_csr_int_col_ctl)(void __iomem *csr_base_addr, u32 bank, 157 u32 value); 158 void (*write_csr_int_flag_and_col)(void __iomem *csr_base_addr, 159 u32 bank, u32 value); 160 void (*write_csr_ring_srv_arb_en)(void __iomem *csr_base_addr, u32 bank, 161 u32 value); 162 }; 163 164 struct adf_cfg_device_data; 165 struct adf_accel_dev; 166 struct adf_etr_data; 167 struct adf_etr_ring_data; 168 169 struct adf_ras_ops { 170 void (*enable_ras_errors)(struct adf_accel_dev *accel_dev); 171 void (*disable_ras_errors)(struct adf_accel_dev *accel_dev); 172 bool (*handle_interrupt)(struct adf_accel_dev *accel_dev, 173 bool *reset_required); 174 }; 175 176 struct adf_pfvf_ops { 177 int (*enable_comms)(struct adf_accel_dev *accel_dev); 178 u32 (*get_pf2vf_offset)(u32 i); 179 u32 (*get_vf2pf_offset)(u32 i); 180 void (*enable_vf2pf_interrupts)(void __iomem *pmisc_addr, u32 vf_mask); 181 void (*disable_all_vf2pf_interrupts)(void __iomem *pmisc_addr); 182 u32 (*disable_pending_vf2pf_interrupts)(void __iomem *pmisc_addr); 183 int (*send_msg)(struct adf_accel_dev *accel_dev, struct pfvf_message msg, 184 u32 pfvf_offset, struct mutex *csr_lock); 185 struct pfvf_message (*recv_msg)(struct adf_accel_dev *accel_dev, 186 u32 pfvf_offset, u8 compat_ver); 187 }; 188 189 struct adf_dc_ops { 190 void (*build_deflate_ctx)(void *ctx); 191 }; 192 193 struct adf_dev_err_mask { 194 u32 cppagentcmdpar_mask; 195 u32 parerr_ath_cph_mask; 196 u32 parerr_cpr_xlt_mask; 197 u32 parerr_dcpr_ucs_mask; 198 u32 parerr_pke_mask; 199 u32 parerr_wat_wcp_mask; 200 u32 ssmfeatren_mask; 201 }; 202 203 struct adf_hw_device_data { 204 struct adf_hw_device_class *dev_class; 205 u32 (*get_accel_mask)(struct adf_hw_device_data *self); 206 u32 (*get_ae_mask)(struct adf_hw_device_data *self); 207 u32 (*get_accel_cap)(struct adf_accel_dev *accel_dev); 208 u32 (*get_sram_bar_id)(struct adf_hw_device_data *self); 209 u32 (*get_misc_bar_id)(struct adf_hw_device_data *self); 210 u32 (*get_etr_bar_id)(struct adf_hw_device_data *self); 211 u32 (*get_num_aes)(struct adf_hw_device_data *self); 212 u32 (*get_num_accels)(struct adf_hw_device_data *self); 213 void (*get_arb_info)(struct arb_info *arb_csrs_info); 214 void (*get_admin_info)(struct admin_info *admin_csrs_info); 215 enum dev_sku_info (*get_sku)(struct adf_hw_device_data *self); 216 u16 (*get_ring_to_svc_map)(struct adf_accel_dev *accel_dev); 217 int (*alloc_irq)(struct adf_accel_dev *accel_dev); 218 void (*free_irq)(struct adf_accel_dev *accel_dev); 219 void (*enable_error_correction)(struct adf_accel_dev *accel_dev); 220 int (*init_admin_comms)(struct adf_accel_dev *accel_dev); 221 void (*exit_admin_comms)(struct adf_accel_dev *accel_dev); 222 int (*send_admin_init)(struct adf_accel_dev *accel_dev); 223 int (*start_timer)(struct adf_accel_dev *accel_dev); 224 void (*stop_timer)(struct adf_accel_dev *accel_dev); 225 void (*check_hb_ctrs)(struct adf_accel_dev *accel_dev); 226 uint32_t (*get_hb_clock)(struct adf_hw_device_data *self); 227 int (*measure_clock)(struct adf_accel_dev *accel_dev); 228 int (*init_arb)(struct adf_accel_dev *accel_dev); 229 void (*exit_arb)(struct adf_accel_dev *accel_dev); 230 const u32 *(*get_arb_mapping)(struct adf_accel_dev *accel_dev); 231 int (*init_device)(struct adf_accel_dev *accel_dev); 232 int (*enable_pm)(struct adf_accel_dev *accel_dev); 233 bool (*handle_pm_interrupt)(struct adf_accel_dev *accel_dev); 234 void (*disable_iov)(struct adf_accel_dev *accel_dev); 235 void (*configure_iov_threads)(struct adf_accel_dev *accel_dev, 236 bool enable); 237 void (*enable_ints)(struct adf_accel_dev *accel_dev); 238 void (*set_ssm_wdtimer)(struct adf_accel_dev *accel_dev); 239 int (*ring_pair_reset)(struct adf_accel_dev *accel_dev, u32 bank_nr); 240 void (*reset_device)(struct adf_accel_dev *accel_dev); 241 void (*set_msix_rttable)(struct adf_accel_dev *accel_dev); 242 const char *(*uof_get_name)(struct adf_accel_dev *accel_dev, u32 obj_num); 243 u32 (*uof_get_num_objs)(void); 244 u32 (*uof_get_ae_mask)(struct adf_accel_dev *accel_dev, u32 obj_num); 245 int (*dev_config)(struct adf_accel_dev *accel_dev); 246 struct adf_pfvf_ops pfvf_ops; 247 struct adf_hw_csr_ops csr_ops; 248 struct adf_dc_ops dc_ops; 249 struct adf_ras_ops ras_ops; 250 struct adf_dev_err_mask dev_err_mask; 251 struct adf_rl_hw_data rl_data; 252 const char *fw_name; 253 const char *fw_mmp_name; 254 u32 fuses; 255 u32 straps; 256 u32 accel_capabilities_mask; 257 u32 extended_dc_capabilities; 258 u16 fw_capabilities; 259 u32 clock_frequency; 260 u32 instance_id; 261 u16 accel_mask; 262 u32 ae_mask; 263 u32 admin_ae_mask; 264 u16 tx_rings_mask; 265 u16 ring_to_svc_map; 266 u8 tx_rx_gap; 267 u8 num_banks; 268 u16 num_banks_per_vf; 269 u8 num_rings_per_bank; 270 u8 num_accel; 271 u8 num_logical_accel; 272 u8 num_engines; 273 u32 num_hb_ctrs; 274 }; 275 276 /* CSR write macro */ 277 #define ADF_CSR_WR(csr_base, csr_offset, val) \ 278 __raw_writel(val, csr_base + csr_offset) 279 280 /* CSR read macro */ 281 #define ADF_CSR_RD(csr_base, csr_offset) __raw_readl(csr_base + csr_offset) 282 283 #define ADF_CFG_NUM_SERVICES 4 284 #define ADF_SRV_TYPE_BIT_LEN 3 285 #define ADF_SRV_TYPE_MASK 0x7 286 #define ADF_AE_ADMIN_THREAD 7 287 #define ADF_NUM_THREADS_PER_AE 8 288 #define ADF_NUM_PKE_STRAND 2 289 #define ADF_AE_STRAND0_THREAD 8 290 #define ADF_AE_STRAND1_THREAD 9 291 292 #define GET_DEV(accel_dev) ((accel_dev)->accel_pci_dev.pci_dev->dev) 293 #define GET_BARS(accel_dev) ((accel_dev)->accel_pci_dev.pci_bars) 294 #define GET_HW_DATA(accel_dev) (accel_dev->hw_device) 295 #define GET_MAX_BANKS(accel_dev) (GET_HW_DATA(accel_dev)->num_banks) 296 #define GET_NUM_RINGS_PER_BANK(accel_dev) \ 297 GET_HW_DATA(accel_dev)->num_rings_per_bank 298 #define GET_SRV_TYPE(accel_dev, idx) \ 299 (((GET_HW_DATA(accel_dev)->ring_to_svc_map) >> (ADF_SRV_TYPE_BIT_LEN * (idx))) \ 300 & ADF_SRV_TYPE_MASK) 301 #define GET_ERR_MASK(accel_dev) (&GET_HW_DATA(accel_dev)->dev_err_mask) 302 #define GET_MAX_ACCELENGINES(accel_dev) (GET_HW_DATA(accel_dev)->num_engines) 303 #define GET_CSR_OPS(accel_dev) (&(accel_dev)->hw_device->csr_ops) 304 #define GET_PFVF_OPS(accel_dev) (&(accel_dev)->hw_device->pfvf_ops) 305 #define GET_DC_OPS(accel_dev) (&(accel_dev)->hw_device->dc_ops) 306 #define accel_to_pci_dev(accel_ptr) accel_ptr->accel_pci_dev.pci_dev 307 308 struct adf_admin_comms; 309 struct icp_qat_fw_loader_handle; 310 struct adf_fw_loader_data { 311 struct icp_qat_fw_loader_handle *fw_loader; 312 const struct firmware *uof_fw; 313 const struct firmware *mmp_fw; 314 }; 315 316 struct adf_accel_vf_info { 317 struct adf_accel_dev *accel_dev; 318 struct mutex pf2vf_lock; /* protect CSR access for PF2VF messages */ 319 struct ratelimit_state vf2pf_ratelimit; 320 u32 vf_nr; 321 bool init; 322 u8 vf_compat_ver; 323 }; 324 325 struct adf_dc_data { 326 u8 *ovf_buff; 327 size_t ovf_buff_sz; 328 dma_addr_t ovf_buff_p; 329 }; 330 331 struct adf_pm { 332 struct dentry *debugfs_pm_status; 333 bool present; 334 int idle_irq_counters; 335 int throttle_irq_counters; 336 int fw_irq_counters; 337 int host_ack_counter; 338 int host_nack_counter; 339 ssize_t (*print_pm_status)(struct adf_accel_dev *accel_dev, 340 char __user *buf, size_t count, loff_t *pos); 341 }; 342 343 struct adf_sysfs { 344 int ring_num; 345 struct rw_semaphore lock; /* protects access to the fields in this struct */ 346 }; 347 348 struct adf_accel_dev { 349 struct adf_etr_data *transport; 350 struct adf_hw_device_data *hw_device; 351 struct adf_cfg_device_data *cfg; 352 struct adf_fw_loader_data *fw_loader; 353 struct adf_admin_comms *admin; 354 struct adf_dc_data *dc_data; 355 struct adf_pm power_management; 356 struct list_head crypto_list; 357 struct list_head compression_list; 358 unsigned long status; 359 atomic_t ref_count; 360 struct dentry *debugfs_dir; 361 struct dentry *fw_cntr_dbgfile; 362 struct dentry *cnv_dbgfile; 363 struct list_head list; 364 struct module *owner; 365 struct adf_accel_pci accel_pci_dev; 366 struct adf_timer *timer; 367 struct adf_heartbeat *heartbeat; 368 struct adf_rl *rate_limiting; 369 struct adf_sysfs sysfs; 370 union { 371 struct { 372 /* protects VF2PF interrupts access */ 373 spinlock_t vf2pf_ints_lock; 374 /* vf_info is non-zero when SR-IOV is init'ed */ 375 struct adf_accel_vf_info *vf_info; 376 } pf; 377 struct { 378 bool irq_enabled; 379 char irq_name[ADF_MAX_MSIX_VECTOR_NAME]; 380 struct tasklet_struct pf2vf_bh_tasklet; 381 struct mutex vf2pf_lock; /* protect CSR access */ 382 struct completion msg_received; 383 struct pfvf_message response; /* temp field holding pf2vf response */ 384 u8 pf_compat_ver; 385 } vf; 386 }; 387 struct adf_error_counters ras_errors; 388 struct mutex state_lock; /* protect state of the device */ 389 bool is_vf; 390 u32 accel_id; 391 }; 392 #endif 393