1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2019 HiSilicon Limited. */ 3 #include <linux/acpi.h> 4 #include <linux/bitops.h> 5 #include <linux/debugfs.h> 6 #include <linux/init.h> 7 #include <linux/io.h> 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/pci.h> 11 #include <linux/pm_runtime.h> 12 #include <linux/seq_file.h> 13 #include <linux/topology.h> 14 #include <linux/uacce.h> 15 #include "zip.h" 16 17 #define PCI_DEVICE_ID_HUAWEI_ZIP_PF 0xa250 18 19 #define HZIP_QUEUE_NUM_V1 4096 20 21 #define HZIP_CLOCK_GATE_CTRL 0x301004 22 #define HZIP_DECOMP_CHECK_ENABLE BIT(16) 23 #define HZIP_FSM_MAX_CNT 0x301008 24 25 #define HZIP_PORT_ARCA_CHE_0 0x301040 26 #define HZIP_PORT_ARCA_CHE_1 0x301044 27 #define HZIP_PORT_AWCA_CHE_0 0x301060 28 #define HZIP_PORT_AWCA_CHE_1 0x301064 29 #define HZIP_CACHE_ALL_EN 0xffffffff 30 31 #define HZIP_BD_RUSER_32_63 0x301110 32 #define HZIP_SGL_RUSER_32_63 0x30111c 33 #define HZIP_DATA_RUSER_32_63 0x301128 34 #define HZIP_DATA_WUSER_32_63 0x301134 35 #define HZIP_BD_WUSER_32_63 0x301140 36 37 #define HZIP_QM_IDEL_STATUS 0x3040e4 38 39 #define HZIP_CORE_DFX_BASE 0x301000 40 #define HZIP_CLOCK_GATED_CONTL 0X301004 41 #define HZIP_CORE_DFX_COMP_0 0x302000 42 #define HZIP_CORE_DFX_COMP_1 0x303000 43 #define HZIP_CORE_DFX_DECOMP_0 0x304000 44 #define HZIP_CORE_DFX_DECOMP_1 0x305000 45 #define HZIP_CORE_DFX_DECOMP_2 0x306000 46 #define HZIP_CORE_DFX_DECOMP_3 0x307000 47 #define HZIP_CORE_DFX_DECOMP_4 0x308000 48 #define HZIP_CORE_DFX_DECOMP_5 0x309000 49 #define HZIP_CORE_REGS_BASE_LEN 0xB0 50 #define HZIP_CORE_REGS_DFX_LEN 0x28 51 52 #define HZIP_CORE_INT_SOURCE 0x3010A0 53 #define HZIP_CORE_INT_MASK_REG 0x3010A4 54 #define HZIP_CORE_INT_SET 0x3010A8 55 #define HZIP_CORE_INT_STATUS 0x3010AC 56 #define HZIP_CORE_INT_STATUS_M_ECC BIT(1) 57 #define HZIP_CORE_SRAM_ECC_ERR_INFO 0x301148 58 #define HZIP_CORE_INT_RAS_CE_ENB 0x301160 59 #define HZIP_CORE_INT_RAS_NFE_ENB 0x301164 60 #define HZIP_CORE_INT_RAS_FE_ENB 0x301168 61 #define HZIP_CORE_INT_RAS_FE_ENB_MASK 0x0 62 #define HZIP_OOO_SHUTDOWN_SEL 0x30120C 63 #define HZIP_SRAM_ECC_ERR_NUM_SHIFT 16 64 #define HZIP_SRAM_ECC_ERR_ADDR_SHIFT 24 65 #define HZIP_CORE_INT_MASK_ALL GENMASK(12, 0) 66 #define HZIP_SQE_SIZE 128 67 #define HZIP_PF_DEF_Q_NUM 64 68 #define HZIP_PF_DEF_Q_BASE 0 69 70 #define HZIP_SOFT_CTRL_CNT_CLR_CE 0x301000 71 #define HZIP_SOFT_CTRL_CNT_CLR_CE_BIT BIT(0) 72 #define HZIP_SOFT_CTRL_ZIP_CONTROL 0x30100C 73 #define HZIP_AXI_SHUTDOWN_ENABLE BIT(14) 74 #define HZIP_WR_PORT BIT(11) 75 76 #define HZIP_DEV_ALG_MAX_LEN 256 77 #define HZIP_ALG_ZLIB_BIT GENMASK(1, 0) 78 #define HZIP_ALG_GZIP_BIT GENMASK(3, 2) 79 #define HZIP_ALG_DEFLATE_BIT GENMASK(5, 4) 80 #define HZIP_ALG_LZ77_BIT GENMASK(7, 6) 81 82 #define HZIP_BUF_SIZE 22 83 #define HZIP_SQE_MASK_OFFSET 64 84 #define HZIP_SQE_MASK_LEN 48 85 86 #define HZIP_CNT_CLR_CE_EN BIT(0) 87 #define HZIP_RO_CNT_CLR_CE_EN BIT(2) 88 #define HZIP_RD_CNT_CLR_CE_EN (HZIP_CNT_CLR_CE_EN | \ 89 HZIP_RO_CNT_CLR_CE_EN) 90 91 #define HZIP_PREFETCH_CFG 0x3011B0 92 #define HZIP_SVA_TRANS 0x3011C4 93 #define HZIP_PREFETCH_ENABLE (~(BIT(26) | BIT(17) | BIT(0))) 94 #define HZIP_SVA_PREFETCH_DISABLE BIT(26) 95 #define HZIP_SVA_DISABLE_READY (BIT(26) | BIT(30)) 96 #define HZIP_SHAPER_RATE_COMPRESS 750 97 #define HZIP_SHAPER_RATE_DECOMPRESS 140 98 #define HZIP_DELAY_1_US 1 99 #define HZIP_POLL_TIMEOUT_US 1000 100 101 /* clock gating */ 102 #define HZIP_PEH_CFG_AUTO_GATE 0x3011A8 103 #define HZIP_PEH_CFG_AUTO_GATE_EN BIT(0) 104 #define HZIP_CORE_GATED_EN GENMASK(15, 8) 105 #define HZIP_CORE_GATED_OOO_EN BIT(29) 106 #define HZIP_CLOCK_GATED_EN (HZIP_CORE_GATED_EN | \ 107 HZIP_CORE_GATED_OOO_EN) 108 109 static const char hisi_zip_name[] = "hisi_zip"; 110 static struct dentry *hzip_debugfs_root; 111 112 struct hisi_zip_hw_error { 113 u32 int_msk; 114 const char *msg; 115 }; 116 117 struct zip_dfx_item { 118 const char *name; 119 u32 offset; 120 }; 121 122 struct zip_dev_alg { 123 u32 alg_msk; 124 const char *algs; 125 }; 126 127 static const struct zip_dev_alg zip_dev_algs[] = { { 128 .alg_msk = HZIP_ALG_ZLIB_BIT, 129 .algs = "zlib\n", 130 }, { 131 .alg_msk = HZIP_ALG_GZIP_BIT, 132 .algs = "gzip\n", 133 }, { 134 .alg_msk = HZIP_ALG_DEFLATE_BIT, 135 .algs = "deflate\n", 136 }, { 137 .alg_msk = HZIP_ALG_LZ77_BIT, 138 .algs = "lz77_zstd\n", 139 }, 140 }; 141 142 static struct hisi_qm_list zip_devices = { 143 .register_to_crypto = hisi_zip_register_to_crypto, 144 .unregister_from_crypto = hisi_zip_unregister_from_crypto, 145 }; 146 147 static struct zip_dfx_item zip_dfx_files[] = { 148 {"send_cnt", offsetof(struct hisi_zip_dfx, send_cnt)}, 149 {"recv_cnt", offsetof(struct hisi_zip_dfx, recv_cnt)}, 150 {"send_busy_cnt", offsetof(struct hisi_zip_dfx, send_busy_cnt)}, 151 {"err_bd_cnt", offsetof(struct hisi_zip_dfx, err_bd_cnt)}, 152 }; 153 154 static const struct hisi_zip_hw_error zip_hw_error[] = { 155 { .int_msk = BIT(0), .msg = "zip_ecc_1bitt_err" }, 156 { .int_msk = BIT(1), .msg = "zip_ecc_2bit_err" }, 157 { .int_msk = BIT(2), .msg = "zip_axi_rresp_err" }, 158 { .int_msk = BIT(3), .msg = "zip_axi_bresp_err" }, 159 { .int_msk = BIT(4), .msg = "zip_src_addr_parse_err" }, 160 { .int_msk = BIT(5), .msg = "zip_dst_addr_parse_err" }, 161 { .int_msk = BIT(6), .msg = "zip_pre_in_addr_err" }, 162 { .int_msk = BIT(7), .msg = "zip_pre_in_data_err" }, 163 { .int_msk = BIT(8), .msg = "zip_com_inf_err" }, 164 { .int_msk = BIT(9), .msg = "zip_enc_inf_err" }, 165 { .int_msk = BIT(10), .msg = "zip_pre_out_err" }, 166 { .int_msk = BIT(11), .msg = "zip_axi_poison_err" }, 167 { .int_msk = BIT(12), .msg = "zip_sva_err" }, 168 { /* sentinel */ } 169 }; 170 171 enum ctrl_debug_file_index { 172 HZIP_CLEAR_ENABLE, 173 HZIP_DEBUG_FILE_NUM, 174 }; 175 176 static const char * const ctrl_debug_file_name[] = { 177 [HZIP_CLEAR_ENABLE] = "clear_enable", 178 }; 179 180 struct ctrl_debug_file { 181 enum ctrl_debug_file_index index; 182 spinlock_t lock; 183 struct hisi_zip_ctrl *ctrl; 184 }; 185 186 /* 187 * One ZIP controller has one PF and multiple VFs, some global configurations 188 * which PF has need this structure. 189 * 190 * Just relevant for PF. 191 */ 192 struct hisi_zip_ctrl { 193 struct hisi_zip *hisi_zip; 194 struct ctrl_debug_file files[HZIP_DEBUG_FILE_NUM]; 195 }; 196 197 enum zip_cap_type { 198 ZIP_QM_NFE_MASK_CAP = 0x0, 199 ZIP_QM_RESET_MASK_CAP, 200 ZIP_QM_OOO_SHUTDOWN_MASK_CAP, 201 ZIP_QM_CE_MASK_CAP, 202 ZIP_NFE_MASK_CAP, 203 ZIP_RESET_MASK_CAP, 204 ZIP_OOO_SHUTDOWN_MASK_CAP, 205 ZIP_CE_MASK_CAP, 206 ZIP_CLUSTER_NUM_CAP, 207 ZIP_CORE_TYPE_NUM_CAP, 208 ZIP_CORE_NUM_CAP, 209 ZIP_CLUSTER_COMP_NUM_CAP, 210 ZIP_CLUSTER_DECOMP_NUM_CAP, 211 ZIP_DECOMP_ENABLE_BITMAP, 212 ZIP_COMP_ENABLE_BITMAP, 213 ZIP_DRV_ALG_BITMAP, 214 ZIP_DEV_ALG_BITMAP, 215 ZIP_CORE1_ALG_BITMAP, 216 ZIP_CORE2_ALG_BITMAP, 217 ZIP_CORE3_ALG_BITMAP, 218 ZIP_CORE4_ALG_BITMAP, 219 ZIP_CORE5_ALG_BITMAP, 220 ZIP_CAP_MAX 221 }; 222 223 static struct hisi_qm_cap_info zip_basic_cap_info[] = { 224 {ZIP_QM_NFE_MASK_CAP, 0x3124, 0, GENMASK(31, 0), 0x0, 0x1C57, 0x7C77}, 225 {ZIP_QM_RESET_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0xC57, 0x6C77}, 226 {ZIP_QM_OOO_SHUTDOWN_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0x4, 0x6C77}, 227 {ZIP_QM_CE_MASK_CAP, 0x312C, 0, GENMASK(31, 0), 0x0, 0x8, 0x8}, 228 {ZIP_NFE_MASK_CAP, 0x3130, 0, GENMASK(31, 0), 0x0, 0x7FE, 0x1FFE}, 229 {ZIP_RESET_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x7FE, 0x7FE}, 230 {ZIP_OOO_SHUTDOWN_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x2, 0x7FE}, 231 {ZIP_CE_MASK_CAP, 0x3138, 0, GENMASK(31, 0), 0x0, 0x1, 0x1}, 232 {ZIP_CLUSTER_NUM_CAP, 0x313C, 28, GENMASK(3, 0), 0x1, 0x1, 0x1}, 233 {ZIP_CORE_TYPE_NUM_CAP, 0x313C, 24, GENMASK(3, 0), 0x2, 0x2, 0x2}, 234 {ZIP_CORE_NUM_CAP, 0x313C, 16, GENMASK(7, 0), 0x8, 0x8, 0x5}, 235 {ZIP_CLUSTER_COMP_NUM_CAP, 0x313C, 8, GENMASK(7, 0), 0x2, 0x2, 0x2}, 236 {ZIP_CLUSTER_DECOMP_NUM_CAP, 0x313C, 0, GENMASK(7, 0), 0x6, 0x6, 0x3}, 237 {ZIP_DECOMP_ENABLE_BITMAP, 0x3140, 16, GENMASK(15, 0), 0xFC, 0xFC, 0x1C}, 238 {ZIP_COMP_ENABLE_BITMAP, 0x3140, 0, GENMASK(15, 0), 0x3, 0x3, 0x3}, 239 {ZIP_DRV_ALG_BITMAP, 0x3144, 0, GENMASK(31, 0), 0xF, 0xF, 0xF}, 240 {ZIP_DEV_ALG_BITMAP, 0x3148, 0, GENMASK(31, 0), 0xF, 0xF, 0xFF}, 241 {ZIP_CORE1_ALG_BITMAP, 0x314C, 0, GENMASK(31, 0), 0x5, 0x5, 0xD5}, 242 {ZIP_CORE2_ALG_BITMAP, 0x3150, 0, GENMASK(31, 0), 0x5, 0x5, 0xD5}, 243 {ZIP_CORE3_ALG_BITMAP, 0x3154, 0, GENMASK(31, 0), 0xA, 0xA, 0x2A}, 244 {ZIP_CORE4_ALG_BITMAP, 0x3158, 0, GENMASK(31, 0), 0xA, 0xA, 0x2A}, 245 {ZIP_CORE5_ALG_BITMAP, 0x315C, 0, GENMASK(31, 0), 0xA, 0xA, 0x2A}, 246 {ZIP_CAP_MAX, 0x317c, 0, GENMASK(0, 0), 0x0, 0x0, 0x0} 247 }; 248 249 enum { 250 HZIP_COMP_CORE0, 251 HZIP_COMP_CORE1, 252 HZIP_DECOMP_CORE0, 253 HZIP_DECOMP_CORE1, 254 HZIP_DECOMP_CORE2, 255 HZIP_DECOMP_CORE3, 256 HZIP_DECOMP_CORE4, 257 HZIP_DECOMP_CORE5, 258 }; 259 260 static const u64 core_offsets[] = { 261 [HZIP_COMP_CORE0] = 0x302000, 262 [HZIP_COMP_CORE1] = 0x303000, 263 [HZIP_DECOMP_CORE0] = 0x304000, 264 [HZIP_DECOMP_CORE1] = 0x305000, 265 [HZIP_DECOMP_CORE2] = 0x306000, 266 [HZIP_DECOMP_CORE3] = 0x307000, 267 [HZIP_DECOMP_CORE4] = 0x308000, 268 [HZIP_DECOMP_CORE5] = 0x309000, 269 }; 270 271 static const struct debugfs_reg32 hzip_dfx_regs[] = { 272 {"HZIP_GET_BD_NUM ", 0x00ull}, 273 {"HZIP_GET_RIGHT_BD ", 0x04ull}, 274 {"HZIP_GET_ERROR_BD ", 0x08ull}, 275 {"HZIP_DONE_BD_NUM ", 0x0cull}, 276 {"HZIP_WORK_CYCLE ", 0x10ull}, 277 {"HZIP_IDLE_CYCLE ", 0x18ull}, 278 {"HZIP_MAX_DELAY ", 0x20ull}, 279 {"HZIP_MIN_DELAY ", 0x24ull}, 280 {"HZIP_AVG_DELAY ", 0x28ull}, 281 {"HZIP_MEM_VISIBLE_DATA ", 0x30ull}, 282 {"HZIP_MEM_VISIBLE_ADDR ", 0x34ull}, 283 {"HZIP_CONSUMED_BYTE ", 0x38ull}, 284 {"HZIP_PRODUCED_BYTE ", 0x40ull}, 285 {"HZIP_COMP_INF ", 0x70ull}, 286 {"HZIP_PRE_OUT ", 0x78ull}, 287 {"HZIP_BD_RD ", 0x7cull}, 288 {"HZIP_BD_WR ", 0x80ull}, 289 {"HZIP_GET_BD_AXI_ERR_NUM ", 0x84ull}, 290 {"HZIP_GET_BD_PARSE_ERR_NUM ", 0x88ull}, 291 {"HZIP_ADD_BD_AXI_ERR_NUM ", 0x8cull}, 292 {"HZIP_DECOMP_STF_RELOAD_CURR_ST ", 0x94ull}, 293 {"HZIP_DECOMP_LZ77_CURR_ST ", 0x9cull}, 294 }; 295 296 static const struct debugfs_reg32 hzip_com_dfx_regs[] = { 297 {"HZIP_CLOCK_GATE_CTRL ", 0x301004}, 298 {"HZIP_CORE_INT_RAS_CE_ENB ", 0x301160}, 299 {"HZIP_CORE_INT_RAS_NFE_ENB ", 0x301164}, 300 {"HZIP_CORE_INT_RAS_FE_ENB ", 0x301168}, 301 {"HZIP_UNCOM_ERR_RAS_CTRL ", 0x30116C}, 302 }; 303 304 static const struct debugfs_reg32 hzip_dump_dfx_regs[] = { 305 {"HZIP_GET_BD_NUM ", 0x00ull}, 306 {"HZIP_GET_RIGHT_BD ", 0x04ull}, 307 {"HZIP_GET_ERROR_BD ", 0x08ull}, 308 {"HZIP_DONE_BD_NUM ", 0x0cull}, 309 {"HZIP_MAX_DELAY ", 0x20ull}, 310 }; 311 312 /* define the ZIP's dfx regs region and region length */ 313 static struct dfx_diff_registers hzip_diff_regs[] = { 314 { 315 .reg_offset = HZIP_CORE_DFX_BASE, 316 .reg_len = HZIP_CORE_REGS_BASE_LEN, 317 }, { 318 .reg_offset = HZIP_CORE_DFX_COMP_0, 319 .reg_len = HZIP_CORE_REGS_DFX_LEN, 320 }, { 321 .reg_offset = HZIP_CORE_DFX_COMP_1, 322 .reg_len = HZIP_CORE_REGS_DFX_LEN, 323 }, { 324 .reg_offset = HZIP_CORE_DFX_DECOMP_0, 325 .reg_len = HZIP_CORE_REGS_DFX_LEN, 326 }, { 327 .reg_offset = HZIP_CORE_DFX_DECOMP_1, 328 .reg_len = HZIP_CORE_REGS_DFX_LEN, 329 }, { 330 .reg_offset = HZIP_CORE_DFX_DECOMP_2, 331 .reg_len = HZIP_CORE_REGS_DFX_LEN, 332 }, { 333 .reg_offset = HZIP_CORE_DFX_DECOMP_3, 334 .reg_len = HZIP_CORE_REGS_DFX_LEN, 335 }, { 336 .reg_offset = HZIP_CORE_DFX_DECOMP_4, 337 .reg_len = HZIP_CORE_REGS_DFX_LEN, 338 }, { 339 .reg_offset = HZIP_CORE_DFX_DECOMP_5, 340 .reg_len = HZIP_CORE_REGS_DFX_LEN, 341 }, 342 }; 343 344 static int hzip_diff_regs_show(struct seq_file *s, void *unused) 345 { 346 struct hisi_qm *qm = s->private; 347 348 hisi_qm_acc_diff_regs_dump(qm, s, qm->debug.acc_diff_regs, 349 ARRAY_SIZE(hzip_diff_regs)); 350 351 return 0; 352 } 353 DEFINE_SHOW_ATTRIBUTE(hzip_diff_regs); 354 static const struct kernel_param_ops zip_uacce_mode_ops = { 355 .set = uacce_mode_set, 356 .get = param_get_int, 357 }; 358 359 /* 360 * uacce_mode = 0 means zip only register to crypto, 361 * uacce_mode = 1 means zip both register to crypto and uacce. 362 */ 363 static u32 uacce_mode = UACCE_MODE_NOUACCE; 364 module_param_cb(uacce_mode, &zip_uacce_mode_ops, &uacce_mode, 0444); 365 MODULE_PARM_DESC(uacce_mode, UACCE_MODE_DESC); 366 367 static int pf_q_num_set(const char *val, const struct kernel_param *kp) 368 { 369 return q_num_set(val, kp, PCI_DEVICE_ID_HUAWEI_ZIP_PF); 370 } 371 372 static const struct kernel_param_ops pf_q_num_ops = { 373 .set = pf_q_num_set, 374 .get = param_get_int, 375 }; 376 377 static u32 pf_q_num = HZIP_PF_DEF_Q_NUM; 378 module_param_cb(pf_q_num, &pf_q_num_ops, &pf_q_num, 0444); 379 MODULE_PARM_DESC(pf_q_num, "Number of queues in PF(v1 2-4096, v2 2-1024)"); 380 381 static const struct kernel_param_ops vfs_num_ops = { 382 .set = vfs_num_set, 383 .get = param_get_int, 384 }; 385 386 static u32 vfs_num; 387 module_param_cb(vfs_num, &vfs_num_ops, &vfs_num, 0444); 388 MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63), 0(default)"); 389 390 static const struct pci_device_id hisi_zip_dev_ids[] = { 391 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_ZIP_PF) }, 392 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_ZIP_VF) }, 393 { 0, } 394 }; 395 MODULE_DEVICE_TABLE(pci, hisi_zip_dev_ids); 396 397 int zip_create_qps(struct hisi_qp **qps, int qp_num, int node) 398 { 399 if (node == NUMA_NO_NODE) 400 node = cpu_to_node(smp_processor_id()); 401 402 return hisi_qm_alloc_qps_node(&zip_devices, qp_num, 0, node, qps); 403 } 404 405 bool hisi_zip_alg_support(struct hisi_qm *qm, u32 alg) 406 { 407 u32 cap_val; 408 409 cap_val = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_DRV_ALG_BITMAP, qm->cap_ver); 410 if ((alg & cap_val) == alg) 411 return true; 412 413 return false; 414 } 415 416 static int hisi_zip_set_qm_algs(struct hisi_qm *qm) 417 { 418 struct device *dev = &qm->pdev->dev; 419 char *algs, *ptr; 420 u32 alg_mask; 421 int i; 422 423 if (!qm->use_sva) 424 return 0; 425 426 algs = devm_kzalloc(dev, HZIP_DEV_ALG_MAX_LEN * sizeof(char), GFP_KERNEL); 427 if (!algs) 428 return -ENOMEM; 429 430 alg_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_DEV_ALG_BITMAP, qm->cap_ver); 431 432 for (i = 0; i < ARRAY_SIZE(zip_dev_algs); i++) 433 if (alg_mask & zip_dev_algs[i].alg_msk) 434 strcat(algs, zip_dev_algs[i].algs); 435 436 ptr = strrchr(algs, '\n'); 437 if (ptr) 438 *ptr = '\0'; 439 440 qm->uacce->algs = algs; 441 442 return 0; 443 } 444 445 static void hisi_zip_open_sva_prefetch(struct hisi_qm *qm) 446 { 447 u32 val; 448 int ret; 449 450 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps)) 451 return; 452 453 /* Enable prefetch */ 454 val = readl_relaxed(qm->io_base + HZIP_PREFETCH_CFG); 455 val &= HZIP_PREFETCH_ENABLE; 456 writel(val, qm->io_base + HZIP_PREFETCH_CFG); 457 458 ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_PREFETCH_CFG, 459 val, !(val & HZIP_SVA_PREFETCH_DISABLE), 460 HZIP_DELAY_1_US, HZIP_POLL_TIMEOUT_US); 461 if (ret) 462 pci_err(qm->pdev, "failed to open sva prefetch\n"); 463 } 464 465 static void hisi_zip_close_sva_prefetch(struct hisi_qm *qm) 466 { 467 u32 val; 468 int ret; 469 470 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps)) 471 return; 472 473 val = readl_relaxed(qm->io_base + HZIP_PREFETCH_CFG); 474 val |= HZIP_SVA_PREFETCH_DISABLE; 475 writel(val, qm->io_base + HZIP_PREFETCH_CFG); 476 477 ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_SVA_TRANS, 478 val, !(val & HZIP_SVA_DISABLE_READY), 479 HZIP_DELAY_1_US, HZIP_POLL_TIMEOUT_US); 480 if (ret) 481 pci_err(qm->pdev, "failed to close sva prefetch\n"); 482 } 483 484 static void hisi_zip_enable_clock_gate(struct hisi_qm *qm) 485 { 486 u32 val; 487 488 if (qm->ver < QM_HW_V3) 489 return; 490 491 val = readl(qm->io_base + HZIP_CLOCK_GATE_CTRL); 492 val |= HZIP_CLOCK_GATED_EN; 493 writel(val, qm->io_base + HZIP_CLOCK_GATE_CTRL); 494 495 val = readl(qm->io_base + HZIP_PEH_CFG_AUTO_GATE); 496 val |= HZIP_PEH_CFG_AUTO_GATE_EN; 497 writel(val, qm->io_base + HZIP_PEH_CFG_AUTO_GATE); 498 } 499 500 static int hisi_zip_set_user_domain_and_cache(struct hisi_qm *qm) 501 { 502 void __iomem *base = qm->io_base; 503 u32 dcomp_bm, comp_bm; 504 505 /* qm user domain */ 506 writel(AXUSER_BASE, base + QM_ARUSER_M_CFG_1); 507 writel(ARUSER_M_CFG_ENABLE, base + QM_ARUSER_M_CFG_ENABLE); 508 writel(AXUSER_BASE, base + QM_AWUSER_M_CFG_1); 509 writel(AWUSER_M_CFG_ENABLE, base + QM_AWUSER_M_CFG_ENABLE); 510 writel(WUSER_M_CFG_ENABLE, base + QM_WUSER_M_CFG_ENABLE); 511 512 /* qm cache */ 513 writel(AXI_M_CFG, base + QM_AXI_M_CFG); 514 writel(AXI_M_CFG_ENABLE, base + QM_AXI_M_CFG_ENABLE); 515 516 /* disable FLR triggered by BME(bus master enable) */ 517 writel(PEH_AXUSER_CFG, base + QM_PEH_AXUSER_CFG); 518 writel(PEH_AXUSER_CFG_ENABLE, base + QM_PEH_AXUSER_CFG_ENABLE); 519 520 /* cache */ 521 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_ARCA_CHE_0); 522 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_ARCA_CHE_1); 523 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_AWCA_CHE_0); 524 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_AWCA_CHE_1); 525 526 /* user domain configurations */ 527 writel(AXUSER_BASE, base + HZIP_BD_RUSER_32_63); 528 writel(AXUSER_BASE, base + HZIP_BD_WUSER_32_63); 529 530 if (qm->use_sva && qm->ver == QM_HW_V2) { 531 writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_DATA_RUSER_32_63); 532 writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_DATA_WUSER_32_63); 533 writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_SGL_RUSER_32_63); 534 } else { 535 writel(AXUSER_BASE, base + HZIP_DATA_RUSER_32_63); 536 writel(AXUSER_BASE, base + HZIP_DATA_WUSER_32_63); 537 writel(AXUSER_BASE, base + HZIP_SGL_RUSER_32_63); 538 } 539 540 /* let's open all compression/decompression cores */ 541 dcomp_bm = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 542 ZIP_DECOMP_ENABLE_BITMAP, qm->cap_ver); 543 comp_bm = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 544 ZIP_COMP_ENABLE_BITMAP, qm->cap_ver); 545 writel(HZIP_DECOMP_CHECK_ENABLE | dcomp_bm | comp_bm, base + HZIP_CLOCK_GATE_CTRL); 546 547 /* enable sqc,cqc writeback */ 548 writel(SQC_CACHE_ENABLE | CQC_CACHE_ENABLE | SQC_CACHE_WB_ENABLE | 549 CQC_CACHE_WB_ENABLE | FIELD_PREP(SQC_CACHE_WB_THRD, 1) | 550 FIELD_PREP(CQC_CACHE_WB_THRD, 1), base + QM_CACHE_CTL); 551 552 hisi_zip_enable_clock_gate(qm); 553 554 return 0; 555 } 556 557 static void hisi_zip_master_ooo_ctrl(struct hisi_qm *qm, bool enable) 558 { 559 u32 val1, val2; 560 561 val1 = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 562 if (enable) { 563 val1 |= HZIP_AXI_SHUTDOWN_ENABLE; 564 val2 = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 565 ZIP_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 566 } else { 567 val1 &= ~HZIP_AXI_SHUTDOWN_ENABLE; 568 val2 = 0x0; 569 } 570 571 if (qm->ver > QM_HW_V2) 572 writel(val2, qm->io_base + HZIP_OOO_SHUTDOWN_SEL); 573 574 writel(val1, qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 575 } 576 577 static void hisi_zip_hw_error_enable(struct hisi_qm *qm) 578 { 579 u32 nfe, ce; 580 581 if (qm->ver == QM_HW_V1) { 582 writel(HZIP_CORE_INT_MASK_ALL, 583 qm->io_base + HZIP_CORE_INT_MASK_REG); 584 dev_info(&qm->pdev->dev, "Does not support hw error handle\n"); 585 return; 586 } 587 588 nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_NFE_MASK_CAP, qm->cap_ver); 589 ce = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CE_MASK_CAP, qm->cap_ver); 590 591 /* clear ZIP hw error source if having */ 592 writel(ce | nfe | HZIP_CORE_INT_RAS_FE_ENB_MASK, qm->io_base + HZIP_CORE_INT_SOURCE); 593 594 /* configure error type */ 595 writel(ce, qm->io_base + HZIP_CORE_INT_RAS_CE_ENB); 596 writel(HZIP_CORE_INT_RAS_FE_ENB_MASK, qm->io_base + HZIP_CORE_INT_RAS_FE_ENB); 597 writel(nfe, qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); 598 599 hisi_zip_master_ooo_ctrl(qm, true); 600 601 /* enable ZIP hw error interrupts */ 602 writel(0, qm->io_base + HZIP_CORE_INT_MASK_REG); 603 } 604 605 static void hisi_zip_hw_error_disable(struct hisi_qm *qm) 606 { 607 u32 nfe, ce; 608 609 /* disable ZIP hw error interrupts */ 610 nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_NFE_MASK_CAP, qm->cap_ver); 611 ce = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CE_MASK_CAP, qm->cap_ver); 612 writel(ce | nfe | HZIP_CORE_INT_RAS_FE_ENB_MASK, qm->io_base + HZIP_CORE_INT_MASK_REG); 613 614 hisi_zip_master_ooo_ctrl(qm, false); 615 } 616 617 static inline struct hisi_qm *file_to_qm(struct ctrl_debug_file *file) 618 { 619 struct hisi_zip *hisi_zip = file->ctrl->hisi_zip; 620 621 return &hisi_zip->qm; 622 } 623 624 static u32 clear_enable_read(struct hisi_qm *qm) 625 { 626 return readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) & 627 HZIP_SOFT_CTRL_CNT_CLR_CE_BIT; 628 } 629 630 static int clear_enable_write(struct hisi_qm *qm, u32 val) 631 { 632 u32 tmp; 633 634 if (val != 1 && val != 0) 635 return -EINVAL; 636 637 tmp = (readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) & 638 ~HZIP_SOFT_CTRL_CNT_CLR_CE_BIT) | val; 639 writel(tmp, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE); 640 641 return 0; 642 } 643 644 static ssize_t hisi_zip_ctrl_debug_read(struct file *filp, char __user *buf, 645 size_t count, loff_t *pos) 646 { 647 struct ctrl_debug_file *file = filp->private_data; 648 struct hisi_qm *qm = file_to_qm(file); 649 char tbuf[HZIP_BUF_SIZE]; 650 u32 val; 651 int ret; 652 653 ret = hisi_qm_get_dfx_access(qm); 654 if (ret) 655 return ret; 656 657 spin_lock_irq(&file->lock); 658 switch (file->index) { 659 case HZIP_CLEAR_ENABLE: 660 val = clear_enable_read(qm); 661 break; 662 default: 663 goto err_input; 664 } 665 spin_unlock_irq(&file->lock); 666 667 hisi_qm_put_dfx_access(qm); 668 ret = scnprintf(tbuf, sizeof(tbuf), "%u\n", val); 669 return simple_read_from_buffer(buf, count, pos, tbuf, ret); 670 671 err_input: 672 spin_unlock_irq(&file->lock); 673 hisi_qm_put_dfx_access(qm); 674 return -EINVAL; 675 } 676 677 static ssize_t hisi_zip_ctrl_debug_write(struct file *filp, 678 const char __user *buf, 679 size_t count, loff_t *pos) 680 { 681 struct ctrl_debug_file *file = filp->private_data; 682 struct hisi_qm *qm = file_to_qm(file); 683 char tbuf[HZIP_BUF_SIZE]; 684 unsigned long val; 685 int len, ret; 686 687 if (*pos != 0) 688 return 0; 689 690 if (count >= HZIP_BUF_SIZE) 691 return -ENOSPC; 692 693 len = simple_write_to_buffer(tbuf, HZIP_BUF_SIZE - 1, pos, buf, count); 694 if (len < 0) 695 return len; 696 697 tbuf[len] = '\0'; 698 ret = kstrtoul(tbuf, 0, &val); 699 if (ret) 700 return ret; 701 702 ret = hisi_qm_get_dfx_access(qm); 703 if (ret) 704 return ret; 705 706 spin_lock_irq(&file->lock); 707 switch (file->index) { 708 case HZIP_CLEAR_ENABLE: 709 ret = clear_enable_write(qm, val); 710 if (ret) 711 goto err_input; 712 break; 713 default: 714 ret = -EINVAL; 715 goto err_input; 716 } 717 718 ret = count; 719 720 err_input: 721 spin_unlock_irq(&file->lock); 722 hisi_qm_put_dfx_access(qm); 723 return ret; 724 } 725 726 static const struct file_operations ctrl_debug_fops = { 727 .owner = THIS_MODULE, 728 .open = simple_open, 729 .read = hisi_zip_ctrl_debug_read, 730 .write = hisi_zip_ctrl_debug_write, 731 }; 732 733 static int zip_debugfs_atomic64_set(void *data, u64 val) 734 { 735 if (val) 736 return -EINVAL; 737 738 atomic64_set((atomic64_t *)data, 0); 739 740 return 0; 741 } 742 743 static int zip_debugfs_atomic64_get(void *data, u64 *val) 744 { 745 *val = atomic64_read((atomic64_t *)data); 746 747 return 0; 748 } 749 750 DEFINE_DEBUGFS_ATTRIBUTE(zip_atomic64_ops, zip_debugfs_atomic64_get, 751 zip_debugfs_atomic64_set, "%llu\n"); 752 753 static int hisi_zip_regs_show(struct seq_file *s, void *unused) 754 { 755 hisi_qm_regs_dump(s, s->private); 756 757 return 0; 758 } 759 760 DEFINE_SHOW_ATTRIBUTE(hisi_zip_regs); 761 762 static int hisi_zip_core_debug_init(struct hisi_qm *qm) 763 { 764 u32 zip_core_num, zip_comp_core_num; 765 struct device *dev = &qm->pdev->dev; 766 struct debugfs_regset32 *regset; 767 struct dentry *tmp_d; 768 char buf[HZIP_BUF_SIZE]; 769 int i; 770 771 zip_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CORE_NUM_CAP, qm->cap_ver); 772 zip_comp_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CLUSTER_COMP_NUM_CAP, 773 qm->cap_ver); 774 775 for (i = 0; i < zip_core_num; i++) { 776 if (i < zip_comp_core_num) 777 scnprintf(buf, sizeof(buf), "comp_core%d", i); 778 else 779 scnprintf(buf, sizeof(buf), "decomp_core%d", 780 i - zip_comp_core_num); 781 782 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); 783 if (!regset) 784 return -ENOENT; 785 786 regset->regs = hzip_dfx_regs; 787 regset->nregs = ARRAY_SIZE(hzip_dfx_regs); 788 regset->base = qm->io_base + core_offsets[i]; 789 regset->dev = dev; 790 791 tmp_d = debugfs_create_dir(buf, qm->debug.debug_root); 792 debugfs_create_file("regs", 0444, tmp_d, regset, 793 &hisi_zip_regs_fops); 794 } 795 796 return 0; 797 } 798 799 static void hisi_zip_dfx_debug_init(struct hisi_qm *qm) 800 { 801 struct dfx_diff_registers *hzip_regs = qm->debug.acc_diff_regs; 802 struct hisi_zip *zip = container_of(qm, struct hisi_zip, qm); 803 struct hisi_zip_dfx *dfx = &zip->dfx; 804 struct dentry *tmp_dir; 805 void *data; 806 int i; 807 808 tmp_dir = debugfs_create_dir("zip_dfx", qm->debug.debug_root); 809 for (i = 0; i < ARRAY_SIZE(zip_dfx_files); i++) { 810 data = (atomic64_t *)((uintptr_t)dfx + zip_dfx_files[i].offset); 811 debugfs_create_file(zip_dfx_files[i].name, 812 0644, tmp_dir, data, 813 &zip_atomic64_ops); 814 } 815 816 if (qm->fun_type == QM_HW_PF && hzip_regs) 817 debugfs_create_file("diff_regs", 0444, tmp_dir, 818 qm, &hzip_diff_regs_fops); 819 } 820 821 static int hisi_zip_ctrl_debug_init(struct hisi_qm *qm) 822 { 823 struct hisi_zip *zip = container_of(qm, struct hisi_zip, qm); 824 int i; 825 826 for (i = HZIP_CLEAR_ENABLE; i < HZIP_DEBUG_FILE_NUM; i++) { 827 spin_lock_init(&zip->ctrl->files[i].lock); 828 zip->ctrl->files[i].ctrl = zip->ctrl; 829 zip->ctrl->files[i].index = i; 830 831 debugfs_create_file(ctrl_debug_file_name[i], 0600, 832 qm->debug.debug_root, 833 zip->ctrl->files + i, 834 &ctrl_debug_fops); 835 } 836 837 return hisi_zip_core_debug_init(qm); 838 } 839 840 static int hisi_zip_debugfs_init(struct hisi_qm *qm) 841 { 842 struct device *dev = &qm->pdev->dev; 843 struct dentry *dev_d; 844 int ret; 845 846 dev_d = debugfs_create_dir(dev_name(dev), hzip_debugfs_root); 847 848 qm->debug.sqe_mask_offset = HZIP_SQE_MASK_OFFSET; 849 qm->debug.sqe_mask_len = HZIP_SQE_MASK_LEN; 850 qm->debug.debug_root = dev_d; 851 ret = hisi_qm_regs_debugfs_init(qm, hzip_diff_regs, ARRAY_SIZE(hzip_diff_regs)); 852 if (ret) { 853 dev_warn(dev, "Failed to init ZIP diff regs!\n"); 854 goto debugfs_remove; 855 } 856 857 hisi_qm_debug_init(qm); 858 859 if (qm->fun_type == QM_HW_PF) { 860 ret = hisi_zip_ctrl_debug_init(qm); 861 if (ret) 862 goto failed_to_create; 863 } 864 865 hisi_zip_dfx_debug_init(qm); 866 867 return 0; 868 869 failed_to_create: 870 hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(hzip_diff_regs)); 871 debugfs_remove: 872 debugfs_remove_recursive(hzip_debugfs_root); 873 return ret; 874 } 875 876 /* hisi_zip_debug_regs_clear() - clear the zip debug regs */ 877 static void hisi_zip_debug_regs_clear(struct hisi_qm *qm) 878 { 879 int i, j; 880 881 /* enable register read_clear bit */ 882 writel(HZIP_RD_CNT_CLR_CE_EN, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE); 883 for (i = 0; i < ARRAY_SIZE(core_offsets); i++) 884 for (j = 0; j < ARRAY_SIZE(hzip_dfx_regs); j++) 885 readl(qm->io_base + core_offsets[i] + 886 hzip_dfx_regs[j].offset); 887 888 /* disable register read_clear bit */ 889 writel(0x0, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE); 890 891 hisi_qm_debug_regs_clear(qm); 892 } 893 894 static void hisi_zip_debugfs_exit(struct hisi_qm *qm) 895 { 896 hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(hzip_diff_regs)); 897 898 debugfs_remove_recursive(qm->debug.debug_root); 899 900 if (qm->fun_type == QM_HW_PF) { 901 hisi_zip_debug_regs_clear(qm); 902 qm->debug.curr_qm_qp_num = 0; 903 } 904 } 905 906 static int hisi_zip_show_last_regs_init(struct hisi_qm *qm) 907 { 908 int core_dfx_regs_num = ARRAY_SIZE(hzip_dump_dfx_regs); 909 int com_dfx_regs_num = ARRAY_SIZE(hzip_com_dfx_regs); 910 struct qm_debug *debug = &qm->debug; 911 void __iomem *io_base; 912 u32 zip_core_num; 913 int i, j, idx; 914 915 zip_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CORE_NUM_CAP, qm->cap_ver); 916 917 debug->last_words = kcalloc(core_dfx_regs_num * zip_core_num + com_dfx_regs_num, 918 sizeof(unsigned int), GFP_KERNEL); 919 if (!debug->last_words) 920 return -ENOMEM; 921 922 for (i = 0; i < com_dfx_regs_num; i++) { 923 io_base = qm->io_base + hzip_com_dfx_regs[i].offset; 924 debug->last_words[i] = readl_relaxed(io_base); 925 } 926 927 for (i = 0; i < zip_core_num; i++) { 928 io_base = qm->io_base + core_offsets[i]; 929 for (j = 0; j < core_dfx_regs_num; j++) { 930 idx = com_dfx_regs_num + i * core_dfx_regs_num + j; 931 debug->last_words[idx] = readl_relaxed( 932 io_base + hzip_dump_dfx_regs[j].offset); 933 } 934 } 935 936 return 0; 937 } 938 939 static void hisi_zip_show_last_regs_uninit(struct hisi_qm *qm) 940 { 941 struct qm_debug *debug = &qm->debug; 942 943 if (qm->fun_type == QM_HW_VF || !debug->last_words) 944 return; 945 946 kfree(debug->last_words); 947 debug->last_words = NULL; 948 } 949 950 static void hisi_zip_show_last_dfx_regs(struct hisi_qm *qm) 951 { 952 int core_dfx_regs_num = ARRAY_SIZE(hzip_dump_dfx_regs); 953 int com_dfx_regs_num = ARRAY_SIZE(hzip_com_dfx_regs); 954 u32 zip_core_num, zip_comp_core_num; 955 struct qm_debug *debug = &qm->debug; 956 char buf[HZIP_BUF_SIZE]; 957 void __iomem *base; 958 int i, j, idx; 959 u32 val; 960 961 if (qm->fun_type == QM_HW_VF || !debug->last_words) 962 return; 963 964 for (i = 0; i < com_dfx_regs_num; i++) { 965 val = readl_relaxed(qm->io_base + hzip_com_dfx_regs[i].offset); 966 if (debug->last_words[i] != val) 967 pci_info(qm->pdev, "com_dfx: %s \t= 0x%08x => 0x%08x\n", 968 hzip_com_dfx_regs[i].name, debug->last_words[i], val); 969 } 970 971 zip_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CORE_NUM_CAP, qm->cap_ver); 972 zip_comp_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CLUSTER_COMP_NUM_CAP, 973 qm->cap_ver); 974 for (i = 0; i < zip_core_num; i++) { 975 if (i < zip_comp_core_num) 976 scnprintf(buf, sizeof(buf), "Comp_core-%d", i); 977 else 978 scnprintf(buf, sizeof(buf), "Decomp_core-%d", 979 i - zip_comp_core_num); 980 base = qm->io_base + core_offsets[i]; 981 982 pci_info(qm->pdev, "==>%s:\n", buf); 983 /* dump last word for dfx regs during control resetting */ 984 for (j = 0; j < core_dfx_regs_num; j++) { 985 idx = com_dfx_regs_num + i * core_dfx_regs_num + j; 986 val = readl_relaxed(base + hzip_dump_dfx_regs[j].offset); 987 if (debug->last_words[idx] != val) 988 pci_info(qm->pdev, "%s \t= 0x%08x => 0x%08x\n", 989 hzip_dump_dfx_regs[j].name, 990 debug->last_words[idx], val); 991 } 992 } 993 } 994 995 static void hisi_zip_log_hw_error(struct hisi_qm *qm, u32 err_sts) 996 { 997 const struct hisi_zip_hw_error *err = zip_hw_error; 998 struct device *dev = &qm->pdev->dev; 999 u32 err_val; 1000 1001 while (err->msg) { 1002 if (err->int_msk & err_sts) { 1003 dev_err(dev, "%s [error status=0x%x] found\n", 1004 err->msg, err->int_msk); 1005 1006 if (err->int_msk & HZIP_CORE_INT_STATUS_M_ECC) { 1007 err_val = readl(qm->io_base + 1008 HZIP_CORE_SRAM_ECC_ERR_INFO); 1009 dev_err(dev, "hisi-zip multi ecc sram num=0x%x\n", 1010 ((err_val >> 1011 HZIP_SRAM_ECC_ERR_NUM_SHIFT) & 0xFF)); 1012 } 1013 } 1014 err++; 1015 } 1016 } 1017 1018 static u32 hisi_zip_get_hw_err_status(struct hisi_qm *qm) 1019 { 1020 return readl(qm->io_base + HZIP_CORE_INT_STATUS); 1021 } 1022 1023 static void hisi_zip_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts) 1024 { 1025 u32 nfe; 1026 1027 writel(err_sts, qm->io_base + HZIP_CORE_INT_SOURCE); 1028 nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_NFE_MASK_CAP, qm->cap_ver); 1029 writel(nfe, qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); 1030 } 1031 1032 static void hisi_zip_open_axi_master_ooo(struct hisi_qm *qm) 1033 { 1034 u32 val; 1035 1036 val = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 1037 1038 writel(val & ~HZIP_AXI_SHUTDOWN_ENABLE, 1039 qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 1040 1041 writel(val | HZIP_AXI_SHUTDOWN_ENABLE, 1042 qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 1043 } 1044 1045 static void hisi_zip_close_axi_master_ooo(struct hisi_qm *qm) 1046 { 1047 u32 nfe_enb; 1048 1049 /* Disable ECC Mbit error report. */ 1050 nfe_enb = readl(qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); 1051 writel(nfe_enb & ~HZIP_CORE_INT_STATUS_M_ECC, 1052 qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); 1053 1054 /* Inject zip ECC Mbit error to block master ooo. */ 1055 writel(HZIP_CORE_INT_STATUS_M_ECC, 1056 qm->io_base + HZIP_CORE_INT_SET); 1057 } 1058 1059 static void hisi_zip_err_info_init(struct hisi_qm *qm) 1060 { 1061 struct hisi_qm_err_info *err_info = &qm->err_info; 1062 1063 err_info->fe = HZIP_CORE_INT_RAS_FE_ENB_MASK; 1064 err_info->ce = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_QM_CE_MASK_CAP, qm->cap_ver); 1065 err_info->nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 1066 ZIP_QM_NFE_MASK_CAP, qm->cap_ver); 1067 err_info->ecc_2bits_mask = HZIP_CORE_INT_STATUS_M_ECC; 1068 err_info->qm_shutdown_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 1069 ZIP_QM_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 1070 err_info->dev_shutdown_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 1071 ZIP_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 1072 err_info->qm_reset_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 1073 ZIP_QM_RESET_MASK_CAP, qm->cap_ver); 1074 err_info->dev_reset_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 1075 ZIP_RESET_MASK_CAP, qm->cap_ver); 1076 err_info->msi_wr_port = HZIP_WR_PORT; 1077 err_info->acpi_rst = "ZRST"; 1078 } 1079 1080 static const struct hisi_qm_err_ini hisi_zip_err_ini = { 1081 .hw_init = hisi_zip_set_user_domain_and_cache, 1082 .hw_err_enable = hisi_zip_hw_error_enable, 1083 .hw_err_disable = hisi_zip_hw_error_disable, 1084 .get_dev_hw_err_status = hisi_zip_get_hw_err_status, 1085 .clear_dev_hw_err_status = hisi_zip_clear_hw_err_status, 1086 .log_dev_hw_err = hisi_zip_log_hw_error, 1087 .open_axi_master_ooo = hisi_zip_open_axi_master_ooo, 1088 .close_axi_master_ooo = hisi_zip_close_axi_master_ooo, 1089 .open_sva_prefetch = hisi_zip_open_sva_prefetch, 1090 .close_sva_prefetch = hisi_zip_close_sva_prefetch, 1091 .show_last_dfx_regs = hisi_zip_show_last_dfx_regs, 1092 .err_info_init = hisi_zip_err_info_init, 1093 }; 1094 1095 static int hisi_zip_pf_probe_init(struct hisi_zip *hisi_zip) 1096 { 1097 struct hisi_qm *qm = &hisi_zip->qm; 1098 struct hisi_zip_ctrl *ctrl; 1099 int ret; 1100 1101 ctrl = devm_kzalloc(&qm->pdev->dev, sizeof(*ctrl), GFP_KERNEL); 1102 if (!ctrl) 1103 return -ENOMEM; 1104 1105 hisi_zip->ctrl = ctrl; 1106 ctrl->hisi_zip = hisi_zip; 1107 qm->err_ini = &hisi_zip_err_ini; 1108 qm->err_ini->err_info_init(qm); 1109 1110 ret = hisi_zip_set_user_domain_and_cache(qm); 1111 if (ret) 1112 return ret; 1113 1114 hisi_zip_open_sva_prefetch(qm); 1115 hisi_qm_dev_err_init(qm); 1116 hisi_zip_debug_regs_clear(qm); 1117 1118 ret = hisi_zip_show_last_regs_init(qm); 1119 if (ret) 1120 pci_err(qm->pdev, "Failed to init last word regs!\n"); 1121 1122 return ret; 1123 } 1124 1125 static int hisi_zip_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) 1126 { 1127 int ret; 1128 1129 qm->pdev = pdev; 1130 qm->ver = pdev->revision; 1131 qm->mode = uacce_mode; 1132 qm->sqe_size = HZIP_SQE_SIZE; 1133 qm->dev_name = hisi_zip_name; 1134 1135 qm->fun_type = (pdev->device == PCI_DEVICE_ID_HUAWEI_ZIP_PF) ? 1136 QM_HW_PF : QM_HW_VF; 1137 if (qm->fun_type == QM_HW_PF) { 1138 qm->qp_base = HZIP_PF_DEF_Q_BASE; 1139 qm->qp_num = pf_q_num; 1140 qm->debug.curr_qm_qp_num = pf_q_num; 1141 qm->qm_list = &zip_devices; 1142 } else if (qm->fun_type == QM_HW_VF && qm->ver == QM_HW_V1) { 1143 /* 1144 * have no way to get qm configure in VM in v1 hardware, 1145 * so currently force PF to uses HZIP_PF_DEF_Q_NUM, and force 1146 * to trigger only one VF in v1 hardware. 1147 * 1148 * v2 hardware has no such problem. 1149 */ 1150 qm->qp_base = HZIP_PF_DEF_Q_NUM; 1151 qm->qp_num = HZIP_QUEUE_NUM_V1 - HZIP_PF_DEF_Q_NUM; 1152 } 1153 1154 ret = hisi_qm_init(qm); 1155 if (ret) { 1156 pci_err(qm->pdev, "Failed to init zip qm configures!\n"); 1157 return ret; 1158 } 1159 1160 ret = hisi_zip_set_qm_algs(qm); 1161 if (ret) { 1162 pci_err(qm->pdev, "Failed to set zip algs!\n"); 1163 hisi_qm_uninit(qm); 1164 } 1165 1166 return ret; 1167 } 1168 1169 static void hisi_zip_qm_uninit(struct hisi_qm *qm) 1170 { 1171 hisi_qm_uninit(qm); 1172 } 1173 1174 static int hisi_zip_probe_init(struct hisi_zip *hisi_zip) 1175 { 1176 u32 type_rate = HZIP_SHAPER_RATE_COMPRESS; 1177 struct hisi_qm *qm = &hisi_zip->qm; 1178 int ret; 1179 1180 if (qm->fun_type == QM_HW_PF) { 1181 ret = hisi_zip_pf_probe_init(hisi_zip); 1182 if (ret) 1183 return ret; 1184 /* enable shaper type 0 */ 1185 if (qm->ver >= QM_HW_V3) { 1186 type_rate |= QM_SHAPER_ENABLE; 1187 1188 /* ZIP need to enable shaper type 1 */ 1189 type_rate |= HZIP_SHAPER_RATE_DECOMPRESS << QM_SHAPER_TYPE1_OFFSET; 1190 qm->type_rate = type_rate; 1191 } 1192 } 1193 1194 return 0; 1195 } 1196 1197 static int hisi_zip_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1198 { 1199 struct hisi_zip *hisi_zip; 1200 struct hisi_qm *qm; 1201 int ret; 1202 1203 hisi_zip = devm_kzalloc(&pdev->dev, sizeof(*hisi_zip), GFP_KERNEL); 1204 if (!hisi_zip) 1205 return -ENOMEM; 1206 1207 qm = &hisi_zip->qm; 1208 1209 ret = hisi_zip_qm_init(qm, pdev); 1210 if (ret) { 1211 pci_err(pdev, "Failed to init ZIP QM (%d)!\n", ret); 1212 return ret; 1213 } 1214 1215 ret = hisi_zip_probe_init(hisi_zip); 1216 if (ret) { 1217 pci_err(pdev, "Failed to probe (%d)!\n", ret); 1218 goto err_qm_uninit; 1219 } 1220 1221 ret = hisi_qm_start(qm); 1222 if (ret) 1223 goto err_dev_err_uninit; 1224 1225 ret = hisi_zip_debugfs_init(qm); 1226 if (ret) 1227 pci_err(pdev, "failed to init debugfs (%d)!\n", ret); 1228 1229 ret = hisi_qm_alg_register(qm, &zip_devices); 1230 if (ret < 0) { 1231 pci_err(pdev, "failed to register driver to crypto!\n"); 1232 goto err_qm_stop; 1233 } 1234 1235 if (qm->uacce) { 1236 ret = uacce_register(qm->uacce); 1237 if (ret) { 1238 pci_err(pdev, "failed to register uacce (%d)!\n", ret); 1239 goto err_qm_alg_unregister; 1240 } 1241 } 1242 1243 if (qm->fun_type == QM_HW_PF && vfs_num > 0) { 1244 ret = hisi_qm_sriov_enable(pdev, vfs_num); 1245 if (ret < 0) 1246 goto err_qm_alg_unregister; 1247 } 1248 1249 hisi_qm_pm_init(qm); 1250 1251 return 0; 1252 1253 err_qm_alg_unregister: 1254 hisi_qm_alg_unregister(qm, &zip_devices); 1255 1256 err_qm_stop: 1257 hisi_zip_debugfs_exit(qm); 1258 hisi_qm_stop(qm, QM_NORMAL); 1259 1260 err_dev_err_uninit: 1261 hisi_zip_show_last_regs_uninit(qm); 1262 hisi_qm_dev_err_uninit(qm); 1263 1264 err_qm_uninit: 1265 hisi_zip_qm_uninit(qm); 1266 1267 return ret; 1268 } 1269 1270 static void hisi_zip_remove(struct pci_dev *pdev) 1271 { 1272 struct hisi_qm *qm = pci_get_drvdata(pdev); 1273 1274 hisi_qm_pm_uninit(qm); 1275 hisi_qm_wait_task_finish(qm, &zip_devices); 1276 hisi_qm_alg_unregister(qm, &zip_devices); 1277 1278 if (qm->fun_type == QM_HW_PF && qm->vfs_num) 1279 hisi_qm_sriov_disable(pdev, true); 1280 1281 hisi_zip_debugfs_exit(qm); 1282 hisi_qm_stop(qm, QM_NORMAL); 1283 hisi_zip_show_last_regs_uninit(qm); 1284 hisi_qm_dev_err_uninit(qm); 1285 hisi_zip_qm_uninit(qm); 1286 } 1287 1288 static const struct dev_pm_ops hisi_zip_pm_ops = { 1289 SET_RUNTIME_PM_OPS(hisi_qm_suspend, hisi_qm_resume, NULL) 1290 }; 1291 1292 static const struct pci_error_handlers hisi_zip_err_handler = { 1293 .error_detected = hisi_qm_dev_err_detected, 1294 .slot_reset = hisi_qm_dev_slot_reset, 1295 .reset_prepare = hisi_qm_reset_prepare, 1296 .reset_done = hisi_qm_reset_done, 1297 }; 1298 1299 static struct pci_driver hisi_zip_pci_driver = { 1300 .name = "hisi_zip", 1301 .id_table = hisi_zip_dev_ids, 1302 .probe = hisi_zip_probe, 1303 .remove = hisi_zip_remove, 1304 .sriov_configure = IS_ENABLED(CONFIG_PCI_IOV) ? 1305 hisi_qm_sriov_configure : NULL, 1306 .err_handler = &hisi_zip_err_handler, 1307 .shutdown = hisi_qm_dev_shutdown, 1308 .driver.pm = &hisi_zip_pm_ops, 1309 }; 1310 1311 struct pci_driver *hisi_zip_get_pf_driver(void) 1312 { 1313 return &hisi_zip_pci_driver; 1314 } 1315 EXPORT_SYMBOL_GPL(hisi_zip_get_pf_driver); 1316 1317 static void hisi_zip_register_debugfs(void) 1318 { 1319 if (!debugfs_initialized()) 1320 return; 1321 1322 hzip_debugfs_root = debugfs_create_dir("hisi_zip", NULL); 1323 } 1324 1325 static void hisi_zip_unregister_debugfs(void) 1326 { 1327 debugfs_remove_recursive(hzip_debugfs_root); 1328 } 1329 1330 static int __init hisi_zip_init(void) 1331 { 1332 int ret; 1333 1334 hisi_qm_init_list(&zip_devices); 1335 hisi_zip_register_debugfs(); 1336 1337 ret = pci_register_driver(&hisi_zip_pci_driver); 1338 if (ret < 0) { 1339 hisi_zip_unregister_debugfs(); 1340 pr_err("Failed to register pci driver.\n"); 1341 } 1342 1343 return ret; 1344 } 1345 1346 static void __exit hisi_zip_exit(void) 1347 { 1348 pci_unregister_driver(&hisi_zip_pci_driver); 1349 hisi_zip_unregister_debugfs(); 1350 } 1351 1352 module_init(hisi_zip_init); 1353 module_exit(hisi_zip_exit); 1354 1355 MODULE_LICENSE("GPL v2"); 1356 MODULE_AUTHOR("Zhou Wang <wangzhou1@hisilicon.com>"); 1357 MODULE_DESCRIPTION("Driver for HiSilicon ZIP accelerator"); 1358