1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2019 HiSilicon Limited. */ 3 #include <linux/acpi.h> 4 #include <linux/bitops.h> 5 #include <linux/debugfs.h> 6 #include <linux/init.h> 7 #include <linux/io.h> 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/pci.h> 11 #include <linux/pm_runtime.h> 12 #include <linux/seq_file.h> 13 #include <linux/topology.h> 14 #include <linux/uacce.h> 15 #include "zip.h" 16 17 #define CAP_FILE_PERMISSION 0444 18 #define PCI_DEVICE_ID_HUAWEI_ZIP_PF 0xa250 19 20 #define HZIP_QUEUE_NUM_V1 4096 21 22 #define HZIP_CLOCK_GATE_CTRL 0x301004 23 #define HZIP_DECOMP_CHECK_ENABLE BIT(16) 24 #define HZIP_FSM_MAX_CNT 0x301008 25 26 #define HZIP_PORT_ARCA_CHE_0 0x301040 27 #define HZIP_PORT_ARCA_CHE_1 0x301044 28 #define HZIP_PORT_AWCA_CHE_0 0x301060 29 #define HZIP_PORT_AWCA_CHE_1 0x301064 30 #define HZIP_CACHE_ALL_EN 0xffffffff 31 32 #define HZIP_BD_RUSER_32_63 0x301110 33 #define HZIP_SGL_RUSER_32_63 0x30111c 34 #define HZIP_DATA_RUSER_32_63 0x301128 35 #define HZIP_DATA_WUSER_32_63 0x301134 36 #define HZIP_BD_WUSER_32_63 0x301140 37 38 #define HZIP_QM_IDEL_STATUS 0x3040e4 39 40 #define HZIP_CORE_DFX_BASE 0x301000 41 #define HZIP_CORE_DFX_DECOMP_BASE 0x304000 42 #define HZIP_CORE_DFX_COMP_0 0x302000 43 #define HZIP_CORE_DFX_COMP_1 0x303000 44 #define HZIP_CORE_DFX_DECOMP_0 0x304000 45 #define HZIP_CORE_DFX_DECOMP_1 0x305000 46 #define HZIP_CORE_DFX_DECOMP_2 0x306000 47 #define HZIP_CORE_DFX_DECOMP_3 0x307000 48 #define HZIP_CORE_DFX_DECOMP_4 0x308000 49 #define HZIP_CORE_DFX_DECOMP_5 0x309000 50 #define HZIP_CORE_REGS_BASE_LEN 0xB0 51 #define HZIP_CORE_REGS_DFX_LEN 0x28 52 #define HZIP_CORE_ADDR_INTRVL 0x1000 53 54 #define HZIP_CORE_INT_SOURCE 0x3010A0 55 #define HZIP_CORE_INT_MASK_REG 0x3010A4 56 #define HZIP_CORE_INT_SET 0x3010A8 57 #define HZIP_CORE_INT_STATUS 0x3010AC 58 #define HZIP_CORE_INT_STATUS_M_ECC BIT(1) 59 #define HZIP_CORE_SRAM_ECC_ERR_INFO 0x301148 60 #define HZIP_CORE_INT_RAS_CE_ENB 0x301160 61 #define HZIP_CORE_INT_RAS_NFE_ENB 0x301164 62 #define HZIP_CORE_INT_RAS_FE_ENB 0x301168 63 #define HZIP_CORE_INT_RAS_FE_ENB_MASK 0x0 64 #define HZIP_OOO_SHUTDOWN_SEL 0x30120C 65 #define HZIP_SRAM_ECC_ERR_NUM_SHIFT 16 66 #define HZIP_SRAM_ECC_ERR_ADDR_SHIFT 24 67 #define HZIP_CORE_INT_MASK_ALL GENMASK(12, 0) 68 #define HZIP_SQE_SIZE 128 69 #define HZIP_PF_DEF_Q_NUM 64 70 #define HZIP_PF_DEF_Q_BASE 0 71 #define HZIP_CTX_Q_NUM_DEF 2 72 73 #define HZIP_SOFT_CTRL_CNT_CLR_CE 0x301000 74 #define HZIP_SOFT_CTRL_CNT_CLR_CE_BIT BIT(0) 75 #define HZIP_SOFT_CTRL_ZIP_CONTROL 0x30100C 76 #define HZIP_AXI_SHUTDOWN_ENABLE BIT(14) 77 #define HZIP_WR_PORT BIT(11) 78 79 #define HZIP_ALG_ZLIB_BIT GENMASK(1, 0) 80 #define HZIP_ALG_GZIP_BIT GENMASK(3, 2) 81 #define HZIP_ALG_DEFLATE_BIT GENMASK(5, 4) 82 #define HZIP_ALG_LZ77_BIT GENMASK(7, 6) 83 84 #define HZIP_BUF_SIZE 22 85 #define HZIP_SQE_MASK_OFFSET 64 86 #define HZIP_SQE_MASK_LEN 48 87 88 #define HZIP_CNT_CLR_CE_EN BIT(0) 89 #define HZIP_RO_CNT_CLR_CE_EN BIT(2) 90 #define HZIP_RD_CNT_CLR_CE_EN (HZIP_CNT_CLR_CE_EN | \ 91 HZIP_RO_CNT_CLR_CE_EN) 92 93 #define HZIP_PREFETCH_CFG 0x3011B0 94 #define HZIP_SVA_TRANS 0x3011C4 95 #define HZIP_PREFETCH_ENABLE (~(BIT(26) | BIT(17) | BIT(0))) 96 #define HZIP_SVA_PREFETCH_DISABLE BIT(26) 97 #define HZIP_SVA_DISABLE_READY (BIT(26) | BIT(30)) 98 #define HZIP_SVA_PREFETCH_NUM GENMASK(18, 16) 99 #define HZIP_SVA_STALL_NUM GENMASK(15, 0) 100 #define HZIP_SHAPER_RATE_COMPRESS 750 101 #define HZIP_SHAPER_RATE_DECOMPRESS 140 102 #define HZIP_DELAY_1_US 1 103 #define HZIP_POLL_TIMEOUT_US 1000 104 #define HZIP_WAIT_SVA_READY 500000 105 #define HZIP_READ_SVA_STATUS_TIMES 3 106 #define HZIP_WAIT_US_MIN 10 107 #define HZIP_WAIT_US_MAX 20 108 109 /* clock gating */ 110 #define HZIP_PEH_CFG_AUTO_GATE 0x3011A8 111 #define HZIP_PEH_CFG_AUTO_GATE_EN BIT(0) 112 #define HZIP_CORE_GATED_EN GENMASK(15, 8) 113 #define HZIP_CORE_GATED_OOO_EN BIT(29) 114 #define HZIP_CLOCK_GATED_EN (HZIP_CORE_GATED_EN | \ 115 HZIP_CORE_GATED_OOO_EN) 116 117 /* zip comp high performance */ 118 #define HZIP_HIGH_PERF_OFFSET 0x301208 119 120 #define HZIP_LIT_LEN_EN_OFFSET 0x301204 121 #define HZIP_LIT_LEN_EN_EN BIT(4) 122 123 enum { 124 HZIP_HIGH_COMP_RATE, 125 HZIP_HIGH_COMP_PERF, 126 }; 127 128 static const char hisi_zip_name[] = "hisi_zip"; 129 static struct dentry *hzip_debugfs_root; 130 131 struct hisi_zip_hw_error { 132 u32 int_msk; 133 const char *msg; 134 }; 135 136 struct zip_dfx_item { 137 const char *name; 138 u32 offset; 139 }; 140 141 static const struct qm_dev_alg zip_dev_algs[] = { { 142 .alg_msk = HZIP_ALG_ZLIB_BIT, 143 .alg = "zlib\n", 144 }, { 145 .alg_msk = HZIP_ALG_GZIP_BIT, 146 .alg = "gzip\n", 147 }, { 148 .alg_msk = HZIP_ALG_DEFLATE_BIT, 149 .alg = "deflate\n", 150 }, { 151 .alg_msk = HZIP_ALG_LZ77_BIT, 152 .alg = "lz77_zstd\n", 153 }, 154 }; 155 156 static struct hisi_qm_list zip_devices = { 157 .register_to_crypto = hisi_zip_register_to_crypto, 158 .unregister_from_crypto = hisi_zip_unregister_from_crypto, 159 }; 160 161 static struct zip_dfx_item zip_dfx_files[] = { 162 {"send_cnt", offsetof(struct hisi_zip_dfx, send_cnt)}, 163 {"recv_cnt", offsetof(struct hisi_zip_dfx, recv_cnt)}, 164 {"send_busy_cnt", offsetof(struct hisi_zip_dfx, send_busy_cnt)}, 165 {"err_bd_cnt", offsetof(struct hisi_zip_dfx, err_bd_cnt)}, 166 }; 167 168 static const struct hisi_zip_hw_error zip_hw_error[] = { 169 { .int_msk = BIT(0), .msg = "zip_ecc_1bitt_err" }, 170 { .int_msk = BIT(1), .msg = "zip_ecc_2bit_err" }, 171 { .int_msk = BIT(2), .msg = "zip_axi_rresp_err" }, 172 { .int_msk = BIT(3), .msg = "zip_axi_bresp_err" }, 173 { .int_msk = BIT(4), .msg = "zip_src_addr_parse_err" }, 174 { .int_msk = BIT(5), .msg = "zip_dst_addr_parse_err" }, 175 { .int_msk = BIT(6), .msg = "zip_pre_in_addr_err" }, 176 { .int_msk = BIT(7), .msg = "zip_pre_in_data_err" }, 177 { .int_msk = BIT(8), .msg = "zip_com_inf_err" }, 178 { .int_msk = BIT(9), .msg = "zip_enc_inf_err" }, 179 { .int_msk = BIT(10), .msg = "zip_pre_out_err" }, 180 { .int_msk = BIT(11), .msg = "zip_axi_poison_err" }, 181 { .int_msk = BIT(12), .msg = "zip_sva_err" }, 182 { /* sentinel */ } 183 }; 184 185 enum ctrl_debug_file_index { 186 HZIP_CLEAR_ENABLE, 187 HZIP_DEBUG_FILE_NUM, 188 }; 189 190 static const char * const ctrl_debug_file_name[] = { 191 [HZIP_CLEAR_ENABLE] = "clear_enable", 192 }; 193 194 struct ctrl_debug_file { 195 enum ctrl_debug_file_index index; 196 spinlock_t lock; 197 struct hisi_zip_ctrl *ctrl; 198 }; 199 200 /* 201 * One ZIP controller has one PF and multiple VFs, some global configurations 202 * which PF has need this structure. 203 * 204 * Just relevant for PF. 205 */ 206 struct hisi_zip_ctrl { 207 struct hisi_zip *hisi_zip; 208 struct ctrl_debug_file files[HZIP_DEBUG_FILE_NUM]; 209 }; 210 211 enum zip_cap_type { 212 ZIP_QM_NFE_MASK_CAP = 0x0, 213 ZIP_QM_RESET_MASK_CAP, 214 ZIP_QM_OOO_SHUTDOWN_MASK_CAP, 215 ZIP_QM_CE_MASK_CAP, 216 ZIP_NFE_MASK_CAP, 217 ZIP_RESET_MASK_CAP, 218 ZIP_OOO_SHUTDOWN_MASK_CAP, 219 ZIP_CE_MASK_CAP, 220 ZIP_CLUSTER_NUM_CAP, 221 ZIP_CORE_TYPE_NUM_CAP, 222 ZIP_CORE_NUM_CAP, 223 ZIP_CLUSTER_COMP_NUM_CAP, 224 ZIP_CLUSTER_DECOMP_NUM_CAP, 225 ZIP_DECOMP_ENABLE_BITMAP, 226 ZIP_COMP_ENABLE_BITMAP, 227 ZIP_DRV_ALG_BITMAP, 228 ZIP_DEV_ALG_BITMAP, 229 ZIP_CORE1_ALG_BITMAP, 230 ZIP_CORE2_ALG_BITMAP, 231 ZIP_CORE3_ALG_BITMAP, 232 ZIP_CORE4_ALG_BITMAP, 233 ZIP_CORE5_ALG_BITMAP, 234 ZIP_CAP_MAX 235 }; 236 237 static struct hisi_qm_cap_info zip_basic_cap_info[] = { 238 {ZIP_QM_NFE_MASK_CAP, 0x3124, 0, GENMASK(31, 0), 0x0, 0x1C57, 0x7C77}, 239 {ZIP_QM_RESET_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0xC57, 0x6C77}, 240 {ZIP_QM_OOO_SHUTDOWN_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0x4, 0x6C77}, 241 {ZIP_QM_CE_MASK_CAP, 0x312C, 0, GENMASK(31, 0), 0x0, 0x8, 0x8}, 242 {ZIP_NFE_MASK_CAP, 0x3130, 0, GENMASK(31, 0), 0x0, 0x7FE, 0x1FFE}, 243 {ZIP_RESET_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x7FE, 0x7FE}, 244 {ZIP_OOO_SHUTDOWN_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x2, 0x7FE}, 245 {ZIP_CE_MASK_CAP, 0x3138, 0, GENMASK(31, 0), 0x0, 0x1, 0x1}, 246 {ZIP_CLUSTER_NUM_CAP, 0x313C, 28, GENMASK(3, 0), 0x1, 0x1, 0x1}, 247 {ZIP_CORE_TYPE_NUM_CAP, 0x313C, 24, GENMASK(3, 0), 0x2, 0x2, 0x2}, 248 {ZIP_CORE_NUM_CAP, 0x313C, 16, GENMASK(7, 0), 0x8, 0x8, 0x5}, 249 {ZIP_CLUSTER_COMP_NUM_CAP, 0x313C, 8, GENMASK(7, 0), 0x2, 0x2, 0x2}, 250 {ZIP_CLUSTER_DECOMP_NUM_CAP, 0x313C, 0, GENMASK(7, 0), 0x6, 0x6, 0x3}, 251 {ZIP_DECOMP_ENABLE_BITMAP, 0x3140, 16, GENMASK(15, 0), 0xFC, 0xFC, 0x1C}, 252 {ZIP_COMP_ENABLE_BITMAP, 0x3140, 0, GENMASK(15, 0), 0x3, 0x3, 0x3}, 253 {ZIP_DRV_ALG_BITMAP, 0x3144, 0, GENMASK(31, 0), 0x0, 0x0, 0x30}, 254 {ZIP_DEV_ALG_BITMAP, 0x3148, 0, GENMASK(31, 0), 0xF, 0xF, 0x3F}, 255 {ZIP_CORE1_ALG_BITMAP, 0x314C, 0, GENMASK(31, 0), 0x5, 0x5, 0xD5}, 256 {ZIP_CORE2_ALG_BITMAP, 0x3150, 0, GENMASK(31, 0), 0x5, 0x5, 0xD5}, 257 {ZIP_CORE3_ALG_BITMAP, 0x3154, 0, GENMASK(31, 0), 0xA, 0xA, 0x2A}, 258 {ZIP_CORE4_ALG_BITMAP, 0x3158, 0, GENMASK(31, 0), 0xA, 0xA, 0x2A}, 259 {ZIP_CORE5_ALG_BITMAP, 0x315C, 0, GENMASK(31, 0), 0xA, 0xA, 0x2A}, 260 {ZIP_CAP_MAX, 0x317c, 0, GENMASK(0, 0), 0x0, 0x0, 0x0} 261 }; 262 263 static const struct hisi_qm_cap_query_info zip_cap_query_info[] = { 264 {QM_RAS_NFE_TYPE, "QM_RAS_NFE_TYPE ", 0x3124, 0x0, 0x1C57, 0x7C77}, 265 {QM_RAS_NFE_RESET, "QM_RAS_NFE_RESET ", 0x3128, 0x0, 0xC57, 0x6C77}, 266 {QM_RAS_CE_TYPE, "QM_RAS_CE_TYPE ", 0x312C, 0x0, 0x8, 0x8}, 267 {ZIP_RAS_NFE_TYPE, "ZIP_RAS_NFE_TYPE ", 0x3130, 0x0, 0x7FE, 0x1FFE}, 268 {ZIP_RAS_NFE_RESET, "ZIP_RAS_NFE_RESET ", 0x3134, 0x0, 0x7FE, 0x7FE}, 269 {ZIP_RAS_CE_TYPE, "ZIP_RAS_CE_TYPE ", 0x3138, 0x0, 0x1, 0x1}, 270 {ZIP_CORE_INFO, "ZIP_CORE_INFO ", 0x313C, 0x12080206, 0x12080206, 0x12050203}, 271 {ZIP_CORE_EN, "ZIP_CORE_EN ", 0x3140, 0xFC0003, 0xFC0003, 0x1C0003}, 272 {ZIP_DRV_ALG_BITMAP_TB, "ZIP_DRV_ALG_BITMAP ", 0x3144, 0x0, 0x0, 0x30}, 273 {ZIP_ALG_BITMAP, "ZIP_ALG_BITMAP ", 0x3148, 0xF, 0xF, 0x3F}, 274 {ZIP_CORE1_BITMAP, "ZIP_CORE1_BITMAP ", 0x314C, 0x5, 0x5, 0xD5}, 275 {ZIP_CORE2_BITMAP, "ZIP_CORE2_BITMAP ", 0x3150, 0x5, 0x5, 0xD5}, 276 {ZIP_CORE3_BITMAP, "ZIP_CORE3_BITMAP ", 0x3154, 0xA, 0xA, 0x2A}, 277 {ZIP_CORE4_BITMAP, "ZIP_CORE4_BITMAP ", 0x3158, 0xA, 0xA, 0x2A}, 278 {ZIP_CORE5_BITMAP, "ZIP_CORE5_BITMAP ", 0x315C, 0xA, 0xA, 0x2A}, 279 }; 280 281 static const struct debugfs_reg32 hzip_dfx_regs[] = { 282 {"HZIP_GET_BD_NUM ", 0x00}, 283 {"HZIP_GET_RIGHT_BD ", 0x04}, 284 {"HZIP_GET_ERROR_BD ", 0x08}, 285 {"HZIP_DONE_BD_NUM ", 0x0c}, 286 {"HZIP_WORK_CYCLE ", 0x10}, 287 {"HZIP_IDLE_CYCLE ", 0x18}, 288 {"HZIP_MAX_DELAY ", 0x20}, 289 {"HZIP_MIN_DELAY ", 0x24}, 290 {"HZIP_AVG_DELAY ", 0x28}, 291 {"HZIP_MEM_VISIBLE_DATA ", 0x30}, 292 {"HZIP_MEM_VISIBLE_ADDR ", 0x34}, 293 {"HZIP_CONSUMED_BYTE ", 0x38}, 294 {"HZIP_PRODUCED_BYTE ", 0x40}, 295 {"HZIP_COMP_INF ", 0x70}, 296 {"HZIP_PRE_OUT ", 0x78}, 297 {"HZIP_BD_RD ", 0x7c}, 298 {"HZIP_BD_WR ", 0x80}, 299 {"HZIP_GET_BD_AXI_ERR_NUM ", 0x84}, 300 {"HZIP_GET_BD_PARSE_ERR_NUM ", 0x88}, 301 {"HZIP_ADD_BD_AXI_ERR_NUM ", 0x8c}, 302 {"HZIP_DECOMP_STF_RELOAD_CURR_ST ", 0x94}, 303 {"HZIP_DECOMP_LZ77_CURR_ST ", 0x9c}, 304 }; 305 306 static const struct debugfs_reg32 hzip_com_dfx_regs[] = { 307 {"HZIP_CLOCK_GATE_CTRL ", 0x301004}, 308 {"HZIP_CORE_INT_RAS_CE_ENB ", 0x301160}, 309 {"HZIP_CORE_INT_RAS_NFE_ENB ", 0x301164}, 310 {"HZIP_CORE_INT_RAS_FE_ENB ", 0x301168}, 311 {"HZIP_UNCOM_ERR_RAS_CTRL ", 0x30116C}, 312 }; 313 314 static const struct debugfs_reg32 hzip_dump_dfx_regs[] = { 315 {"HZIP_GET_BD_NUM ", 0x00}, 316 {"HZIP_GET_RIGHT_BD ", 0x04}, 317 {"HZIP_GET_ERROR_BD ", 0x08}, 318 {"HZIP_DONE_BD_NUM ", 0x0c}, 319 {"HZIP_MAX_DELAY ", 0x20}, 320 }; 321 322 /* define the ZIP's dfx regs region and region length */ 323 static struct dfx_diff_registers hzip_diff_regs[] = { 324 { 325 .reg_offset = HZIP_CORE_DFX_BASE, 326 .reg_len = HZIP_CORE_REGS_BASE_LEN, 327 }, { 328 .reg_offset = HZIP_CORE_DFX_COMP_0, 329 .reg_len = HZIP_CORE_REGS_DFX_LEN, 330 }, { 331 .reg_offset = HZIP_CORE_DFX_COMP_1, 332 .reg_len = HZIP_CORE_REGS_DFX_LEN, 333 }, { 334 .reg_offset = HZIP_CORE_DFX_DECOMP_0, 335 .reg_len = HZIP_CORE_REGS_DFX_LEN, 336 }, { 337 .reg_offset = HZIP_CORE_DFX_DECOMP_1, 338 .reg_len = HZIP_CORE_REGS_DFX_LEN, 339 }, { 340 .reg_offset = HZIP_CORE_DFX_DECOMP_2, 341 .reg_len = HZIP_CORE_REGS_DFX_LEN, 342 }, { 343 .reg_offset = HZIP_CORE_DFX_DECOMP_3, 344 .reg_len = HZIP_CORE_REGS_DFX_LEN, 345 }, { 346 .reg_offset = HZIP_CORE_DFX_DECOMP_4, 347 .reg_len = HZIP_CORE_REGS_DFX_LEN, 348 }, { 349 .reg_offset = HZIP_CORE_DFX_DECOMP_5, 350 .reg_len = HZIP_CORE_REGS_DFX_LEN, 351 }, 352 }; 353 354 static int hzip_diff_regs_show(struct seq_file *s, void *unused) 355 { 356 struct hisi_qm *qm = s->private; 357 358 hisi_qm_acc_diff_regs_dump(qm, s, qm->debug.acc_diff_regs, 359 ARRAY_SIZE(hzip_diff_regs)); 360 361 return 0; 362 } 363 DEFINE_SHOW_ATTRIBUTE(hzip_diff_regs); 364 365 static int perf_mode_set(const char *val, const struct kernel_param *kp) 366 { 367 int ret; 368 u32 n; 369 370 if (!val) 371 return -EINVAL; 372 373 ret = kstrtou32(val, 10, &n); 374 if (ret != 0 || (n != HZIP_HIGH_COMP_PERF && 375 n != HZIP_HIGH_COMP_RATE)) 376 return -EINVAL; 377 378 return param_set_int(val, kp); 379 } 380 381 static const struct kernel_param_ops zip_com_perf_ops = { 382 .set = perf_mode_set, 383 .get = param_get_int, 384 }; 385 386 /* 387 * perf_mode = 0 means enable high compression rate mode, 388 * perf_mode = 1 means enable high compression performance mode. 389 * These two modes only apply to the compression direction. 390 */ 391 static u32 perf_mode = HZIP_HIGH_COMP_RATE; 392 module_param_cb(perf_mode, &zip_com_perf_ops, &perf_mode, 0444); 393 MODULE_PARM_DESC(perf_mode, "ZIP high perf mode 0(default), 1(enable)"); 394 395 static const struct kernel_param_ops zip_uacce_mode_ops = { 396 .set = uacce_mode_set, 397 .get = param_get_int, 398 }; 399 400 /* 401 * uacce_mode = 0 means zip only register to crypto, 402 * uacce_mode = 1 means zip both register to crypto and uacce. 403 */ 404 static u32 uacce_mode = UACCE_MODE_NOUACCE; 405 module_param_cb(uacce_mode, &zip_uacce_mode_ops, &uacce_mode, 0444); 406 MODULE_PARM_DESC(uacce_mode, UACCE_MODE_DESC); 407 408 static bool pf_q_num_flag; 409 static int pf_q_num_set(const char *val, const struct kernel_param *kp) 410 { 411 pf_q_num_flag = true; 412 413 return hisi_qm_q_num_set(val, kp, PCI_DEVICE_ID_HUAWEI_ZIP_PF); 414 } 415 416 static const struct kernel_param_ops pf_q_num_ops = { 417 .set = pf_q_num_set, 418 .get = param_get_int, 419 }; 420 421 static u32 pf_q_num = HZIP_PF_DEF_Q_NUM; 422 module_param_cb(pf_q_num, &pf_q_num_ops, &pf_q_num, 0444); 423 MODULE_PARM_DESC(pf_q_num, "Number of queues in PF(v1 2-4096, v2 2-1024)"); 424 425 static const struct kernel_param_ops vfs_num_ops = { 426 .set = vfs_num_set, 427 .get = param_get_int, 428 }; 429 430 static u32 vfs_num; 431 module_param_cb(vfs_num, &vfs_num_ops, &vfs_num, 0444); 432 MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63), 0(default)"); 433 434 static const struct pci_device_id hisi_zip_dev_ids[] = { 435 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_ZIP_PF) }, 436 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_ZIP_VF) }, 437 { 0, } 438 }; 439 MODULE_DEVICE_TABLE(pci, hisi_zip_dev_ids); 440 441 int zip_create_qps(struct hisi_qp **qps, int qp_num, int node) 442 { 443 if (node == NUMA_NO_NODE) 444 node = cpu_to_node(raw_smp_processor_id()); 445 446 return hisi_qm_alloc_qps_node(&zip_devices, qp_num, 0, node, qps); 447 } 448 449 bool hisi_zip_alg_support(struct hisi_qm *qm, u32 alg) 450 { 451 u32 cap_val; 452 453 cap_val = qm->cap_tables.dev_cap_table[ZIP_DRV_ALG_BITMAP_TB].cap_val; 454 if ((alg & cap_val) == alg) 455 return true; 456 457 return false; 458 } 459 460 static void hisi_zip_literal_set(struct hisi_qm *qm) 461 { 462 u32 val; 463 464 if (qm->ver < QM_HW_V3) 465 return; 466 467 val = readl_relaxed(qm->io_base + HZIP_LIT_LEN_EN_OFFSET); 468 val &= ~HZIP_LIT_LEN_EN_EN; 469 470 /* enable literal length in stream mode compression */ 471 writel(val, qm->io_base + HZIP_LIT_LEN_EN_OFFSET); 472 } 473 474 static void hisi_zip_set_high_perf(struct hisi_qm *qm) 475 { 476 u32 val; 477 478 val = readl_relaxed(qm->io_base + HZIP_HIGH_PERF_OFFSET); 479 if (perf_mode == HZIP_HIGH_COMP_PERF) 480 val |= HZIP_HIGH_COMP_PERF; 481 else 482 val &= ~HZIP_HIGH_COMP_PERF; 483 484 /* Set perf mode */ 485 writel(val, qm->io_base + HZIP_HIGH_PERF_OFFSET); 486 } 487 488 static int hisi_zip_wait_sva_ready(struct hisi_qm *qm, __u32 offset, __u32 mask) 489 { 490 u32 val, try_times = 0; 491 u8 count = 0; 492 493 /* 494 * Read the register value every 10-20us. If the value is 0 for three 495 * consecutive times, the SVA module is ready. 496 */ 497 do { 498 val = readl(qm->io_base + offset); 499 if (val & mask) 500 count = 0; 501 else if (++count == HZIP_READ_SVA_STATUS_TIMES) 502 break; 503 504 usleep_range(HZIP_WAIT_US_MIN, HZIP_WAIT_US_MAX); 505 } while (++try_times < HZIP_WAIT_SVA_READY); 506 507 if (try_times == HZIP_WAIT_SVA_READY) { 508 pci_err(qm->pdev, "failed to wait sva prefetch ready\n"); 509 return -ETIMEDOUT; 510 } 511 512 return 0; 513 } 514 515 static void hisi_zip_close_sva_prefetch(struct hisi_qm *qm) 516 { 517 u32 val; 518 int ret; 519 520 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps)) 521 return; 522 523 val = readl_relaxed(qm->io_base + HZIP_PREFETCH_CFG); 524 val |= HZIP_SVA_PREFETCH_DISABLE; 525 writel(val, qm->io_base + HZIP_PREFETCH_CFG); 526 527 ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_SVA_TRANS, 528 val, !(val & HZIP_SVA_DISABLE_READY), 529 HZIP_DELAY_1_US, HZIP_POLL_TIMEOUT_US); 530 if (ret) 531 pci_err(qm->pdev, "failed to close sva prefetch\n"); 532 533 (void)hisi_zip_wait_sva_ready(qm, HZIP_SVA_TRANS, HZIP_SVA_STALL_NUM); 534 } 535 536 static void hisi_zip_open_sva_prefetch(struct hisi_qm *qm) 537 { 538 u32 val; 539 int ret; 540 541 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps)) 542 return; 543 544 /* Enable prefetch */ 545 val = readl_relaxed(qm->io_base + HZIP_PREFETCH_CFG); 546 val &= HZIP_PREFETCH_ENABLE; 547 writel(val, qm->io_base + HZIP_PREFETCH_CFG); 548 549 ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_PREFETCH_CFG, 550 val, !(val & HZIP_SVA_PREFETCH_DISABLE), 551 HZIP_DELAY_1_US, HZIP_POLL_TIMEOUT_US); 552 if (ret) { 553 pci_err(qm->pdev, "failed to open sva prefetch\n"); 554 hisi_zip_close_sva_prefetch(qm); 555 return; 556 } 557 558 ret = hisi_zip_wait_sva_ready(qm, HZIP_SVA_TRANS, HZIP_SVA_PREFETCH_NUM); 559 if (ret) 560 hisi_zip_close_sva_prefetch(qm); 561 } 562 563 static void hisi_zip_enable_clock_gate(struct hisi_qm *qm) 564 { 565 u32 val; 566 567 if (qm->ver < QM_HW_V3) 568 return; 569 570 val = readl(qm->io_base + HZIP_CLOCK_GATE_CTRL); 571 val |= HZIP_CLOCK_GATED_EN; 572 writel(val, qm->io_base + HZIP_CLOCK_GATE_CTRL); 573 574 val = readl(qm->io_base + HZIP_PEH_CFG_AUTO_GATE); 575 val |= HZIP_PEH_CFG_AUTO_GATE_EN; 576 writel(val, qm->io_base + HZIP_PEH_CFG_AUTO_GATE); 577 } 578 579 static int hisi_zip_set_user_domain_and_cache(struct hisi_qm *qm) 580 { 581 void __iomem *base = qm->io_base; 582 u32 dcomp_bm, comp_bm; 583 u32 zip_core_en; 584 int ret; 585 586 /* qm user domain */ 587 writel(AXUSER_BASE, base + QM_ARUSER_M_CFG_1); 588 writel(ARUSER_M_CFG_ENABLE, base + QM_ARUSER_M_CFG_ENABLE); 589 writel(AXUSER_BASE, base + QM_AWUSER_M_CFG_1); 590 writel(AWUSER_M_CFG_ENABLE, base + QM_AWUSER_M_CFG_ENABLE); 591 writel(WUSER_M_CFG_ENABLE, base + QM_WUSER_M_CFG_ENABLE); 592 593 /* qm cache */ 594 writel(AXI_M_CFG, base + QM_AXI_M_CFG); 595 writel(AXI_M_CFG_ENABLE, base + QM_AXI_M_CFG_ENABLE); 596 597 /* disable FLR triggered by BME(bus master enable) */ 598 writel(PEH_AXUSER_CFG, base + QM_PEH_AXUSER_CFG); 599 writel(PEH_AXUSER_CFG_ENABLE, base + QM_PEH_AXUSER_CFG_ENABLE); 600 601 /* cache */ 602 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_ARCA_CHE_0); 603 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_ARCA_CHE_1); 604 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_AWCA_CHE_0); 605 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_AWCA_CHE_1); 606 607 /* user domain configurations */ 608 writel(AXUSER_BASE, base + HZIP_BD_RUSER_32_63); 609 writel(AXUSER_BASE, base + HZIP_BD_WUSER_32_63); 610 611 if (qm->use_sva && qm->ver == QM_HW_V2) { 612 writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_DATA_RUSER_32_63); 613 writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_DATA_WUSER_32_63); 614 writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_SGL_RUSER_32_63); 615 } else { 616 writel(AXUSER_BASE, base + HZIP_DATA_RUSER_32_63); 617 writel(AXUSER_BASE, base + HZIP_DATA_WUSER_32_63); 618 writel(AXUSER_BASE, base + HZIP_SGL_RUSER_32_63); 619 } 620 hisi_zip_open_sva_prefetch(qm); 621 622 /* let's open all compression/decompression cores */ 623 624 zip_core_en = qm->cap_tables.dev_cap_table[ZIP_CORE_EN].cap_val; 625 dcomp_bm = (zip_core_en >> zip_basic_cap_info[ZIP_DECOMP_ENABLE_BITMAP].shift) & 626 zip_basic_cap_info[ZIP_DECOMP_ENABLE_BITMAP].mask; 627 comp_bm = (zip_core_en >> zip_basic_cap_info[ZIP_COMP_ENABLE_BITMAP].shift) & 628 zip_basic_cap_info[ZIP_COMP_ENABLE_BITMAP].mask; 629 writel(HZIP_DECOMP_CHECK_ENABLE | dcomp_bm | comp_bm, base + HZIP_CLOCK_GATE_CTRL); 630 631 /* enable sqc,cqc writeback */ 632 writel(SQC_CACHE_ENABLE | CQC_CACHE_ENABLE | SQC_CACHE_WB_ENABLE | 633 CQC_CACHE_WB_ENABLE | FIELD_PREP(SQC_CACHE_WB_THRD, 1) | 634 FIELD_PREP(CQC_CACHE_WB_THRD, 1), base + QM_CACHE_CTL); 635 636 hisi_zip_set_high_perf(qm); 637 hisi_zip_literal_set(qm); 638 hisi_zip_enable_clock_gate(qm); 639 640 ret = hisi_dae_set_user_domain(qm); 641 if (ret) 642 goto close_sva_prefetch; 643 644 return 0; 645 646 close_sva_prefetch: 647 hisi_zip_close_sva_prefetch(qm); 648 return ret; 649 } 650 651 static void hisi_zip_master_ooo_ctrl(struct hisi_qm *qm, bool enable) 652 { 653 u32 val1, val2; 654 655 val1 = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 656 if (enable) { 657 val1 |= HZIP_AXI_SHUTDOWN_ENABLE; 658 val2 = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 659 ZIP_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 660 } else { 661 val1 &= ~HZIP_AXI_SHUTDOWN_ENABLE; 662 val2 = 0x0; 663 } 664 665 if (qm->ver > QM_HW_V2) 666 writel(val2, qm->io_base + HZIP_OOO_SHUTDOWN_SEL); 667 668 writel(val1, qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 669 } 670 671 static void hisi_zip_hw_error_enable(struct hisi_qm *qm) 672 { 673 u32 nfe, ce; 674 675 if (qm->ver == QM_HW_V1) { 676 writel(HZIP_CORE_INT_MASK_ALL, 677 qm->io_base + HZIP_CORE_INT_MASK_REG); 678 dev_info(&qm->pdev->dev, "Does not support hw error handle\n"); 679 return; 680 } 681 682 nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_NFE_MASK_CAP, qm->cap_ver); 683 ce = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CE_MASK_CAP, qm->cap_ver); 684 685 /* clear ZIP hw error source if having */ 686 writel(ce | nfe | HZIP_CORE_INT_RAS_FE_ENB_MASK, qm->io_base + HZIP_CORE_INT_SOURCE); 687 688 /* configure error type */ 689 writel(ce, qm->io_base + HZIP_CORE_INT_RAS_CE_ENB); 690 writel(HZIP_CORE_INT_RAS_FE_ENB_MASK, qm->io_base + HZIP_CORE_INT_RAS_FE_ENB); 691 writel(nfe, qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); 692 693 hisi_zip_master_ooo_ctrl(qm, true); 694 695 /* enable ZIP hw error interrupts */ 696 writel(0, qm->io_base + HZIP_CORE_INT_MASK_REG); 697 698 hisi_dae_hw_error_enable(qm); 699 } 700 701 static void hisi_zip_hw_error_disable(struct hisi_qm *qm) 702 { 703 u32 nfe, ce; 704 705 /* disable ZIP hw error interrupts */ 706 nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_NFE_MASK_CAP, qm->cap_ver); 707 ce = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CE_MASK_CAP, qm->cap_ver); 708 writel(ce | nfe | HZIP_CORE_INT_RAS_FE_ENB_MASK, qm->io_base + HZIP_CORE_INT_MASK_REG); 709 710 hisi_zip_master_ooo_ctrl(qm, false); 711 712 hisi_dae_hw_error_disable(qm); 713 } 714 715 static inline struct hisi_qm *file_to_qm(struct ctrl_debug_file *file) 716 { 717 struct hisi_zip *hisi_zip = file->ctrl->hisi_zip; 718 719 return &hisi_zip->qm; 720 } 721 722 static u32 clear_enable_read(struct hisi_qm *qm) 723 { 724 return readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) & 725 HZIP_SOFT_CTRL_CNT_CLR_CE_BIT; 726 } 727 728 static int clear_enable_write(struct hisi_qm *qm, u32 val) 729 { 730 u32 tmp; 731 732 if (val != 1 && val != 0) 733 return -EINVAL; 734 735 tmp = (readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) & 736 ~HZIP_SOFT_CTRL_CNT_CLR_CE_BIT) | val; 737 writel(tmp, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE); 738 739 return 0; 740 } 741 742 static ssize_t hisi_zip_ctrl_debug_read(struct file *filp, char __user *buf, 743 size_t count, loff_t *pos) 744 { 745 struct ctrl_debug_file *file = filp->private_data; 746 struct hisi_qm *qm = file_to_qm(file); 747 char tbuf[HZIP_BUF_SIZE]; 748 u32 val; 749 int ret; 750 751 ret = hisi_qm_get_dfx_access(qm); 752 if (ret) 753 return ret; 754 755 spin_lock_irq(&file->lock); 756 switch (file->index) { 757 case HZIP_CLEAR_ENABLE: 758 val = clear_enable_read(qm); 759 break; 760 default: 761 goto err_input; 762 } 763 spin_unlock_irq(&file->lock); 764 765 hisi_qm_put_dfx_access(qm); 766 ret = scnprintf(tbuf, sizeof(tbuf), "%u\n", val); 767 return simple_read_from_buffer(buf, count, pos, tbuf, ret); 768 769 err_input: 770 spin_unlock_irq(&file->lock); 771 hisi_qm_put_dfx_access(qm); 772 return -EINVAL; 773 } 774 775 static ssize_t hisi_zip_ctrl_debug_write(struct file *filp, 776 const char __user *buf, 777 size_t count, loff_t *pos) 778 { 779 struct ctrl_debug_file *file = filp->private_data; 780 struct hisi_qm *qm = file_to_qm(file); 781 char tbuf[HZIP_BUF_SIZE]; 782 unsigned long val; 783 int len, ret; 784 785 if (*pos != 0) 786 return 0; 787 788 if (count >= HZIP_BUF_SIZE) 789 return -ENOSPC; 790 791 len = simple_write_to_buffer(tbuf, HZIP_BUF_SIZE - 1, pos, buf, count); 792 if (len < 0) 793 return len; 794 795 tbuf[len] = '\0'; 796 ret = kstrtoul(tbuf, 0, &val); 797 if (ret) 798 return ret; 799 800 ret = hisi_qm_get_dfx_access(qm); 801 if (ret) 802 return ret; 803 804 spin_lock_irq(&file->lock); 805 switch (file->index) { 806 case HZIP_CLEAR_ENABLE: 807 ret = clear_enable_write(qm, val); 808 if (ret) 809 goto err_input; 810 break; 811 default: 812 ret = -EINVAL; 813 goto err_input; 814 } 815 816 ret = count; 817 818 err_input: 819 spin_unlock_irq(&file->lock); 820 hisi_qm_put_dfx_access(qm); 821 return ret; 822 } 823 824 static const struct file_operations ctrl_debug_fops = { 825 .owner = THIS_MODULE, 826 .open = simple_open, 827 .read = hisi_zip_ctrl_debug_read, 828 .write = hisi_zip_ctrl_debug_write, 829 }; 830 831 static int zip_debugfs_atomic64_set(void *data, u64 val) 832 { 833 if (val) 834 return -EINVAL; 835 836 atomic64_set((atomic64_t *)data, 0); 837 838 return 0; 839 } 840 841 static int zip_debugfs_atomic64_get(void *data, u64 *val) 842 { 843 *val = atomic64_read((atomic64_t *)data); 844 845 return 0; 846 } 847 848 DEFINE_DEBUGFS_ATTRIBUTE(zip_atomic64_ops, zip_debugfs_atomic64_get, 849 zip_debugfs_atomic64_set, "%llu\n"); 850 851 static int hisi_zip_regs_show(struct seq_file *s, void *unused) 852 { 853 hisi_qm_regs_dump(s, s->private); 854 855 return 0; 856 } 857 858 DEFINE_SHOW_ATTRIBUTE(hisi_zip_regs); 859 860 static void __iomem *get_zip_core_addr(struct hisi_qm *qm, int core_num) 861 { 862 u8 zip_comp_core_num; 863 u32 zip_core_info; 864 865 zip_core_info = qm->cap_tables.dev_cap_table[ZIP_CORE_INFO].cap_val; 866 zip_comp_core_num = (zip_core_info >> zip_basic_cap_info[ZIP_CLUSTER_COMP_NUM_CAP].shift) & 867 zip_basic_cap_info[ZIP_CLUSTER_COMP_NUM_CAP].mask; 868 869 if (core_num < zip_comp_core_num) 870 return qm->io_base + HZIP_CORE_DFX_BASE + 871 (core_num + 1) * HZIP_CORE_ADDR_INTRVL; 872 873 return qm->io_base + HZIP_CORE_DFX_DECOMP_BASE + 874 (core_num - zip_comp_core_num) * HZIP_CORE_ADDR_INTRVL; 875 } 876 877 static int hisi_zip_core_debug_init(struct hisi_qm *qm) 878 { 879 u32 zip_core_num, zip_comp_core_num; 880 struct device *dev = &qm->pdev->dev; 881 struct debugfs_regset32 *regset; 882 u32 zip_core_info; 883 struct dentry *tmp_d; 884 char buf[HZIP_BUF_SIZE]; 885 int i; 886 887 zip_core_info = qm->cap_tables.dev_cap_table[ZIP_CORE_INFO].cap_val; 888 zip_core_num = (zip_core_info >> zip_basic_cap_info[ZIP_CORE_NUM_CAP].shift) & 889 zip_basic_cap_info[ZIP_CORE_NUM_CAP].mask; 890 zip_comp_core_num = (zip_core_info >> zip_basic_cap_info[ZIP_CLUSTER_COMP_NUM_CAP].shift) & 891 zip_basic_cap_info[ZIP_CLUSTER_COMP_NUM_CAP].mask; 892 893 for (i = 0; i < zip_core_num; i++) { 894 if (i < zip_comp_core_num) 895 scnprintf(buf, sizeof(buf), "comp_core%d", i); 896 else 897 scnprintf(buf, sizeof(buf), "decomp_core%d", 898 i - zip_comp_core_num); 899 900 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); 901 if (!regset) 902 return -ENOENT; 903 904 regset->regs = hzip_dfx_regs; 905 regset->nregs = ARRAY_SIZE(hzip_dfx_regs); 906 regset->base = get_zip_core_addr(qm, i); 907 regset->dev = dev; 908 909 tmp_d = debugfs_create_dir(buf, qm->debug.debug_root); 910 debugfs_create_file("regs", 0444, tmp_d, regset, 911 &hisi_zip_regs_fops); 912 } 913 914 return 0; 915 } 916 917 static int zip_cap_regs_show(struct seq_file *s, void *unused) 918 { 919 struct hisi_qm *qm = s->private; 920 u32 i, size; 921 922 size = qm->cap_tables.qm_cap_size; 923 for (i = 0; i < size; i++) 924 seq_printf(s, "%s= 0x%08x\n", qm->cap_tables.qm_cap_table[i].name, 925 qm->cap_tables.qm_cap_table[i].cap_val); 926 927 size = qm->cap_tables.dev_cap_size; 928 for (i = 0; i < size; i++) 929 seq_printf(s, "%s= 0x%08x\n", qm->cap_tables.dev_cap_table[i].name, 930 qm->cap_tables.dev_cap_table[i].cap_val); 931 932 return 0; 933 } 934 935 DEFINE_SHOW_ATTRIBUTE(zip_cap_regs); 936 937 static void hisi_zip_dfx_debug_init(struct hisi_qm *qm) 938 { 939 struct dfx_diff_registers *hzip_regs = qm->debug.acc_diff_regs; 940 struct hisi_zip *zip = container_of(qm, struct hisi_zip, qm); 941 struct hisi_zip_dfx *dfx = &zip->dfx; 942 struct dentry *tmp_dir; 943 void *data; 944 int i; 945 946 tmp_dir = debugfs_create_dir("zip_dfx", qm->debug.debug_root); 947 for (i = 0; i < ARRAY_SIZE(zip_dfx_files); i++) { 948 data = (atomic64_t *)((uintptr_t)dfx + zip_dfx_files[i].offset); 949 debugfs_create_file(zip_dfx_files[i].name, 950 0644, tmp_dir, data, 951 &zip_atomic64_ops); 952 } 953 954 if (qm->fun_type == QM_HW_PF && hzip_regs) 955 debugfs_create_file("diff_regs", 0444, tmp_dir, 956 qm, &hzip_diff_regs_fops); 957 958 debugfs_create_file("cap_regs", CAP_FILE_PERMISSION, 959 qm->debug.debug_root, qm, &zip_cap_regs_fops); 960 } 961 962 static int hisi_zip_ctrl_debug_init(struct hisi_qm *qm) 963 { 964 struct hisi_zip *zip = container_of(qm, struct hisi_zip, qm); 965 int i; 966 967 for (i = HZIP_CLEAR_ENABLE; i < HZIP_DEBUG_FILE_NUM; i++) { 968 spin_lock_init(&zip->ctrl->files[i].lock); 969 zip->ctrl->files[i].ctrl = zip->ctrl; 970 zip->ctrl->files[i].index = i; 971 972 debugfs_create_file(ctrl_debug_file_name[i], 0600, 973 qm->debug.debug_root, 974 zip->ctrl->files + i, 975 &ctrl_debug_fops); 976 } 977 978 return hisi_zip_core_debug_init(qm); 979 } 980 981 static int hisi_zip_debugfs_init(struct hisi_qm *qm) 982 { 983 struct device *dev = &qm->pdev->dev; 984 int ret; 985 986 ret = hisi_qm_regs_debugfs_init(qm, hzip_diff_regs, ARRAY_SIZE(hzip_diff_regs)); 987 if (ret) { 988 dev_warn(dev, "Failed to init ZIP diff regs!\n"); 989 return ret; 990 } 991 992 qm->debug.sqe_mask_offset = HZIP_SQE_MASK_OFFSET; 993 qm->debug.sqe_mask_len = HZIP_SQE_MASK_LEN; 994 qm->debug.debug_root = debugfs_create_dir(dev_name(dev), 995 hzip_debugfs_root); 996 997 hisi_qm_debug_init(qm); 998 999 if (qm->fun_type == QM_HW_PF) { 1000 ret = hisi_zip_ctrl_debug_init(qm); 1001 if (ret) 1002 goto debugfs_remove; 1003 } 1004 1005 hisi_zip_dfx_debug_init(qm); 1006 1007 return 0; 1008 1009 debugfs_remove: 1010 debugfs_remove_recursive(qm->debug.debug_root); 1011 hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(hzip_diff_regs)); 1012 return ret; 1013 } 1014 1015 /* hisi_zip_debug_regs_clear() - clear the zip debug regs */ 1016 static void hisi_zip_debug_regs_clear(struct hisi_qm *qm) 1017 { 1018 u32 zip_core_info; 1019 u8 zip_core_num; 1020 int i, j; 1021 1022 zip_core_info = qm->cap_tables.dev_cap_table[ZIP_CORE_INFO].cap_val; 1023 zip_core_num = (zip_core_info >> zip_basic_cap_info[ZIP_CORE_NUM_CAP].shift) & 1024 zip_basic_cap_info[ZIP_CORE_NUM_CAP].mask; 1025 1026 /* enable register read_clear bit */ 1027 writel(HZIP_RD_CNT_CLR_CE_EN, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE); 1028 for (i = 0; i < zip_core_num; i++) 1029 for (j = 0; j < ARRAY_SIZE(hzip_dfx_regs); j++) 1030 readl(get_zip_core_addr(qm, i) + 1031 hzip_dfx_regs[j].offset); 1032 1033 /* disable register read_clear bit */ 1034 writel(0x0, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE); 1035 1036 hisi_qm_debug_regs_clear(qm); 1037 } 1038 1039 static void hisi_zip_debugfs_exit(struct hisi_qm *qm) 1040 { 1041 debugfs_remove_recursive(qm->debug.debug_root); 1042 1043 hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(hzip_diff_regs)); 1044 1045 if (qm->fun_type == QM_HW_PF) { 1046 hisi_zip_debug_regs_clear(qm); 1047 qm->debug.curr_qm_qp_num = 0; 1048 } 1049 } 1050 1051 static int hisi_zip_show_last_regs_init(struct hisi_qm *qm) 1052 { 1053 int core_dfx_regs_num = ARRAY_SIZE(hzip_dump_dfx_regs); 1054 int com_dfx_regs_num = ARRAY_SIZE(hzip_com_dfx_regs); 1055 struct qm_debug *debug = &qm->debug; 1056 void __iomem *io_base; 1057 u32 zip_core_info; 1058 u32 zip_core_num; 1059 int i, j, idx; 1060 1061 zip_core_info = qm->cap_tables.dev_cap_table[ZIP_CORE_INFO].cap_val; 1062 zip_core_num = (zip_core_info >> zip_basic_cap_info[ZIP_CORE_NUM_CAP].shift) & 1063 zip_basic_cap_info[ZIP_CORE_NUM_CAP].mask; 1064 1065 debug->last_words = kcalloc(core_dfx_regs_num * zip_core_num + com_dfx_regs_num, 1066 sizeof(unsigned int), GFP_KERNEL); 1067 if (!debug->last_words) 1068 return -ENOMEM; 1069 1070 for (i = 0; i < com_dfx_regs_num; i++) { 1071 io_base = qm->io_base + hzip_com_dfx_regs[i].offset; 1072 debug->last_words[i] = readl_relaxed(io_base); 1073 } 1074 1075 for (i = 0; i < zip_core_num; i++) { 1076 io_base = get_zip_core_addr(qm, i); 1077 for (j = 0; j < core_dfx_regs_num; j++) { 1078 idx = com_dfx_regs_num + i * core_dfx_regs_num + j; 1079 debug->last_words[idx] = readl_relaxed( 1080 io_base + hzip_dump_dfx_regs[j].offset); 1081 } 1082 } 1083 1084 return 0; 1085 } 1086 1087 static void hisi_zip_show_last_regs_uninit(struct hisi_qm *qm) 1088 { 1089 struct qm_debug *debug = &qm->debug; 1090 1091 if (qm->fun_type == QM_HW_VF || !debug->last_words) 1092 return; 1093 1094 kfree(debug->last_words); 1095 debug->last_words = NULL; 1096 } 1097 1098 static void hisi_zip_show_last_dfx_regs(struct hisi_qm *qm) 1099 { 1100 int core_dfx_regs_num = ARRAY_SIZE(hzip_dump_dfx_regs); 1101 int com_dfx_regs_num = ARRAY_SIZE(hzip_com_dfx_regs); 1102 u32 zip_core_num, zip_comp_core_num; 1103 struct qm_debug *debug = &qm->debug; 1104 char buf[HZIP_BUF_SIZE]; 1105 u32 zip_core_info; 1106 void __iomem *base; 1107 int i, j, idx; 1108 u32 val; 1109 1110 if (qm->fun_type == QM_HW_VF || !debug->last_words) 1111 return; 1112 1113 for (i = 0; i < com_dfx_regs_num; i++) { 1114 val = readl_relaxed(qm->io_base + hzip_com_dfx_regs[i].offset); 1115 if (debug->last_words[i] != val) 1116 pci_info(qm->pdev, "com_dfx: %s \t= 0x%08x => 0x%08x\n", 1117 hzip_com_dfx_regs[i].name, debug->last_words[i], val); 1118 } 1119 1120 zip_core_info = qm->cap_tables.dev_cap_table[ZIP_CORE_INFO].cap_val; 1121 zip_core_num = (zip_core_info >> zip_basic_cap_info[ZIP_CORE_NUM_CAP].shift) & 1122 zip_basic_cap_info[ZIP_CORE_NUM_CAP].mask; 1123 zip_comp_core_num = (zip_core_info >> zip_basic_cap_info[ZIP_CLUSTER_COMP_NUM_CAP].shift) & 1124 zip_basic_cap_info[ZIP_CLUSTER_COMP_NUM_CAP].mask; 1125 1126 for (i = 0; i < zip_core_num; i++) { 1127 if (i < zip_comp_core_num) 1128 scnprintf(buf, sizeof(buf), "Comp_core-%d", i); 1129 else 1130 scnprintf(buf, sizeof(buf), "Decomp_core-%d", 1131 i - zip_comp_core_num); 1132 base = get_zip_core_addr(qm, i); 1133 1134 pci_info(qm->pdev, "==>%s:\n", buf); 1135 /* dump last word for dfx regs during control resetting */ 1136 for (j = 0; j < core_dfx_regs_num; j++) { 1137 idx = com_dfx_regs_num + i * core_dfx_regs_num + j; 1138 val = readl_relaxed(base + hzip_dump_dfx_regs[j].offset); 1139 if (debug->last_words[idx] != val) 1140 pci_info(qm->pdev, "%s \t= 0x%08x => 0x%08x\n", 1141 hzip_dump_dfx_regs[j].name, 1142 debug->last_words[idx], val); 1143 } 1144 } 1145 } 1146 1147 static void hisi_zip_log_hw_error(struct hisi_qm *qm, u32 err_sts) 1148 { 1149 const struct hisi_zip_hw_error *err = zip_hw_error; 1150 struct device *dev = &qm->pdev->dev; 1151 u32 err_val; 1152 1153 while (err->msg) { 1154 if (err->int_msk & err_sts) { 1155 dev_err(dev, "%s [error status=0x%x] found\n", 1156 err->msg, err->int_msk); 1157 1158 if (err->int_msk & HZIP_CORE_INT_STATUS_M_ECC) { 1159 err_val = readl(qm->io_base + 1160 HZIP_CORE_SRAM_ECC_ERR_INFO); 1161 dev_err(dev, "hisi-zip multi ecc sram num=0x%x\n", 1162 ((err_val >> 1163 HZIP_SRAM_ECC_ERR_NUM_SHIFT) & 0xFF)); 1164 } 1165 } 1166 err++; 1167 } 1168 } 1169 1170 static u32 hisi_zip_get_hw_err_status(struct hisi_qm *qm) 1171 { 1172 return readl(qm->io_base + HZIP_CORE_INT_STATUS); 1173 } 1174 1175 static void hisi_zip_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts) 1176 { 1177 writel(err_sts, qm->io_base + HZIP_CORE_INT_SOURCE); 1178 } 1179 1180 static void hisi_zip_disable_error_report(struct hisi_qm *qm, u32 err_type) 1181 { 1182 u32 nfe_mask; 1183 1184 nfe_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_NFE_MASK_CAP, qm->cap_ver); 1185 writel(nfe_mask & (~err_type), qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); 1186 } 1187 1188 static void hisi_zip_open_axi_master_ooo(struct hisi_qm *qm) 1189 { 1190 u32 val; 1191 1192 val = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 1193 1194 writel(val & ~HZIP_AXI_SHUTDOWN_ENABLE, 1195 qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 1196 1197 writel(val | HZIP_AXI_SHUTDOWN_ENABLE, 1198 qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 1199 1200 hisi_dae_open_axi_master_ooo(qm); 1201 } 1202 1203 static void hisi_zip_close_axi_master_ooo(struct hisi_qm *qm) 1204 { 1205 u32 nfe_enb; 1206 1207 /* Disable ECC Mbit error report. */ 1208 nfe_enb = readl(qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); 1209 writel(nfe_enb & ~HZIP_CORE_INT_STATUS_M_ECC, 1210 qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); 1211 1212 /* Inject zip ECC Mbit error to block master ooo. */ 1213 writel(HZIP_CORE_INT_STATUS_M_ECC, 1214 qm->io_base + HZIP_CORE_INT_SET); 1215 } 1216 1217 static enum acc_err_result hisi_zip_get_err_result(struct hisi_qm *qm) 1218 { 1219 enum acc_err_result zip_result = ACC_ERR_NONE; 1220 enum acc_err_result dae_result; 1221 u32 err_status; 1222 1223 /* Get device hardware new error status */ 1224 err_status = hisi_zip_get_hw_err_status(qm); 1225 if (err_status) { 1226 if (err_status & qm->err_info.ecc_2bits_mask) 1227 qm->err_status.is_dev_ecc_mbit = true; 1228 hisi_zip_log_hw_error(qm, err_status); 1229 1230 if (err_status & qm->err_info.dev_reset_mask) { 1231 /* Disable the same error reporting until device is recovered. */ 1232 hisi_zip_disable_error_report(qm, err_status); 1233 return ACC_ERR_NEED_RESET; 1234 } else { 1235 hisi_zip_clear_hw_err_status(qm, err_status); 1236 } 1237 } 1238 1239 dae_result = hisi_dae_get_err_result(qm); 1240 1241 return (zip_result == ACC_ERR_NEED_RESET || 1242 dae_result == ACC_ERR_NEED_RESET) ? 1243 ACC_ERR_NEED_RESET : ACC_ERR_RECOVERED; 1244 } 1245 1246 static bool hisi_zip_dev_is_abnormal(struct hisi_qm *qm) 1247 { 1248 u32 err_status; 1249 1250 err_status = hisi_zip_get_hw_err_status(qm); 1251 if (err_status & qm->err_info.dev_shutdown_mask) 1252 return true; 1253 1254 return hisi_dae_dev_is_abnormal(qm); 1255 } 1256 1257 static int hisi_zip_set_priv_status(struct hisi_qm *qm) 1258 { 1259 return hisi_dae_close_axi_master_ooo(qm); 1260 } 1261 1262 static void hisi_zip_err_info_init(struct hisi_qm *qm) 1263 { 1264 struct hisi_qm_err_info *err_info = &qm->err_info; 1265 1266 err_info->fe = HZIP_CORE_INT_RAS_FE_ENB_MASK; 1267 err_info->ce = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_QM_CE_MASK_CAP, qm->cap_ver); 1268 err_info->nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 1269 ZIP_QM_NFE_MASK_CAP, qm->cap_ver); 1270 err_info->ecc_2bits_mask = HZIP_CORE_INT_STATUS_M_ECC; 1271 err_info->qm_shutdown_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 1272 ZIP_QM_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 1273 err_info->dev_shutdown_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 1274 ZIP_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 1275 err_info->qm_reset_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 1276 ZIP_QM_RESET_MASK_CAP, qm->cap_ver); 1277 err_info->dev_reset_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 1278 ZIP_RESET_MASK_CAP, qm->cap_ver); 1279 err_info->msi_wr_port = HZIP_WR_PORT; 1280 err_info->acpi_rst = "ZRST"; 1281 } 1282 1283 static const struct hisi_qm_err_ini hisi_zip_err_ini = { 1284 .hw_init = hisi_zip_set_user_domain_and_cache, 1285 .hw_err_enable = hisi_zip_hw_error_enable, 1286 .hw_err_disable = hisi_zip_hw_error_disable, 1287 .get_dev_hw_err_status = hisi_zip_get_hw_err_status, 1288 .clear_dev_hw_err_status = hisi_zip_clear_hw_err_status, 1289 .open_axi_master_ooo = hisi_zip_open_axi_master_ooo, 1290 .close_axi_master_ooo = hisi_zip_close_axi_master_ooo, 1291 .open_sva_prefetch = hisi_zip_open_sva_prefetch, 1292 .close_sva_prefetch = hisi_zip_close_sva_prefetch, 1293 .show_last_dfx_regs = hisi_zip_show_last_dfx_regs, 1294 .err_info_init = hisi_zip_err_info_init, 1295 .get_err_result = hisi_zip_get_err_result, 1296 .set_priv_status = hisi_zip_set_priv_status, 1297 .dev_is_abnormal = hisi_zip_dev_is_abnormal, 1298 }; 1299 1300 static int hisi_zip_pf_probe_init(struct hisi_zip *hisi_zip) 1301 { 1302 struct hisi_qm *qm = &hisi_zip->qm; 1303 struct hisi_zip_ctrl *ctrl; 1304 int ret; 1305 1306 ctrl = devm_kzalloc(&qm->pdev->dev, sizeof(*ctrl), GFP_KERNEL); 1307 if (!ctrl) 1308 return -ENOMEM; 1309 1310 hisi_zip->ctrl = ctrl; 1311 ctrl->hisi_zip = hisi_zip; 1312 1313 ret = hisi_zip_set_user_domain_and_cache(qm); 1314 if (ret) 1315 return ret; 1316 1317 hisi_qm_dev_err_init(qm); 1318 hisi_zip_debug_regs_clear(qm); 1319 1320 ret = hisi_zip_show_last_regs_init(qm); 1321 if (ret) 1322 pci_err(qm->pdev, "Failed to init last word regs!\n"); 1323 1324 return ret; 1325 } 1326 1327 static int zip_pre_store_cap_reg(struct hisi_qm *qm) 1328 { 1329 struct hisi_qm_cap_record *zip_cap; 1330 struct pci_dev *pdev = qm->pdev; 1331 size_t i, size; 1332 1333 size = ARRAY_SIZE(zip_cap_query_info); 1334 zip_cap = devm_kzalloc(&pdev->dev, sizeof(*zip_cap) * size, GFP_KERNEL); 1335 if (!zip_cap) 1336 return -ENOMEM; 1337 1338 for (i = 0; i < size; i++) { 1339 zip_cap[i].type = zip_cap_query_info[i].type; 1340 zip_cap[i].name = zip_cap_query_info[i].name; 1341 zip_cap[i].cap_val = hisi_qm_get_cap_value(qm, zip_cap_query_info, 1342 i, qm->cap_ver); 1343 } 1344 1345 qm->cap_tables.dev_cap_table = zip_cap; 1346 qm->cap_tables.dev_cap_size = size; 1347 1348 return 0; 1349 } 1350 1351 static int hisi_zip_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) 1352 { 1353 u64 alg_msk; 1354 int ret; 1355 1356 qm->pdev = pdev; 1357 qm->mode = uacce_mode; 1358 qm->sqe_size = HZIP_SQE_SIZE; 1359 qm->dev_name = hisi_zip_name; 1360 1361 qm->fun_type = (pdev->device == PCI_DEVICE_ID_HUAWEI_ZIP_PF) ? 1362 QM_HW_PF : QM_HW_VF; 1363 if (qm->fun_type == QM_HW_PF) { 1364 qm->qp_base = HZIP_PF_DEF_Q_BASE; 1365 qm->qp_num = pf_q_num; 1366 qm->debug.curr_qm_qp_num = pf_q_num; 1367 qm->qm_list = &zip_devices; 1368 qm->err_ini = &hisi_zip_err_ini; 1369 if (pf_q_num_flag) 1370 set_bit(QM_MODULE_PARAM, &qm->misc_ctl); 1371 } else if (qm->fun_type == QM_HW_VF && qm->ver == QM_HW_V1) { 1372 /* 1373 * have no way to get qm configure in VM in v1 hardware, 1374 * so currently force PF to uses HZIP_PF_DEF_Q_NUM, and force 1375 * to trigger only one VF in v1 hardware. 1376 * 1377 * v2 hardware has no such problem. 1378 */ 1379 qm->qp_base = HZIP_PF_DEF_Q_NUM; 1380 qm->qp_num = HZIP_QUEUE_NUM_V1 - HZIP_PF_DEF_Q_NUM; 1381 } 1382 1383 ret = hisi_qm_init(qm); 1384 if (ret) { 1385 pci_err(qm->pdev, "Failed to init zip qm configures!\n"); 1386 return ret; 1387 } 1388 1389 /* Fetch and save the value of capability registers */ 1390 ret = zip_pre_store_cap_reg(qm); 1391 if (ret) { 1392 pci_err(qm->pdev, "Failed to pre-store capability registers!\n"); 1393 goto err_qm_uninit; 1394 } 1395 1396 alg_msk = qm->cap_tables.dev_cap_table[ZIP_ALG_BITMAP].cap_val; 1397 ret = hisi_qm_set_algs(qm, alg_msk, zip_dev_algs, ARRAY_SIZE(zip_dev_algs)); 1398 if (ret) { 1399 pci_err(qm->pdev, "Failed to set zip algs!\n"); 1400 goto err_qm_uninit; 1401 } 1402 1403 ret = hisi_dae_set_alg(qm); 1404 if (ret) 1405 goto err_qm_uninit; 1406 1407 return 0; 1408 1409 err_qm_uninit: 1410 hisi_qm_uninit(qm); 1411 return ret; 1412 } 1413 1414 static void hisi_zip_qm_uninit(struct hisi_qm *qm) 1415 { 1416 hisi_qm_uninit(qm); 1417 } 1418 1419 static int hisi_zip_probe_init(struct hisi_zip *hisi_zip) 1420 { 1421 u32 type_rate = HZIP_SHAPER_RATE_COMPRESS; 1422 struct hisi_qm *qm = &hisi_zip->qm; 1423 int ret; 1424 1425 if (qm->fun_type == QM_HW_PF) { 1426 ret = hisi_zip_pf_probe_init(hisi_zip); 1427 if (ret) 1428 return ret; 1429 /* enable shaper type 0 */ 1430 if (qm->ver >= QM_HW_V3) { 1431 type_rate |= QM_SHAPER_ENABLE; 1432 1433 /* ZIP need to enable shaper type 1 */ 1434 type_rate |= HZIP_SHAPER_RATE_DECOMPRESS << QM_SHAPER_TYPE1_OFFSET; 1435 qm->type_rate = type_rate; 1436 } 1437 } 1438 1439 return 0; 1440 } 1441 1442 static void hisi_zip_probe_uninit(struct hisi_qm *qm) 1443 { 1444 if (qm->fun_type == QM_HW_VF) 1445 return; 1446 1447 hisi_zip_show_last_regs_uninit(qm); 1448 hisi_zip_close_sva_prefetch(qm); 1449 hisi_qm_dev_err_uninit(qm); 1450 } 1451 1452 static int hisi_zip_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1453 { 1454 struct hisi_zip *hisi_zip; 1455 struct hisi_qm *qm; 1456 int ret; 1457 1458 hisi_zip = devm_kzalloc(&pdev->dev, sizeof(*hisi_zip), GFP_KERNEL); 1459 if (!hisi_zip) 1460 return -ENOMEM; 1461 1462 qm = &hisi_zip->qm; 1463 1464 ret = hisi_zip_qm_init(qm, pdev); 1465 if (ret) { 1466 pci_err(pdev, "Failed to init ZIP QM (%d)!\n", ret); 1467 return ret; 1468 } 1469 1470 ret = hisi_zip_probe_init(hisi_zip); 1471 if (ret) { 1472 pci_err(pdev, "Failed to probe (%d)!\n", ret); 1473 goto err_qm_uninit; 1474 } 1475 1476 ret = hisi_qm_start(qm); 1477 if (ret) 1478 goto err_probe_uninit; 1479 1480 ret = hisi_zip_debugfs_init(qm); 1481 if (ret) 1482 pci_err(pdev, "failed to init debugfs (%d)!\n", ret); 1483 1484 hisi_qm_add_list(qm, &zip_devices); 1485 ret = hisi_qm_alg_register(qm, &zip_devices, HZIP_CTX_Q_NUM_DEF); 1486 if (ret < 0) { 1487 pci_err(pdev, "failed to register driver to crypto!\n"); 1488 goto err_qm_del_list; 1489 } 1490 1491 if (qm->uacce) { 1492 ret = uacce_register(qm->uacce); 1493 if (ret) { 1494 pci_err(pdev, "failed to register uacce (%d)!\n", ret); 1495 goto err_qm_alg_unregister; 1496 } 1497 } 1498 1499 if (qm->fun_type == QM_HW_PF && vfs_num > 0) { 1500 ret = hisi_qm_sriov_enable(pdev, vfs_num); 1501 if (ret < 0) 1502 goto err_qm_alg_unregister; 1503 } 1504 1505 hisi_qm_pm_init(qm); 1506 1507 return 0; 1508 1509 err_qm_alg_unregister: 1510 hisi_qm_alg_unregister(qm, &zip_devices, HZIP_CTX_Q_NUM_DEF); 1511 1512 err_qm_del_list: 1513 hisi_qm_del_list(qm, &zip_devices); 1514 hisi_zip_debugfs_exit(qm); 1515 hisi_qm_stop(qm, QM_NORMAL); 1516 1517 err_probe_uninit: 1518 hisi_zip_probe_uninit(qm); 1519 1520 err_qm_uninit: 1521 hisi_zip_qm_uninit(qm); 1522 1523 return ret; 1524 } 1525 1526 static void hisi_zip_remove(struct pci_dev *pdev) 1527 { 1528 struct hisi_qm *qm = pci_get_drvdata(pdev); 1529 1530 hisi_qm_pm_uninit(qm); 1531 hisi_qm_wait_task_finish(qm, &zip_devices); 1532 hisi_qm_alg_unregister(qm, &zip_devices, HZIP_CTX_Q_NUM_DEF); 1533 hisi_qm_del_list(qm, &zip_devices); 1534 1535 if (qm->fun_type == QM_HW_PF && qm->vfs_num) 1536 hisi_qm_sriov_disable(pdev, true); 1537 1538 hisi_zip_debugfs_exit(qm); 1539 hisi_qm_stop(qm, QM_NORMAL); 1540 hisi_zip_probe_uninit(qm); 1541 hisi_zip_qm_uninit(qm); 1542 } 1543 1544 static const struct dev_pm_ops hisi_zip_pm_ops = { 1545 SET_RUNTIME_PM_OPS(hisi_qm_suspend, hisi_qm_resume, NULL) 1546 }; 1547 1548 static const struct pci_error_handlers hisi_zip_err_handler = { 1549 .error_detected = hisi_qm_dev_err_detected, 1550 .slot_reset = hisi_qm_dev_slot_reset, 1551 .reset_prepare = hisi_qm_reset_prepare, 1552 .reset_done = hisi_qm_reset_done, 1553 }; 1554 1555 static struct pci_driver hisi_zip_pci_driver = { 1556 .name = "hisi_zip", 1557 .id_table = hisi_zip_dev_ids, 1558 .probe = hisi_zip_probe, 1559 .remove = hisi_zip_remove, 1560 .sriov_configure = IS_ENABLED(CONFIG_PCI_IOV) ? 1561 hisi_qm_sriov_configure : NULL, 1562 .err_handler = &hisi_zip_err_handler, 1563 .shutdown = hisi_qm_dev_shutdown, 1564 .driver.pm = &hisi_zip_pm_ops, 1565 }; 1566 1567 struct pci_driver *hisi_zip_get_pf_driver(void) 1568 { 1569 return &hisi_zip_pci_driver; 1570 } 1571 EXPORT_SYMBOL_GPL(hisi_zip_get_pf_driver); 1572 1573 static void hisi_zip_register_debugfs(void) 1574 { 1575 if (!debugfs_initialized()) 1576 return; 1577 1578 hzip_debugfs_root = debugfs_create_dir("hisi_zip", NULL); 1579 } 1580 1581 static void hisi_zip_unregister_debugfs(void) 1582 { 1583 debugfs_remove_recursive(hzip_debugfs_root); 1584 } 1585 1586 static int __init hisi_zip_init(void) 1587 { 1588 int ret; 1589 1590 hisi_qm_init_list(&zip_devices); 1591 hisi_zip_register_debugfs(); 1592 1593 ret = pci_register_driver(&hisi_zip_pci_driver); 1594 if (ret < 0) { 1595 hisi_zip_unregister_debugfs(); 1596 pr_err("Failed to register pci driver.\n"); 1597 } 1598 1599 return ret; 1600 } 1601 1602 static void __exit hisi_zip_exit(void) 1603 { 1604 pci_unregister_driver(&hisi_zip_pci_driver); 1605 hisi_zip_unregister_debugfs(); 1606 } 1607 1608 module_init(hisi_zip_init); 1609 module_exit(hisi_zip_exit); 1610 1611 MODULE_LICENSE("GPL v2"); 1612 MODULE_AUTHOR("Zhou Wang <wangzhou1@hisilicon.com>"); 1613 MODULE_DESCRIPTION("Driver for HiSilicon ZIP accelerator"); 1614