1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2019 HiSilicon Limited. */ 3 #include <linux/acpi.h> 4 #include <linux/aer.h> 5 #include <linux/bitops.h> 6 #include <linux/debugfs.h> 7 #include <linux/init.h> 8 #include <linux/io.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 #include <linux/seq_file.h> 13 #include <linux/topology.h> 14 #include <linux/uacce.h> 15 #include "zip.h" 16 17 #define PCI_DEVICE_ID_ZIP_PF 0xa250 18 #define PCI_DEVICE_ID_ZIP_VF 0xa251 19 20 #define HZIP_QUEUE_NUM_V1 4096 21 22 #define HZIP_CLOCK_GATE_CTRL 0x301004 23 #define COMP0_ENABLE BIT(0) 24 #define COMP1_ENABLE BIT(1) 25 #define DECOMP0_ENABLE BIT(2) 26 #define DECOMP1_ENABLE BIT(3) 27 #define DECOMP2_ENABLE BIT(4) 28 #define DECOMP3_ENABLE BIT(5) 29 #define DECOMP4_ENABLE BIT(6) 30 #define DECOMP5_ENABLE BIT(7) 31 #define HZIP_ALL_COMP_DECOMP_EN (COMP0_ENABLE | COMP1_ENABLE | \ 32 DECOMP0_ENABLE | DECOMP1_ENABLE | \ 33 DECOMP2_ENABLE | DECOMP3_ENABLE | \ 34 DECOMP4_ENABLE | DECOMP5_ENABLE) 35 #define HZIP_DECOMP_CHECK_ENABLE BIT(16) 36 #define HZIP_FSM_MAX_CNT 0x301008 37 38 #define HZIP_PORT_ARCA_CHE_0 0x301040 39 #define HZIP_PORT_ARCA_CHE_1 0x301044 40 #define HZIP_PORT_AWCA_CHE_0 0x301060 41 #define HZIP_PORT_AWCA_CHE_1 0x301064 42 #define HZIP_CACHE_ALL_EN 0xffffffff 43 44 #define HZIP_BD_RUSER_32_63 0x301110 45 #define HZIP_SGL_RUSER_32_63 0x30111c 46 #define HZIP_DATA_RUSER_32_63 0x301128 47 #define HZIP_DATA_WUSER_32_63 0x301134 48 #define HZIP_BD_WUSER_32_63 0x301140 49 50 #define HZIP_QM_IDEL_STATUS 0x3040e4 51 52 #define HZIP_CORE_DEBUG_COMP_0 0x302000 53 #define HZIP_CORE_DEBUG_COMP_1 0x303000 54 #define HZIP_CORE_DEBUG_DECOMP_0 0x304000 55 #define HZIP_CORE_DEBUG_DECOMP_1 0x305000 56 #define HZIP_CORE_DEBUG_DECOMP_2 0x306000 57 #define HZIP_CORE_DEBUG_DECOMP_3 0x307000 58 #define HZIP_CORE_DEBUG_DECOMP_4 0x308000 59 #define HZIP_CORE_DEBUG_DECOMP_5 0x309000 60 61 #define HZIP_CORE_INT_SOURCE 0x3010A0 62 #define HZIP_CORE_INT_MASK_REG 0x3010A4 63 #define HZIP_CORE_INT_SET 0x3010A8 64 #define HZIP_CORE_INT_STATUS 0x3010AC 65 #define HZIP_CORE_INT_STATUS_M_ECC BIT(1) 66 #define HZIP_CORE_SRAM_ECC_ERR_INFO 0x301148 67 #define HZIP_CORE_INT_RAS_CE_ENB 0x301160 68 #define HZIP_CORE_INT_RAS_CE_ENABLE 0x1 69 #define HZIP_CORE_INT_RAS_NFE_ENB 0x301164 70 #define HZIP_CORE_INT_RAS_FE_ENB 0x301168 71 #define HZIP_OOO_SHUTDOWN_SEL 0x30120C 72 #define HZIP_CORE_INT_RAS_NFE_ENABLE 0x1FFE 73 #define HZIP_SRAM_ECC_ERR_NUM_SHIFT 16 74 #define HZIP_SRAM_ECC_ERR_ADDR_SHIFT 24 75 #define HZIP_CORE_INT_MASK_ALL GENMASK(12, 0) 76 #define HZIP_COMP_CORE_NUM 2 77 #define HZIP_DECOMP_CORE_NUM 6 78 #define HZIP_CORE_NUM (HZIP_COMP_CORE_NUM + \ 79 HZIP_DECOMP_CORE_NUM) 80 #define HZIP_SQE_SIZE 128 81 #define HZIP_SQ_SIZE (HZIP_SQE_SIZE * QM_Q_DEPTH) 82 #define HZIP_PF_DEF_Q_NUM 64 83 #define HZIP_PF_DEF_Q_BASE 0 84 85 #define HZIP_SOFT_CTRL_CNT_CLR_CE 0x301000 86 #define HZIP_SOFT_CTRL_CNT_CLR_CE_BIT BIT(0) 87 #define HZIP_SOFT_CTRL_ZIP_CONTROL 0x30100C 88 #define HZIP_AXI_SHUTDOWN_ENABLE BIT(14) 89 #define HZIP_WR_PORT BIT(11) 90 91 #define HZIP_BUF_SIZE 22 92 #define HZIP_SQE_MASK_OFFSET 64 93 #define HZIP_SQE_MASK_LEN 48 94 95 #define HZIP_CNT_CLR_CE_EN BIT(0) 96 #define HZIP_RO_CNT_CLR_CE_EN BIT(2) 97 #define HZIP_RD_CNT_CLR_CE_EN (HZIP_CNT_CLR_CE_EN | \ 98 HZIP_RO_CNT_CLR_CE_EN) 99 100 #define HZIP_PREFETCH_CFG 0x3011B0 101 #define HZIP_SVA_TRANS 0x3011C4 102 #define HZIP_PREFETCH_ENABLE (~(BIT(26) | BIT(17) | BIT(0))) 103 #define HZIP_SVA_PREFETCH_DISABLE BIT(26) 104 #define HZIP_SVA_DISABLE_READY (BIT(26) | BIT(30)) 105 #define HZIP_SHAPER_RATE_COMPRESS 252 106 #define HZIP_SHAPER_RATE_DECOMPRESS 229 107 #define HZIP_DELAY_1_US 1 108 #define HZIP_POLL_TIMEOUT_US 1000 109 110 static const char hisi_zip_name[] = "hisi_zip"; 111 static struct dentry *hzip_debugfs_root; 112 113 struct hisi_zip_hw_error { 114 u32 int_msk; 115 const char *msg; 116 }; 117 118 struct zip_dfx_item { 119 const char *name; 120 u32 offset; 121 }; 122 123 static struct hisi_qm_list zip_devices = { 124 .register_to_crypto = hisi_zip_register_to_crypto, 125 .unregister_from_crypto = hisi_zip_unregister_from_crypto, 126 }; 127 128 static struct zip_dfx_item zip_dfx_files[] = { 129 {"send_cnt", offsetof(struct hisi_zip_dfx, send_cnt)}, 130 {"recv_cnt", offsetof(struct hisi_zip_dfx, recv_cnt)}, 131 {"send_busy_cnt", offsetof(struct hisi_zip_dfx, send_busy_cnt)}, 132 {"err_bd_cnt", offsetof(struct hisi_zip_dfx, err_bd_cnt)}, 133 }; 134 135 static const struct hisi_zip_hw_error zip_hw_error[] = { 136 { .int_msk = BIT(0), .msg = "zip_ecc_1bitt_err" }, 137 { .int_msk = BIT(1), .msg = "zip_ecc_2bit_err" }, 138 { .int_msk = BIT(2), .msg = "zip_axi_rresp_err" }, 139 { .int_msk = BIT(3), .msg = "zip_axi_bresp_err" }, 140 { .int_msk = BIT(4), .msg = "zip_src_addr_parse_err" }, 141 { .int_msk = BIT(5), .msg = "zip_dst_addr_parse_err" }, 142 { .int_msk = BIT(6), .msg = "zip_pre_in_addr_err" }, 143 { .int_msk = BIT(7), .msg = "zip_pre_in_data_err" }, 144 { .int_msk = BIT(8), .msg = "zip_com_inf_err" }, 145 { .int_msk = BIT(9), .msg = "zip_enc_inf_err" }, 146 { .int_msk = BIT(10), .msg = "zip_pre_out_err" }, 147 { .int_msk = BIT(11), .msg = "zip_axi_poison_err" }, 148 { .int_msk = BIT(12), .msg = "zip_sva_err" }, 149 { /* sentinel */ } 150 }; 151 152 enum ctrl_debug_file_index { 153 HZIP_CLEAR_ENABLE, 154 HZIP_DEBUG_FILE_NUM, 155 }; 156 157 static const char * const ctrl_debug_file_name[] = { 158 [HZIP_CLEAR_ENABLE] = "clear_enable", 159 }; 160 161 struct ctrl_debug_file { 162 enum ctrl_debug_file_index index; 163 spinlock_t lock; 164 struct hisi_zip_ctrl *ctrl; 165 }; 166 167 /* 168 * One ZIP controller has one PF and multiple VFs, some global configurations 169 * which PF has need this structure. 170 * 171 * Just relevant for PF. 172 */ 173 struct hisi_zip_ctrl { 174 struct hisi_zip *hisi_zip; 175 struct ctrl_debug_file files[HZIP_DEBUG_FILE_NUM]; 176 }; 177 178 enum { 179 HZIP_COMP_CORE0, 180 HZIP_COMP_CORE1, 181 HZIP_DECOMP_CORE0, 182 HZIP_DECOMP_CORE1, 183 HZIP_DECOMP_CORE2, 184 HZIP_DECOMP_CORE3, 185 HZIP_DECOMP_CORE4, 186 HZIP_DECOMP_CORE5, 187 }; 188 189 static const u64 core_offsets[] = { 190 [HZIP_COMP_CORE0] = 0x302000, 191 [HZIP_COMP_CORE1] = 0x303000, 192 [HZIP_DECOMP_CORE0] = 0x304000, 193 [HZIP_DECOMP_CORE1] = 0x305000, 194 [HZIP_DECOMP_CORE2] = 0x306000, 195 [HZIP_DECOMP_CORE3] = 0x307000, 196 [HZIP_DECOMP_CORE4] = 0x308000, 197 [HZIP_DECOMP_CORE5] = 0x309000, 198 }; 199 200 static const struct debugfs_reg32 hzip_dfx_regs[] = { 201 {"HZIP_GET_BD_NUM ", 0x00ull}, 202 {"HZIP_GET_RIGHT_BD ", 0x04ull}, 203 {"HZIP_GET_ERROR_BD ", 0x08ull}, 204 {"HZIP_DONE_BD_NUM ", 0x0cull}, 205 {"HZIP_WORK_CYCLE ", 0x10ull}, 206 {"HZIP_IDLE_CYCLE ", 0x18ull}, 207 {"HZIP_MAX_DELAY ", 0x20ull}, 208 {"HZIP_MIN_DELAY ", 0x24ull}, 209 {"HZIP_AVG_DELAY ", 0x28ull}, 210 {"HZIP_MEM_VISIBLE_DATA ", 0x30ull}, 211 {"HZIP_MEM_VISIBLE_ADDR ", 0x34ull}, 212 {"HZIP_COMSUMED_BYTE ", 0x38ull}, 213 {"HZIP_PRODUCED_BYTE ", 0x40ull}, 214 {"HZIP_COMP_INF ", 0x70ull}, 215 {"HZIP_PRE_OUT ", 0x78ull}, 216 {"HZIP_BD_RD ", 0x7cull}, 217 {"HZIP_BD_WR ", 0x80ull}, 218 {"HZIP_GET_BD_AXI_ERR_NUM ", 0x84ull}, 219 {"HZIP_GET_BD_PARSE_ERR_NUM ", 0x88ull}, 220 {"HZIP_ADD_BD_AXI_ERR_NUM ", 0x8cull}, 221 {"HZIP_DECOMP_STF_RELOAD_CURR_ST ", 0x94ull}, 222 {"HZIP_DECOMP_LZ77_CURR_ST ", 0x9cull}, 223 }; 224 225 static const struct kernel_param_ops zip_uacce_mode_ops = { 226 .set = uacce_mode_set, 227 .get = param_get_int, 228 }; 229 230 /* 231 * uacce_mode = 0 means zip only register to crypto, 232 * uacce_mode = 1 means zip both register to crypto and uacce. 233 */ 234 static u32 uacce_mode = UACCE_MODE_NOUACCE; 235 module_param_cb(uacce_mode, &zip_uacce_mode_ops, &uacce_mode, 0444); 236 MODULE_PARM_DESC(uacce_mode, UACCE_MODE_DESC); 237 238 static int pf_q_num_set(const char *val, const struct kernel_param *kp) 239 { 240 return q_num_set(val, kp, PCI_DEVICE_ID_ZIP_PF); 241 } 242 243 static const struct kernel_param_ops pf_q_num_ops = { 244 .set = pf_q_num_set, 245 .get = param_get_int, 246 }; 247 248 static u32 pf_q_num = HZIP_PF_DEF_Q_NUM; 249 module_param_cb(pf_q_num, &pf_q_num_ops, &pf_q_num, 0444); 250 MODULE_PARM_DESC(pf_q_num, "Number of queues in PF(v1 2-4096, v2 2-1024)"); 251 252 static const struct kernel_param_ops vfs_num_ops = { 253 .set = vfs_num_set, 254 .get = param_get_int, 255 }; 256 257 static u32 vfs_num; 258 module_param_cb(vfs_num, &vfs_num_ops, &vfs_num, 0444); 259 MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63), 0(default)"); 260 261 static const struct pci_device_id hisi_zip_dev_ids[] = { 262 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_ZIP_PF) }, 263 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_ZIP_VF) }, 264 { 0, } 265 }; 266 MODULE_DEVICE_TABLE(pci, hisi_zip_dev_ids); 267 268 int zip_create_qps(struct hisi_qp **qps, int qp_num, int node) 269 { 270 if (node == NUMA_NO_NODE) 271 node = cpu_to_node(smp_processor_id()); 272 273 return hisi_qm_alloc_qps_node(&zip_devices, qp_num, 0, node, qps); 274 } 275 276 static void hisi_zip_open_sva_prefetch(struct hisi_qm *qm) 277 { 278 u32 val; 279 int ret; 280 281 if (qm->ver < QM_HW_V3) 282 return; 283 284 /* Enable prefetch */ 285 val = readl_relaxed(qm->io_base + HZIP_PREFETCH_CFG); 286 val &= HZIP_PREFETCH_ENABLE; 287 writel(val, qm->io_base + HZIP_PREFETCH_CFG); 288 289 ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_PREFETCH_CFG, 290 val, !(val & HZIP_SVA_PREFETCH_DISABLE), 291 HZIP_DELAY_1_US, HZIP_POLL_TIMEOUT_US); 292 if (ret) 293 pci_err(qm->pdev, "failed to open sva prefetch\n"); 294 } 295 296 static void hisi_zip_close_sva_prefetch(struct hisi_qm *qm) 297 { 298 u32 val; 299 int ret; 300 301 if (qm->ver < QM_HW_V3) 302 return; 303 304 val = readl_relaxed(qm->io_base + HZIP_PREFETCH_CFG); 305 val |= HZIP_SVA_PREFETCH_DISABLE; 306 writel(val, qm->io_base + HZIP_PREFETCH_CFG); 307 308 ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_SVA_TRANS, 309 val, !(val & HZIP_SVA_DISABLE_READY), 310 HZIP_DELAY_1_US, HZIP_POLL_TIMEOUT_US); 311 if (ret) 312 pci_err(qm->pdev, "failed to close sva prefetch\n"); 313 } 314 315 static int hisi_zip_set_user_domain_and_cache(struct hisi_qm *qm) 316 { 317 void __iomem *base = qm->io_base; 318 319 /* qm user domain */ 320 writel(AXUSER_BASE, base + QM_ARUSER_M_CFG_1); 321 writel(ARUSER_M_CFG_ENABLE, base + QM_ARUSER_M_CFG_ENABLE); 322 writel(AXUSER_BASE, base + QM_AWUSER_M_CFG_1); 323 writel(AWUSER_M_CFG_ENABLE, base + QM_AWUSER_M_CFG_ENABLE); 324 writel(WUSER_M_CFG_ENABLE, base + QM_WUSER_M_CFG_ENABLE); 325 326 /* qm cache */ 327 writel(AXI_M_CFG, base + QM_AXI_M_CFG); 328 writel(AXI_M_CFG_ENABLE, base + QM_AXI_M_CFG_ENABLE); 329 330 /* disable FLR triggered by BME(bus master enable) */ 331 writel(PEH_AXUSER_CFG, base + QM_PEH_AXUSER_CFG); 332 writel(PEH_AXUSER_CFG_ENABLE, base + QM_PEH_AXUSER_CFG_ENABLE); 333 334 /* cache */ 335 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_ARCA_CHE_0); 336 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_ARCA_CHE_1); 337 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_AWCA_CHE_0); 338 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_AWCA_CHE_1); 339 340 /* user domain configurations */ 341 writel(AXUSER_BASE, base + HZIP_BD_RUSER_32_63); 342 writel(AXUSER_BASE, base + HZIP_SGL_RUSER_32_63); 343 writel(AXUSER_BASE, base + HZIP_BD_WUSER_32_63); 344 345 if (qm->use_sva && qm->ver == QM_HW_V2) { 346 writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_DATA_RUSER_32_63); 347 writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_DATA_WUSER_32_63); 348 } else { 349 writel(AXUSER_BASE, base + HZIP_DATA_RUSER_32_63); 350 writel(AXUSER_BASE, base + HZIP_DATA_WUSER_32_63); 351 } 352 353 /* let's open all compression/decompression cores */ 354 writel(HZIP_DECOMP_CHECK_ENABLE | HZIP_ALL_COMP_DECOMP_EN, 355 base + HZIP_CLOCK_GATE_CTRL); 356 357 /* enable sqc,cqc writeback */ 358 writel(SQC_CACHE_ENABLE | CQC_CACHE_ENABLE | SQC_CACHE_WB_ENABLE | 359 CQC_CACHE_WB_ENABLE | FIELD_PREP(SQC_CACHE_WB_THRD, 1) | 360 FIELD_PREP(CQC_CACHE_WB_THRD, 1), base + QM_CACHE_CTL); 361 362 return 0; 363 } 364 365 static void hisi_zip_master_ooo_ctrl(struct hisi_qm *qm, bool enable) 366 { 367 u32 val1, val2; 368 369 val1 = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 370 if (enable) { 371 val1 |= HZIP_AXI_SHUTDOWN_ENABLE; 372 val2 = HZIP_CORE_INT_RAS_NFE_ENABLE; 373 } else { 374 val1 &= ~HZIP_AXI_SHUTDOWN_ENABLE; 375 val2 = 0x0; 376 } 377 378 if (qm->ver > QM_HW_V2) 379 writel(val2, qm->io_base + HZIP_OOO_SHUTDOWN_SEL); 380 381 writel(val1, qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 382 } 383 384 static void hisi_zip_hw_error_enable(struct hisi_qm *qm) 385 { 386 if (qm->ver == QM_HW_V1) { 387 writel(HZIP_CORE_INT_MASK_ALL, 388 qm->io_base + HZIP_CORE_INT_MASK_REG); 389 dev_info(&qm->pdev->dev, "Does not support hw error handle\n"); 390 return; 391 } 392 393 /* clear ZIP hw error source if having */ 394 writel(HZIP_CORE_INT_MASK_ALL, qm->io_base + HZIP_CORE_INT_SOURCE); 395 396 /* configure error type */ 397 writel(HZIP_CORE_INT_RAS_CE_ENABLE, 398 qm->io_base + HZIP_CORE_INT_RAS_CE_ENB); 399 writel(0x0, qm->io_base + HZIP_CORE_INT_RAS_FE_ENB); 400 writel(HZIP_CORE_INT_RAS_NFE_ENABLE, 401 qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); 402 403 /* enable ZIP block master OOO when nfe occurs on Kunpeng930 */ 404 hisi_zip_master_ooo_ctrl(qm, true); 405 406 /* enable ZIP hw error interrupts */ 407 writel(0, qm->io_base + HZIP_CORE_INT_MASK_REG); 408 } 409 410 static void hisi_zip_hw_error_disable(struct hisi_qm *qm) 411 { 412 /* disable ZIP hw error interrupts */ 413 writel(HZIP_CORE_INT_MASK_ALL, qm->io_base + HZIP_CORE_INT_MASK_REG); 414 415 /* disable ZIP block master OOO when nfe occurs on Kunpeng930 */ 416 hisi_zip_master_ooo_ctrl(qm, false); 417 } 418 419 static inline struct hisi_qm *file_to_qm(struct ctrl_debug_file *file) 420 { 421 struct hisi_zip *hisi_zip = file->ctrl->hisi_zip; 422 423 return &hisi_zip->qm; 424 } 425 426 static u32 clear_enable_read(struct ctrl_debug_file *file) 427 { 428 struct hisi_qm *qm = file_to_qm(file); 429 430 return readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) & 431 HZIP_SOFT_CTRL_CNT_CLR_CE_BIT; 432 } 433 434 static int clear_enable_write(struct ctrl_debug_file *file, u32 val) 435 { 436 struct hisi_qm *qm = file_to_qm(file); 437 u32 tmp; 438 439 if (val != 1 && val != 0) 440 return -EINVAL; 441 442 tmp = (readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) & 443 ~HZIP_SOFT_CTRL_CNT_CLR_CE_BIT) | val; 444 writel(tmp, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE); 445 446 return 0; 447 } 448 449 static ssize_t hisi_zip_ctrl_debug_read(struct file *filp, char __user *buf, 450 size_t count, loff_t *pos) 451 { 452 struct ctrl_debug_file *file = filp->private_data; 453 char tbuf[HZIP_BUF_SIZE]; 454 u32 val; 455 int ret; 456 457 spin_lock_irq(&file->lock); 458 switch (file->index) { 459 case HZIP_CLEAR_ENABLE: 460 val = clear_enable_read(file); 461 break; 462 default: 463 spin_unlock_irq(&file->lock); 464 return -EINVAL; 465 } 466 spin_unlock_irq(&file->lock); 467 ret = scnprintf(tbuf, sizeof(tbuf), "%u\n", val); 468 return simple_read_from_buffer(buf, count, pos, tbuf, ret); 469 } 470 471 static ssize_t hisi_zip_ctrl_debug_write(struct file *filp, 472 const char __user *buf, 473 size_t count, loff_t *pos) 474 { 475 struct ctrl_debug_file *file = filp->private_data; 476 char tbuf[HZIP_BUF_SIZE]; 477 unsigned long val; 478 int len, ret; 479 480 if (*pos != 0) 481 return 0; 482 483 if (count >= HZIP_BUF_SIZE) 484 return -ENOSPC; 485 486 len = simple_write_to_buffer(tbuf, HZIP_BUF_SIZE - 1, pos, buf, count); 487 if (len < 0) 488 return len; 489 490 tbuf[len] = '\0'; 491 if (kstrtoul(tbuf, 0, &val)) 492 return -EFAULT; 493 494 spin_lock_irq(&file->lock); 495 switch (file->index) { 496 case HZIP_CLEAR_ENABLE: 497 ret = clear_enable_write(file, val); 498 if (ret) 499 goto err_input; 500 break; 501 default: 502 ret = -EINVAL; 503 goto err_input; 504 } 505 spin_unlock_irq(&file->lock); 506 507 return count; 508 509 err_input: 510 spin_unlock_irq(&file->lock); 511 return ret; 512 } 513 514 static const struct file_operations ctrl_debug_fops = { 515 .owner = THIS_MODULE, 516 .open = simple_open, 517 .read = hisi_zip_ctrl_debug_read, 518 .write = hisi_zip_ctrl_debug_write, 519 }; 520 521 static int zip_debugfs_atomic64_set(void *data, u64 val) 522 { 523 if (val) 524 return -EINVAL; 525 526 atomic64_set((atomic64_t *)data, 0); 527 528 return 0; 529 } 530 531 static int zip_debugfs_atomic64_get(void *data, u64 *val) 532 { 533 *val = atomic64_read((atomic64_t *)data); 534 535 return 0; 536 } 537 538 DEFINE_DEBUGFS_ATTRIBUTE(zip_atomic64_ops, zip_debugfs_atomic64_get, 539 zip_debugfs_atomic64_set, "%llu\n"); 540 541 static int hisi_zip_core_debug_init(struct hisi_qm *qm) 542 { 543 struct device *dev = &qm->pdev->dev; 544 struct debugfs_regset32 *regset; 545 struct dentry *tmp_d; 546 char buf[HZIP_BUF_SIZE]; 547 int i; 548 549 for (i = 0; i < HZIP_CORE_NUM; i++) { 550 if (i < HZIP_COMP_CORE_NUM) 551 scnprintf(buf, sizeof(buf), "comp_core%d", i); 552 else 553 scnprintf(buf, sizeof(buf), "decomp_core%d", 554 i - HZIP_COMP_CORE_NUM); 555 556 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); 557 if (!regset) 558 return -ENOENT; 559 560 regset->regs = hzip_dfx_regs; 561 regset->nregs = ARRAY_SIZE(hzip_dfx_regs); 562 regset->base = qm->io_base + core_offsets[i]; 563 564 tmp_d = debugfs_create_dir(buf, qm->debug.debug_root); 565 debugfs_create_regset32("regs", 0444, tmp_d, regset); 566 } 567 568 return 0; 569 } 570 571 static void hisi_zip_dfx_debug_init(struct hisi_qm *qm) 572 { 573 struct hisi_zip *zip = container_of(qm, struct hisi_zip, qm); 574 struct hisi_zip_dfx *dfx = &zip->dfx; 575 struct dentry *tmp_dir; 576 void *data; 577 int i; 578 579 tmp_dir = debugfs_create_dir("zip_dfx", qm->debug.debug_root); 580 for (i = 0; i < ARRAY_SIZE(zip_dfx_files); i++) { 581 data = (atomic64_t *)((uintptr_t)dfx + zip_dfx_files[i].offset); 582 debugfs_create_file(zip_dfx_files[i].name, 583 0644, tmp_dir, data, 584 &zip_atomic64_ops); 585 } 586 } 587 588 static int hisi_zip_ctrl_debug_init(struct hisi_qm *qm) 589 { 590 struct hisi_zip *zip = container_of(qm, struct hisi_zip, qm); 591 int i; 592 593 for (i = HZIP_CLEAR_ENABLE; i < HZIP_DEBUG_FILE_NUM; i++) { 594 spin_lock_init(&zip->ctrl->files[i].lock); 595 zip->ctrl->files[i].ctrl = zip->ctrl; 596 zip->ctrl->files[i].index = i; 597 598 debugfs_create_file(ctrl_debug_file_name[i], 0600, 599 qm->debug.debug_root, 600 zip->ctrl->files + i, 601 &ctrl_debug_fops); 602 } 603 604 return hisi_zip_core_debug_init(qm); 605 } 606 607 static int hisi_zip_debugfs_init(struct hisi_qm *qm) 608 { 609 struct device *dev = &qm->pdev->dev; 610 struct dentry *dev_d; 611 int ret; 612 613 dev_d = debugfs_create_dir(dev_name(dev), hzip_debugfs_root); 614 615 qm->debug.sqe_mask_offset = HZIP_SQE_MASK_OFFSET; 616 qm->debug.sqe_mask_len = HZIP_SQE_MASK_LEN; 617 qm->debug.debug_root = dev_d; 618 hisi_qm_debug_init(qm); 619 620 if (qm->fun_type == QM_HW_PF) { 621 ret = hisi_zip_ctrl_debug_init(qm); 622 if (ret) 623 goto failed_to_create; 624 } 625 626 hisi_zip_dfx_debug_init(qm); 627 628 return 0; 629 630 failed_to_create: 631 debugfs_remove_recursive(hzip_debugfs_root); 632 return ret; 633 } 634 635 /* hisi_zip_debug_regs_clear() - clear the zip debug regs */ 636 static void hisi_zip_debug_regs_clear(struct hisi_qm *qm) 637 { 638 int i, j; 639 640 /* enable register read_clear bit */ 641 writel(HZIP_RD_CNT_CLR_CE_EN, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE); 642 for (i = 0; i < ARRAY_SIZE(core_offsets); i++) 643 for (j = 0; j < ARRAY_SIZE(hzip_dfx_regs); j++) 644 readl(qm->io_base + core_offsets[i] + 645 hzip_dfx_regs[j].offset); 646 647 /* disable register read_clear bit */ 648 writel(0x0, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE); 649 650 hisi_qm_debug_regs_clear(qm); 651 } 652 653 static void hisi_zip_debugfs_exit(struct hisi_qm *qm) 654 { 655 debugfs_remove_recursive(qm->debug.debug_root); 656 657 if (qm->fun_type == QM_HW_PF) { 658 hisi_zip_debug_regs_clear(qm); 659 qm->debug.curr_qm_qp_num = 0; 660 } 661 } 662 663 static void hisi_zip_log_hw_error(struct hisi_qm *qm, u32 err_sts) 664 { 665 const struct hisi_zip_hw_error *err = zip_hw_error; 666 struct device *dev = &qm->pdev->dev; 667 u32 err_val; 668 669 while (err->msg) { 670 if (err->int_msk & err_sts) { 671 dev_err(dev, "%s [error status=0x%x] found\n", 672 err->msg, err->int_msk); 673 674 if (err->int_msk & HZIP_CORE_INT_STATUS_M_ECC) { 675 err_val = readl(qm->io_base + 676 HZIP_CORE_SRAM_ECC_ERR_INFO); 677 dev_err(dev, "hisi-zip multi ecc sram num=0x%x\n", 678 ((err_val >> 679 HZIP_SRAM_ECC_ERR_NUM_SHIFT) & 0xFF)); 680 } 681 } 682 err++; 683 } 684 } 685 686 static u32 hisi_zip_get_hw_err_status(struct hisi_qm *qm) 687 { 688 return readl(qm->io_base + HZIP_CORE_INT_STATUS); 689 } 690 691 static void hisi_zip_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts) 692 { 693 writel(err_sts, qm->io_base + HZIP_CORE_INT_SOURCE); 694 } 695 696 static void hisi_zip_open_axi_master_ooo(struct hisi_qm *qm) 697 { 698 u32 val; 699 700 val = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 701 702 writel(val & ~HZIP_AXI_SHUTDOWN_ENABLE, 703 qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 704 705 writel(val | HZIP_AXI_SHUTDOWN_ENABLE, 706 qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 707 } 708 709 static void hisi_zip_close_axi_master_ooo(struct hisi_qm *qm) 710 { 711 u32 nfe_enb; 712 713 /* Disable ECC Mbit error report. */ 714 nfe_enb = readl(qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); 715 writel(nfe_enb & ~HZIP_CORE_INT_STATUS_M_ECC, 716 qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); 717 718 /* Inject zip ECC Mbit error to block master ooo. */ 719 writel(HZIP_CORE_INT_STATUS_M_ECC, 720 qm->io_base + HZIP_CORE_INT_SET); 721 } 722 723 static void hisi_zip_err_info_init(struct hisi_qm *qm) 724 { 725 struct hisi_qm_err_info *err_info = &qm->err_info; 726 727 err_info->ce = QM_BASE_CE; 728 err_info->fe = 0; 729 err_info->ecc_2bits_mask = HZIP_CORE_INT_STATUS_M_ECC; 730 err_info->dev_ce_mask = HZIP_CORE_INT_RAS_CE_ENABLE; 731 err_info->msi_wr_port = HZIP_WR_PORT; 732 err_info->acpi_rst = "ZRST"; 733 err_info->nfe = QM_BASE_NFE | QM_ACC_WB_NOT_READY_TIMEOUT; 734 735 if (qm->ver >= QM_HW_V3) 736 err_info->nfe |= QM_ACC_DO_TASK_TIMEOUT; 737 } 738 739 static const struct hisi_qm_err_ini hisi_zip_err_ini = { 740 .hw_init = hisi_zip_set_user_domain_and_cache, 741 .hw_err_enable = hisi_zip_hw_error_enable, 742 .hw_err_disable = hisi_zip_hw_error_disable, 743 .get_dev_hw_err_status = hisi_zip_get_hw_err_status, 744 .clear_dev_hw_err_status = hisi_zip_clear_hw_err_status, 745 .log_dev_hw_err = hisi_zip_log_hw_error, 746 .open_axi_master_ooo = hisi_zip_open_axi_master_ooo, 747 .close_axi_master_ooo = hisi_zip_close_axi_master_ooo, 748 .open_sva_prefetch = hisi_zip_open_sva_prefetch, 749 .close_sva_prefetch = hisi_zip_close_sva_prefetch, 750 .err_info_init = hisi_zip_err_info_init, 751 }; 752 753 static int hisi_zip_pf_probe_init(struct hisi_zip *hisi_zip) 754 { 755 struct hisi_qm *qm = &hisi_zip->qm; 756 struct hisi_zip_ctrl *ctrl; 757 758 ctrl = devm_kzalloc(&qm->pdev->dev, sizeof(*ctrl), GFP_KERNEL); 759 if (!ctrl) 760 return -ENOMEM; 761 762 hisi_zip->ctrl = ctrl; 763 ctrl->hisi_zip = hisi_zip; 764 qm->err_ini = &hisi_zip_err_ini; 765 qm->err_ini->err_info_init(qm); 766 767 hisi_zip_set_user_domain_and_cache(qm); 768 hisi_zip_open_sva_prefetch(qm); 769 hisi_qm_dev_err_init(qm); 770 hisi_zip_debug_regs_clear(qm); 771 772 return 0; 773 } 774 775 static int hisi_zip_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) 776 { 777 int ret; 778 779 qm->pdev = pdev; 780 qm->ver = pdev->revision; 781 qm->algs = "zlib\ngzip"; 782 qm->mode = uacce_mode; 783 qm->sqe_size = HZIP_SQE_SIZE; 784 qm->dev_name = hisi_zip_name; 785 786 qm->fun_type = (pdev->device == PCI_DEVICE_ID_ZIP_PF) ? 787 QM_HW_PF : QM_HW_VF; 788 if (qm->fun_type == QM_HW_PF) { 789 qm->qp_base = HZIP_PF_DEF_Q_BASE; 790 qm->qp_num = pf_q_num; 791 qm->debug.curr_qm_qp_num = pf_q_num; 792 qm->qm_list = &zip_devices; 793 } else if (qm->fun_type == QM_HW_VF && qm->ver == QM_HW_V1) { 794 /* 795 * have no way to get qm configure in VM in v1 hardware, 796 * so currently force PF to uses HZIP_PF_DEF_Q_NUM, and force 797 * to trigger only one VF in v1 hardware. 798 * 799 * v2 hardware has no such problem. 800 */ 801 qm->qp_base = HZIP_PF_DEF_Q_NUM; 802 qm->qp_num = HZIP_QUEUE_NUM_V1 - HZIP_PF_DEF_Q_NUM; 803 } 804 805 qm->wq = alloc_workqueue("%s", WQ_HIGHPRI | WQ_MEM_RECLAIM | 806 WQ_UNBOUND, num_online_cpus(), 807 pci_name(qm->pdev)); 808 if (!qm->wq) { 809 pci_err(qm->pdev, "fail to alloc workqueue\n"); 810 return -ENOMEM; 811 } 812 813 ret = hisi_qm_init(qm); 814 if (ret) 815 destroy_workqueue(qm->wq); 816 817 return ret; 818 } 819 820 static void hisi_zip_qm_uninit(struct hisi_qm *qm) 821 { 822 hisi_qm_uninit(qm); 823 destroy_workqueue(qm->wq); 824 } 825 826 static int hisi_zip_probe_init(struct hisi_zip *hisi_zip) 827 { 828 u32 type_rate = HZIP_SHAPER_RATE_COMPRESS; 829 struct hisi_qm *qm = &hisi_zip->qm; 830 int ret; 831 832 if (qm->fun_type == QM_HW_PF) { 833 ret = hisi_zip_pf_probe_init(hisi_zip); 834 if (ret) 835 return ret; 836 /* enable shaper type 0 */ 837 if (qm->ver >= QM_HW_V3) { 838 type_rate |= QM_SHAPER_ENABLE; 839 840 /* ZIP need to enable shaper type 1 */ 841 type_rate |= HZIP_SHAPER_RATE_DECOMPRESS << QM_SHAPER_TYPE1_OFFSET; 842 qm->type_rate = type_rate; 843 } 844 } 845 846 return 0; 847 } 848 849 static int hisi_zip_probe(struct pci_dev *pdev, const struct pci_device_id *id) 850 { 851 struct hisi_zip *hisi_zip; 852 struct hisi_qm *qm; 853 int ret; 854 855 hisi_zip = devm_kzalloc(&pdev->dev, sizeof(*hisi_zip), GFP_KERNEL); 856 if (!hisi_zip) 857 return -ENOMEM; 858 859 qm = &hisi_zip->qm; 860 861 ret = hisi_zip_qm_init(qm, pdev); 862 if (ret) { 863 pci_err(pdev, "Failed to init ZIP QM (%d)!\n", ret); 864 return ret; 865 } 866 867 ret = hisi_zip_probe_init(hisi_zip); 868 if (ret) { 869 pci_err(pdev, "Failed to probe (%d)!\n", ret); 870 goto err_qm_uninit; 871 } 872 873 ret = hisi_qm_start(qm); 874 if (ret) 875 goto err_dev_err_uninit; 876 877 ret = hisi_zip_debugfs_init(qm); 878 if (ret) 879 pci_err(pdev, "failed to init debugfs (%d)!\n", ret); 880 881 ret = hisi_qm_alg_register(qm, &zip_devices); 882 if (ret < 0) { 883 pci_err(pdev, "failed to register driver to crypto!\n"); 884 goto err_qm_stop; 885 } 886 887 if (qm->uacce) { 888 ret = uacce_register(qm->uacce); 889 if (ret) { 890 pci_err(pdev, "failed to register uacce (%d)!\n", ret); 891 goto err_qm_alg_unregister; 892 } 893 } 894 895 if (qm->fun_type == QM_HW_PF && vfs_num > 0) { 896 ret = hisi_qm_sriov_enable(pdev, vfs_num); 897 if (ret < 0) 898 goto err_qm_alg_unregister; 899 } 900 901 return 0; 902 903 err_qm_alg_unregister: 904 hisi_qm_alg_unregister(qm, &zip_devices); 905 906 err_qm_stop: 907 hisi_zip_debugfs_exit(qm); 908 hisi_qm_stop(qm, QM_NORMAL); 909 910 err_dev_err_uninit: 911 hisi_qm_dev_err_uninit(qm); 912 913 err_qm_uninit: 914 hisi_zip_qm_uninit(qm); 915 916 return ret; 917 } 918 919 static void hisi_zip_remove(struct pci_dev *pdev) 920 { 921 struct hisi_qm *qm = pci_get_drvdata(pdev); 922 923 hisi_qm_wait_task_finish(qm, &zip_devices); 924 hisi_qm_alg_unregister(qm, &zip_devices); 925 926 if (qm->fun_type == QM_HW_PF && qm->vfs_num) 927 hisi_qm_sriov_disable(pdev, true); 928 929 hisi_zip_debugfs_exit(qm); 930 hisi_qm_stop(qm, QM_NORMAL); 931 hisi_qm_dev_err_uninit(qm); 932 hisi_zip_qm_uninit(qm); 933 } 934 935 static const struct pci_error_handlers hisi_zip_err_handler = { 936 .error_detected = hisi_qm_dev_err_detected, 937 .slot_reset = hisi_qm_dev_slot_reset, 938 .reset_prepare = hisi_qm_reset_prepare, 939 .reset_done = hisi_qm_reset_done, 940 }; 941 942 static struct pci_driver hisi_zip_pci_driver = { 943 .name = "hisi_zip", 944 .id_table = hisi_zip_dev_ids, 945 .probe = hisi_zip_probe, 946 .remove = hisi_zip_remove, 947 .sriov_configure = IS_ENABLED(CONFIG_PCI_IOV) ? 948 hisi_qm_sriov_configure : NULL, 949 .err_handler = &hisi_zip_err_handler, 950 .shutdown = hisi_qm_dev_shutdown, 951 }; 952 953 static void hisi_zip_register_debugfs(void) 954 { 955 if (!debugfs_initialized()) 956 return; 957 958 hzip_debugfs_root = debugfs_create_dir("hisi_zip", NULL); 959 } 960 961 static void hisi_zip_unregister_debugfs(void) 962 { 963 debugfs_remove_recursive(hzip_debugfs_root); 964 } 965 966 static int __init hisi_zip_init(void) 967 { 968 int ret; 969 970 hisi_qm_init_list(&zip_devices); 971 hisi_zip_register_debugfs(); 972 973 ret = pci_register_driver(&hisi_zip_pci_driver); 974 if (ret < 0) { 975 hisi_zip_unregister_debugfs(); 976 pr_err("Failed to register pci driver.\n"); 977 } 978 979 return ret; 980 } 981 982 static void __exit hisi_zip_exit(void) 983 { 984 pci_unregister_driver(&hisi_zip_pci_driver); 985 hisi_zip_unregister_debugfs(); 986 } 987 988 module_init(hisi_zip_init); 989 module_exit(hisi_zip_exit); 990 991 MODULE_LICENSE("GPL v2"); 992 MODULE_AUTHOR("Zhou Wang <wangzhou1@hisilicon.com>"); 993 MODULE_DESCRIPTION("Driver for HiSilicon ZIP accelerator"); 994