1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2019 HiSilicon Limited. */ 3 #include <linux/acpi.h> 4 #include <linux/bitops.h> 5 #include <linux/debugfs.h> 6 #include <linux/init.h> 7 #include <linux/io.h> 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/pci.h> 11 #include <linux/pm_runtime.h> 12 #include <linux/seq_file.h> 13 #include <linux/topology.h> 14 #include <linux/uacce.h> 15 #include "zip.h" 16 17 #define CAP_FILE_PERMISSION 0444 18 #define PCI_DEVICE_ID_HUAWEI_ZIP_PF 0xa250 19 20 #define HZIP_QUEUE_NUM_V1 4096 21 22 #define HZIP_CLOCK_GATE_CTRL 0x301004 23 #define HZIP_DECOMP_CHECK_ENABLE BIT(16) 24 #define HZIP_FSM_MAX_CNT 0x301008 25 26 #define HZIP_PORT_ARCA_CHE_0 0x301040 27 #define HZIP_PORT_ARCA_CHE_1 0x301044 28 #define HZIP_PORT_AWCA_CHE_0 0x301060 29 #define HZIP_PORT_AWCA_CHE_1 0x301064 30 #define HZIP_CACHE_ALL_EN 0xffffffff 31 32 #define HZIP_BD_RUSER_32_63 0x301110 33 #define HZIP_SGL_RUSER_32_63 0x30111c 34 #define HZIP_DATA_RUSER_32_63 0x301128 35 #define HZIP_DATA_WUSER_32_63 0x301134 36 #define HZIP_BD_WUSER_32_63 0x301140 37 38 #define HZIP_QM_IDEL_STATUS 0x3040e4 39 40 #define HZIP_CORE_DFX_BASE 0x301000 41 #define HZIP_CORE_DFX_DECOMP_BASE 0x304000 42 #define HZIP_CORE_DFX_COMP_0 0x302000 43 #define HZIP_CORE_DFX_COMP_1 0x303000 44 #define HZIP_CORE_DFX_DECOMP_0 0x304000 45 #define HZIP_CORE_DFX_DECOMP_1 0x305000 46 #define HZIP_CORE_DFX_DECOMP_2 0x306000 47 #define HZIP_CORE_DFX_DECOMP_3 0x307000 48 #define HZIP_CORE_DFX_DECOMP_4 0x308000 49 #define HZIP_CORE_DFX_DECOMP_5 0x309000 50 #define HZIP_CORE_REGS_BASE_LEN 0xB0 51 #define HZIP_CORE_REGS_DFX_LEN 0x28 52 #define HZIP_CORE_ADDR_INTRVL 0x1000 53 54 #define HZIP_CORE_INT_SOURCE 0x3010A0 55 #define HZIP_CORE_INT_MASK_REG 0x3010A4 56 #define HZIP_CORE_INT_SET 0x3010A8 57 #define HZIP_CORE_INT_STATUS 0x3010AC 58 #define HZIP_CORE_INT_STATUS_M_ECC BIT(1) 59 #define HZIP_CORE_SRAM_ECC_ERR_INFO 0x301148 60 #define HZIP_CORE_INT_RAS_CE_ENB 0x301160 61 #define HZIP_CORE_INT_RAS_NFE_ENB 0x301164 62 #define HZIP_CORE_INT_RAS_FE_ENB 0x301168 63 #define HZIP_CORE_INT_RAS_FE_ENB_MASK 0x0 64 #define HZIP_OOO_SHUTDOWN_SEL 0x30120C 65 #define HZIP_SRAM_ECC_ERR_NUM_SHIFT 16 66 #define HZIP_SRAM_ECC_ERR_ADDR_SHIFT 24 67 #define HZIP_CORE_INT_MASK_ALL GENMASK(31, 0) 68 #define HZIP_CORE_RAS_CLEAR_ALL GENMASK(31, 0) 69 #define HZIP_AXI_ERROR_MASK (BIT(2) | BIT(3)) 70 #define HZIP_SQE_SIZE 128 71 #define HZIP_PF_DEF_Q_NUM 64 72 #define HZIP_PF_DEF_Q_BASE 0 73 #define HZIP_CTX_Q_NUM_DEF 2 74 75 #define HZIP_SOFT_CTRL_CNT_CLR_CE 0x301000 76 #define HZIP_SOFT_CTRL_CNT_CLR_CE_BIT BIT(0) 77 #define HZIP_SOFT_CTRL_ZIP_CONTROL 0x30100C 78 #define HZIP_AXI_SHUTDOWN_ENABLE BIT(14) 79 #define HZIP_WR_PORT BIT(11) 80 81 #define HZIP_ALG_ZLIB_BIT GENMASK(1, 0) 82 #define HZIP_ALG_GZIP_BIT GENMASK(3, 2) 83 #define HZIP_ALG_DEFLATE_BIT GENMASK(5, 4) 84 #define HZIP_ALG_LZ77_BIT GENMASK(7, 6) 85 #define HZIP_ALG_LZ4_BIT GENMASK(9, 8) 86 87 #define HZIP_BUF_SIZE 22 88 #define HZIP_SQE_MASK_OFFSET 64 89 #define HZIP_SQE_MASK_LEN 48 90 91 #define HZIP_CNT_CLR_CE_EN BIT(0) 92 #define HZIP_RO_CNT_CLR_CE_EN BIT(2) 93 #define HZIP_RD_CNT_CLR_CE_EN (HZIP_CNT_CLR_CE_EN | \ 94 HZIP_RO_CNT_CLR_CE_EN) 95 96 #define HZIP_PREFETCH_CFG 0x3011B0 97 #define HZIP_SVA_TRANS 0x3011C4 98 #define HZIP_PREFETCH_ENABLE (~(BIT(26) | BIT(17) | BIT(0))) 99 #define HZIP_SVA_PREFETCH_DISABLE BIT(26) 100 #define HZIP_SVA_DISABLE_READY (BIT(26) | BIT(30)) 101 #define HZIP_SVA_PREFETCH_NUM GENMASK(18, 16) 102 #define HZIP_SVA_STALL_NUM GENMASK(15, 0) 103 #define HZIP_SHAPER_RATE_COMPRESS 750 104 #define HZIP_SHAPER_RATE_DECOMPRESS 140 105 #define HZIP_DELAY_1_US 1 106 #define HZIP_POLL_TIMEOUT_US 1000 107 #define HZIP_WAIT_SVA_READY 500000 108 #define HZIP_READ_SVA_STATUS_TIMES 3 109 #define HZIP_WAIT_US_MIN 10 110 #define HZIP_WAIT_US_MAX 20 111 112 /* clock gating */ 113 #define HZIP_PEH_CFG_AUTO_GATE 0x3011A8 114 #define HZIP_PEH_CFG_AUTO_GATE_EN BIT(0) 115 #define HZIP_CORE_GATED_EN GENMASK(15, 8) 116 #define HZIP_CORE_GATED_OOO_EN BIT(29) 117 #define HZIP_CLOCK_GATED_EN (HZIP_CORE_GATED_EN | \ 118 HZIP_CORE_GATED_OOO_EN) 119 120 /* zip comp high performance */ 121 #define HZIP_HIGH_PERF_OFFSET 0x301208 122 123 #define HZIP_LIT_LEN_EN_OFFSET 0x301204 124 #define HZIP_LIT_LEN_EN_EN BIT(4) 125 126 #define HZIP_MAX_CHANNEL_NUM 3 127 128 enum { 129 HZIP_HIGH_COMP_RATE, 130 HZIP_HIGH_COMP_PERF, 131 }; 132 133 static const char hisi_zip_name[] = "hisi_zip"; 134 static struct dentry *hzip_debugfs_root; 135 136 struct hisi_zip_hw_error { 137 u32 int_msk; 138 const char *msg; 139 }; 140 141 struct zip_dfx_item { 142 const char *name; 143 u32 offset; 144 }; 145 146 static const struct qm_dev_alg zip_dev_algs[] = { { 147 .alg_msk = HZIP_ALG_ZLIB_BIT, 148 .alg = "zlib\n", 149 }, { 150 .alg_msk = HZIP_ALG_GZIP_BIT, 151 .alg = "gzip\n", 152 }, { 153 .alg_msk = HZIP_ALG_DEFLATE_BIT, 154 .alg = "deflate\n", 155 }, { 156 .alg_msk = HZIP_ALG_LZ77_BIT, 157 .alg = "lz77_zstd\n", 158 }, { 159 .alg_msk = HZIP_ALG_LZ77_BIT, 160 .alg = "lz77_only\n", 161 }, { 162 .alg_msk = HZIP_ALG_LZ4_BIT, 163 .alg = "lz4\n", 164 }, 165 }; 166 167 static struct hisi_qm_list zip_devices = { 168 .register_to_crypto = hisi_zip_register_to_crypto, 169 .unregister_from_crypto = hisi_zip_unregister_from_crypto, 170 }; 171 172 static struct zip_dfx_item zip_dfx_files[] = { 173 {"send_cnt", offsetof(struct hisi_zip_dfx, send_cnt)}, 174 {"recv_cnt", offsetof(struct hisi_zip_dfx, recv_cnt)}, 175 {"send_busy_cnt", offsetof(struct hisi_zip_dfx, send_busy_cnt)}, 176 {"err_bd_cnt", offsetof(struct hisi_zip_dfx, err_bd_cnt)}, 177 }; 178 179 static const struct hisi_zip_hw_error zip_hw_error[] = { 180 { .int_msk = BIT(0), .msg = "zip_ecc_1bitt_err" }, 181 { .int_msk = BIT(1), .msg = "zip_ecc_2bit_err" }, 182 { .int_msk = BIT(2), .msg = "zip_axi_rresp_err" }, 183 { .int_msk = BIT(3), .msg = "zip_axi_bresp_err" }, 184 { .int_msk = BIT(4), .msg = "zip_src_addr_parse_err" }, 185 { .int_msk = BIT(5), .msg = "zip_dst_addr_parse_err" }, 186 { .int_msk = BIT(6), .msg = "zip_pre_in_addr_err" }, 187 { .int_msk = BIT(7), .msg = "zip_pre_in_data_err" }, 188 { .int_msk = BIT(8), .msg = "zip_com_inf_err" }, 189 { .int_msk = BIT(9), .msg = "zip_enc_inf_err" }, 190 { .int_msk = BIT(10), .msg = "zip_pre_out_err" }, 191 { .int_msk = BIT(11), .msg = "zip_axi_poison_err" }, 192 { .int_msk = BIT(12), .msg = "zip_sva_err" }, 193 { /* sentinel */ } 194 }; 195 196 enum ctrl_debug_file_index { 197 HZIP_CLEAR_ENABLE, 198 HZIP_DEBUG_FILE_NUM, 199 }; 200 201 static const char * const ctrl_debug_file_name[] = { 202 [HZIP_CLEAR_ENABLE] = "clear_enable", 203 }; 204 205 struct ctrl_debug_file { 206 enum ctrl_debug_file_index index; 207 spinlock_t lock; 208 struct hisi_zip_ctrl *ctrl; 209 }; 210 211 /* 212 * One ZIP controller has one PF and multiple VFs, some global configurations 213 * which PF has need this structure. 214 * 215 * Just relevant for PF. 216 */ 217 struct hisi_zip_ctrl { 218 struct hisi_zip *hisi_zip; 219 struct ctrl_debug_file files[HZIP_DEBUG_FILE_NUM]; 220 }; 221 222 enum zip_cap_type { 223 ZIP_QM_NFE_MASK_CAP = 0x0, 224 ZIP_QM_RESET_MASK_CAP, 225 ZIP_QM_OOO_SHUTDOWN_MASK_CAP, 226 ZIP_QM_CE_MASK_CAP, 227 ZIP_NFE_MASK_CAP, 228 ZIP_RESET_MASK_CAP, 229 ZIP_OOO_SHUTDOWN_MASK_CAP, 230 ZIP_CE_MASK_CAP, 231 ZIP_CLUSTER_NUM_CAP, 232 ZIP_CORE_TYPE_NUM_CAP, 233 ZIP_CORE_NUM_CAP, 234 ZIP_CLUSTER_COMP_NUM_CAP, 235 ZIP_CLUSTER_DECOMP_NUM_CAP, 236 ZIP_DECOMP_ENABLE_BITMAP, 237 ZIP_COMP_ENABLE_BITMAP, 238 ZIP_DRV_ALG_BITMAP, 239 ZIP_DEV_ALG_BITMAP, 240 ZIP_CORE1_ALG_BITMAP, 241 ZIP_CORE2_ALG_BITMAP, 242 ZIP_CORE3_ALG_BITMAP, 243 ZIP_CORE4_ALG_BITMAP, 244 ZIP_CORE5_ALG_BITMAP, 245 ZIP_CAP_MAX 246 }; 247 248 static struct hisi_qm_cap_info zip_basic_cap_info[] = { 249 {ZIP_QM_NFE_MASK_CAP, 0x3124, 0, GENMASK(31, 0), 0x0, 0x1C57, 0x7C77}, 250 {ZIP_QM_RESET_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0xC57, 0x6C77}, 251 {ZIP_QM_OOO_SHUTDOWN_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0x4, 0x6C77}, 252 {ZIP_QM_CE_MASK_CAP, 0x312C, 0, GENMASK(31, 0), 0x0, 0x8, 0x8}, 253 {ZIP_NFE_MASK_CAP, 0x3130, 0, GENMASK(31, 0), 0x0, 0x7FE, 0x1FFE}, 254 {ZIP_RESET_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x7FE, 0x7FE}, 255 {ZIP_OOO_SHUTDOWN_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x2, 0x7FE}, 256 {ZIP_CE_MASK_CAP, 0x3138, 0, GENMASK(31, 0), 0x0, 0x1, 0x1}, 257 {ZIP_CLUSTER_NUM_CAP, 0x313C, 28, GENMASK(3, 0), 0x1, 0x1, 0x1}, 258 {ZIP_CORE_TYPE_NUM_CAP, 0x313C, 24, GENMASK(3, 0), 0x2, 0x2, 0x2}, 259 {ZIP_CORE_NUM_CAP, 0x313C, 16, GENMASK(7, 0), 0x8, 0x8, 0x5}, 260 {ZIP_CLUSTER_COMP_NUM_CAP, 0x313C, 8, GENMASK(7, 0), 0x2, 0x2, 0x2}, 261 {ZIP_CLUSTER_DECOMP_NUM_CAP, 0x313C, 0, GENMASK(7, 0), 0x6, 0x6, 0x3}, 262 {ZIP_DECOMP_ENABLE_BITMAP, 0x3140, 16, GENMASK(15, 0), 0xFC, 0xFC, 0x1C}, 263 {ZIP_COMP_ENABLE_BITMAP, 0x3140, 0, GENMASK(15, 0), 0x3, 0x3, 0x3}, 264 {ZIP_DRV_ALG_BITMAP, 0x3144, 0, GENMASK(31, 0), 0x0, 0x0, 0x30}, 265 {ZIP_DEV_ALG_BITMAP, 0x3148, 0, GENMASK(31, 0), 0xF, 0xF, 0x3F}, 266 {ZIP_CORE1_ALG_BITMAP, 0x314C, 0, GENMASK(31, 0), 0x5, 0x5, 0xD5}, 267 {ZIP_CORE2_ALG_BITMAP, 0x3150, 0, GENMASK(31, 0), 0x5, 0x5, 0xD5}, 268 {ZIP_CORE3_ALG_BITMAP, 0x3154, 0, GENMASK(31, 0), 0xA, 0xA, 0x2A}, 269 {ZIP_CORE4_ALG_BITMAP, 0x3158, 0, GENMASK(31, 0), 0xA, 0xA, 0x2A}, 270 {ZIP_CORE5_ALG_BITMAP, 0x315C, 0, GENMASK(31, 0), 0xA, 0xA, 0x2A}, 271 {ZIP_CAP_MAX, 0x317c, 0, GENMASK(0, 0), 0x0, 0x0, 0x0} 272 }; 273 274 static const struct hisi_qm_cap_query_info zip_cap_query_info[] = { 275 {QM_RAS_NFE_TYPE, "QM_RAS_NFE_TYPE ", 0x3124, 0x0, 0x1C57, 0x7C77}, 276 {QM_RAS_NFE_RESET, "QM_RAS_NFE_RESET ", 0x3128, 0x0, 0xC57, 0x6C77}, 277 {QM_RAS_CE_TYPE, "QM_RAS_CE_TYPE ", 0x312C, 0x0, 0x8, 0x8}, 278 {ZIP_RAS_NFE_TYPE, "ZIP_RAS_NFE_TYPE ", 0x3130, 0x0, 0x7FE, 0x1FFE}, 279 {ZIP_RAS_NFE_RESET, "ZIP_RAS_NFE_RESET ", 0x3134, 0x0, 0x7FE, 0x7FE}, 280 {ZIP_RAS_CE_TYPE, "ZIP_RAS_CE_TYPE ", 0x3138, 0x0, 0x1, 0x1}, 281 {ZIP_CORE_INFO, "ZIP_CORE_INFO ", 0x313C, 0x12080206, 0x12080206, 0x12050203}, 282 {ZIP_CORE_EN, "ZIP_CORE_EN ", 0x3140, 0xFC0003, 0xFC0003, 0x1C0003}, 283 {ZIP_DRV_ALG_BITMAP_TB, "ZIP_DRV_ALG_BITMAP ", 0x3144, 0x0, 0x0, 0x30}, 284 {ZIP_ALG_BITMAP, "ZIP_ALG_BITMAP ", 0x3148, 0xF, 0xF, 0x3F}, 285 {ZIP_CORE1_BITMAP, "ZIP_CORE1_BITMAP ", 0x314C, 0x5, 0x5, 0xD5}, 286 {ZIP_CORE2_BITMAP, "ZIP_CORE2_BITMAP ", 0x3150, 0x5, 0x5, 0xD5}, 287 {ZIP_CORE3_BITMAP, "ZIP_CORE3_BITMAP ", 0x3154, 0xA, 0xA, 0x2A}, 288 {ZIP_CORE4_BITMAP, "ZIP_CORE4_BITMAP ", 0x3158, 0xA, 0xA, 0x2A}, 289 {ZIP_CORE5_BITMAP, "ZIP_CORE5_BITMAP ", 0x315C, 0xA, 0xA, 0x2A}, 290 }; 291 292 static const struct debugfs_reg32 hzip_dfx_regs[] = { 293 {"HZIP_GET_BD_NUM ", 0x00}, 294 {"HZIP_GET_RIGHT_BD ", 0x04}, 295 {"HZIP_GET_ERROR_BD ", 0x08}, 296 {"HZIP_DONE_BD_NUM ", 0x0c}, 297 {"HZIP_WORK_CYCLE ", 0x10}, 298 {"HZIP_IDLE_CYCLE ", 0x18}, 299 {"HZIP_MAX_DELAY ", 0x20}, 300 {"HZIP_MIN_DELAY ", 0x24}, 301 {"HZIP_AVG_DELAY ", 0x28}, 302 {"HZIP_MEM_VISIBLE_DATA ", 0x30}, 303 {"HZIP_MEM_VISIBLE_ADDR ", 0x34}, 304 {"HZIP_CONSUMED_BYTE ", 0x38}, 305 {"HZIP_PRODUCED_BYTE ", 0x40}, 306 {"HZIP_COMP_INF ", 0x70}, 307 {"HZIP_PRE_OUT ", 0x78}, 308 {"HZIP_BD_RD ", 0x7c}, 309 {"HZIP_BD_WR ", 0x80}, 310 {"HZIP_GET_BD_AXI_ERR_NUM ", 0x84}, 311 {"HZIP_GET_BD_PARSE_ERR_NUM ", 0x88}, 312 {"HZIP_ADD_BD_AXI_ERR_NUM ", 0x8c}, 313 {"HZIP_DECOMP_STF_RELOAD_CURR_ST ", 0x94}, 314 {"HZIP_DECOMP_LZ77_CURR_ST ", 0x9c}, 315 }; 316 317 static const struct debugfs_reg32 hzip_com_dfx_regs[] = { 318 {"HZIP_CLOCK_GATE_CTRL ", 0x301004}, 319 {"HZIP_CORE_INT_RAS_CE_ENB ", 0x301160}, 320 {"HZIP_CORE_INT_RAS_NFE_ENB ", 0x301164}, 321 {"HZIP_CORE_INT_RAS_FE_ENB ", 0x301168}, 322 {"HZIP_UNCOM_ERR_RAS_CTRL ", 0x30116C}, 323 }; 324 325 static const struct debugfs_reg32 hzip_dump_dfx_regs[] = { 326 {"HZIP_GET_BD_NUM ", 0x00}, 327 {"HZIP_GET_RIGHT_BD ", 0x04}, 328 {"HZIP_GET_ERROR_BD ", 0x08}, 329 {"HZIP_DONE_BD_NUM ", 0x0c}, 330 {"HZIP_MAX_DELAY ", 0x20}, 331 }; 332 333 /* define the ZIP's dfx regs region and region length */ 334 static struct dfx_diff_registers hzip_diff_regs[] = { 335 { 336 .reg_offset = HZIP_CORE_DFX_BASE, 337 .reg_len = HZIP_CORE_REGS_BASE_LEN, 338 }, { 339 .reg_offset = HZIP_CORE_DFX_COMP_0, 340 .reg_len = HZIP_CORE_REGS_DFX_LEN, 341 }, { 342 .reg_offset = HZIP_CORE_DFX_COMP_1, 343 .reg_len = HZIP_CORE_REGS_DFX_LEN, 344 }, { 345 .reg_offset = HZIP_CORE_DFX_DECOMP_0, 346 .reg_len = HZIP_CORE_REGS_DFX_LEN, 347 }, { 348 .reg_offset = HZIP_CORE_DFX_DECOMP_1, 349 .reg_len = HZIP_CORE_REGS_DFX_LEN, 350 }, { 351 .reg_offset = HZIP_CORE_DFX_DECOMP_2, 352 .reg_len = HZIP_CORE_REGS_DFX_LEN, 353 }, { 354 .reg_offset = HZIP_CORE_DFX_DECOMP_3, 355 .reg_len = HZIP_CORE_REGS_DFX_LEN, 356 }, { 357 .reg_offset = HZIP_CORE_DFX_DECOMP_4, 358 .reg_len = HZIP_CORE_REGS_DFX_LEN, 359 }, { 360 .reg_offset = HZIP_CORE_DFX_DECOMP_5, 361 .reg_len = HZIP_CORE_REGS_DFX_LEN, 362 }, 363 }; 364 365 static const char *zip_channel_name[HZIP_MAX_CHANNEL_NUM] = { 366 "COMPRESS", 367 "DECOMPRESS", 368 "DAE" 369 }; 370 371 static int hzip_diff_regs_show(struct seq_file *s, void *unused) 372 { 373 struct hisi_qm *qm = s->private; 374 375 hisi_qm_acc_diff_regs_dump(qm, s, qm->debug.acc_diff_regs, 376 ARRAY_SIZE(hzip_diff_regs)); 377 378 return 0; 379 } 380 DEFINE_SHOW_ATTRIBUTE(hzip_diff_regs); 381 382 static int perf_mode_set(const char *val, const struct kernel_param *kp) 383 { 384 int ret; 385 u32 n; 386 387 if (!val) 388 return -EINVAL; 389 390 ret = kstrtou32(val, 10, &n); 391 if (ret != 0 || (n != HZIP_HIGH_COMP_PERF && 392 n != HZIP_HIGH_COMP_RATE)) 393 return -EINVAL; 394 395 return param_set_int(val, kp); 396 } 397 398 static const struct kernel_param_ops zip_com_perf_ops = { 399 .set = perf_mode_set, 400 .get = param_get_int, 401 }; 402 403 /* 404 * perf_mode = 0 means enable high compression rate mode, 405 * perf_mode = 1 means enable high compression performance mode. 406 * These two modes only apply to the compression direction. 407 */ 408 static u32 perf_mode = HZIP_HIGH_COMP_RATE; 409 module_param_cb(perf_mode, &zip_com_perf_ops, &perf_mode, 0444); 410 MODULE_PARM_DESC(perf_mode, "ZIP high perf mode 0(default), 1(enable)"); 411 412 static const struct kernel_param_ops zip_uacce_mode_ops = { 413 .set = uacce_mode_set, 414 .get = param_get_int, 415 }; 416 417 /* 418 * uacce_mode = 0 means zip only register to crypto, 419 * uacce_mode = 1 means zip both register to crypto and uacce. 420 */ 421 static u32 uacce_mode = UACCE_MODE_NOUACCE; 422 module_param_cb(uacce_mode, &zip_uacce_mode_ops, &uacce_mode, 0444); 423 MODULE_PARM_DESC(uacce_mode, UACCE_MODE_DESC); 424 425 static bool pf_q_num_flag; 426 static int pf_q_num_set(const char *val, const struct kernel_param *kp) 427 { 428 pf_q_num_flag = true; 429 430 return hisi_qm_q_num_set(val, kp, PCI_DEVICE_ID_HUAWEI_ZIP_PF); 431 } 432 433 static const struct kernel_param_ops pf_q_num_ops = { 434 .set = pf_q_num_set, 435 .get = param_get_int, 436 }; 437 438 static u32 pf_q_num = HZIP_PF_DEF_Q_NUM; 439 module_param_cb(pf_q_num, &pf_q_num_ops, &pf_q_num, 0444); 440 MODULE_PARM_DESC(pf_q_num, "Number of queues in PF(v1 2-4096, v2 2-1024)"); 441 442 static const struct kernel_param_ops vfs_num_ops = { 443 .set = vfs_num_set, 444 .get = param_get_int, 445 }; 446 447 static u32 vfs_num; 448 module_param_cb(vfs_num, &vfs_num_ops, &vfs_num, 0444); 449 MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63), 0(default)"); 450 451 static const struct pci_device_id hisi_zip_dev_ids[] = { 452 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_ZIP_PF) }, 453 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_ZIP_VF) }, 454 { 0, } 455 }; 456 MODULE_DEVICE_TABLE(pci, hisi_zip_dev_ids); 457 458 int zip_create_qps(struct hisi_qp **qps, int qp_num, int node, u8 *alg_type) 459 { 460 if (node == NUMA_NO_NODE) 461 node = cpu_to_node(raw_smp_processor_id()); 462 463 return hisi_qm_alloc_qps_node(&zip_devices, qp_num, alg_type, node, qps); 464 } 465 466 bool hisi_zip_alg_support(struct hisi_qm *qm, u32 alg) 467 { 468 u32 cap_val; 469 470 cap_val = qm->cap_tables.dev_cap_table[ZIP_DRV_ALG_BITMAP_TB].cap_val; 471 if ((alg & cap_val) == alg) 472 return true; 473 474 return false; 475 } 476 477 static void hisi_zip_literal_set(struct hisi_qm *qm) 478 { 479 u32 val; 480 481 if (qm->ver < QM_HW_V3) 482 return; 483 484 val = readl_relaxed(qm->io_base + HZIP_LIT_LEN_EN_OFFSET); 485 val &= ~HZIP_LIT_LEN_EN_EN; 486 487 /* enable literal length in stream mode compression */ 488 writel(val, qm->io_base + HZIP_LIT_LEN_EN_OFFSET); 489 } 490 491 static void hisi_zip_set_high_perf(struct hisi_qm *qm) 492 { 493 u32 val; 494 495 val = readl_relaxed(qm->io_base + HZIP_HIGH_PERF_OFFSET); 496 if (perf_mode == HZIP_HIGH_COMP_PERF) 497 val |= HZIP_HIGH_COMP_PERF; 498 else 499 val &= ~HZIP_HIGH_COMP_PERF; 500 501 /* Set perf mode */ 502 writel(val, qm->io_base + HZIP_HIGH_PERF_OFFSET); 503 } 504 505 static int hisi_zip_wait_sva_ready(struct hisi_qm *qm, __u32 offset, __u32 mask) 506 { 507 u32 val, try_times = 0; 508 u8 count = 0; 509 510 /* 511 * Read the register value every 10-20us. If the value is 0 for three 512 * consecutive times, the SVA module is ready. 513 */ 514 do { 515 val = readl(qm->io_base + offset); 516 if (val & mask) 517 count = 0; 518 else if (++count == HZIP_READ_SVA_STATUS_TIMES) 519 break; 520 521 usleep_range(HZIP_WAIT_US_MIN, HZIP_WAIT_US_MAX); 522 } while (++try_times < HZIP_WAIT_SVA_READY); 523 524 if (try_times == HZIP_WAIT_SVA_READY) { 525 pci_err(qm->pdev, "failed to wait sva prefetch ready\n"); 526 return -ETIMEDOUT; 527 } 528 529 return 0; 530 } 531 532 static void hisi_zip_close_sva_prefetch(struct hisi_qm *qm) 533 { 534 u32 val; 535 int ret; 536 537 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps)) 538 return; 539 540 val = readl_relaxed(qm->io_base + HZIP_PREFETCH_CFG); 541 val |= HZIP_SVA_PREFETCH_DISABLE; 542 writel(val, qm->io_base + HZIP_PREFETCH_CFG); 543 544 ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_SVA_TRANS, 545 val, !(val & HZIP_SVA_DISABLE_READY), 546 HZIP_DELAY_1_US, HZIP_POLL_TIMEOUT_US); 547 if (ret) 548 pci_err(qm->pdev, "failed to close sva prefetch\n"); 549 550 (void)hisi_zip_wait_sva_ready(qm, HZIP_SVA_TRANS, HZIP_SVA_STALL_NUM); 551 } 552 553 static void hisi_zip_open_sva_prefetch(struct hisi_qm *qm) 554 { 555 u32 val; 556 int ret; 557 558 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps)) 559 return; 560 561 /* Enable prefetch */ 562 val = readl_relaxed(qm->io_base + HZIP_PREFETCH_CFG); 563 val &= HZIP_PREFETCH_ENABLE; 564 writel(val, qm->io_base + HZIP_PREFETCH_CFG); 565 566 ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_PREFETCH_CFG, 567 val, !(val & HZIP_SVA_PREFETCH_DISABLE), 568 HZIP_DELAY_1_US, HZIP_POLL_TIMEOUT_US); 569 if (ret) { 570 pci_err(qm->pdev, "failed to open sva prefetch\n"); 571 hisi_zip_close_sva_prefetch(qm); 572 return; 573 } 574 575 ret = hisi_zip_wait_sva_ready(qm, HZIP_SVA_TRANS, HZIP_SVA_PREFETCH_NUM); 576 if (ret) 577 hisi_zip_close_sva_prefetch(qm); 578 } 579 580 static void hisi_zip_enable_clock_gate(struct hisi_qm *qm) 581 { 582 u32 val; 583 584 if (qm->ver < QM_HW_V3) 585 return; 586 587 val = readl(qm->io_base + HZIP_CLOCK_GATE_CTRL); 588 val |= HZIP_CLOCK_GATED_EN; 589 writel(val, qm->io_base + HZIP_CLOCK_GATE_CTRL); 590 591 val = readl(qm->io_base + HZIP_PEH_CFG_AUTO_GATE); 592 val |= HZIP_PEH_CFG_AUTO_GATE_EN; 593 writel(val, qm->io_base + HZIP_PEH_CFG_AUTO_GATE); 594 } 595 596 static int hisi_zip_set_user_domain_and_cache(struct hisi_qm *qm) 597 { 598 void __iomem *base = qm->io_base; 599 u32 dcomp_bm, comp_bm; 600 u32 zip_core_en; 601 int ret; 602 603 /* qm user domain */ 604 writel(AXUSER_BASE, base + QM_ARUSER_M_CFG_1); 605 writel(ARUSER_M_CFG_ENABLE, base + QM_ARUSER_M_CFG_ENABLE); 606 writel(AXUSER_BASE, base + QM_AWUSER_M_CFG_1); 607 writel(AWUSER_M_CFG_ENABLE, base + QM_AWUSER_M_CFG_ENABLE); 608 writel(WUSER_M_CFG_ENABLE, base + QM_WUSER_M_CFG_ENABLE); 609 610 /* qm cache */ 611 writel(AXI_M_CFG, base + QM_AXI_M_CFG); 612 writel(AXI_M_CFG_ENABLE, base + QM_AXI_M_CFG_ENABLE); 613 614 /* disable FLR triggered by BME(bus master enable) */ 615 writel(PEH_AXUSER_CFG, base + QM_PEH_AXUSER_CFG); 616 writel(PEH_AXUSER_CFG_ENABLE, base + QM_PEH_AXUSER_CFG_ENABLE); 617 618 /* cache */ 619 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_ARCA_CHE_0); 620 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_ARCA_CHE_1); 621 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_AWCA_CHE_0); 622 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_AWCA_CHE_1); 623 624 /* user domain configurations */ 625 writel(AXUSER_BASE, base + HZIP_BD_RUSER_32_63); 626 writel(AXUSER_BASE, base + HZIP_BD_WUSER_32_63); 627 628 if (qm->use_sva && qm->ver == QM_HW_V2) { 629 writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_DATA_RUSER_32_63); 630 writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_DATA_WUSER_32_63); 631 writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_SGL_RUSER_32_63); 632 } else { 633 writel(AXUSER_BASE, base + HZIP_DATA_RUSER_32_63); 634 writel(AXUSER_BASE, base + HZIP_DATA_WUSER_32_63); 635 writel(AXUSER_BASE, base + HZIP_SGL_RUSER_32_63); 636 } 637 hisi_zip_open_sva_prefetch(qm); 638 639 /* let's open all compression/decompression cores */ 640 641 zip_core_en = qm->cap_tables.dev_cap_table[ZIP_CORE_EN].cap_val; 642 dcomp_bm = (zip_core_en >> zip_basic_cap_info[ZIP_DECOMP_ENABLE_BITMAP].shift) & 643 zip_basic_cap_info[ZIP_DECOMP_ENABLE_BITMAP].mask; 644 comp_bm = (zip_core_en >> zip_basic_cap_info[ZIP_COMP_ENABLE_BITMAP].shift) & 645 zip_basic_cap_info[ZIP_COMP_ENABLE_BITMAP].mask; 646 writel(HZIP_DECOMP_CHECK_ENABLE | dcomp_bm | comp_bm, base + HZIP_CLOCK_GATE_CTRL); 647 648 /* enable sqc,cqc writeback */ 649 writel(SQC_CACHE_ENABLE | CQC_CACHE_ENABLE | SQC_CACHE_WB_ENABLE | 650 CQC_CACHE_WB_ENABLE | FIELD_PREP(SQC_CACHE_WB_THRD, 1) | 651 FIELD_PREP(CQC_CACHE_WB_THRD, 1), base + QM_CACHE_CTL); 652 653 hisi_zip_set_high_perf(qm); 654 hisi_zip_literal_set(qm); 655 hisi_zip_enable_clock_gate(qm); 656 657 ret = hisi_dae_set_user_domain(qm); 658 if (ret) 659 goto close_sva_prefetch; 660 661 return 0; 662 663 close_sva_prefetch: 664 hisi_zip_close_sva_prefetch(qm); 665 return ret; 666 } 667 668 static void hisi_zip_master_ooo_ctrl(struct hisi_qm *qm, bool enable) 669 { 670 u32 val1, val2; 671 672 val1 = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 673 if (enable) { 674 val1 |= HZIP_AXI_SHUTDOWN_ENABLE; 675 val2 = qm->err_info.dev_err.shutdown_mask; 676 } else { 677 val1 &= ~HZIP_AXI_SHUTDOWN_ENABLE; 678 val2 = 0x0; 679 } 680 681 if (qm->ver > QM_HW_V2) 682 writel(val2, qm->io_base + HZIP_OOO_SHUTDOWN_SEL); 683 684 writel(val1, qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 685 } 686 687 static void hisi_zip_hw_error_enable(struct hisi_qm *qm) 688 { 689 struct hisi_qm_err_mask *dev_err = &qm->err_info.dev_err; 690 u32 err_mask = dev_err->ce | dev_err->nfe | dev_err->fe; 691 692 if (qm->ver == QM_HW_V1) { 693 writel(HZIP_CORE_INT_MASK_ALL, 694 qm->io_base + HZIP_CORE_INT_MASK_REG); 695 dev_info(&qm->pdev->dev, "Does not support hw error handle\n"); 696 return; 697 } 698 699 /* clear ZIP hw error source if having */ 700 writel(HZIP_CORE_RAS_CLEAR_ALL, qm->io_base + HZIP_CORE_INT_SOURCE); 701 702 /* configure error type */ 703 writel(dev_err->ce, qm->io_base + HZIP_CORE_INT_RAS_CE_ENB); 704 writel(dev_err->fe, qm->io_base + HZIP_CORE_INT_RAS_FE_ENB); 705 writel(dev_err->nfe, qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); 706 707 hisi_zip_master_ooo_ctrl(qm, true); 708 709 /* enable ZIP hw error interrupts */ 710 writel(~err_mask, qm->io_base + HZIP_CORE_INT_MASK_REG); 711 712 hisi_dae_hw_error_enable(qm); 713 } 714 715 static void hisi_zip_hw_error_disable(struct hisi_qm *qm) 716 { 717 /* disable ZIP hw error interrupts */ 718 writel(HZIP_CORE_INT_MASK_ALL, qm->io_base + HZIP_CORE_INT_MASK_REG); 719 720 hisi_zip_master_ooo_ctrl(qm, false); 721 722 hisi_dae_hw_error_disable(qm); 723 } 724 725 static inline struct hisi_qm *file_to_qm(struct ctrl_debug_file *file) 726 { 727 struct hisi_zip *hisi_zip = file->ctrl->hisi_zip; 728 729 return &hisi_zip->qm; 730 } 731 732 static u32 clear_enable_read(struct hisi_qm *qm) 733 { 734 return readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) & 735 HZIP_SOFT_CTRL_CNT_CLR_CE_BIT; 736 } 737 738 static int clear_enable_write(struct hisi_qm *qm, u32 val) 739 { 740 u32 tmp; 741 742 if (val != 1 && val != 0) 743 return -EINVAL; 744 745 tmp = (readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) & 746 ~HZIP_SOFT_CTRL_CNT_CLR_CE_BIT) | val; 747 writel(tmp, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE); 748 749 return 0; 750 } 751 752 static ssize_t hisi_zip_ctrl_debug_read(struct file *filp, char __user *buf, 753 size_t count, loff_t *pos) 754 { 755 struct ctrl_debug_file *file = filp->private_data; 756 struct hisi_qm *qm = file_to_qm(file); 757 char tbuf[HZIP_BUF_SIZE]; 758 u32 val; 759 int ret; 760 761 ret = hisi_qm_get_dfx_access(qm); 762 if (ret) 763 return ret; 764 765 spin_lock_irq(&file->lock); 766 switch (file->index) { 767 case HZIP_CLEAR_ENABLE: 768 val = clear_enable_read(qm); 769 break; 770 default: 771 goto err_input; 772 } 773 spin_unlock_irq(&file->lock); 774 775 hisi_qm_put_dfx_access(qm); 776 ret = scnprintf(tbuf, sizeof(tbuf), "%u\n", val); 777 return simple_read_from_buffer(buf, count, pos, tbuf, ret); 778 779 err_input: 780 spin_unlock_irq(&file->lock); 781 hisi_qm_put_dfx_access(qm); 782 return -EINVAL; 783 } 784 785 static ssize_t hisi_zip_ctrl_debug_write(struct file *filp, 786 const char __user *buf, 787 size_t count, loff_t *pos) 788 { 789 struct ctrl_debug_file *file = filp->private_data; 790 struct hisi_qm *qm = file_to_qm(file); 791 char tbuf[HZIP_BUF_SIZE]; 792 unsigned long val; 793 int len, ret; 794 795 if (*pos != 0) 796 return 0; 797 798 if (count >= HZIP_BUF_SIZE) 799 return -ENOSPC; 800 801 len = simple_write_to_buffer(tbuf, HZIP_BUF_SIZE - 1, pos, buf, count); 802 if (len < 0) 803 return len; 804 805 tbuf[len] = '\0'; 806 ret = kstrtoul(tbuf, 0, &val); 807 if (ret) 808 return ret; 809 810 ret = hisi_qm_get_dfx_access(qm); 811 if (ret) 812 return ret; 813 814 spin_lock_irq(&file->lock); 815 switch (file->index) { 816 case HZIP_CLEAR_ENABLE: 817 ret = clear_enable_write(qm, val); 818 if (ret) 819 goto err_input; 820 break; 821 default: 822 ret = -EINVAL; 823 goto err_input; 824 } 825 826 ret = count; 827 828 err_input: 829 spin_unlock_irq(&file->lock); 830 hisi_qm_put_dfx_access(qm); 831 return ret; 832 } 833 834 static const struct file_operations ctrl_debug_fops = { 835 .owner = THIS_MODULE, 836 .open = simple_open, 837 .read = hisi_zip_ctrl_debug_read, 838 .write = hisi_zip_ctrl_debug_write, 839 }; 840 841 static int zip_debugfs_atomic64_set(void *data, u64 val) 842 { 843 if (val) 844 return -EINVAL; 845 846 atomic64_set((atomic64_t *)data, 0); 847 848 return 0; 849 } 850 851 static int zip_debugfs_atomic64_get(void *data, u64 *val) 852 { 853 *val = atomic64_read((atomic64_t *)data); 854 855 return 0; 856 } 857 858 DEFINE_DEBUGFS_ATTRIBUTE(zip_atomic64_ops, zip_debugfs_atomic64_get, 859 zip_debugfs_atomic64_set, "%llu\n"); 860 861 static int hisi_zip_regs_show(struct seq_file *s, void *unused) 862 { 863 hisi_qm_regs_dump(s, s->private); 864 865 return 0; 866 } 867 868 DEFINE_SHOW_ATTRIBUTE(hisi_zip_regs); 869 870 static void __iomem *get_zip_core_addr(struct hisi_qm *qm, int core_num) 871 { 872 u8 zip_comp_core_num; 873 u32 zip_core_info; 874 875 zip_core_info = qm->cap_tables.dev_cap_table[ZIP_CORE_INFO].cap_val; 876 zip_comp_core_num = (zip_core_info >> zip_basic_cap_info[ZIP_CLUSTER_COMP_NUM_CAP].shift) & 877 zip_basic_cap_info[ZIP_CLUSTER_COMP_NUM_CAP].mask; 878 879 if (core_num < zip_comp_core_num) 880 return qm->io_base + HZIP_CORE_DFX_BASE + 881 (core_num + 1) * HZIP_CORE_ADDR_INTRVL; 882 883 return qm->io_base + HZIP_CORE_DFX_DECOMP_BASE + 884 (core_num - zip_comp_core_num) * HZIP_CORE_ADDR_INTRVL; 885 } 886 887 static int hisi_zip_core_debug_init(struct hisi_qm *qm) 888 { 889 u32 zip_core_num, zip_comp_core_num; 890 struct device *dev = &qm->pdev->dev; 891 struct debugfs_regset32 *regset; 892 u32 zip_core_info; 893 struct dentry *tmp_d; 894 char buf[HZIP_BUF_SIZE]; 895 int i; 896 897 zip_core_info = qm->cap_tables.dev_cap_table[ZIP_CORE_INFO].cap_val; 898 zip_core_num = (zip_core_info >> zip_basic_cap_info[ZIP_CORE_NUM_CAP].shift) & 899 zip_basic_cap_info[ZIP_CORE_NUM_CAP].mask; 900 zip_comp_core_num = (zip_core_info >> zip_basic_cap_info[ZIP_CLUSTER_COMP_NUM_CAP].shift) & 901 zip_basic_cap_info[ZIP_CLUSTER_COMP_NUM_CAP].mask; 902 903 for (i = 0; i < zip_core_num; i++) { 904 if (i < zip_comp_core_num) 905 scnprintf(buf, sizeof(buf), "comp_core%d", i); 906 else 907 scnprintf(buf, sizeof(buf), "decomp_core%d", 908 i - zip_comp_core_num); 909 910 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); 911 if (!regset) 912 return -ENOENT; 913 914 regset->regs = hzip_dfx_regs; 915 regset->nregs = ARRAY_SIZE(hzip_dfx_regs); 916 regset->base = get_zip_core_addr(qm, i); 917 regset->dev = dev; 918 919 tmp_d = debugfs_create_dir(buf, qm->debug.debug_root); 920 debugfs_create_file("regs", 0444, tmp_d, regset, 921 &hisi_zip_regs_fops); 922 } 923 924 return 0; 925 } 926 927 static int zip_cap_regs_show(struct seq_file *s, void *unused) 928 { 929 struct hisi_qm *qm = s->private; 930 u32 i, size; 931 932 size = qm->cap_tables.qm_cap_size; 933 for (i = 0; i < size; i++) 934 seq_printf(s, "%s= 0x%08x\n", qm->cap_tables.qm_cap_table[i].name, 935 qm->cap_tables.qm_cap_table[i].cap_val); 936 937 size = qm->cap_tables.dev_cap_size; 938 for (i = 0; i < size; i++) 939 seq_printf(s, "%s= 0x%08x\n", qm->cap_tables.dev_cap_table[i].name, 940 qm->cap_tables.dev_cap_table[i].cap_val); 941 942 return 0; 943 } 944 945 DEFINE_SHOW_ATTRIBUTE(zip_cap_regs); 946 947 static void hisi_zip_dfx_debug_init(struct hisi_qm *qm) 948 { 949 struct dfx_diff_registers *hzip_regs = qm->debug.acc_diff_regs; 950 struct hisi_zip *zip = container_of(qm, struct hisi_zip, qm); 951 struct hisi_zip_dfx *dfx = &zip->dfx; 952 struct dentry *tmp_dir; 953 void *data; 954 int i; 955 956 tmp_dir = debugfs_create_dir("zip_dfx", qm->debug.debug_root); 957 for (i = 0; i < ARRAY_SIZE(zip_dfx_files); i++) { 958 data = (atomic64_t *)((uintptr_t)dfx + zip_dfx_files[i].offset); 959 debugfs_create_file(zip_dfx_files[i].name, 960 0644, tmp_dir, data, 961 &zip_atomic64_ops); 962 } 963 964 if (qm->fun_type == QM_HW_PF && hzip_regs) 965 debugfs_create_file("diff_regs", 0444, tmp_dir, 966 qm, &hzip_diff_regs_fops); 967 968 debugfs_create_file("cap_regs", CAP_FILE_PERMISSION, 969 qm->debug.debug_root, qm, &zip_cap_regs_fops); 970 } 971 972 static int hisi_zip_ctrl_debug_init(struct hisi_qm *qm) 973 { 974 struct hisi_zip *zip = container_of(qm, struct hisi_zip, qm); 975 int i; 976 977 for (i = HZIP_CLEAR_ENABLE; i < HZIP_DEBUG_FILE_NUM; i++) { 978 spin_lock_init(&zip->ctrl->files[i].lock); 979 zip->ctrl->files[i].ctrl = zip->ctrl; 980 zip->ctrl->files[i].index = i; 981 982 debugfs_create_file(ctrl_debug_file_name[i], 0600, 983 qm->debug.debug_root, 984 zip->ctrl->files + i, 985 &ctrl_debug_fops); 986 } 987 988 return hisi_zip_core_debug_init(qm); 989 } 990 991 static int hisi_zip_debugfs_init(struct hisi_qm *qm) 992 { 993 struct device *dev = &qm->pdev->dev; 994 int ret; 995 996 ret = hisi_qm_regs_debugfs_init(qm, hzip_diff_regs, ARRAY_SIZE(hzip_diff_regs)); 997 if (ret) { 998 dev_warn(dev, "Failed to init ZIP diff regs!\n"); 999 return ret; 1000 } 1001 1002 qm->debug.sqe_mask_offset = HZIP_SQE_MASK_OFFSET; 1003 qm->debug.sqe_mask_len = HZIP_SQE_MASK_LEN; 1004 qm->debug.debug_root = debugfs_create_dir(dev_name(dev), 1005 hzip_debugfs_root); 1006 1007 hisi_qm_debug_init(qm); 1008 1009 if (qm->fun_type == QM_HW_PF) { 1010 ret = hisi_zip_ctrl_debug_init(qm); 1011 if (ret) 1012 goto debugfs_remove; 1013 } 1014 1015 hisi_zip_dfx_debug_init(qm); 1016 1017 return 0; 1018 1019 debugfs_remove: 1020 debugfs_remove_recursive(qm->debug.debug_root); 1021 hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(hzip_diff_regs)); 1022 return ret; 1023 } 1024 1025 /* hisi_zip_debug_regs_clear() - clear the zip debug regs */ 1026 static void hisi_zip_debug_regs_clear(struct hisi_qm *qm) 1027 { 1028 u32 zip_core_info; 1029 u8 zip_core_num; 1030 int i, j; 1031 1032 zip_core_info = qm->cap_tables.dev_cap_table[ZIP_CORE_INFO].cap_val; 1033 zip_core_num = (zip_core_info >> zip_basic_cap_info[ZIP_CORE_NUM_CAP].shift) & 1034 zip_basic_cap_info[ZIP_CORE_NUM_CAP].mask; 1035 1036 /* enable register read_clear bit */ 1037 writel(HZIP_RD_CNT_CLR_CE_EN, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE); 1038 for (i = 0; i < zip_core_num; i++) 1039 for (j = 0; j < ARRAY_SIZE(hzip_dfx_regs); j++) 1040 readl(get_zip_core_addr(qm, i) + 1041 hzip_dfx_regs[j].offset); 1042 1043 /* disable register read_clear bit */ 1044 writel(0x0, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE); 1045 1046 hisi_qm_debug_regs_clear(qm); 1047 } 1048 1049 static void hisi_zip_debugfs_exit(struct hisi_qm *qm) 1050 { 1051 debugfs_remove_recursive(qm->debug.debug_root); 1052 1053 hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(hzip_diff_regs)); 1054 1055 if (qm->fun_type == QM_HW_PF) { 1056 hisi_zip_debug_regs_clear(qm); 1057 qm->debug.curr_qm_qp_num = 0; 1058 } 1059 } 1060 1061 static int hisi_zip_show_last_regs_init(struct hisi_qm *qm) 1062 { 1063 int core_dfx_regs_num = ARRAY_SIZE(hzip_dump_dfx_regs); 1064 int com_dfx_regs_num = ARRAY_SIZE(hzip_com_dfx_regs); 1065 struct qm_debug *debug = &qm->debug; 1066 void __iomem *io_base; 1067 u32 zip_core_info; 1068 u32 zip_core_num; 1069 int i, j, idx; 1070 1071 zip_core_info = qm->cap_tables.dev_cap_table[ZIP_CORE_INFO].cap_val; 1072 zip_core_num = (zip_core_info >> zip_basic_cap_info[ZIP_CORE_NUM_CAP].shift) & 1073 zip_basic_cap_info[ZIP_CORE_NUM_CAP].mask; 1074 1075 debug->last_words = kcalloc(core_dfx_regs_num * zip_core_num + com_dfx_regs_num, 1076 sizeof(unsigned int), GFP_KERNEL); 1077 if (!debug->last_words) 1078 return -ENOMEM; 1079 1080 for (i = 0; i < com_dfx_regs_num; i++) { 1081 io_base = qm->io_base + hzip_com_dfx_regs[i].offset; 1082 debug->last_words[i] = readl_relaxed(io_base); 1083 } 1084 1085 for (i = 0; i < zip_core_num; i++) { 1086 io_base = get_zip_core_addr(qm, i); 1087 for (j = 0; j < core_dfx_regs_num; j++) { 1088 idx = com_dfx_regs_num + i * core_dfx_regs_num + j; 1089 debug->last_words[idx] = readl_relaxed( 1090 io_base + hzip_dump_dfx_regs[j].offset); 1091 } 1092 } 1093 1094 return 0; 1095 } 1096 1097 static void hisi_zip_show_last_regs_uninit(struct hisi_qm *qm) 1098 { 1099 struct qm_debug *debug = &qm->debug; 1100 1101 if (qm->fun_type == QM_HW_VF || !debug->last_words) 1102 return; 1103 1104 kfree(debug->last_words); 1105 debug->last_words = NULL; 1106 } 1107 1108 static void hisi_zip_show_last_dfx_regs(struct hisi_qm *qm) 1109 { 1110 int core_dfx_regs_num = ARRAY_SIZE(hzip_dump_dfx_regs); 1111 int com_dfx_regs_num = ARRAY_SIZE(hzip_com_dfx_regs); 1112 u32 zip_core_num, zip_comp_core_num; 1113 struct qm_debug *debug = &qm->debug; 1114 char buf[HZIP_BUF_SIZE]; 1115 u32 zip_core_info; 1116 void __iomem *base; 1117 int i, j, idx; 1118 u32 val; 1119 1120 if (qm->fun_type == QM_HW_VF || !debug->last_words) 1121 return; 1122 1123 for (i = 0; i < com_dfx_regs_num; i++) { 1124 val = readl_relaxed(qm->io_base + hzip_com_dfx_regs[i].offset); 1125 if (debug->last_words[i] != val) 1126 pci_info(qm->pdev, "com_dfx: %s \t= 0x%08x => 0x%08x\n", 1127 hzip_com_dfx_regs[i].name, debug->last_words[i], val); 1128 } 1129 1130 zip_core_info = qm->cap_tables.dev_cap_table[ZIP_CORE_INFO].cap_val; 1131 zip_core_num = (zip_core_info >> zip_basic_cap_info[ZIP_CORE_NUM_CAP].shift) & 1132 zip_basic_cap_info[ZIP_CORE_NUM_CAP].mask; 1133 zip_comp_core_num = (zip_core_info >> zip_basic_cap_info[ZIP_CLUSTER_COMP_NUM_CAP].shift) & 1134 zip_basic_cap_info[ZIP_CLUSTER_COMP_NUM_CAP].mask; 1135 1136 for (i = 0; i < zip_core_num; i++) { 1137 if (i < zip_comp_core_num) 1138 scnprintf(buf, sizeof(buf), "Comp_core-%d", i); 1139 else 1140 scnprintf(buf, sizeof(buf), "Decomp_core-%d", 1141 i - zip_comp_core_num); 1142 base = get_zip_core_addr(qm, i); 1143 1144 pci_info(qm->pdev, "==>%s:\n", buf); 1145 /* dump last word for dfx regs during control resetting */ 1146 for (j = 0; j < core_dfx_regs_num; j++) { 1147 idx = com_dfx_regs_num + i * core_dfx_regs_num + j; 1148 val = readl_relaxed(base + hzip_dump_dfx_regs[j].offset); 1149 if (debug->last_words[idx] != val) 1150 pci_info(qm->pdev, "%s \t= 0x%08x => 0x%08x\n", 1151 hzip_dump_dfx_regs[j].name, 1152 debug->last_words[idx], val); 1153 } 1154 } 1155 } 1156 1157 static void hisi_zip_log_hw_error(struct hisi_qm *qm, u32 err_sts) 1158 { 1159 const struct hisi_zip_hw_error *err = zip_hw_error; 1160 struct device *dev = &qm->pdev->dev; 1161 u32 err_val; 1162 1163 while (err->msg) { 1164 if (err->int_msk & err_sts) { 1165 dev_err(dev, "%s [error status=0x%x] found\n", 1166 err->msg, err->int_msk); 1167 1168 if (err->int_msk & HZIP_CORE_INT_STATUS_M_ECC) { 1169 err_val = readl(qm->io_base + 1170 HZIP_CORE_SRAM_ECC_ERR_INFO); 1171 dev_err(dev, "hisi-zip multi ecc sram num=0x%x\n", 1172 ((err_val >> 1173 HZIP_SRAM_ECC_ERR_NUM_SHIFT) & 0xFF)); 1174 } 1175 } 1176 err++; 1177 } 1178 } 1179 1180 static u32 hisi_zip_get_hw_err_status(struct hisi_qm *qm) 1181 { 1182 return readl(qm->io_base + HZIP_CORE_INT_STATUS); 1183 } 1184 1185 static void hisi_zip_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts) 1186 { 1187 writel(err_sts, qm->io_base + HZIP_CORE_INT_SOURCE); 1188 } 1189 1190 static void hisi_zip_disable_error_report(struct hisi_qm *qm, u32 err_type) 1191 { 1192 u32 nfe_mask = qm->err_info.dev_err.nfe; 1193 1194 writel(nfe_mask & (~err_type), qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); 1195 } 1196 1197 static void hisi_zip_enable_error_report(struct hisi_qm *qm) 1198 { 1199 u32 nfe_mask = qm->err_info.dev_err.nfe; 1200 u32 ce_mask = qm->err_info.dev_err.ce; 1201 1202 writel(nfe_mask, qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); 1203 writel(ce_mask, qm->io_base + HZIP_CORE_INT_RAS_CE_ENB); 1204 } 1205 1206 static void hisi_zip_open_axi_master_ooo(struct hisi_qm *qm) 1207 { 1208 u32 val; 1209 1210 val = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 1211 1212 writel(val & ~HZIP_AXI_SHUTDOWN_ENABLE, 1213 qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 1214 1215 writel(val | HZIP_AXI_SHUTDOWN_ENABLE, 1216 qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 1217 1218 hisi_dae_open_axi_master_ooo(qm); 1219 } 1220 1221 static void hisi_zip_close_axi_master_ooo(struct hisi_qm *qm) 1222 { 1223 u32 nfe_enb; 1224 1225 /* Disable ECC Mbit error report. */ 1226 nfe_enb = readl(qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); 1227 writel(nfe_enb & ~HZIP_CORE_INT_STATUS_M_ECC, 1228 qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); 1229 1230 /* Inject zip ECC Mbit error to block master ooo. */ 1231 writel(HZIP_CORE_INT_STATUS_M_ECC, 1232 qm->io_base + HZIP_CORE_INT_SET); 1233 } 1234 1235 static enum acc_err_result hisi_zip_get_err_result(struct hisi_qm *qm) 1236 { 1237 enum acc_err_result zip_result = ACC_ERR_NONE; 1238 enum acc_err_result dae_result; 1239 u32 err_status; 1240 1241 /* Get device hardware new error status */ 1242 err_status = hisi_zip_get_hw_err_status(qm); 1243 if (err_status) { 1244 if (err_status & qm->err_info.dev_err.ecc_2bits_mask) 1245 qm->err_status.is_dev_ecc_mbit = true; 1246 hisi_zip_log_hw_error(qm, err_status); 1247 1248 if (err_status & qm->err_info.dev_err.reset_mask) { 1249 /* Disable the same error reporting until device is recovered. */ 1250 hisi_zip_disable_error_report(qm, err_status); 1251 zip_result = ACC_ERR_NEED_RESET; 1252 } else { 1253 hisi_zip_clear_hw_err_status(qm, err_status); 1254 /* Avoid firmware disable error report, re-enable. */ 1255 hisi_zip_enable_error_report(qm); 1256 } 1257 } 1258 1259 dae_result = hisi_dae_get_err_result(qm); 1260 1261 return (zip_result == ACC_ERR_NEED_RESET || 1262 dae_result == ACC_ERR_NEED_RESET) ? 1263 ACC_ERR_NEED_RESET : ACC_ERR_RECOVERED; 1264 } 1265 1266 static bool hisi_zip_dev_is_abnormal(struct hisi_qm *qm) 1267 { 1268 u32 err_status; 1269 1270 err_status = hisi_zip_get_hw_err_status(qm); 1271 if (err_status & qm->err_info.dev_err.shutdown_mask) 1272 return true; 1273 1274 return hisi_dae_dev_is_abnormal(qm); 1275 } 1276 1277 static int hisi_zip_set_priv_status(struct hisi_qm *qm) 1278 { 1279 return hisi_dae_close_axi_master_ooo(qm); 1280 } 1281 1282 static void hisi_zip_disable_axi_error(struct hisi_qm *qm) 1283 { 1284 struct hisi_qm_err_mask *dev_err = &qm->err_info.dev_err; 1285 u32 err_mask = dev_err->ce | dev_err->nfe | dev_err->fe; 1286 u32 val; 1287 1288 val = ~(err_mask & (~HZIP_AXI_ERROR_MASK)); 1289 writel(val, qm->io_base + HZIP_CORE_INT_MASK_REG); 1290 1291 if (qm->ver > QM_HW_V2) 1292 writel(dev_err->shutdown_mask & (~HZIP_AXI_ERROR_MASK), 1293 qm->io_base + HZIP_OOO_SHUTDOWN_SEL); 1294 } 1295 1296 static void hisi_zip_enable_axi_error(struct hisi_qm *qm) 1297 { 1298 struct hisi_qm_err_mask *dev_err = &qm->err_info.dev_err; 1299 u32 err_mask = dev_err->ce | dev_err->nfe | dev_err->fe; 1300 1301 /* clear axi error source */ 1302 writel(HZIP_AXI_ERROR_MASK, qm->io_base + HZIP_CORE_INT_SOURCE); 1303 1304 writel(~err_mask, qm->io_base + HZIP_CORE_INT_MASK_REG); 1305 1306 if (qm->ver > QM_HW_V2) 1307 writel(dev_err->shutdown_mask, qm->io_base + HZIP_OOO_SHUTDOWN_SEL); 1308 } 1309 1310 static void hisi_zip_err_info_init(struct hisi_qm *qm) 1311 { 1312 struct hisi_qm_err_info *err_info = &qm->err_info; 1313 struct hisi_qm_err_mask *qm_err = &err_info->qm_err; 1314 struct hisi_qm_err_mask *dev_err = &err_info->dev_err; 1315 1316 qm_err->fe = HZIP_CORE_INT_RAS_FE_ENB_MASK; 1317 qm_err->ce = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_QM_CE_MASK_CAP, qm->cap_ver); 1318 qm_err->nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 1319 ZIP_QM_NFE_MASK_CAP, qm->cap_ver); 1320 qm_err->ecc_2bits_mask = QM_ECC_MBIT; 1321 qm_err->reset_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 1322 ZIP_QM_RESET_MASK_CAP, qm->cap_ver); 1323 qm_err->shutdown_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 1324 ZIP_QM_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 1325 1326 dev_err->fe = HZIP_CORE_INT_RAS_FE_ENB_MASK; 1327 dev_err->ce = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CE_MASK_CAP, qm->cap_ver); 1328 dev_err->nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_NFE_MASK_CAP, qm->cap_ver); 1329 dev_err->ecc_2bits_mask = HZIP_CORE_INT_STATUS_M_ECC; 1330 dev_err->shutdown_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 1331 ZIP_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 1332 dev_err->reset_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 1333 ZIP_RESET_MASK_CAP, qm->cap_ver); 1334 1335 err_info->msi_wr_port = HZIP_WR_PORT; 1336 err_info->acpi_rst = "ZRST"; 1337 } 1338 1339 static const struct hisi_qm_err_ini hisi_zip_err_ini = { 1340 .hw_init = hisi_zip_set_user_domain_and_cache, 1341 .hw_err_enable = hisi_zip_hw_error_enable, 1342 .hw_err_disable = hisi_zip_hw_error_disable, 1343 .get_dev_hw_err_status = hisi_zip_get_hw_err_status, 1344 .clear_dev_hw_err_status = hisi_zip_clear_hw_err_status, 1345 .open_axi_master_ooo = hisi_zip_open_axi_master_ooo, 1346 .close_axi_master_ooo = hisi_zip_close_axi_master_ooo, 1347 .open_sva_prefetch = hisi_zip_open_sva_prefetch, 1348 .close_sva_prefetch = hisi_zip_close_sva_prefetch, 1349 .show_last_dfx_regs = hisi_zip_show_last_dfx_regs, 1350 .err_info_init = hisi_zip_err_info_init, 1351 .get_err_result = hisi_zip_get_err_result, 1352 .set_priv_status = hisi_zip_set_priv_status, 1353 .dev_is_abnormal = hisi_zip_dev_is_abnormal, 1354 .disable_axi_error = hisi_zip_disable_axi_error, 1355 .enable_axi_error = hisi_zip_enable_axi_error, 1356 }; 1357 1358 static int hisi_zip_pf_probe_init(struct hisi_zip *hisi_zip) 1359 { 1360 struct hisi_qm *qm = &hisi_zip->qm; 1361 struct hisi_zip_ctrl *ctrl; 1362 int ret; 1363 1364 ctrl = devm_kzalloc(&qm->pdev->dev, sizeof(*ctrl), GFP_KERNEL); 1365 if (!ctrl) 1366 return -ENOMEM; 1367 1368 hisi_zip->ctrl = ctrl; 1369 ctrl->hisi_zip = hisi_zip; 1370 1371 ret = hisi_zip_set_user_domain_and_cache(qm); 1372 if (ret) 1373 return ret; 1374 1375 hisi_qm_dev_err_init(qm); 1376 hisi_zip_debug_regs_clear(qm); 1377 1378 ret = hisi_zip_show_last_regs_init(qm); 1379 if (ret) 1380 pci_err(qm->pdev, "Failed to init last word regs!\n"); 1381 1382 return ret; 1383 } 1384 1385 static int zip_pre_store_cap_reg(struct hisi_qm *qm) 1386 { 1387 struct hisi_qm_cap_record *zip_cap; 1388 struct pci_dev *pdev = qm->pdev; 1389 size_t i, size; 1390 1391 size = ARRAY_SIZE(zip_cap_query_info); 1392 zip_cap = devm_kcalloc(&pdev->dev, size, sizeof(*zip_cap), GFP_KERNEL); 1393 if (!zip_cap) 1394 return -ENOMEM; 1395 1396 for (i = 0; i < size; i++) { 1397 zip_cap[i].type = zip_cap_query_info[i].type; 1398 zip_cap[i].name = zip_cap_query_info[i].name; 1399 zip_cap[i].cap_val = hisi_qm_get_cap_value(qm, zip_cap_query_info, 1400 i, qm->cap_ver); 1401 } 1402 1403 qm->cap_tables.dev_cap_table = zip_cap; 1404 qm->cap_tables.dev_cap_size = size; 1405 1406 return 0; 1407 } 1408 1409 static void zip_set_channels(struct hisi_qm *qm) 1410 { 1411 struct qm_channel *channel_data = &qm->channel_data; 1412 int i; 1413 1414 channel_data->channel_num = HZIP_MAX_CHANNEL_NUM; 1415 for (i = 0; i < HZIP_MAX_CHANNEL_NUM; i++) 1416 channel_data->channel_name[i] = zip_channel_name[i]; 1417 } 1418 1419 static int hisi_zip_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) 1420 { 1421 u64 alg_msk; 1422 int ret; 1423 1424 qm->pdev = pdev; 1425 qm->mode = uacce_mode; 1426 qm->sqe_size = HZIP_SQE_SIZE; 1427 qm->dev_name = hisi_zip_name; 1428 1429 qm->fun_type = (pdev->device == PCI_DEVICE_ID_HUAWEI_ZIP_PF) ? 1430 QM_HW_PF : QM_HW_VF; 1431 if (qm->fun_type == QM_HW_PF) { 1432 qm->qp_base = HZIP_PF_DEF_Q_BASE; 1433 qm->qp_num = pf_q_num; 1434 qm->debug.curr_qm_qp_num = pf_q_num; 1435 qm->qm_list = &zip_devices; 1436 qm->err_ini = &hisi_zip_err_ini; 1437 if (pf_q_num_flag) 1438 set_bit(QM_MODULE_PARAM, &qm->misc_ctl); 1439 } else if (qm->fun_type == QM_HW_VF && qm->ver == QM_HW_V1) { 1440 /* 1441 * have no way to get qm configure in VM in v1 hardware, 1442 * so currently force PF to uses HZIP_PF_DEF_Q_NUM, and force 1443 * to trigger only one VF in v1 hardware. 1444 * 1445 * v2 hardware has no such problem. 1446 */ 1447 qm->qp_base = HZIP_PF_DEF_Q_NUM; 1448 qm->qp_num = HZIP_QUEUE_NUM_V1 - HZIP_PF_DEF_Q_NUM; 1449 } 1450 1451 ret = hisi_qm_init(qm); 1452 if (ret) { 1453 pci_err(qm->pdev, "Failed to init zip qm configures!\n"); 1454 return ret; 1455 } 1456 1457 zip_set_channels(qm); 1458 /* Fetch and save the value of capability registers */ 1459 ret = zip_pre_store_cap_reg(qm); 1460 if (ret) { 1461 pci_err(qm->pdev, "Failed to pre-store capability registers!\n"); 1462 goto err_qm_uninit; 1463 } 1464 1465 alg_msk = qm->cap_tables.dev_cap_table[ZIP_ALG_BITMAP].cap_val; 1466 ret = hisi_qm_set_algs(qm, alg_msk, zip_dev_algs, ARRAY_SIZE(zip_dev_algs)); 1467 if (ret) { 1468 pci_err(qm->pdev, "Failed to set zip algs!\n"); 1469 goto err_qm_uninit; 1470 } 1471 1472 ret = hisi_dae_set_alg(qm); 1473 if (ret) 1474 goto err_qm_uninit; 1475 1476 return 0; 1477 1478 err_qm_uninit: 1479 hisi_qm_uninit(qm); 1480 return ret; 1481 } 1482 1483 static void hisi_zip_qm_uninit(struct hisi_qm *qm) 1484 { 1485 hisi_qm_uninit(qm); 1486 } 1487 1488 static int hisi_zip_probe_init(struct hisi_zip *hisi_zip) 1489 { 1490 u32 type_rate = HZIP_SHAPER_RATE_COMPRESS; 1491 struct hisi_qm *qm = &hisi_zip->qm; 1492 int ret; 1493 1494 if (qm->fun_type == QM_HW_PF) { 1495 ret = hisi_zip_pf_probe_init(hisi_zip); 1496 if (ret) 1497 return ret; 1498 /* enable shaper type 0 */ 1499 if (qm->ver >= QM_HW_V3) { 1500 type_rate |= QM_SHAPER_ENABLE; 1501 1502 /* ZIP need to enable shaper type 1 */ 1503 type_rate |= HZIP_SHAPER_RATE_DECOMPRESS << QM_SHAPER_TYPE1_OFFSET; 1504 qm->type_rate = type_rate; 1505 } 1506 } 1507 1508 return 0; 1509 } 1510 1511 static void hisi_zip_probe_uninit(struct hisi_qm *qm) 1512 { 1513 if (qm->fun_type == QM_HW_VF) 1514 return; 1515 1516 hisi_zip_show_last_regs_uninit(qm); 1517 hisi_zip_close_sva_prefetch(qm); 1518 hisi_qm_dev_err_uninit(qm); 1519 } 1520 1521 static int hisi_zip_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1522 { 1523 struct hisi_zip *hisi_zip; 1524 struct hisi_qm *qm; 1525 int ret; 1526 1527 hisi_zip = devm_kzalloc(&pdev->dev, sizeof(*hisi_zip), GFP_KERNEL); 1528 if (!hisi_zip) 1529 return -ENOMEM; 1530 1531 qm = &hisi_zip->qm; 1532 1533 ret = hisi_zip_qm_init(qm, pdev); 1534 if (ret) { 1535 pci_err(pdev, "Failed to init ZIP QM (%d)!\n", ret); 1536 return ret; 1537 } 1538 1539 ret = hisi_zip_probe_init(hisi_zip); 1540 if (ret) { 1541 pci_err(pdev, "Failed to probe (%d)!\n", ret); 1542 goto err_qm_uninit; 1543 } 1544 1545 ret = hisi_qm_start(qm); 1546 if (ret) 1547 goto err_probe_uninit; 1548 1549 ret = hisi_zip_debugfs_init(qm); 1550 if (ret) 1551 pci_err(pdev, "failed to init debugfs (%d)!\n", ret); 1552 1553 hisi_qm_add_list(qm, &zip_devices); 1554 ret = hisi_qm_alg_register(qm, &zip_devices, HZIP_CTX_Q_NUM_DEF); 1555 if (ret < 0) { 1556 pci_err(pdev, "failed to register driver to crypto!\n"); 1557 goto err_qm_del_list; 1558 } 1559 1560 ret = hisi_qm_register_uacce(qm); 1561 if (ret) { 1562 pci_err(pdev, "failed to register uacce (%d)!\n", ret); 1563 goto err_qm_alg_unregister; 1564 } 1565 1566 if (qm->fun_type == QM_HW_PF && vfs_num > 0) { 1567 ret = hisi_qm_sriov_enable(pdev, vfs_num); 1568 if (ret < 0) 1569 goto err_qm_alg_unregister; 1570 } 1571 1572 hisi_qm_pm_init(qm); 1573 1574 return 0; 1575 1576 err_qm_alg_unregister: 1577 hisi_qm_alg_unregister(qm, &zip_devices, HZIP_CTX_Q_NUM_DEF); 1578 1579 err_qm_del_list: 1580 hisi_qm_del_list(qm, &zip_devices); 1581 hisi_zip_debugfs_exit(qm); 1582 hisi_qm_stop(qm, QM_NORMAL); 1583 1584 err_probe_uninit: 1585 hisi_zip_probe_uninit(qm); 1586 1587 err_qm_uninit: 1588 hisi_zip_qm_uninit(qm); 1589 1590 return ret; 1591 } 1592 1593 static void hisi_zip_remove(struct pci_dev *pdev) 1594 { 1595 struct hisi_qm *qm = pci_get_drvdata(pdev); 1596 1597 hisi_qm_pm_uninit(qm); 1598 hisi_qm_wait_task_finish(qm, &zip_devices); 1599 hisi_qm_alg_unregister(qm, &zip_devices, HZIP_CTX_Q_NUM_DEF); 1600 hisi_qm_del_list(qm, &zip_devices); 1601 1602 if (qm->fun_type == QM_HW_PF && qm->vfs_num) 1603 hisi_qm_sriov_disable(pdev, true); 1604 1605 hisi_zip_debugfs_exit(qm); 1606 hisi_qm_stop(qm, QM_NORMAL); 1607 hisi_zip_probe_uninit(qm); 1608 hisi_zip_qm_uninit(qm); 1609 } 1610 1611 static const struct dev_pm_ops hisi_zip_pm_ops = { 1612 SET_RUNTIME_PM_OPS(hisi_qm_suspend, hisi_qm_resume, NULL) 1613 }; 1614 1615 static const struct pci_error_handlers hisi_zip_err_handler = { 1616 .error_detected = hisi_qm_dev_err_detected, 1617 .slot_reset = hisi_qm_dev_slot_reset, 1618 .reset_prepare = hisi_qm_reset_prepare, 1619 .reset_done = hisi_qm_reset_done, 1620 }; 1621 1622 static struct pci_driver hisi_zip_pci_driver = { 1623 .name = "hisi_zip", 1624 .id_table = hisi_zip_dev_ids, 1625 .probe = hisi_zip_probe, 1626 .remove = hisi_zip_remove, 1627 .sriov_configure = IS_ENABLED(CONFIG_PCI_IOV) ? 1628 hisi_qm_sriov_configure : NULL, 1629 .err_handler = &hisi_zip_err_handler, 1630 .shutdown = hisi_qm_dev_shutdown, 1631 .driver.pm = &hisi_zip_pm_ops, 1632 }; 1633 1634 struct pci_driver *hisi_zip_get_pf_driver(void) 1635 { 1636 return &hisi_zip_pci_driver; 1637 } 1638 EXPORT_SYMBOL_GPL(hisi_zip_get_pf_driver); 1639 1640 static void hisi_zip_register_debugfs(void) 1641 { 1642 if (!debugfs_initialized()) 1643 return; 1644 1645 hzip_debugfs_root = debugfs_create_dir("hisi_zip", NULL); 1646 } 1647 1648 static void hisi_zip_unregister_debugfs(void) 1649 { 1650 debugfs_remove_recursive(hzip_debugfs_root); 1651 } 1652 1653 static int __init hisi_zip_init(void) 1654 { 1655 int ret; 1656 1657 hisi_qm_init_list(&zip_devices); 1658 hisi_zip_register_debugfs(); 1659 1660 ret = pci_register_driver(&hisi_zip_pci_driver); 1661 if (ret < 0) { 1662 hisi_zip_unregister_debugfs(); 1663 pr_err("Failed to register pci driver.\n"); 1664 } 1665 1666 return ret; 1667 } 1668 1669 static void __exit hisi_zip_exit(void) 1670 { 1671 pci_unregister_driver(&hisi_zip_pci_driver); 1672 hisi_zip_unregister_debugfs(); 1673 } 1674 1675 module_init(hisi_zip_init); 1676 module_exit(hisi_zip_exit); 1677 1678 MODULE_LICENSE("GPL v2"); 1679 MODULE_AUTHOR("Zhou Wang <wangzhou1@hisilicon.com>"); 1680 MODULE_DESCRIPTION("Driver for HiSilicon ZIP accelerator"); 1681