1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2019 HiSilicon Limited. */ 3 #include <linux/acpi.h> 4 #include <linux/bitops.h> 5 #include <linux/debugfs.h> 6 #include <linux/init.h> 7 #include <linux/io.h> 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/pci.h> 11 #include <linux/pm_runtime.h> 12 #include <linux/seq_file.h> 13 #include <linux/topology.h> 14 #include <linux/uacce.h> 15 #include "zip.h" 16 17 #define PCI_DEVICE_ID_HUAWEI_ZIP_PF 0xa250 18 19 #define HZIP_QUEUE_NUM_V1 4096 20 21 #define HZIP_CLOCK_GATE_CTRL 0x301004 22 #define HZIP_DECOMP_CHECK_ENABLE BIT(16) 23 #define HZIP_FSM_MAX_CNT 0x301008 24 25 #define HZIP_PORT_ARCA_CHE_0 0x301040 26 #define HZIP_PORT_ARCA_CHE_1 0x301044 27 #define HZIP_PORT_AWCA_CHE_0 0x301060 28 #define HZIP_PORT_AWCA_CHE_1 0x301064 29 #define HZIP_CACHE_ALL_EN 0xffffffff 30 31 #define HZIP_BD_RUSER_32_63 0x301110 32 #define HZIP_SGL_RUSER_32_63 0x30111c 33 #define HZIP_DATA_RUSER_32_63 0x301128 34 #define HZIP_DATA_WUSER_32_63 0x301134 35 #define HZIP_BD_WUSER_32_63 0x301140 36 37 #define HZIP_QM_IDEL_STATUS 0x3040e4 38 39 #define HZIP_CORE_DFX_BASE 0x301000 40 #define HZIP_CLOCK_GATED_CONTL 0X301004 41 #define HZIP_CORE_DFX_COMP_0 0x302000 42 #define HZIP_CORE_DFX_COMP_1 0x303000 43 #define HZIP_CORE_DFX_DECOMP_0 0x304000 44 #define HZIP_CORE_DFX_DECOMP_1 0x305000 45 #define HZIP_CORE_DFX_DECOMP_2 0x306000 46 #define HZIP_CORE_DFX_DECOMP_3 0x307000 47 #define HZIP_CORE_DFX_DECOMP_4 0x308000 48 #define HZIP_CORE_DFX_DECOMP_5 0x309000 49 #define HZIP_CORE_REGS_BASE_LEN 0xB0 50 #define HZIP_CORE_REGS_DFX_LEN 0x28 51 52 #define HZIP_CORE_INT_SOURCE 0x3010A0 53 #define HZIP_CORE_INT_MASK_REG 0x3010A4 54 #define HZIP_CORE_INT_SET 0x3010A8 55 #define HZIP_CORE_INT_STATUS 0x3010AC 56 #define HZIP_CORE_INT_STATUS_M_ECC BIT(1) 57 #define HZIP_CORE_SRAM_ECC_ERR_INFO 0x301148 58 #define HZIP_CORE_INT_RAS_CE_ENB 0x301160 59 #define HZIP_CORE_INT_RAS_NFE_ENB 0x301164 60 #define HZIP_CORE_INT_RAS_FE_ENB 0x301168 61 #define HZIP_CORE_INT_RAS_FE_ENB_MASK 0x0 62 #define HZIP_OOO_SHUTDOWN_SEL 0x30120C 63 #define HZIP_SRAM_ECC_ERR_NUM_SHIFT 16 64 #define HZIP_SRAM_ECC_ERR_ADDR_SHIFT 24 65 #define HZIP_CORE_INT_MASK_ALL GENMASK(12, 0) 66 #define HZIP_SQE_SIZE 128 67 #define HZIP_PF_DEF_Q_NUM 64 68 #define HZIP_PF_DEF_Q_BASE 0 69 #define HZIP_CTX_Q_NUM_DEF 2 70 71 #define HZIP_SOFT_CTRL_CNT_CLR_CE 0x301000 72 #define HZIP_SOFT_CTRL_CNT_CLR_CE_BIT BIT(0) 73 #define HZIP_SOFT_CTRL_ZIP_CONTROL 0x30100C 74 #define HZIP_AXI_SHUTDOWN_ENABLE BIT(14) 75 #define HZIP_WR_PORT BIT(11) 76 77 #define HZIP_DEV_ALG_MAX_LEN 256 78 #define HZIP_ALG_ZLIB_BIT GENMASK(1, 0) 79 #define HZIP_ALG_GZIP_BIT GENMASK(3, 2) 80 #define HZIP_ALG_DEFLATE_BIT GENMASK(5, 4) 81 #define HZIP_ALG_LZ77_BIT GENMASK(7, 6) 82 83 #define HZIP_BUF_SIZE 22 84 #define HZIP_SQE_MASK_OFFSET 64 85 #define HZIP_SQE_MASK_LEN 48 86 87 #define HZIP_CNT_CLR_CE_EN BIT(0) 88 #define HZIP_RO_CNT_CLR_CE_EN BIT(2) 89 #define HZIP_RD_CNT_CLR_CE_EN (HZIP_CNT_CLR_CE_EN | \ 90 HZIP_RO_CNT_CLR_CE_EN) 91 92 #define HZIP_PREFETCH_CFG 0x3011B0 93 #define HZIP_SVA_TRANS 0x3011C4 94 #define HZIP_PREFETCH_ENABLE (~(BIT(26) | BIT(17) | BIT(0))) 95 #define HZIP_SVA_PREFETCH_DISABLE BIT(26) 96 #define HZIP_SVA_DISABLE_READY (BIT(26) | BIT(30)) 97 #define HZIP_SHAPER_RATE_COMPRESS 750 98 #define HZIP_SHAPER_RATE_DECOMPRESS 140 99 #define HZIP_DELAY_1_US 1 100 #define HZIP_POLL_TIMEOUT_US 1000 101 102 /* clock gating */ 103 #define HZIP_PEH_CFG_AUTO_GATE 0x3011A8 104 #define HZIP_PEH_CFG_AUTO_GATE_EN BIT(0) 105 #define HZIP_CORE_GATED_EN GENMASK(15, 8) 106 #define HZIP_CORE_GATED_OOO_EN BIT(29) 107 #define HZIP_CLOCK_GATED_EN (HZIP_CORE_GATED_EN | \ 108 HZIP_CORE_GATED_OOO_EN) 109 110 static const char hisi_zip_name[] = "hisi_zip"; 111 static struct dentry *hzip_debugfs_root; 112 113 struct hisi_zip_hw_error { 114 u32 int_msk; 115 const char *msg; 116 }; 117 118 struct zip_dfx_item { 119 const char *name; 120 u32 offset; 121 }; 122 123 struct zip_dev_alg { 124 u32 alg_msk; 125 const char *algs; 126 }; 127 128 static const struct zip_dev_alg zip_dev_algs[] = { { 129 .alg_msk = HZIP_ALG_ZLIB_BIT, 130 .algs = "zlib\n", 131 }, { 132 .alg_msk = HZIP_ALG_GZIP_BIT, 133 .algs = "gzip\n", 134 }, { 135 .alg_msk = HZIP_ALG_DEFLATE_BIT, 136 .algs = "deflate\n", 137 }, { 138 .alg_msk = HZIP_ALG_LZ77_BIT, 139 .algs = "lz77_zstd\n", 140 }, 141 }; 142 143 static struct hisi_qm_list zip_devices = { 144 .register_to_crypto = hisi_zip_register_to_crypto, 145 .unregister_from_crypto = hisi_zip_unregister_from_crypto, 146 }; 147 148 static struct zip_dfx_item zip_dfx_files[] = { 149 {"send_cnt", offsetof(struct hisi_zip_dfx, send_cnt)}, 150 {"recv_cnt", offsetof(struct hisi_zip_dfx, recv_cnt)}, 151 {"send_busy_cnt", offsetof(struct hisi_zip_dfx, send_busy_cnt)}, 152 {"err_bd_cnt", offsetof(struct hisi_zip_dfx, err_bd_cnt)}, 153 }; 154 155 static const struct hisi_zip_hw_error zip_hw_error[] = { 156 { .int_msk = BIT(0), .msg = "zip_ecc_1bitt_err" }, 157 { .int_msk = BIT(1), .msg = "zip_ecc_2bit_err" }, 158 { .int_msk = BIT(2), .msg = "zip_axi_rresp_err" }, 159 { .int_msk = BIT(3), .msg = "zip_axi_bresp_err" }, 160 { .int_msk = BIT(4), .msg = "zip_src_addr_parse_err" }, 161 { .int_msk = BIT(5), .msg = "zip_dst_addr_parse_err" }, 162 { .int_msk = BIT(6), .msg = "zip_pre_in_addr_err" }, 163 { .int_msk = BIT(7), .msg = "zip_pre_in_data_err" }, 164 { .int_msk = BIT(8), .msg = "zip_com_inf_err" }, 165 { .int_msk = BIT(9), .msg = "zip_enc_inf_err" }, 166 { .int_msk = BIT(10), .msg = "zip_pre_out_err" }, 167 { .int_msk = BIT(11), .msg = "zip_axi_poison_err" }, 168 { .int_msk = BIT(12), .msg = "zip_sva_err" }, 169 { /* sentinel */ } 170 }; 171 172 enum ctrl_debug_file_index { 173 HZIP_CLEAR_ENABLE, 174 HZIP_DEBUG_FILE_NUM, 175 }; 176 177 static const char * const ctrl_debug_file_name[] = { 178 [HZIP_CLEAR_ENABLE] = "clear_enable", 179 }; 180 181 struct ctrl_debug_file { 182 enum ctrl_debug_file_index index; 183 spinlock_t lock; 184 struct hisi_zip_ctrl *ctrl; 185 }; 186 187 /* 188 * One ZIP controller has one PF and multiple VFs, some global configurations 189 * which PF has need this structure. 190 * 191 * Just relevant for PF. 192 */ 193 struct hisi_zip_ctrl { 194 struct hisi_zip *hisi_zip; 195 struct ctrl_debug_file files[HZIP_DEBUG_FILE_NUM]; 196 }; 197 198 enum zip_cap_type { 199 ZIP_QM_NFE_MASK_CAP = 0x0, 200 ZIP_QM_RESET_MASK_CAP, 201 ZIP_QM_OOO_SHUTDOWN_MASK_CAP, 202 ZIP_QM_CE_MASK_CAP, 203 ZIP_NFE_MASK_CAP, 204 ZIP_RESET_MASK_CAP, 205 ZIP_OOO_SHUTDOWN_MASK_CAP, 206 ZIP_CE_MASK_CAP, 207 ZIP_CLUSTER_NUM_CAP, 208 ZIP_CORE_TYPE_NUM_CAP, 209 ZIP_CORE_NUM_CAP, 210 ZIP_CLUSTER_COMP_NUM_CAP, 211 ZIP_CLUSTER_DECOMP_NUM_CAP, 212 ZIP_DECOMP_ENABLE_BITMAP, 213 ZIP_COMP_ENABLE_BITMAP, 214 ZIP_DRV_ALG_BITMAP, 215 ZIP_DEV_ALG_BITMAP, 216 ZIP_CORE1_ALG_BITMAP, 217 ZIP_CORE2_ALG_BITMAP, 218 ZIP_CORE3_ALG_BITMAP, 219 ZIP_CORE4_ALG_BITMAP, 220 ZIP_CORE5_ALG_BITMAP, 221 ZIP_CAP_MAX 222 }; 223 224 static struct hisi_qm_cap_info zip_basic_cap_info[] = { 225 {ZIP_QM_NFE_MASK_CAP, 0x3124, 0, GENMASK(31, 0), 0x0, 0x1C57, 0x7C77}, 226 {ZIP_QM_RESET_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0xC57, 0x6C77}, 227 {ZIP_QM_OOO_SHUTDOWN_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0x4, 0x6C77}, 228 {ZIP_QM_CE_MASK_CAP, 0x312C, 0, GENMASK(31, 0), 0x0, 0x8, 0x8}, 229 {ZIP_NFE_MASK_CAP, 0x3130, 0, GENMASK(31, 0), 0x0, 0x7FE, 0x1FFE}, 230 {ZIP_RESET_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x7FE, 0x7FE}, 231 {ZIP_OOO_SHUTDOWN_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x2, 0x7FE}, 232 {ZIP_CE_MASK_CAP, 0x3138, 0, GENMASK(31, 0), 0x0, 0x1, 0x1}, 233 {ZIP_CLUSTER_NUM_CAP, 0x313C, 28, GENMASK(3, 0), 0x1, 0x1, 0x1}, 234 {ZIP_CORE_TYPE_NUM_CAP, 0x313C, 24, GENMASK(3, 0), 0x2, 0x2, 0x2}, 235 {ZIP_CORE_NUM_CAP, 0x313C, 16, GENMASK(7, 0), 0x8, 0x8, 0x5}, 236 {ZIP_CLUSTER_COMP_NUM_CAP, 0x313C, 8, GENMASK(7, 0), 0x2, 0x2, 0x2}, 237 {ZIP_CLUSTER_DECOMP_NUM_CAP, 0x313C, 0, GENMASK(7, 0), 0x6, 0x6, 0x3}, 238 {ZIP_DECOMP_ENABLE_BITMAP, 0x3140, 16, GENMASK(15, 0), 0xFC, 0xFC, 0x1C}, 239 {ZIP_COMP_ENABLE_BITMAP, 0x3140, 0, GENMASK(15, 0), 0x3, 0x3, 0x3}, 240 {ZIP_DRV_ALG_BITMAP, 0x3144, 0, GENMASK(31, 0), 0x0, 0x0, 0x30}, 241 {ZIP_DEV_ALG_BITMAP, 0x3148, 0, GENMASK(31, 0), 0xF, 0xF, 0x3F}, 242 {ZIP_CORE1_ALG_BITMAP, 0x314C, 0, GENMASK(31, 0), 0x5, 0x5, 0xD5}, 243 {ZIP_CORE2_ALG_BITMAP, 0x3150, 0, GENMASK(31, 0), 0x5, 0x5, 0xD5}, 244 {ZIP_CORE3_ALG_BITMAP, 0x3154, 0, GENMASK(31, 0), 0xA, 0xA, 0x2A}, 245 {ZIP_CORE4_ALG_BITMAP, 0x3158, 0, GENMASK(31, 0), 0xA, 0xA, 0x2A}, 246 {ZIP_CORE5_ALG_BITMAP, 0x315C, 0, GENMASK(31, 0), 0xA, 0xA, 0x2A}, 247 {ZIP_CAP_MAX, 0x317c, 0, GENMASK(0, 0), 0x0, 0x0, 0x0} 248 }; 249 250 enum { 251 HZIP_COMP_CORE0, 252 HZIP_COMP_CORE1, 253 HZIP_DECOMP_CORE0, 254 HZIP_DECOMP_CORE1, 255 HZIP_DECOMP_CORE2, 256 HZIP_DECOMP_CORE3, 257 HZIP_DECOMP_CORE4, 258 HZIP_DECOMP_CORE5, 259 }; 260 261 static const u64 core_offsets[] = { 262 [HZIP_COMP_CORE0] = 0x302000, 263 [HZIP_COMP_CORE1] = 0x303000, 264 [HZIP_DECOMP_CORE0] = 0x304000, 265 [HZIP_DECOMP_CORE1] = 0x305000, 266 [HZIP_DECOMP_CORE2] = 0x306000, 267 [HZIP_DECOMP_CORE3] = 0x307000, 268 [HZIP_DECOMP_CORE4] = 0x308000, 269 [HZIP_DECOMP_CORE5] = 0x309000, 270 }; 271 272 static const struct debugfs_reg32 hzip_dfx_regs[] = { 273 {"HZIP_GET_BD_NUM ", 0x00ull}, 274 {"HZIP_GET_RIGHT_BD ", 0x04ull}, 275 {"HZIP_GET_ERROR_BD ", 0x08ull}, 276 {"HZIP_DONE_BD_NUM ", 0x0cull}, 277 {"HZIP_WORK_CYCLE ", 0x10ull}, 278 {"HZIP_IDLE_CYCLE ", 0x18ull}, 279 {"HZIP_MAX_DELAY ", 0x20ull}, 280 {"HZIP_MIN_DELAY ", 0x24ull}, 281 {"HZIP_AVG_DELAY ", 0x28ull}, 282 {"HZIP_MEM_VISIBLE_DATA ", 0x30ull}, 283 {"HZIP_MEM_VISIBLE_ADDR ", 0x34ull}, 284 {"HZIP_CONSUMED_BYTE ", 0x38ull}, 285 {"HZIP_PRODUCED_BYTE ", 0x40ull}, 286 {"HZIP_COMP_INF ", 0x70ull}, 287 {"HZIP_PRE_OUT ", 0x78ull}, 288 {"HZIP_BD_RD ", 0x7cull}, 289 {"HZIP_BD_WR ", 0x80ull}, 290 {"HZIP_GET_BD_AXI_ERR_NUM ", 0x84ull}, 291 {"HZIP_GET_BD_PARSE_ERR_NUM ", 0x88ull}, 292 {"HZIP_ADD_BD_AXI_ERR_NUM ", 0x8cull}, 293 {"HZIP_DECOMP_STF_RELOAD_CURR_ST ", 0x94ull}, 294 {"HZIP_DECOMP_LZ77_CURR_ST ", 0x9cull}, 295 }; 296 297 static const struct debugfs_reg32 hzip_com_dfx_regs[] = { 298 {"HZIP_CLOCK_GATE_CTRL ", 0x301004}, 299 {"HZIP_CORE_INT_RAS_CE_ENB ", 0x301160}, 300 {"HZIP_CORE_INT_RAS_NFE_ENB ", 0x301164}, 301 {"HZIP_CORE_INT_RAS_FE_ENB ", 0x301168}, 302 {"HZIP_UNCOM_ERR_RAS_CTRL ", 0x30116C}, 303 }; 304 305 static const struct debugfs_reg32 hzip_dump_dfx_regs[] = { 306 {"HZIP_GET_BD_NUM ", 0x00ull}, 307 {"HZIP_GET_RIGHT_BD ", 0x04ull}, 308 {"HZIP_GET_ERROR_BD ", 0x08ull}, 309 {"HZIP_DONE_BD_NUM ", 0x0cull}, 310 {"HZIP_MAX_DELAY ", 0x20ull}, 311 }; 312 313 /* define the ZIP's dfx regs region and region length */ 314 static struct dfx_diff_registers hzip_diff_regs[] = { 315 { 316 .reg_offset = HZIP_CORE_DFX_BASE, 317 .reg_len = HZIP_CORE_REGS_BASE_LEN, 318 }, { 319 .reg_offset = HZIP_CORE_DFX_COMP_0, 320 .reg_len = HZIP_CORE_REGS_DFX_LEN, 321 }, { 322 .reg_offset = HZIP_CORE_DFX_COMP_1, 323 .reg_len = HZIP_CORE_REGS_DFX_LEN, 324 }, { 325 .reg_offset = HZIP_CORE_DFX_DECOMP_0, 326 .reg_len = HZIP_CORE_REGS_DFX_LEN, 327 }, { 328 .reg_offset = HZIP_CORE_DFX_DECOMP_1, 329 .reg_len = HZIP_CORE_REGS_DFX_LEN, 330 }, { 331 .reg_offset = HZIP_CORE_DFX_DECOMP_2, 332 .reg_len = HZIP_CORE_REGS_DFX_LEN, 333 }, { 334 .reg_offset = HZIP_CORE_DFX_DECOMP_3, 335 .reg_len = HZIP_CORE_REGS_DFX_LEN, 336 }, { 337 .reg_offset = HZIP_CORE_DFX_DECOMP_4, 338 .reg_len = HZIP_CORE_REGS_DFX_LEN, 339 }, { 340 .reg_offset = HZIP_CORE_DFX_DECOMP_5, 341 .reg_len = HZIP_CORE_REGS_DFX_LEN, 342 }, 343 }; 344 345 static int hzip_diff_regs_show(struct seq_file *s, void *unused) 346 { 347 struct hisi_qm *qm = s->private; 348 349 hisi_qm_acc_diff_regs_dump(qm, s, qm->debug.acc_diff_regs, 350 ARRAY_SIZE(hzip_diff_regs)); 351 352 return 0; 353 } 354 DEFINE_SHOW_ATTRIBUTE(hzip_diff_regs); 355 static const struct kernel_param_ops zip_uacce_mode_ops = { 356 .set = uacce_mode_set, 357 .get = param_get_int, 358 }; 359 360 /* 361 * uacce_mode = 0 means zip only register to crypto, 362 * uacce_mode = 1 means zip both register to crypto and uacce. 363 */ 364 static u32 uacce_mode = UACCE_MODE_NOUACCE; 365 module_param_cb(uacce_mode, &zip_uacce_mode_ops, &uacce_mode, 0444); 366 MODULE_PARM_DESC(uacce_mode, UACCE_MODE_DESC); 367 368 static bool pf_q_num_flag; 369 static int pf_q_num_set(const char *val, const struct kernel_param *kp) 370 { 371 pf_q_num_flag = true; 372 373 return q_num_set(val, kp, PCI_DEVICE_ID_HUAWEI_ZIP_PF); 374 } 375 376 static const struct kernel_param_ops pf_q_num_ops = { 377 .set = pf_q_num_set, 378 .get = param_get_int, 379 }; 380 381 static u32 pf_q_num = HZIP_PF_DEF_Q_NUM; 382 module_param_cb(pf_q_num, &pf_q_num_ops, &pf_q_num, 0444); 383 MODULE_PARM_DESC(pf_q_num, "Number of queues in PF(v1 2-4096, v2 2-1024)"); 384 385 static const struct kernel_param_ops vfs_num_ops = { 386 .set = vfs_num_set, 387 .get = param_get_int, 388 }; 389 390 static u32 vfs_num; 391 module_param_cb(vfs_num, &vfs_num_ops, &vfs_num, 0444); 392 MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63), 0(default)"); 393 394 static const struct pci_device_id hisi_zip_dev_ids[] = { 395 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_ZIP_PF) }, 396 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_ZIP_VF) }, 397 { 0, } 398 }; 399 MODULE_DEVICE_TABLE(pci, hisi_zip_dev_ids); 400 401 int zip_create_qps(struct hisi_qp **qps, int qp_num, int node) 402 { 403 if (node == NUMA_NO_NODE) 404 node = cpu_to_node(smp_processor_id()); 405 406 return hisi_qm_alloc_qps_node(&zip_devices, qp_num, 0, node, qps); 407 } 408 409 bool hisi_zip_alg_support(struct hisi_qm *qm, u32 alg) 410 { 411 u32 cap_val; 412 413 cap_val = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_DRV_ALG_BITMAP, qm->cap_ver); 414 if ((alg & cap_val) == alg) 415 return true; 416 417 return false; 418 } 419 420 static int hisi_zip_set_qm_algs(struct hisi_qm *qm) 421 { 422 struct device *dev = &qm->pdev->dev; 423 char *algs, *ptr; 424 u32 alg_mask; 425 int i; 426 427 if (!qm->use_sva) 428 return 0; 429 430 algs = devm_kzalloc(dev, HZIP_DEV_ALG_MAX_LEN * sizeof(char), GFP_KERNEL); 431 if (!algs) 432 return -ENOMEM; 433 434 alg_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_DEV_ALG_BITMAP, qm->cap_ver); 435 436 for (i = 0; i < ARRAY_SIZE(zip_dev_algs); i++) 437 if (alg_mask & zip_dev_algs[i].alg_msk) 438 strcat(algs, zip_dev_algs[i].algs); 439 440 ptr = strrchr(algs, '\n'); 441 if (ptr) 442 *ptr = '\0'; 443 444 qm->uacce->algs = algs; 445 446 return 0; 447 } 448 449 static void hisi_zip_open_sva_prefetch(struct hisi_qm *qm) 450 { 451 u32 val; 452 int ret; 453 454 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps)) 455 return; 456 457 /* Enable prefetch */ 458 val = readl_relaxed(qm->io_base + HZIP_PREFETCH_CFG); 459 val &= HZIP_PREFETCH_ENABLE; 460 writel(val, qm->io_base + HZIP_PREFETCH_CFG); 461 462 ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_PREFETCH_CFG, 463 val, !(val & HZIP_SVA_PREFETCH_DISABLE), 464 HZIP_DELAY_1_US, HZIP_POLL_TIMEOUT_US); 465 if (ret) 466 pci_err(qm->pdev, "failed to open sva prefetch\n"); 467 } 468 469 static void hisi_zip_close_sva_prefetch(struct hisi_qm *qm) 470 { 471 u32 val; 472 int ret; 473 474 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps)) 475 return; 476 477 val = readl_relaxed(qm->io_base + HZIP_PREFETCH_CFG); 478 val |= HZIP_SVA_PREFETCH_DISABLE; 479 writel(val, qm->io_base + HZIP_PREFETCH_CFG); 480 481 ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_SVA_TRANS, 482 val, !(val & HZIP_SVA_DISABLE_READY), 483 HZIP_DELAY_1_US, HZIP_POLL_TIMEOUT_US); 484 if (ret) 485 pci_err(qm->pdev, "failed to close sva prefetch\n"); 486 } 487 488 static void hisi_zip_enable_clock_gate(struct hisi_qm *qm) 489 { 490 u32 val; 491 492 if (qm->ver < QM_HW_V3) 493 return; 494 495 val = readl(qm->io_base + HZIP_CLOCK_GATE_CTRL); 496 val |= HZIP_CLOCK_GATED_EN; 497 writel(val, qm->io_base + HZIP_CLOCK_GATE_CTRL); 498 499 val = readl(qm->io_base + HZIP_PEH_CFG_AUTO_GATE); 500 val |= HZIP_PEH_CFG_AUTO_GATE_EN; 501 writel(val, qm->io_base + HZIP_PEH_CFG_AUTO_GATE); 502 } 503 504 static int hisi_zip_set_user_domain_and_cache(struct hisi_qm *qm) 505 { 506 void __iomem *base = qm->io_base; 507 u32 dcomp_bm, comp_bm; 508 509 /* qm user domain */ 510 writel(AXUSER_BASE, base + QM_ARUSER_M_CFG_1); 511 writel(ARUSER_M_CFG_ENABLE, base + QM_ARUSER_M_CFG_ENABLE); 512 writel(AXUSER_BASE, base + QM_AWUSER_M_CFG_1); 513 writel(AWUSER_M_CFG_ENABLE, base + QM_AWUSER_M_CFG_ENABLE); 514 writel(WUSER_M_CFG_ENABLE, base + QM_WUSER_M_CFG_ENABLE); 515 516 /* qm cache */ 517 writel(AXI_M_CFG, base + QM_AXI_M_CFG); 518 writel(AXI_M_CFG_ENABLE, base + QM_AXI_M_CFG_ENABLE); 519 520 /* disable FLR triggered by BME(bus master enable) */ 521 writel(PEH_AXUSER_CFG, base + QM_PEH_AXUSER_CFG); 522 writel(PEH_AXUSER_CFG_ENABLE, base + QM_PEH_AXUSER_CFG_ENABLE); 523 524 /* cache */ 525 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_ARCA_CHE_0); 526 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_ARCA_CHE_1); 527 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_AWCA_CHE_0); 528 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_AWCA_CHE_1); 529 530 /* user domain configurations */ 531 writel(AXUSER_BASE, base + HZIP_BD_RUSER_32_63); 532 writel(AXUSER_BASE, base + HZIP_BD_WUSER_32_63); 533 534 if (qm->use_sva && qm->ver == QM_HW_V2) { 535 writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_DATA_RUSER_32_63); 536 writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_DATA_WUSER_32_63); 537 writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_SGL_RUSER_32_63); 538 } else { 539 writel(AXUSER_BASE, base + HZIP_DATA_RUSER_32_63); 540 writel(AXUSER_BASE, base + HZIP_DATA_WUSER_32_63); 541 writel(AXUSER_BASE, base + HZIP_SGL_RUSER_32_63); 542 } 543 544 /* let's open all compression/decompression cores */ 545 dcomp_bm = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 546 ZIP_DECOMP_ENABLE_BITMAP, qm->cap_ver); 547 comp_bm = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 548 ZIP_COMP_ENABLE_BITMAP, qm->cap_ver); 549 writel(HZIP_DECOMP_CHECK_ENABLE | dcomp_bm | comp_bm, base + HZIP_CLOCK_GATE_CTRL); 550 551 /* enable sqc,cqc writeback */ 552 writel(SQC_CACHE_ENABLE | CQC_CACHE_ENABLE | SQC_CACHE_WB_ENABLE | 553 CQC_CACHE_WB_ENABLE | FIELD_PREP(SQC_CACHE_WB_THRD, 1) | 554 FIELD_PREP(CQC_CACHE_WB_THRD, 1), base + QM_CACHE_CTL); 555 556 hisi_zip_enable_clock_gate(qm); 557 558 return 0; 559 } 560 561 static void hisi_zip_master_ooo_ctrl(struct hisi_qm *qm, bool enable) 562 { 563 u32 val1, val2; 564 565 val1 = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 566 if (enable) { 567 val1 |= HZIP_AXI_SHUTDOWN_ENABLE; 568 val2 = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 569 ZIP_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 570 } else { 571 val1 &= ~HZIP_AXI_SHUTDOWN_ENABLE; 572 val2 = 0x0; 573 } 574 575 if (qm->ver > QM_HW_V2) 576 writel(val2, qm->io_base + HZIP_OOO_SHUTDOWN_SEL); 577 578 writel(val1, qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 579 } 580 581 static void hisi_zip_hw_error_enable(struct hisi_qm *qm) 582 { 583 u32 nfe, ce; 584 585 if (qm->ver == QM_HW_V1) { 586 writel(HZIP_CORE_INT_MASK_ALL, 587 qm->io_base + HZIP_CORE_INT_MASK_REG); 588 dev_info(&qm->pdev->dev, "Does not support hw error handle\n"); 589 return; 590 } 591 592 nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_NFE_MASK_CAP, qm->cap_ver); 593 ce = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CE_MASK_CAP, qm->cap_ver); 594 595 /* clear ZIP hw error source if having */ 596 writel(ce | nfe | HZIP_CORE_INT_RAS_FE_ENB_MASK, qm->io_base + HZIP_CORE_INT_SOURCE); 597 598 /* configure error type */ 599 writel(ce, qm->io_base + HZIP_CORE_INT_RAS_CE_ENB); 600 writel(HZIP_CORE_INT_RAS_FE_ENB_MASK, qm->io_base + HZIP_CORE_INT_RAS_FE_ENB); 601 writel(nfe, qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); 602 603 hisi_zip_master_ooo_ctrl(qm, true); 604 605 /* enable ZIP hw error interrupts */ 606 writel(0, qm->io_base + HZIP_CORE_INT_MASK_REG); 607 } 608 609 static void hisi_zip_hw_error_disable(struct hisi_qm *qm) 610 { 611 u32 nfe, ce; 612 613 /* disable ZIP hw error interrupts */ 614 nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_NFE_MASK_CAP, qm->cap_ver); 615 ce = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CE_MASK_CAP, qm->cap_ver); 616 writel(ce | nfe | HZIP_CORE_INT_RAS_FE_ENB_MASK, qm->io_base + HZIP_CORE_INT_MASK_REG); 617 618 hisi_zip_master_ooo_ctrl(qm, false); 619 } 620 621 static inline struct hisi_qm *file_to_qm(struct ctrl_debug_file *file) 622 { 623 struct hisi_zip *hisi_zip = file->ctrl->hisi_zip; 624 625 return &hisi_zip->qm; 626 } 627 628 static u32 clear_enable_read(struct hisi_qm *qm) 629 { 630 return readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) & 631 HZIP_SOFT_CTRL_CNT_CLR_CE_BIT; 632 } 633 634 static int clear_enable_write(struct hisi_qm *qm, u32 val) 635 { 636 u32 tmp; 637 638 if (val != 1 && val != 0) 639 return -EINVAL; 640 641 tmp = (readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) & 642 ~HZIP_SOFT_CTRL_CNT_CLR_CE_BIT) | val; 643 writel(tmp, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE); 644 645 return 0; 646 } 647 648 static ssize_t hisi_zip_ctrl_debug_read(struct file *filp, char __user *buf, 649 size_t count, loff_t *pos) 650 { 651 struct ctrl_debug_file *file = filp->private_data; 652 struct hisi_qm *qm = file_to_qm(file); 653 char tbuf[HZIP_BUF_SIZE]; 654 u32 val; 655 int ret; 656 657 ret = hisi_qm_get_dfx_access(qm); 658 if (ret) 659 return ret; 660 661 spin_lock_irq(&file->lock); 662 switch (file->index) { 663 case HZIP_CLEAR_ENABLE: 664 val = clear_enable_read(qm); 665 break; 666 default: 667 goto err_input; 668 } 669 spin_unlock_irq(&file->lock); 670 671 hisi_qm_put_dfx_access(qm); 672 ret = scnprintf(tbuf, sizeof(tbuf), "%u\n", val); 673 return simple_read_from_buffer(buf, count, pos, tbuf, ret); 674 675 err_input: 676 spin_unlock_irq(&file->lock); 677 hisi_qm_put_dfx_access(qm); 678 return -EINVAL; 679 } 680 681 static ssize_t hisi_zip_ctrl_debug_write(struct file *filp, 682 const char __user *buf, 683 size_t count, loff_t *pos) 684 { 685 struct ctrl_debug_file *file = filp->private_data; 686 struct hisi_qm *qm = file_to_qm(file); 687 char tbuf[HZIP_BUF_SIZE]; 688 unsigned long val; 689 int len, ret; 690 691 if (*pos != 0) 692 return 0; 693 694 if (count >= HZIP_BUF_SIZE) 695 return -ENOSPC; 696 697 len = simple_write_to_buffer(tbuf, HZIP_BUF_SIZE - 1, pos, buf, count); 698 if (len < 0) 699 return len; 700 701 tbuf[len] = '\0'; 702 ret = kstrtoul(tbuf, 0, &val); 703 if (ret) 704 return ret; 705 706 ret = hisi_qm_get_dfx_access(qm); 707 if (ret) 708 return ret; 709 710 spin_lock_irq(&file->lock); 711 switch (file->index) { 712 case HZIP_CLEAR_ENABLE: 713 ret = clear_enable_write(qm, val); 714 if (ret) 715 goto err_input; 716 break; 717 default: 718 ret = -EINVAL; 719 goto err_input; 720 } 721 722 ret = count; 723 724 err_input: 725 spin_unlock_irq(&file->lock); 726 hisi_qm_put_dfx_access(qm); 727 return ret; 728 } 729 730 static const struct file_operations ctrl_debug_fops = { 731 .owner = THIS_MODULE, 732 .open = simple_open, 733 .read = hisi_zip_ctrl_debug_read, 734 .write = hisi_zip_ctrl_debug_write, 735 }; 736 737 static int zip_debugfs_atomic64_set(void *data, u64 val) 738 { 739 if (val) 740 return -EINVAL; 741 742 atomic64_set((atomic64_t *)data, 0); 743 744 return 0; 745 } 746 747 static int zip_debugfs_atomic64_get(void *data, u64 *val) 748 { 749 *val = atomic64_read((atomic64_t *)data); 750 751 return 0; 752 } 753 754 DEFINE_DEBUGFS_ATTRIBUTE(zip_atomic64_ops, zip_debugfs_atomic64_get, 755 zip_debugfs_atomic64_set, "%llu\n"); 756 757 static int hisi_zip_regs_show(struct seq_file *s, void *unused) 758 { 759 hisi_qm_regs_dump(s, s->private); 760 761 return 0; 762 } 763 764 DEFINE_SHOW_ATTRIBUTE(hisi_zip_regs); 765 766 static int hisi_zip_core_debug_init(struct hisi_qm *qm) 767 { 768 u32 zip_core_num, zip_comp_core_num; 769 struct device *dev = &qm->pdev->dev; 770 struct debugfs_regset32 *regset; 771 struct dentry *tmp_d; 772 char buf[HZIP_BUF_SIZE]; 773 int i; 774 775 zip_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CORE_NUM_CAP, qm->cap_ver); 776 zip_comp_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CLUSTER_COMP_NUM_CAP, 777 qm->cap_ver); 778 779 for (i = 0; i < zip_core_num; i++) { 780 if (i < zip_comp_core_num) 781 scnprintf(buf, sizeof(buf), "comp_core%d", i); 782 else 783 scnprintf(buf, sizeof(buf), "decomp_core%d", 784 i - zip_comp_core_num); 785 786 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); 787 if (!regset) 788 return -ENOENT; 789 790 regset->regs = hzip_dfx_regs; 791 regset->nregs = ARRAY_SIZE(hzip_dfx_regs); 792 regset->base = qm->io_base + core_offsets[i]; 793 regset->dev = dev; 794 795 tmp_d = debugfs_create_dir(buf, qm->debug.debug_root); 796 debugfs_create_file("regs", 0444, tmp_d, regset, 797 &hisi_zip_regs_fops); 798 } 799 800 return 0; 801 } 802 803 static void hisi_zip_dfx_debug_init(struct hisi_qm *qm) 804 { 805 struct dfx_diff_registers *hzip_regs = qm->debug.acc_diff_regs; 806 struct hisi_zip *zip = container_of(qm, struct hisi_zip, qm); 807 struct hisi_zip_dfx *dfx = &zip->dfx; 808 struct dentry *tmp_dir; 809 void *data; 810 int i; 811 812 tmp_dir = debugfs_create_dir("zip_dfx", qm->debug.debug_root); 813 for (i = 0; i < ARRAY_SIZE(zip_dfx_files); i++) { 814 data = (atomic64_t *)((uintptr_t)dfx + zip_dfx_files[i].offset); 815 debugfs_create_file(zip_dfx_files[i].name, 816 0644, tmp_dir, data, 817 &zip_atomic64_ops); 818 } 819 820 if (qm->fun_type == QM_HW_PF && hzip_regs) 821 debugfs_create_file("diff_regs", 0444, tmp_dir, 822 qm, &hzip_diff_regs_fops); 823 } 824 825 static int hisi_zip_ctrl_debug_init(struct hisi_qm *qm) 826 { 827 struct hisi_zip *zip = container_of(qm, struct hisi_zip, qm); 828 int i; 829 830 for (i = HZIP_CLEAR_ENABLE; i < HZIP_DEBUG_FILE_NUM; i++) { 831 spin_lock_init(&zip->ctrl->files[i].lock); 832 zip->ctrl->files[i].ctrl = zip->ctrl; 833 zip->ctrl->files[i].index = i; 834 835 debugfs_create_file(ctrl_debug_file_name[i], 0600, 836 qm->debug.debug_root, 837 zip->ctrl->files + i, 838 &ctrl_debug_fops); 839 } 840 841 return hisi_zip_core_debug_init(qm); 842 } 843 844 static int hisi_zip_debugfs_init(struct hisi_qm *qm) 845 { 846 struct device *dev = &qm->pdev->dev; 847 struct dentry *dev_d; 848 int ret; 849 850 dev_d = debugfs_create_dir(dev_name(dev), hzip_debugfs_root); 851 852 qm->debug.sqe_mask_offset = HZIP_SQE_MASK_OFFSET; 853 qm->debug.sqe_mask_len = HZIP_SQE_MASK_LEN; 854 qm->debug.debug_root = dev_d; 855 ret = hisi_qm_regs_debugfs_init(qm, hzip_diff_regs, ARRAY_SIZE(hzip_diff_regs)); 856 if (ret) { 857 dev_warn(dev, "Failed to init ZIP diff regs!\n"); 858 goto debugfs_remove; 859 } 860 861 hisi_qm_debug_init(qm); 862 863 if (qm->fun_type == QM_HW_PF) { 864 ret = hisi_zip_ctrl_debug_init(qm); 865 if (ret) 866 goto failed_to_create; 867 } 868 869 hisi_zip_dfx_debug_init(qm); 870 871 return 0; 872 873 failed_to_create: 874 hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(hzip_diff_regs)); 875 debugfs_remove: 876 debugfs_remove_recursive(hzip_debugfs_root); 877 return ret; 878 } 879 880 /* hisi_zip_debug_regs_clear() - clear the zip debug regs */ 881 static void hisi_zip_debug_regs_clear(struct hisi_qm *qm) 882 { 883 int i, j; 884 885 /* enable register read_clear bit */ 886 writel(HZIP_RD_CNT_CLR_CE_EN, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE); 887 for (i = 0; i < ARRAY_SIZE(core_offsets); i++) 888 for (j = 0; j < ARRAY_SIZE(hzip_dfx_regs); j++) 889 readl(qm->io_base + core_offsets[i] + 890 hzip_dfx_regs[j].offset); 891 892 /* disable register read_clear bit */ 893 writel(0x0, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE); 894 895 hisi_qm_debug_regs_clear(qm); 896 } 897 898 static void hisi_zip_debugfs_exit(struct hisi_qm *qm) 899 { 900 hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(hzip_diff_regs)); 901 902 debugfs_remove_recursive(qm->debug.debug_root); 903 904 if (qm->fun_type == QM_HW_PF) { 905 hisi_zip_debug_regs_clear(qm); 906 qm->debug.curr_qm_qp_num = 0; 907 } 908 } 909 910 static int hisi_zip_show_last_regs_init(struct hisi_qm *qm) 911 { 912 int core_dfx_regs_num = ARRAY_SIZE(hzip_dump_dfx_regs); 913 int com_dfx_regs_num = ARRAY_SIZE(hzip_com_dfx_regs); 914 struct qm_debug *debug = &qm->debug; 915 void __iomem *io_base; 916 u32 zip_core_num; 917 int i, j, idx; 918 919 zip_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CORE_NUM_CAP, qm->cap_ver); 920 921 debug->last_words = kcalloc(core_dfx_regs_num * zip_core_num + com_dfx_regs_num, 922 sizeof(unsigned int), GFP_KERNEL); 923 if (!debug->last_words) 924 return -ENOMEM; 925 926 for (i = 0; i < com_dfx_regs_num; i++) { 927 io_base = qm->io_base + hzip_com_dfx_regs[i].offset; 928 debug->last_words[i] = readl_relaxed(io_base); 929 } 930 931 for (i = 0; i < zip_core_num; i++) { 932 io_base = qm->io_base + core_offsets[i]; 933 for (j = 0; j < core_dfx_regs_num; j++) { 934 idx = com_dfx_regs_num + i * core_dfx_regs_num + j; 935 debug->last_words[idx] = readl_relaxed( 936 io_base + hzip_dump_dfx_regs[j].offset); 937 } 938 } 939 940 return 0; 941 } 942 943 static void hisi_zip_show_last_regs_uninit(struct hisi_qm *qm) 944 { 945 struct qm_debug *debug = &qm->debug; 946 947 if (qm->fun_type == QM_HW_VF || !debug->last_words) 948 return; 949 950 kfree(debug->last_words); 951 debug->last_words = NULL; 952 } 953 954 static void hisi_zip_show_last_dfx_regs(struct hisi_qm *qm) 955 { 956 int core_dfx_regs_num = ARRAY_SIZE(hzip_dump_dfx_regs); 957 int com_dfx_regs_num = ARRAY_SIZE(hzip_com_dfx_regs); 958 u32 zip_core_num, zip_comp_core_num; 959 struct qm_debug *debug = &qm->debug; 960 char buf[HZIP_BUF_SIZE]; 961 void __iomem *base; 962 int i, j, idx; 963 u32 val; 964 965 if (qm->fun_type == QM_HW_VF || !debug->last_words) 966 return; 967 968 for (i = 0; i < com_dfx_regs_num; i++) { 969 val = readl_relaxed(qm->io_base + hzip_com_dfx_regs[i].offset); 970 if (debug->last_words[i] != val) 971 pci_info(qm->pdev, "com_dfx: %s \t= 0x%08x => 0x%08x\n", 972 hzip_com_dfx_regs[i].name, debug->last_words[i], val); 973 } 974 975 zip_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CORE_NUM_CAP, qm->cap_ver); 976 zip_comp_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CLUSTER_COMP_NUM_CAP, 977 qm->cap_ver); 978 for (i = 0; i < zip_core_num; i++) { 979 if (i < zip_comp_core_num) 980 scnprintf(buf, sizeof(buf), "Comp_core-%d", i); 981 else 982 scnprintf(buf, sizeof(buf), "Decomp_core-%d", 983 i - zip_comp_core_num); 984 base = qm->io_base + core_offsets[i]; 985 986 pci_info(qm->pdev, "==>%s:\n", buf); 987 /* dump last word for dfx regs during control resetting */ 988 for (j = 0; j < core_dfx_regs_num; j++) { 989 idx = com_dfx_regs_num + i * core_dfx_regs_num + j; 990 val = readl_relaxed(base + hzip_dump_dfx_regs[j].offset); 991 if (debug->last_words[idx] != val) 992 pci_info(qm->pdev, "%s \t= 0x%08x => 0x%08x\n", 993 hzip_dump_dfx_regs[j].name, 994 debug->last_words[idx], val); 995 } 996 } 997 } 998 999 static void hisi_zip_log_hw_error(struct hisi_qm *qm, u32 err_sts) 1000 { 1001 const struct hisi_zip_hw_error *err = zip_hw_error; 1002 struct device *dev = &qm->pdev->dev; 1003 u32 err_val; 1004 1005 while (err->msg) { 1006 if (err->int_msk & err_sts) { 1007 dev_err(dev, "%s [error status=0x%x] found\n", 1008 err->msg, err->int_msk); 1009 1010 if (err->int_msk & HZIP_CORE_INT_STATUS_M_ECC) { 1011 err_val = readl(qm->io_base + 1012 HZIP_CORE_SRAM_ECC_ERR_INFO); 1013 dev_err(dev, "hisi-zip multi ecc sram num=0x%x\n", 1014 ((err_val >> 1015 HZIP_SRAM_ECC_ERR_NUM_SHIFT) & 0xFF)); 1016 } 1017 } 1018 err++; 1019 } 1020 } 1021 1022 static u32 hisi_zip_get_hw_err_status(struct hisi_qm *qm) 1023 { 1024 return readl(qm->io_base + HZIP_CORE_INT_STATUS); 1025 } 1026 1027 static void hisi_zip_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts) 1028 { 1029 u32 nfe; 1030 1031 writel(err_sts, qm->io_base + HZIP_CORE_INT_SOURCE); 1032 nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_NFE_MASK_CAP, qm->cap_ver); 1033 writel(nfe, qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); 1034 } 1035 1036 static void hisi_zip_open_axi_master_ooo(struct hisi_qm *qm) 1037 { 1038 u32 val; 1039 1040 val = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 1041 1042 writel(val & ~HZIP_AXI_SHUTDOWN_ENABLE, 1043 qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 1044 1045 writel(val | HZIP_AXI_SHUTDOWN_ENABLE, 1046 qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 1047 } 1048 1049 static void hisi_zip_close_axi_master_ooo(struct hisi_qm *qm) 1050 { 1051 u32 nfe_enb; 1052 1053 /* Disable ECC Mbit error report. */ 1054 nfe_enb = readl(qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); 1055 writel(nfe_enb & ~HZIP_CORE_INT_STATUS_M_ECC, 1056 qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); 1057 1058 /* Inject zip ECC Mbit error to block master ooo. */ 1059 writel(HZIP_CORE_INT_STATUS_M_ECC, 1060 qm->io_base + HZIP_CORE_INT_SET); 1061 } 1062 1063 static void hisi_zip_err_info_init(struct hisi_qm *qm) 1064 { 1065 struct hisi_qm_err_info *err_info = &qm->err_info; 1066 1067 err_info->fe = HZIP_CORE_INT_RAS_FE_ENB_MASK; 1068 err_info->ce = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_QM_CE_MASK_CAP, qm->cap_ver); 1069 err_info->nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 1070 ZIP_QM_NFE_MASK_CAP, qm->cap_ver); 1071 err_info->ecc_2bits_mask = HZIP_CORE_INT_STATUS_M_ECC; 1072 err_info->qm_shutdown_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 1073 ZIP_QM_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 1074 err_info->dev_shutdown_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 1075 ZIP_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 1076 err_info->qm_reset_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 1077 ZIP_QM_RESET_MASK_CAP, qm->cap_ver); 1078 err_info->dev_reset_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 1079 ZIP_RESET_MASK_CAP, qm->cap_ver); 1080 err_info->msi_wr_port = HZIP_WR_PORT; 1081 err_info->acpi_rst = "ZRST"; 1082 } 1083 1084 static const struct hisi_qm_err_ini hisi_zip_err_ini = { 1085 .hw_init = hisi_zip_set_user_domain_and_cache, 1086 .hw_err_enable = hisi_zip_hw_error_enable, 1087 .hw_err_disable = hisi_zip_hw_error_disable, 1088 .get_dev_hw_err_status = hisi_zip_get_hw_err_status, 1089 .clear_dev_hw_err_status = hisi_zip_clear_hw_err_status, 1090 .log_dev_hw_err = hisi_zip_log_hw_error, 1091 .open_axi_master_ooo = hisi_zip_open_axi_master_ooo, 1092 .close_axi_master_ooo = hisi_zip_close_axi_master_ooo, 1093 .open_sva_prefetch = hisi_zip_open_sva_prefetch, 1094 .close_sva_prefetch = hisi_zip_close_sva_prefetch, 1095 .show_last_dfx_regs = hisi_zip_show_last_dfx_regs, 1096 .err_info_init = hisi_zip_err_info_init, 1097 }; 1098 1099 static int hisi_zip_pf_probe_init(struct hisi_zip *hisi_zip) 1100 { 1101 struct hisi_qm *qm = &hisi_zip->qm; 1102 struct hisi_zip_ctrl *ctrl; 1103 int ret; 1104 1105 ctrl = devm_kzalloc(&qm->pdev->dev, sizeof(*ctrl), GFP_KERNEL); 1106 if (!ctrl) 1107 return -ENOMEM; 1108 1109 hisi_zip->ctrl = ctrl; 1110 ctrl->hisi_zip = hisi_zip; 1111 qm->err_ini = &hisi_zip_err_ini; 1112 qm->err_ini->err_info_init(qm); 1113 1114 ret = hisi_zip_set_user_domain_and_cache(qm); 1115 if (ret) 1116 return ret; 1117 1118 hisi_zip_open_sva_prefetch(qm); 1119 hisi_qm_dev_err_init(qm); 1120 hisi_zip_debug_regs_clear(qm); 1121 1122 ret = hisi_zip_show_last_regs_init(qm); 1123 if (ret) 1124 pci_err(qm->pdev, "Failed to init last word regs!\n"); 1125 1126 return ret; 1127 } 1128 1129 static int hisi_zip_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) 1130 { 1131 int ret; 1132 1133 qm->pdev = pdev; 1134 qm->ver = pdev->revision; 1135 qm->mode = uacce_mode; 1136 qm->sqe_size = HZIP_SQE_SIZE; 1137 qm->dev_name = hisi_zip_name; 1138 1139 qm->fun_type = (pdev->device == PCI_DEVICE_ID_HUAWEI_ZIP_PF) ? 1140 QM_HW_PF : QM_HW_VF; 1141 if (qm->fun_type == QM_HW_PF) { 1142 qm->qp_base = HZIP_PF_DEF_Q_BASE; 1143 qm->qp_num = pf_q_num; 1144 qm->debug.curr_qm_qp_num = pf_q_num; 1145 qm->qm_list = &zip_devices; 1146 if (pf_q_num_flag) 1147 set_bit(QM_MODULE_PARAM, &qm->misc_ctl); 1148 } else if (qm->fun_type == QM_HW_VF && qm->ver == QM_HW_V1) { 1149 /* 1150 * have no way to get qm configure in VM in v1 hardware, 1151 * so currently force PF to uses HZIP_PF_DEF_Q_NUM, and force 1152 * to trigger only one VF in v1 hardware. 1153 * 1154 * v2 hardware has no such problem. 1155 */ 1156 qm->qp_base = HZIP_PF_DEF_Q_NUM; 1157 qm->qp_num = HZIP_QUEUE_NUM_V1 - HZIP_PF_DEF_Q_NUM; 1158 } 1159 1160 ret = hisi_qm_init(qm); 1161 if (ret) { 1162 pci_err(qm->pdev, "Failed to init zip qm configures!\n"); 1163 return ret; 1164 } 1165 1166 ret = hisi_zip_set_qm_algs(qm); 1167 if (ret) { 1168 pci_err(qm->pdev, "Failed to set zip algs!\n"); 1169 hisi_qm_uninit(qm); 1170 } 1171 1172 return ret; 1173 } 1174 1175 static void hisi_zip_qm_uninit(struct hisi_qm *qm) 1176 { 1177 hisi_qm_uninit(qm); 1178 } 1179 1180 static int hisi_zip_probe_init(struct hisi_zip *hisi_zip) 1181 { 1182 u32 type_rate = HZIP_SHAPER_RATE_COMPRESS; 1183 struct hisi_qm *qm = &hisi_zip->qm; 1184 int ret; 1185 1186 if (qm->fun_type == QM_HW_PF) { 1187 ret = hisi_zip_pf_probe_init(hisi_zip); 1188 if (ret) 1189 return ret; 1190 /* enable shaper type 0 */ 1191 if (qm->ver >= QM_HW_V3) { 1192 type_rate |= QM_SHAPER_ENABLE; 1193 1194 /* ZIP need to enable shaper type 1 */ 1195 type_rate |= HZIP_SHAPER_RATE_DECOMPRESS << QM_SHAPER_TYPE1_OFFSET; 1196 qm->type_rate = type_rate; 1197 } 1198 } 1199 1200 return 0; 1201 } 1202 1203 static int hisi_zip_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1204 { 1205 struct hisi_zip *hisi_zip; 1206 struct hisi_qm *qm; 1207 int ret; 1208 1209 hisi_zip = devm_kzalloc(&pdev->dev, sizeof(*hisi_zip), GFP_KERNEL); 1210 if (!hisi_zip) 1211 return -ENOMEM; 1212 1213 qm = &hisi_zip->qm; 1214 1215 ret = hisi_zip_qm_init(qm, pdev); 1216 if (ret) { 1217 pci_err(pdev, "Failed to init ZIP QM (%d)!\n", ret); 1218 return ret; 1219 } 1220 1221 ret = hisi_zip_probe_init(hisi_zip); 1222 if (ret) { 1223 pci_err(pdev, "Failed to probe (%d)!\n", ret); 1224 goto err_qm_uninit; 1225 } 1226 1227 ret = hisi_qm_start(qm); 1228 if (ret) 1229 goto err_dev_err_uninit; 1230 1231 ret = hisi_zip_debugfs_init(qm); 1232 if (ret) 1233 pci_err(pdev, "failed to init debugfs (%d)!\n", ret); 1234 1235 hisi_qm_add_list(qm, &zip_devices); 1236 ret = hisi_qm_alg_register(qm, &zip_devices, HZIP_CTX_Q_NUM_DEF); 1237 if (ret < 0) { 1238 pci_err(pdev, "failed to register driver to crypto!\n"); 1239 goto err_qm_del_list; 1240 } 1241 1242 if (qm->uacce) { 1243 ret = uacce_register(qm->uacce); 1244 if (ret) { 1245 pci_err(pdev, "failed to register uacce (%d)!\n", ret); 1246 goto err_qm_alg_unregister; 1247 } 1248 } 1249 1250 if (qm->fun_type == QM_HW_PF && vfs_num > 0) { 1251 ret = hisi_qm_sriov_enable(pdev, vfs_num); 1252 if (ret < 0) 1253 goto err_qm_alg_unregister; 1254 } 1255 1256 hisi_qm_pm_init(qm); 1257 1258 return 0; 1259 1260 err_qm_alg_unregister: 1261 hisi_qm_alg_unregister(qm, &zip_devices, HZIP_CTX_Q_NUM_DEF); 1262 1263 err_qm_del_list: 1264 hisi_qm_del_list(qm, &zip_devices); 1265 hisi_zip_debugfs_exit(qm); 1266 hisi_qm_stop(qm, QM_NORMAL); 1267 1268 err_dev_err_uninit: 1269 hisi_zip_show_last_regs_uninit(qm); 1270 hisi_qm_dev_err_uninit(qm); 1271 1272 err_qm_uninit: 1273 hisi_zip_qm_uninit(qm); 1274 1275 return ret; 1276 } 1277 1278 static void hisi_zip_remove(struct pci_dev *pdev) 1279 { 1280 struct hisi_qm *qm = pci_get_drvdata(pdev); 1281 1282 hisi_qm_pm_uninit(qm); 1283 hisi_qm_wait_task_finish(qm, &zip_devices); 1284 hisi_qm_alg_unregister(qm, &zip_devices, HZIP_CTX_Q_NUM_DEF); 1285 hisi_qm_del_list(qm, &zip_devices); 1286 1287 if (qm->fun_type == QM_HW_PF && qm->vfs_num) 1288 hisi_qm_sriov_disable(pdev, true); 1289 1290 hisi_zip_debugfs_exit(qm); 1291 hisi_qm_stop(qm, QM_NORMAL); 1292 hisi_zip_show_last_regs_uninit(qm); 1293 hisi_qm_dev_err_uninit(qm); 1294 hisi_zip_qm_uninit(qm); 1295 } 1296 1297 static const struct dev_pm_ops hisi_zip_pm_ops = { 1298 SET_RUNTIME_PM_OPS(hisi_qm_suspend, hisi_qm_resume, NULL) 1299 }; 1300 1301 static const struct pci_error_handlers hisi_zip_err_handler = { 1302 .error_detected = hisi_qm_dev_err_detected, 1303 .slot_reset = hisi_qm_dev_slot_reset, 1304 .reset_prepare = hisi_qm_reset_prepare, 1305 .reset_done = hisi_qm_reset_done, 1306 }; 1307 1308 static struct pci_driver hisi_zip_pci_driver = { 1309 .name = "hisi_zip", 1310 .id_table = hisi_zip_dev_ids, 1311 .probe = hisi_zip_probe, 1312 .remove = hisi_zip_remove, 1313 .sriov_configure = IS_ENABLED(CONFIG_PCI_IOV) ? 1314 hisi_qm_sriov_configure : NULL, 1315 .err_handler = &hisi_zip_err_handler, 1316 .shutdown = hisi_qm_dev_shutdown, 1317 .driver.pm = &hisi_zip_pm_ops, 1318 }; 1319 1320 struct pci_driver *hisi_zip_get_pf_driver(void) 1321 { 1322 return &hisi_zip_pci_driver; 1323 } 1324 EXPORT_SYMBOL_GPL(hisi_zip_get_pf_driver); 1325 1326 static void hisi_zip_register_debugfs(void) 1327 { 1328 if (!debugfs_initialized()) 1329 return; 1330 1331 hzip_debugfs_root = debugfs_create_dir("hisi_zip", NULL); 1332 } 1333 1334 static void hisi_zip_unregister_debugfs(void) 1335 { 1336 debugfs_remove_recursive(hzip_debugfs_root); 1337 } 1338 1339 static int __init hisi_zip_init(void) 1340 { 1341 int ret; 1342 1343 hisi_qm_init_list(&zip_devices); 1344 hisi_zip_register_debugfs(); 1345 1346 ret = pci_register_driver(&hisi_zip_pci_driver); 1347 if (ret < 0) { 1348 hisi_zip_unregister_debugfs(); 1349 pr_err("Failed to register pci driver.\n"); 1350 } 1351 1352 return ret; 1353 } 1354 1355 static void __exit hisi_zip_exit(void) 1356 { 1357 pci_unregister_driver(&hisi_zip_pci_driver); 1358 hisi_zip_unregister_debugfs(); 1359 } 1360 1361 module_init(hisi_zip_init); 1362 module_exit(hisi_zip_exit); 1363 1364 MODULE_LICENSE("GPL v2"); 1365 MODULE_AUTHOR("Zhou Wang <wangzhou1@hisilicon.com>"); 1366 MODULE_DESCRIPTION("Driver for HiSilicon ZIP accelerator"); 1367