1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2019 HiSilicon Limited. */ 3 4 #include <linux/acpi.h> 5 #include <linux/bitops.h> 6 #include <linux/debugfs.h> 7 #include <linux/init.h> 8 #include <linux/io.h> 9 #include <linux/iommu.h> 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/pci.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/seq_file.h> 15 #include <linux/topology.h> 16 #include <linux/uacce.h> 17 18 #include "sec.h" 19 20 #define SEC_VF_NUM 63 21 #define SEC_QUEUE_NUM_V1 4096 22 #define PCI_DEVICE_ID_HUAWEI_SEC_PF 0xa255 23 24 #define SEC_BD_ERR_CHK_EN0 0xEFFFFFFF 25 #define SEC_BD_ERR_CHK_EN1 0x7ffff7fd 26 #define SEC_BD_ERR_CHK_EN3 0xffffbfff 27 28 #define SEC_SQE_SIZE 128 29 #define SEC_PF_DEF_Q_NUM 256 30 #define SEC_PF_DEF_Q_BASE 0 31 #define SEC_CTX_Q_NUM_DEF 2 32 #define SEC_CTX_Q_NUM_MAX 32 33 34 #define SEC_CTRL_CNT_CLR_CE 0x301120 35 #define SEC_CTRL_CNT_CLR_CE_BIT BIT(0) 36 #define SEC_CORE_INT_SOURCE 0x301010 37 #define SEC_CORE_INT_MASK 0x301000 38 #define SEC_CORE_INT_STATUS 0x301008 39 #define SEC_CORE_SRAM_ECC_ERR_INFO 0x301C14 40 #define SEC_ECC_NUM 16 41 #define SEC_ECC_MASH 0xFF 42 #define SEC_CORE_INT_DISABLE 0x0 43 44 #define SEC_RAS_CE_REG 0x301050 45 #define SEC_RAS_FE_REG 0x301054 46 #define SEC_RAS_NFE_REG 0x301058 47 #define SEC_RAS_FE_ENB_MSK 0x0 48 #define SEC_OOO_SHUTDOWN_SEL 0x301014 49 #define SEC_RAS_DISABLE 0x0 50 #define SEC_MEM_START_INIT_REG 0x301100 51 #define SEC_MEM_INIT_DONE_REG 0x301104 52 53 /* clock gating */ 54 #define SEC_CONTROL_REG 0x301200 55 #define SEC_DYNAMIC_GATE_REG 0x30121c 56 #define SEC_CORE_AUTO_GATE 0x30212c 57 #define SEC_DYNAMIC_GATE_EN 0x7fff 58 #define SEC_CORE_AUTO_GATE_EN GENMASK(3, 0) 59 #define SEC_CLK_GATE_ENABLE BIT(3) 60 #define SEC_CLK_GATE_DISABLE (~BIT(3)) 61 62 #define SEC_TRNG_EN_SHIFT 8 63 #define SEC_AXI_SHUTDOWN_ENABLE BIT(12) 64 #define SEC_AXI_SHUTDOWN_DISABLE 0xFFFFEFFF 65 66 #define SEC_INTERFACE_USER_CTRL0_REG 0x301220 67 #define SEC_INTERFACE_USER_CTRL1_REG 0x301224 68 #define SEC_SAA_EN_REG 0x301270 69 #define SEC_BD_ERR_CHK_EN_REG0 0x301380 70 #define SEC_BD_ERR_CHK_EN_REG1 0x301384 71 #define SEC_BD_ERR_CHK_EN_REG3 0x30138c 72 73 #define SEC_USER0_SMMU_NORMAL (BIT(23) | BIT(15)) 74 #define SEC_USER1_SMMU_NORMAL (BIT(31) | BIT(23) | BIT(15) | BIT(7)) 75 #define SEC_USER1_ENABLE_CONTEXT_SSV BIT(24) 76 #define SEC_USER1_ENABLE_DATA_SSV BIT(16) 77 #define SEC_USER1_WB_CONTEXT_SSV BIT(8) 78 #define SEC_USER1_WB_DATA_SSV BIT(0) 79 #define SEC_USER1_SVA_SET (SEC_USER1_ENABLE_CONTEXT_SSV | \ 80 SEC_USER1_ENABLE_DATA_SSV | \ 81 SEC_USER1_WB_CONTEXT_SSV | \ 82 SEC_USER1_WB_DATA_SSV) 83 #define SEC_USER1_SMMU_SVA (SEC_USER1_SMMU_NORMAL | SEC_USER1_SVA_SET) 84 #define SEC_USER1_SMMU_MASK (~SEC_USER1_SVA_SET) 85 #define SEC_INTERFACE_USER_CTRL0_REG_V3 0x302220 86 #define SEC_INTERFACE_USER_CTRL1_REG_V3 0x302224 87 #define SEC_USER1_SMMU_NORMAL_V3 (BIT(23) | BIT(17) | BIT(11) | BIT(5)) 88 #define SEC_USER1_SMMU_MASK_V3 0xFF79E79E 89 #define SEC_CORE_INT_STATUS_M_ECC BIT(2) 90 91 #define SEC_PREFETCH_CFG 0x301130 92 #define SEC_SVA_TRANS 0x301EC4 93 #define SEC_PREFETCH_ENABLE (~(BIT(0) | BIT(1) | BIT(11))) 94 #define SEC_PREFETCH_DISABLE BIT(1) 95 #define SEC_SVA_DISABLE_READY (BIT(7) | BIT(11)) 96 97 #define SEC_DELAY_10_US 10 98 #define SEC_POLL_TIMEOUT_US 1000 99 #define SEC_DBGFS_VAL_MAX_LEN 20 100 #define SEC_SINGLE_PORT_MAX_TRANS 0x2060 101 102 #define SEC_SQE_MASK_OFFSET 64 103 #define SEC_SQE_MASK_LEN 48 104 #define SEC_SHAPER_TYPE_RATE 400 105 106 #define SEC_DFX_BASE 0x301000 107 #define SEC_DFX_CORE 0x302100 108 #define SEC_DFX_COMMON1 0x301600 109 #define SEC_DFX_COMMON2 0x301C00 110 #define SEC_DFX_BASE_LEN 0x9D 111 #define SEC_DFX_CORE_LEN 0x32B 112 #define SEC_DFX_COMMON1_LEN 0x45 113 #define SEC_DFX_COMMON2_LEN 0xBA 114 115 #define SEC_ALG_BITMAP_SHIFT 32 116 117 #define SEC_CIPHER_BITMAP (GENMASK_ULL(5, 0) | GENMASK_ULL(16, 12) | \ 118 GENMASK(24, 21)) 119 #define SEC_DIGEST_BITMAP (GENMASK_ULL(11, 8) | GENMASK_ULL(20, 19) | \ 120 GENMASK_ULL(42, 25)) 121 #define SEC_AEAD_BITMAP (GENMASK_ULL(7, 6) | GENMASK_ULL(18, 17) | \ 122 GENMASK_ULL(45, 43)) 123 #define SEC_DEV_ALG_MAX_LEN 256 124 125 struct sec_hw_error { 126 u32 int_msk; 127 const char *msg; 128 }; 129 130 struct sec_dfx_item { 131 const char *name; 132 u32 offset; 133 }; 134 135 struct sec_dev_alg { 136 u64 alg_msk; 137 const char *algs; 138 }; 139 140 static const char sec_name[] = "hisi_sec2"; 141 static struct dentry *sec_debugfs_root; 142 143 static struct hisi_qm_list sec_devices = { 144 .register_to_crypto = sec_register_to_crypto, 145 .unregister_from_crypto = sec_unregister_from_crypto, 146 }; 147 148 static const struct hisi_qm_cap_info sec_basic_info[] = { 149 {SEC_QM_NFE_MASK_CAP, 0x3124, 0, GENMASK(31, 0), 0x0, 0x1C77, 0x7C77}, 150 {SEC_QM_RESET_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0xC77, 0x6C77}, 151 {SEC_QM_OOO_SHUTDOWN_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0x4, 0x6C77}, 152 {SEC_QM_CE_MASK_CAP, 0x312C, 0, GENMASK(31, 0), 0x0, 0x8, 0x8}, 153 {SEC_NFE_MASK_CAP, 0x3130, 0, GENMASK(31, 0), 0x0, 0x177, 0x60177}, 154 {SEC_RESET_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x177, 0x177}, 155 {SEC_OOO_SHUTDOWN_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x4, 0x177}, 156 {SEC_CE_MASK_CAP, 0x3138, 0, GENMASK(31, 0), 0x0, 0x88, 0xC088}, 157 {SEC_CLUSTER_NUM_CAP, 0x313c, 20, GENMASK(3, 0), 0x1, 0x1, 0x1}, 158 {SEC_CORE_TYPE_NUM_CAP, 0x313c, 16, GENMASK(3, 0), 0x1, 0x1, 0x1}, 159 {SEC_CORE_NUM_CAP, 0x313c, 8, GENMASK(7, 0), 0x4, 0x4, 0x4}, 160 {SEC_CORES_PER_CLUSTER_NUM_CAP, 0x313c, 0, GENMASK(7, 0), 0x4, 0x4, 0x4}, 161 {SEC_CORE_ENABLE_BITMAP, 0x3140, 32, GENMASK(31, 0), 0x17F, 0x17F, 0xF}, 162 {SEC_DRV_ALG_BITMAP_LOW, 0x3144, 0, GENMASK(31, 0), 0x18050CB, 0x18050CB, 0x187F0FF}, 163 {SEC_DRV_ALG_BITMAP_HIGH, 0x3148, 0, GENMASK(31, 0), 0x395C, 0x395C, 0x395C}, 164 {SEC_DEV_ALG_BITMAP_LOW, 0x314c, 0, GENMASK(31, 0), 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}, 165 {SEC_DEV_ALG_BITMAP_HIGH, 0x3150, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF}, 166 {SEC_CORE1_ALG_BITMAP_LOW, 0x3154, 0, GENMASK(31, 0), 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}, 167 {SEC_CORE1_ALG_BITMAP_HIGH, 0x3158, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF}, 168 {SEC_CORE2_ALG_BITMAP_LOW, 0x315c, 0, GENMASK(31, 0), 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}, 169 {SEC_CORE2_ALG_BITMAP_HIGH, 0x3160, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF}, 170 {SEC_CORE3_ALG_BITMAP_LOW, 0x3164, 0, GENMASK(31, 0), 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}, 171 {SEC_CORE3_ALG_BITMAP_HIGH, 0x3168, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF}, 172 {SEC_CORE4_ALG_BITMAP_LOW, 0x316c, 0, GENMASK(31, 0), 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}, 173 {SEC_CORE4_ALG_BITMAP_HIGH, 0x3170, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF}, 174 }; 175 176 static const struct sec_dev_alg sec_dev_algs[] = { { 177 .alg_msk = SEC_CIPHER_BITMAP, 178 .algs = "cipher\n", 179 }, { 180 .alg_msk = SEC_DIGEST_BITMAP, 181 .algs = "digest\n", 182 }, { 183 .alg_msk = SEC_AEAD_BITMAP, 184 .algs = "aead\n", 185 }, 186 }; 187 188 static const struct sec_hw_error sec_hw_errors[] = { 189 { 190 .int_msk = BIT(0), 191 .msg = "sec_axi_rresp_err_rint" 192 }, 193 { 194 .int_msk = BIT(1), 195 .msg = "sec_axi_bresp_err_rint" 196 }, 197 { 198 .int_msk = BIT(2), 199 .msg = "sec_ecc_2bit_err_rint" 200 }, 201 { 202 .int_msk = BIT(3), 203 .msg = "sec_ecc_1bit_err_rint" 204 }, 205 { 206 .int_msk = BIT(4), 207 .msg = "sec_req_trng_timeout_rint" 208 }, 209 { 210 .int_msk = BIT(5), 211 .msg = "sec_fsm_hbeat_rint" 212 }, 213 { 214 .int_msk = BIT(6), 215 .msg = "sec_channel_req_rng_timeout_rint" 216 }, 217 { 218 .int_msk = BIT(7), 219 .msg = "sec_bd_err_rint" 220 }, 221 { 222 .int_msk = BIT(8), 223 .msg = "sec_chain_buff_err_rint" 224 }, 225 { 226 .int_msk = BIT(14), 227 .msg = "sec_no_secure_access" 228 }, 229 { 230 .int_msk = BIT(15), 231 .msg = "sec_wrapping_key_auth_err" 232 }, 233 { 234 .int_msk = BIT(16), 235 .msg = "sec_km_key_crc_fail" 236 }, 237 { 238 .int_msk = BIT(17), 239 .msg = "sec_axi_poison_err" 240 }, 241 { 242 .int_msk = BIT(18), 243 .msg = "sec_sva_err" 244 }, 245 {} 246 }; 247 248 static const char * const sec_dbg_file_name[] = { 249 [SEC_CLEAR_ENABLE] = "clear_enable", 250 }; 251 252 static struct sec_dfx_item sec_dfx_labels[] = { 253 {"send_cnt", offsetof(struct sec_dfx, send_cnt)}, 254 {"recv_cnt", offsetof(struct sec_dfx, recv_cnt)}, 255 {"send_busy_cnt", offsetof(struct sec_dfx, send_busy_cnt)}, 256 {"recv_busy_cnt", offsetof(struct sec_dfx, recv_busy_cnt)}, 257 {"err_bd_cnt", offsetof(struct sec_dfx, err_bd_cnt)}, 258 {"invalid_req_cnt", offsetof(struct sec_dfx, invalid_req_cnt)}, 259 {"done_flag_cnt", offsetof(struct sec_dfx, done_flag_cnt)}, 260 }; 261 262 static const struct debugfs_reg32 sec_dfx_regs[] = { 263 {"SEC_PF_ABNORMAL_INT_SOURCE ", 0x301010}, 264 {"SEC_SAA_EN ", 0x301270}, 265 {"SEC_BD_LATENCY_MIN ", 0x301600}, 266 {"SEC_BD_LATENCY_MAX ", 0x301608}, 267 {"SEC_BD_LATENCY_AVG ", 0x30160C}, 268 {"SEC_BD_NUM_IN_SAA0 ", 0x301670}, 269 {"SEC_BD_NUM_IN_SAA1 ", 0x301674}, 270 {"SEC_BD_NUM_IN_SEC ", 0x301680}, 271 {"SEC_ECC_1BIT_CNT ", 0x301C00}, 272 {"SEC_ECC_1BIT_INFO ", 0x301C04}, 273 {"SEC_ECC_2BIT_CNT ", 0x301C10}, 274 {"SEC_ECC_2BIT_INFO ", 0x301C14}, 275 {"SEC_BD_SAA0 ", 0x301C20}, 276 {"SEC_BD_SAA1 ", 0x301C24}, 277 {"SEC_BD_SAA2 ", 0x301C28}, 278 {"SEC_BD_SAA3 ", 0x301C2C}, 279 {"SEC_BD_SAA4 ", 0x301C30}, 280 {"SEC_BD_SAA5 ", 0x301C34}, 281 {"SEC_BD_SAA6 ", 0x301C38}, 282 {"SEC_BD_SAA7 ", 0x301C3C}, 283 {"SEC_BD_SAA8 ", 0x301C40}, 284 }; 285 286 /* define the SEC's dfx regs region and region length */ 287 static struct dfx_diff_registers sec_diff_regs[] = { 288 { 289 .reg_offset = SEC_DFX_BASE, 290 .reg_len = SEC_DFX_BASE_LEN, 291 }, { 292 .reg_offset = SEC_DFX_COMMON1, 293 .reg_len = SEC_DFX_COMMON1_LEN, 294 }, { 295 .reg_offset = SEC_DFX_COMMON2, 296 .reg_len = SEC_DFX_COMMON2_LEN, 297 }, { 298 .reg_offset = SEC_DFX_CORE, 299 .reg_len = SEC_DFX_CORE_LEN, 300 }, 301 }; 302 303 static int sec_diff_regs_show(struct seq_file *s, void *unused) 304 { 305 struct hisi_qm *qm = s->private; 306 307 hisi_qm_acc_diff_regs_dump(qm, s, qm->debug.acc_diff_regs, 308 ARRAY_SIZE(sec_diff_regs)); 309 310 return 0; 311 } 312 DEFINE_SHOW_ATTRIBUTE(sec_diff_regs); 313 314 static bool pf_q_num_flag; 315 static int sec_pf_q_num_set(const char *val, const struct kernel_param *kp) 316 { 317 pf_q_num_flag = true; 318 319 return q_num_set(val, kp, PCI_DEVICE_ID_HUAWEI_SEC_PF); 320 } 321 322 static const struct kernel_param_ops sec_pf_q_num_ops = { 323 .set = sec_pf_q_num_set, 324 .get = param_get_int, 325 }; 326 327 static u32 pf_q_num = SEC_PF_DEF_Q_NUM; 328 module_param_cb(pf_q_num, &sec_pf_q_num_ops, &pf_q_num, 0444); 329 MODULE_PARM_DESC(pf_q_num, "Number of queues in PF(v1 2-4096, v2 2-1024)"); 330 331 static int sec_ctx_q_num_set(const char *val, const struct kernel_param *kp) 332 { 333 u32 ctx_q_num; 334 int ret; 335 336 if (!val) 337 return -EINVAL; 338 339 ret = kstrtou32(val, 10, &ctx_q_num); 340 if (ret) 341 return -EINVAL; 342 343 if (!ctx_q_num || ctx_q_num > SEC_CTX_Q_NUM_MAX || ctx_q_num & 0x1) { 344 pr_err("ctx queue num[%u] is invalid!\n", ctx_q_num); 345 return -EINVAL; 346 } 347 348 return param_set_int(val, kp); 349 } 350 351 static const struct kernel_param_ops sec_ctx_q_num_ops = { 352 .set = sec_ctx_q_num_set, 353 .get = param_get_int, 354 }; 355 static u32 ctx_q_num = SEC_CTX_Q_NUM_DEF; 356 module_param_cb(ctx_q_num, &sec_ctx_q_num_ops, &ctx_q_num, 0444); 357 MODULE_PARM_DESC(ctx_q_num, "Queue num in ctx (2 default, 2, 4, ..., 32)"); 358 359 static const struct kernel_param_ops vfs_num_ops = { 360 .set = vfs_num_set, 361 .get = param_get_int, 362 }; 363 364 static u32 vfs_num; 365 module_param_cb(vfs_num, &vfs_num_ops, &vfs_num, 0444); 366 MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63), 0(default)"); 367 368 void sec_destroy_qps(struct hisi_qp **qps, int qp_num) 369 { 370 hisi_qm_free_qps(qps, qp_num); 371 kfree(qps); 372 } 373 374 struct hisi_qp **sec_create_qps(void) 375 { 376 int node = cpu_to_node(smp_processor_id()); 377 u32 ctx_num = ctx_q_num; 378 struct hisi_qp **qps; 379 int ret; 380 381 qps = kcalloc(ctx_num, sizeof(struct hisi_qp *), GFP_KERNEL); 382 if (!qps) 383 return NULL; 384 385 ret = hisi_qm_alloc_qps_node(&sec_devices, ctx_num, 0, node, qps); 386 if (!ret) 387 return qps; 388 389 kfree(qps); 390 return NULL; 391 } 392 393 u64 sec_get_alg_bitmap(struct hisi_qm *qm, u32 high, u32 low) 394 { 395 u32 cap_val_h, cap_val_l; 396 397 cap_val_h = hisi_qm_get_hw_info(qm, sec_basic_info, high, qm->cap_ver); 398 cap_val_l = hisi_qm_get_hw_info(qm, sec_basic_info, low, qm->cap_ver); 399 400 return ((u64)cap_val_h << SEC_ALG_BITMAP_SHIFT) | (u64)cap_val_l; 401 } 402 403 static const struct kernel_param_ops sec_uacce_mode_ops = { 404 .set = uacce_mode_set, 405 .get = param_get_int, 406 }; 407 408 /* 409 * uacce_mode = 0 means sec only register to crypto, 410 * uacce_mode = 1 means sec both register to crypto and uacce. 411 */ 412 static u32 uacce_mode = UACCE_MODE_NOUACCE; 413 module_param_cb(uacce_mode, &sec_uacce_mode_ops, &uacce_mode, 0444); 414 MODULE_PARM_DESC(uacce_mode, UACCE_MODE_DESC); 415 416 static const struct pci_device_id sec_dev_ids[] = { 417 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_SEC_PF) }, 418 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_SEC_VF) }, 419 { 0, } 420 }; 421 MODULE_DEVICE_TABLE(pci, sec_dev_ids); 422 423 static void sec_set_endian(struct hisi_qm *qm) 424 { 425 u32 reg; 426 427 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG); 428 reg &= ~(BIT(1) | BIT(0)); 429 if (!IS_ENABLED(CONFIG_64BIT)) 430 reg |= BIT(1); 431 432 if (!IS_ENABLED(CONFIG_CPU_LITTLE_ENDIAN)) 433 reg |= BIT(0); 434 435 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG); 436 } 437 438 static void sec_engine_sva_config(struct hisi_qm *qm) 439 { 440 u32 reg; 441 442 if (qm->ver > QM_HW_V2) { 443 reg = readl_relaxed(qm->io_base + 444 SEC_INTERFACE_USER_CTRL0_REG_V3); 445 reg |= SEC_USER0_SMMU_NORMAL; 446 writel_relaxed(reg, qm->io_base + 447 SEC_INTERFACE_USER_CTRL0_REG_V3); 448 449 reg = readl_relaxed(qm->io_base + 450 SEC_INTERFACE_USER_CTRL1_REG_V3); 451 reg &= SEC_USER1_SMMU_MASK_V3; 452 reg |= SEC_USER1_SMMU_NORMAL_V3; 453 writel_relaxed(reg, qm->io_base + 454 SEC_INTERFACE_USER_CTRL1_REG_V3); 455 } else { 456 reg = readl_relaxed(qm->io_base + 457 SEC_INTERFACE_USER_CTRL0_REG); 458 reg |= SEC_USER0_SMMU_NORMAL; 459 writel_relaxed(reg, qm->io_base + 460 SEC_INTERFACE_USER_CTRL0_REG); 461 reg = readl_relaxed(qm->io_base + 462 SEC_INTERFACE_USER_CTRL1_REG); 463 reg &= SEC_USER1_SMMU_MASK; 464 if (qm->use_sva) 465 reg |= SEC_USER1_SMMU_SVA; 466 else 467 reg |= SEC_USER1_SMMU_NORMAL; 468 writel_relaxed(reg, qm->io_base + 469 SEC_INTERFACE_USER_CTRL1_REG); 470 } 471 } 472 473 static void sec_open_sva_prefetch(struct hisi_qm *qm) 474 { 475 u32 val; 476 int ret; 477 478 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps)) 479 return; 480 481 /* Enable prefetch */ 482 val = readl_relaxed(qm->io_base + SEC_PREFETCH_CFG); 483 val &= SEC_PREFETCH_ENABLE; 484 writel(val, qm->io_base + SEC_PREFETCH_CFG); 485 486 ret = readl_relaxed_poll_timeout(qm->io_base + SEC_PREFETCH_CFG, 487 val, !(val & SEC_PREFETCH_DISABLE), 488 SEC_DELAY_10_US, SEC_POLL_TIMEOUT_US); 489 if (ret) 490 pci_err(qm->pdev, "failed to open sva prefetch\n"); 491 } 492 493 static void sec_close_sva_prefetch(struct hisi_qm *qm) 494 { 495 u32 val; 496 int ret; 497 498 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps)) 499 return; 500 501 val = readl_relaxed(qm->io_base + SEC_PREFETCH_CFG); 502 val |= SEC_PREFETCH_DISABLE; 503 writel(val, qm->io_base + SEC_PREFETCH_CFG); 504 505 ret = readl_relaxed_poll_timeout(qm->io_base + SEC_SVA_TRANS, 506 val, !(val & SEC_SVA_DISABLE_READY), 507 SEC_DELAY_10_US, SEC_POLL_TIMEOUT_US); 508 if (ret) 509 pci_err(qm->pdev, "failed to close sva prefetch\n"); 510 } 511 512 static void sec_enable_clock_gate(struct hisi_qm *qm) 513 { 514 u32 val; 515 516 if (qm->ver < QM_HW_V3) 517 return; 518 519 val = readl_relaxed(qm->io_base + SEC_CONTROL_REG); 520 val |= SEC_CLK_GATE_ENABLE; 521 writel_relaxed(val, qm->io_base + SEC_CONTROL_REG); 522 523 val = readl(qm->io_base + SEC_DYNAMIC_GATE_REG); 524 val |= SEC_DYNAMIC_GATE_EN; 525 writel(val, qm->io_base + SEC_DYNAMIC_GATE_REG); 526 527 val = readl(qm->io_base + SEC_CORE_AUTO_GATE); 528 val |= SEC_CORE_AUTO_GATE_EN; 529 writel(val, qm->io_base + SEC_CORE_AUTO_GATE); 530 } 531 532 static void sec_disable_clock_gate(struct hisi_qm *qm) 533 { 534 u32 val; 535 536 /* Kunpeng920 needs to close clock gating */ 537 val = readl_relaxed(qm->io_base + SEC_CONTROL_REG); 538 val &= SEC_CLK_GATE_DISABLE; 539 writel_relaxed(val, qm->io_base + SEC_CONTROL_REG); 540 } 541 542 static int sec_engine_init(struct hisi_qm *qm) 543 { 544 int ret; 545 u32 reg; 546 547 /* disable clock gate control before mem init */ 548 sec_disable_clock_gate(qm); 549 550 writel_relaxed(0x1, qm->io_base + SEC_MEM_START_INIT_REG); 551 552 ret = readl_relaxed_poll_timeout(qm->io_base + SEC_MEM_INIT_DONE_REG, 553 reg, reg & 0x1, SEC_DELAY_10_US, 554 SEC_POLL_TIMEOUT_US); 555 if (ret) { 556 pci_err(qm->pdev, "fail to init sec mem\n"); 557 return ret; 558 } 559 560 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG); 561 reg |= (0x1 << SEC_TRNG_EN_SHIFT); 562 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG); 563 564 sec_engine_sva_config(qm); 565 566 writel(SEC_SINGLE_PORT_MAX_TRANS, 567 qm->io_base + AM_CFG_SINGLE_PORT_MAX_TRANS); 568 569 reg = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_CORE_ENABLE_BITMAP, qm->cap_ver); 570 writel(reg, qm->io_base + SEC_SAA_EN_REG); 571 572 if (qm->ver < QM_HW_V3) { 573 /* HW V2 enable sm4 extra mode, as ctr/ecb */ 574 writel_relaxed(SEC_BD_ERR_CHK_EN0, 575 qm->io_base + SEC_BD_ERR_CHK_EN_REG0); 576 577 /* HW V2 enable sm4 xts mode multiple iv */ 578 writel_relaxed(SEC_BD_ERR_CHK_EN1, 579 qm->io_base + SEC_BD_ERR_CHK_EN_REG1); 580 writel_relaxed(SEC_BD_ERR_CHK_EN3, 581 qm->io_base + SEC_BD_ERR_CHK_EN_REG3); 582 } 583 584 /* config endian */ 585 sec_set_endian(qm); 586 587 sec_enable_clock_gate(qm); 588 589 return 0; 590 } 591 592 static int sec_set_user_domain_and_cache(struct hisi_qm *qm) 593 { 594 /* qm user domain */ 595 writel(AXUSER_BASE, qm->io_base + QM_ARUSER_M_CFG_1); 596 writel(ARUSER_M_CFG_ENABLE, qm->io_base + QM_ARUSER_M_CFG_ENABLE); 597 writel(AXUSER_BASE, qm->io_base + QM_AWUSER_M_CFG_1); 598 writel(AWUSER_M_CFG_ENABLE, qm->io_base + QM_AWUSER_M_CFG_ENABLE); 599 writel(WUSER_M_CFG_ENABLE, qm->io_base + QM_WUSER_M_CFG_ENABLE); 600 601 /* qm cache */ 602 writel(AXI_M_CFG, qm->io_base + QM_AXI_M_CFG); 603 writel(AXI_M_CFG_ENABLE, qm->io_base + QM_AXI_M_CFG_ENABLE); 604 605 /* disable FLR triggered by BME(bus master enable) */ 606 writel(PEH_AXUSER_CFG, qm->io_base + QM_PEH_AXUSER_CFG); 607 writel(PEH_AXUSER_CFG_ENABLE, qm->io_base + QM_PEH_AXUSER_CFG_ENABLE); 608 609 /* enable sqc,cqc writeback */ 610 writel(SQC_CACHE_ENABLE | CQC_CACHE_ENABLE | SQC_CACHE_WB_ENABLE | 611 CQC_CACHE_WB_ENABLE | FIELD_PREP(SQC_CACHE_WB_THRD, 1) | 612 FIELD_PREP(CQC_CACHE_WB_THRD, 1), qm->io_base + QM_CACHE_CTL); 613 614 return sec_engine_init(qm); 615 } 616 617 /* sec_debug_regs_clear() - clear the sec debug regs */ 618 static void sec_debug_regs_clear(struct hisi_qm *qm) 619 { 620 int i; 621 622 /* clear sec dfx regs */ 623 writel(0x1, qm->io_base + SEC_CTRL_CNT_CLR_CE); 624 for (i = 0; i < ARRAY_SIZE(sec_dfx_regs); i++) 625 readl(qm->io_base + sec_dfx_regs[i].offset); 626 627 /* clear rdclr_en */ 628 writel(0x0, qm->io_base + SEC_CTRL_CNT_CLR_CE); 629 630 hisi_qm_debug_regs_clear(qm); 631 } 632 633 static void sec_master_ooo_ctrl(struct hisi_qm *qm, bool enable) 634 { 635 u32 val1, val2; 636 637 val1 = readl(qm->io_base + SEC_CONTROL_REG); 638 if (enable) { 639 val1 |= SEC_AXI_SHUTDOWN_ENABLE; 640 val2 = hisi_qm_get_hw_info(qm, sec_basic_info, 641 SEC_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 642 } else { 643 val1 &= SEC_AXI_SHUTDOWN_DISABLE; 644 val2 = 0x0; 645 } 646 647 if (qm->ver > QM_HW_V2) 648 writel(val2, qm->io_base + SEC_OOO_SHUTDOWN_SEL); 649 650 writel(val1, qm->io_base + SEC_CONTROL_REG); 651 } 652 653 static void sec_hw_error_enable(struct hisi_qm *qm) 654 { 655 u32 ce, nfe; 656 657 if (qm->ver == QM_HW_V1) { 658 writel(SEC_CORE_INT_DISABLE, qm->io_base + SEC_CORE_INT_MASK); 659 pci_info(qm->pdev, "V1 not support hw error handle\n"); 660 return; 661 } 662 663 ce = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_CE_MASK_CAP, qm->cap_ver); 664 nfe = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_NFE_MASK_CAP, qm->cap_ver); 665 666 /* clear SEC hw error source if having */ 667 writel(ce | nfe | SEC_RAS_FE_ENB_MSK, qm->io_base + SEC_CORE_INT_SOURCE); 668 669 /* enable RAS int */ 670 writel(ce, qm->io_base + SEC_RAS_CE_REG); 671 writel(SEC_RAS_FE_ENB_MSK, qm->io_base + SEC_RAS_FE_REG); 672 writel(nfe, qm->io_base + SEC_RAS_NFE_REG); 673 674 /* enable SEC block master OOO when nfe occurs on Kunpeng930 */ 675 sec_master_ooo_ctrl(qm, true); 676 677 /* enable SEC hw error interrupts */ 678 writel(ce | nfe | SEC_RAS_FE_ENB_MSK, qm->io_base + SEC_CORE_INT_MASK); 679 } 680 681 static void sec_hw_error_disable(struct hisi_qm *qm) 682 { 683 /* disable SEC hw error interrupts */ 684 writel(SEC_CORE_INT_DISABLE, qm->io_base + SEC_CORE_INT_MASK); 685 686 /* disable SEC block master OOO when nfe occurs on Kunpeng930 */ 687 sec_master_ooo_ctrl(qm, false); 688 689 /* disable RAS int */ 690 writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_CE_REG); 691 writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_FE_REG); 692 writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_NFE_REG); 693 } 694 695 static u32 sec_clear_enable_read(struct hisi_qm *qm) 696 { 697 return readl(qm->io_base + SEC_CTRL_CNT_CLR_CE) & 698 SEC_CTRL_CNT_CLR_CE_BIT; 699 } 700 701 static int sec_clear_enable_write(struct hisi_qm *qm, u32 val) 702 { 703 u32 tmp; 704 705 if (val != 1 && val) 706 return -EINVAL; 707 708 tmp = (readl(qm->io_base + SEC_CTRL_CNT_CLR_CE) & 709 ~SEC_CTRL_CNT_CLR_CE_BIT) | val; 710 writel(tmp, qm->io_base + SEC_CTRL_CNT_CLR_CE); 711 712 return 0; 713 } 714 715 static ssize_t sec_debug_read(struct file *filp, char __user *buf, 716 size_t count, loff_t *pos) 717 { 718 struct sec_debug_file *file = filp->private_data; 719 char tbuf[SEC_DBGFS_VAL_MAX_LEN]; 720 struct hisi_qm *qm = file->qm; 721 u32 val; 722 int ret; 723 724 ret = hisi_qm_get_dfx_access(qm); 725 if (ret) 726 return ret; 727 728 spin_lock_irq(&file->lock); 729 730 switch (file->index) { 731 case SEC_CLEAR_ENABLE: 732 val = sec_clear_enable_read(qm); 733 break; 734 default: 735 goto err_input; 736 } 737 738 spin_unlock_irq(&file->lock); 739 740 hisi_qm_put_dfx_access(qm); 741 ret = snprintf(tbuf, SEC_DBGFS_VAL_MAX_LEN, "%u\n", val); 742 return simple_read_from_buffer(buf, count, pos, tbuf, ret); 743 744 err_input: 745 spin_unlock_irq(&file->lock); 746 hisi_qm_put_dfx_access(qm); 747 return -EINVAL; 748 } 749 750 static ssize_t sec_debug_write(struct file *filp, const char __user *buf, 751 size_t count, loff_t *pos) 752 { 753 struct sec_debug_file *file = filp->private_data; 754 char tbuf[SEC_DBGFS_VAL_MAX_LEN]; 755 struct hisi_qm *qm = file->qm; 756 unsigned long val; 757 int len, ret; 758 759 if (*pos != 0) 760 return 0; 761 762 if (count >= SEC_DBGFS_VAL_MAX_LEN) 763 return -ENOSPC; 764 765 len = simple_write_to_buffer(tbuf, SEC_DBGFS_VAL_MAX_LEN - 1, 766 pos, buf, count); 767 if (len < 0) 768 return len; 769 770 tbuf[len] = '\0'; 771 if (kstrtoul(tbuf, 0, &val)) 772 return -EFAULT; 773 774 ret = hisi_qm_get_dfx_access(qm); 775 if (ret) 776 return ret; 777 778 spin_lock_irq(&file->lock); 779 780 switch (file->index) { 781 case SEC_CLEAR_ENABLE: 782 ret = sec_clear_enable_write(qm, val); 783 if (ret) 784 goto err_input; 785 break; 786 default: 787 ret = -EINVAL; 788 goto err_input; 789 } 790 791 ret = count; 792 793 err_input: 794 spin_unlock_irq(&file->lock); 795 hisi_qm_put_dfx_access(qm); 796 return ret; 797 } 798 799 static const struct file_operations sec_dbg_fops = { 800 .owner = THIS_MODULE, 801 .open = simple_open, 802 .read = sec_debug_read, 803 .write = sec_debug_write, 804 }; 805 806 static int sec_debugfs_atomic64_get(void *data, u64 *val) 807 { 808 *val = atomic64_read((atomic64_t *)data); 809 810 return 0; 811 } 812 813 static int sec_debugfs_atomic64_set(void *data, u64 val) 814 { 815 if (val) 816 return -EINVAL; 817 818 atomic64_set((atomic64_t *)data, 0); 819 820 return 0; 821 } 822 823 DEFINE_DEBUGFS_ATTRIBUTE(sec_atomic64_ops, sec_debugfs_atomic64_get, 824 sec_debugfs_atomic64_set, "%lld\n"); 825 826 static int sec_regs_show(struct seq_file *s, void *unused) 827 { 828 hisi_qm_regs_dump(s, s->private); 829 830 return 0; 831 } 832 833 DEFINE_SHOW_ATTRIBUTE(sec_regs); 834 835 static int sec_core_debug_init(struct hisi_qm *qm) 836 { 837 struct dfx_diff_registers *sec_regs = qm->debug.acc_diff_regs; 838 struct sec_dev *sec = container_of(qm, struct sec_dev, qm); 839 struct device *dev = &qm->pdev->dev; 840 struct sec_dfx *dfx = &sec->debug.dfx; 841 struct debugfs_regset32 *regset; 842 struct dentry *tmp_d; 843 int i; 844 845 tmp_d = debugfs_create_dir("sec_dfx", qm->debug.debug_root); 846 847 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); 848 if (!regset) 849 return -ENOMEM; 850 851 regset->regs = sec_dfx_regs; 852 regset->nregs = ARRAY_SIZE(sec_dfx_regs); 853 regset->base = qm->io_base; 854 regset->dev = dev; 855 856 if (qm->pdev->device == PCI_DEVICE_ID_HUAWEI_SEC_PF) 857 debugfs_create_file("regs", 0444, tmp_d, regset, &sec_regs_fops); 858 if (qm->fun_type == QM_HW_PF && sec_regs) 859 debugfs_create_file("diff_regs", 0444, tmp_d, 860 qm, &sec_diff_regs_fops); 861 862 for (i = 0; i < ARRAY_SIZE(sec_dfx_labels); i++) { 863 atomic64_t *data = (atomic64_t *)((uintptr_t)dfx + 864 sec_dfx_labels[i].offset); 865 debugfs_create_file(sec_dfx_labels[i].name, 0644, 866 tmp_d, data, &sec_atomic64_ops); 867 } 868 869 return 0; 870 } 871 872 static int sec_debug_init(struct hisi_qm *qm) 873 { 874 struct sec_dev *sec = container_of(qm, struct sec_dev, qm); 875 int i; 876 877 if (qm->pdev->device == PCI_DEVICE_ID_HUAWEI_SEC_PF) { 878 for (i = SEC_CLEAR_ENABLE; i < SEC_DEBUG_FILE_NUM; i++) { 879 spin_lock_init(&sec->debug.files[i].lock); 880 sec->debug.files[i].index = i; 881 sec->debug.files[i].qm = qm; 882 883 debugfs_create_file(sec_dbg_file_name[i], 0600, 884 qm->debug.debug_root, 885 sec->debug.files + i, 886 &sec_dbg_fops); 887 } 888 } 889 890 return sec_core_debug_init(qm); 891 } 892 893 static int sec_debugfs_init(struct hisi_qm *qm) 894 { 895 struct device *dev = &qm->pdev->dev; 896 int ret; 897 898 qm->debug.debug_root = debugfs_create_dir(dev_name(dev), 899 sec_debugfs_root); 900 qm->debug.sqe_mask_offset = SEC_SQE_MASK_OFFSET; 901 qm->debug.sqe_mask_len = SEC_SQE_MASK_LEN; 902 903 ret = hisi_qm_regs_debugfs_init(qm, sec_diff_regs, ARRAY_SIZE(sec_diff_regs)); 904 if (ret) { 905 dev_warn(dev, "Failed to init SEC diff regs!\n"); 906 goto debugfs_remove; 907 } 908 909 hisi_qm_debug_init(qm); 910 911 ret = sec_debug_init(qm); 912 if (ret) 913 goto failed_to_create; 914 915 return 0; 916 917 failed_to_create: 918 hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(sec_diff_regs)); 919 debugfs_remove: 920 debugfs_remove_recursive(sec_debugfs_root); 921 return ret; 922 } 923 924 static void sec_debugfs_exit(struct hisi_qm *qm) 925 { 926 hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(sec_diff_regs)); 927 928 debugfs_remove_recursive(qm->debug.debug_root); 929 } 930 931 static int sec_show_last_regs_init(struct hisi_qm *qm) 932 { 933 struct qm_debug *debug = &qm->debug; 934 int i; 935 936 debug->last_words = kcalloc(ARRAY_SIZE(sec_dfx_regs), 937 sizeof(unsigned int), GFP_KERNEL); 938 if (!debug->last_words) 939 return -ENOMEM; 940 941 for (i = 0; i < ARRAY_SIZE(sec_dfx_regs); i++) 942 debug->last_words[i] = readl_relaxed(qm->io_base + 943 sec_dfx_regs[i].offset); 944 945 return 0; 946 } 947 948 static void sec_show_last_regs_uninit(struct hisi_qm *qm) 949 { 950 struct qm_debug *debug = &qm->debug; 951 952 if (qm->fun_type == QM_HW_VF || !debug->last_words) 953 return; 954 955 kfree(debug->last_words); 956 debug->last_words = NULL; 957 } 958 959 static void sec_show_last_dfx_regs(struct hisi_qm *qm) 960 { 961 struct qm_debug *debug = &qm->debug; 962 struct pci_dev *pdev = qm->pdev; 963 u32 val; 964 int i; 965 966 if (qm->fun_type == QM_HW_VF || !debug->last_words) 967 return; 968 969 /* dumps last word of the debugging registers during controller reset */ 970 for (i = 0; i < ARRAY_SIZE(sec_dfx_regs); i++) { 971 val = readl_relaxed(qm->io_base + sec_dfx_regs[i].offset); 972 if (val != debug->last_words[i]) 973 pci_info(pdev, "%s \t= 0x%08x => 0x%08x\n", 974 sec_dfx_regs[i].name, debug->last_words[i], val); 975 } 976 } 977 978 static void sec_log_hw_error(struct hisi_qm *qm, u32 err_sts) 979 { 980 const struct sec_hw_error *errs = sec_hw_errors; 981 struct device *dev = &qm->pdev->dev; 982 u32 err_val; 983 984 while (errs->msg) { 985 if (errs->int_msk & err_sts) { 986 dev_err(dev, "%s [error status=0x%x] found\n", 987 errs->msg, errs->int_msk); 988 989 if (SEC_CORE_INT_STATUS_M_ECC & errs->int_msk) { 990 err_val = readl(qm->io_base + 991 SEC_CORE_SRAM_ECC_ERR_INFO); 992 dev_err(dev, "multi ecc sram num=0x%x\n", 993 ((err_val) >> SEC_ECC_NUM) & 994 SEC_ECC_MASH); 995 } 996 } 997 errs++; 998 } 999 } 1000 1001 static u32 sec_get_hw_err_status(struct hisi_qm *qm) 1002 { 1003 return readl(qm->io_base + SEC_CORE_INT_STATUS); 1004 } 1005 1006 static void sec_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts) 1007 { 1008 u32 nfe; 1009 1010 writel(err_sts, qm->io_base + SEC_CORE_INT_SOURCE); 1011 nfe = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_NFE_MASK_CAP, qm->cap_ver); 1012 writel(nfe, qm->io_base + SEC_RAS_NFE_REG); 1013 } 1014 1015 static void sec_open_axi_master_ooo(struct hisi_qm *qm) 1016 { 1017 u32 val; 1018 1019 val = readl(qm->io_base + SEC_CONTROL_REG); 1020 writel(val & SEC_AXI_SHUTDOWN_DISABLE, qm->io_base + SEC_CONTROL_REG); 1021 writel(val | SEC_AXI_SHUTDOWN_ENABLE, qm->io_base + SEC_CONTROL_REG); 1022 } 1023 1024 static void sec_err_info_init(struct hisi_qm *qm) 1025 { 1026 struct hisi_qm_err_info *err_info = &qm->err_info; 1027 1028 err_info->fe = SEC_RAS_FE_ENB_MSK; 1029 err_info->ce = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_QM_CE_MASK_CAP, qm->cap_ver); 1030 err_info->nfe = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_QM_NFE_MASK_CAP, qm->cap_ver); 1031 err_info->ecc_2bits_mask = SEC_CORE_INT_STATUS_M_ECC; 1032 err_info->qm_shutdown_mask = hisi_qm_get_hw_info(qm, sec_basic_info, 1033 SEC_QM_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 1034 err_info->dev_shutdown_mask = hisi_qm_get_hw_info(qm, sec_basic_info, 1035 SEC_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 1036 err_info->qm_reset_mask = hisi_qm_get_hw_info(qm, sec_basic_info, 1037 SEC_QM_RESET_MASK_CAP, qm->cap_ver); 1038 err_info->dev_reset_mask = hisi_qm_get_hw_info(qm, sec_basic_info, 1039 SEC_RESET_MASK_CAP, qm->cap_ver); 1040 err_info->msi_wr_port = BIT(0); 1041 err_info->acpi_rst = "SRST"; 1042 } 1043 1044 static const struct hisi_qm_err_ini sec_err_ini = { 1045 .hw_init = sec_set_user_domain_and_cache, 1046 .hw_err_enable = sec_hw_error_enable, 1047 .hw_err_disable = sec_hw_error_disable, 1048 .get_dev_hw_err_status = sec_get_hw_err_status, 1049 .clear_dev_hw_err_status = sec_clear_hw_err_status, 1050 .log_dev_hw_err = sec_log_hw_error, 1051 .open_axi_master_ooo = sec_open_axi_master_ooo, 1052 .open_sva_prefetch = sec_open_sva_prefetch, 1053 .close_sva_prefetch = sec_close_sva_prefetch, 1054 .show_last_dfx_regs = sec_show_last_dfx_regs, 1055 .err_info_init = sec_err_info_init, 1056 }; 1057 1058 static int sec_pf_probe_init(struct sec_dev *sec) 1059 { 1060 struct hisi_qm *qm = &sec->qm; 1061 int ret; 1062 1063 qm->err_ini = &sec_err_ini; 1064 qm->err_ini->err_info_init(qm); 1065 1066 ret = sec_set_user_domain_and_cache(qm); 1067 if (ret) 1068 return ret; 1069 1070 sec_open_sva_prefetch(qm); 1071 hisi_qm_dev_err_init(qm); 1072 sec_debug_regs_clear(qm); 1073 ret = sec_show_last_regs_init(qm); 1074 if (ret) 1075 pci_err(qm->pdev, "Failed to init last word regs!\n"); 1076 1077 return ret; 1078 } 1079 1080 static int sec_set_qm_algs(struct hisi_qm *qm) 1081 { 1082 struct device *dev = &qm->pdev->dev; 1083 char *algs, *ptr; 1084 u64 alg_mask; 1085 int i; 1086 1087 if (!qm->use_sva) 1088 return 0; 1089 1090 algs = devm_kzalloc(dev, SEC_DEV_ALG_MAX_LEN * sizeof(char), GFP_KERNEL); 1091 if (!algs) 1092 return -ENOMEM; 1093 1094 alg_mask = sec_get_alg_bitmap(qm, SEC_DEV_ALG_BITMAP_HIGH, SEC_DEV_ALG_BITMAP_LOW); 1095 1096 for (i = 0; i < ARRAY_SIZE(sec_dev_algs); i++) 1097 if (alg_mask & sec_dev_algs[i].alg_msk) 1098 strcat(algs, sec_dev_algs[i].algs); 1099 1100 ptr = strrchr(algs, '\n'); 1101 if (ptr) 1102 *ptr = '\0'; 1103 1104 qm->uacce->algs = algs; 1105 1106 return 0; 1107 } 1108 1109 static int sec_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) 1110 { 1111 int ret; 1112 1113 qm->pdev = pdev; 1114 qm->ver = pdev->revision; 1115 qm->mode = uacce_mode; 1116 qm->sqe_size = SEC_SQE_SIZE; 1117 qm->dev_name = sec_name; 1118 1119 qm->fun_type = (pdev->device == PCI_DEVICE_ID_HUAWEI_SEC_PF) ? 1120 QM_HW_PF : QM_HW_VF; 1121 if (qm->fun_type == QM_HW_PF) { 1122 qm->qp_base = SEC_PF_DEF_Q_BASE; 1123 qm->qp_num = pf_q_num; 1124 qm->debug.curr_qm_qp_num = pf_q_num; 1125 qm->qm_list = &sec_devices; 1126 if (pf_q_num_flag) 1127 set_bit(QM_MODULE_PARAM, &qm->misc_ctl); 1128 } else if (qm->fun_type == QM_HW_VF && qm->ver == QM_HW_V1) { 1129 /* 1130 * have no way to get qm configure in VM in v1 hardware, 1131 * so currently force PF to uses SEC_PF_DEF_Q_NUM, and force 1132 * to trigger only one VF in v1 hardware. 1133 * v2 hardware has no such problem. 1134 */ 1135 qm->qp_base = SEC_PF_DEF_Q_NUM; 1136 qm->qp_num = SEC_QUEUE_NUM_V1 - SEC_PF_DEF_Q_NUM; 1137 } 1138 1139 ret = hisi_qm_init(qm); 1140 if (ret) { 1141 pci_err(qm->pdev, "Failed to init sec qm configures!\n"); 1142 return ret; 1143 } 1144 1145 ret = sec_set_qm_algs(qm); 1146 if (ret) { 1147 pci_err(qm->pdev, "Failed to set sec algs!\n"); 1148 hisi_qm_uninit(qm); 1149 } 1150 1151 return ret; 1152 } 1153 1154 static void sec_qm_uninit(struct hisi_qm *qm) 1155 { 1156 hisi_qm_uninit(qm); 1157 } 1158 1159 static int sec_probe_init(struct sec_dev *sec) 1160 { 1161 u32 type_rate = SEC_SHAPER_TYPE_RATE; 1162 struct hisi_qm *qm = &sec->qm; 1163 int ret; 1164 1165 if (qm->fun_type == QM_HW_PF) { 1166 ret = sec_pf_probe_init(sec); 1167 if (ret) 1168 return ret; 1169 /* enable shaper type 0 */ 1170 if (qm->ver >= QM_HW_V3) { 1171 type_rate |= QM_SHAPER_ENABLE; 1172 qm->type_rate = type_rate; 1173 } 1174 } 1175 1176 return 0; 1177 } 1178 1179 static void sec_probe_uninit(struct hisi_qm *qm) 1180 { 1181 hisi_qm_dev_err_uninit(qm); 1182 } 1183 1184 static void sec_iommu_used_check(struct sec_dev *sec) 1185 { 1186 struct iommu_domain *domain; 1187 struct device *dev = &sec->qm.pdev->dev; 1188 1189 domain = iommu_get_domain_for_dev(dev); 1190 1191 /* Check if iommu is used */ 1192 sec->iommu_used = false; 1193 if (domain) { 1194 if (domain->type & __IOMMU_DOMAIN_PAGING) 1195 sec->iommu_used = true; 1196 dev_info(dev, "SMMU Opened, the iommu type = %u\n", 1197 domain->type); 1198 } 1199 } 1200 1201 static int sec_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1202 { 1203 struct sec_dev *sec; 1204 struct hisi_qm *qm; 1205 int ret; 1206 1207 sec = devm_kzalloc(&pdev->dev, sizeof(*sec), GFP_KERNEL); 1208 if (!sec) 1209 return -ENOMEM; 1210 1211 qm = &sec->qm; 1212 ret = sec_qm_init(qm, pdev); 1213 if (ret) { 1214 pci_err(pdev, "Failed to init SEC QM (%d)!\n", ret); 1215 return ret; 1216 } 1217 1218 sec->ctx_q_num = ctx_q_num; 1219 sec_iommu_used_check(sec); 1220 1221 ret = sec_probe_init(sec); 1222 if (ret) { 1223 pci_err(pdev, "Failed to probe!\n"); 1224 goto err_qm_uninit; 1225 } 1226 1227 ret = hisi_qm_start(qm); 1228 if (ret) { 1229 pci_err(pdev, "Failed to start sec qm!\n"); 1230 goto err_probe_uninit; 1231 } 1232 1233 ret = sec_debugfs_init(qm); 1234 if (ret) 1235 pci_warn(pdev, "Failed to init debugfs!\n"); 1236 1237 hisi_qm_add_list(qm, &sec_devices); 1238 ret = hisi_qm_alg_register(qm, &sec_devices, ctx_q_num); 1239 if (ret < 0) { 1240 pr_err("Failed to register driver to crypto.\n"); 1241 goto err_qm_del_list; 1242 } 1243 1244 if (qm->uacce) { 1245 ret = uacce_register(qm->uacce); 1246 if (ret) { 1247 pci_err(pdev, "failed to register uacce (%d)!\n", ret); 1248 goto err_alg_unregister; 1249 } 1250 } 1251 1252 if (qm->fun_type == QM_HW_PF && vfs_num) { 1253 ret = hisi_qm_sriov_enable(pdev, vfs_num); 1254 if (ret < 0) 1255 goto err_alg_unregister; 1256 } 1257 1258 hisi_qm_pm_init(qm); 1259 1260 return 0; 1261 1262 err_alg_unregister: 1263 hisi_qm_alg_unregister(qm, &sec_devices, ctx_q_num); 1264 err_qm_del_list: 1265 hisi_qm_del_list(qm, &sec_devices); 1266 sec_debugfs_exit(qm); 1267 hisi_qm_stop(qm, QM_NORMAL); 1268 err_probe_uninit: 1269 sec_show_last_regs_uninit(qm); 1270 sec_probe_uninit(qm); 1271 err_qm_uninit: 1272 sec_qm_uninit(qm); 1273 return ret; 1274 } 1275 1276 static void sec_remove(struct pci_dev *pdev) 1277 { 1278 struct hisi_qm *qm = pci_get_drvdata(pdev); 1279 1280 hisi_qm_pm_uninit(qm); 1281 hisi_qm_wait_task_finish(qm, &sec_devices); 1282 hisi_qm_alg_unregister(qm, &sec_devices, ctx_q_num); 1283 hisi_qm_del_list(qm, &sec_devices); 1284 1285 if (qm->fun_type == QM_HW_PF && qm->vfs_num) 1286 hisi_qm_sriov_disable(pdev, true); 1287 1288 sec_debugfs_exit(qm); 1289 1290 (void)hisi_qm_stop(qm, QM_NORMAL); 1291 1292 if (qm->fun_type == QM_HW_PF) 1293 sec_debug_regs_clear(qm); 1294 sec_show_last_regs_uninit(qm); 1295 1296 sec_probe_uninit(qm); 1297 1298 sec_qm_uninit(qm); 1299 } 1300 1301 static const struct dev_pm_ops sec_pm_ops = { 1302 SET_RUNTIME_PM_OPS(hisi_qm_suspend, hisi_qm_resume, NULL) 1303 }; 1304 1305 static const struct pci_error_handlers sec_err_handler = { 1306 .error_detected = hisi_qm_dev_err_detected, 1307 .slot_reset = hisi_qm_dev_slot_reset, 1308 .reset_prepare = hisi_qm_reset_prepare, 1309 .reset_done = hisi_qm_reset_done, 1310 }; 1311 1312 static struct pci_driver sec_pci_driver = { 1313 .name = "hisi_sec2", 1314 .id_table = sec_dev_ids, 1315 .probe = sec_probe, 1316 .remove = sec_remove, 1317 .err_handler = &sec_err_handler, 1318 .sriov_configure = hisi_qm_sriov_configure, 1319 .shutdown = hisi_qm_dev_shutdown, 1320 .driver.pm = &sec_pm_ops, 1321 }; 1322 1323 struct pci_driver *hisi_sec_get_pf_driver(void) 1324 { 1325 return &sec_pci_driver; 1326 } 1327 EXPORT_SYMBOL_GPL(hisi_sec_get_pf_driver); 1328 1329 static void sec_register_debugfs(void) 1330 { 1331 if (!debugfs_initialized()) 1332 return; 1333 1334 sec_debugfs_root = debugfs_create_dir("hisi_sec2", NULL); 1335 } 1336 1337 static void sec_unregister_debugfs(void) 1338 { 1339 debugfs_remove_recursive(sec_debugfs_root); 1340 } 1341 1342 static int __init sec_init(void) 1343 { 1344 int ret; 1345 1346 hisi_qm_init_list(&sec_devices); 1347 sec_register_debugfs(); 1348 1349 ret = pci_register_driver(&sec_pci_driver); 1350 if (ret < 0) { 1351 sec_unregister_debugfs(); 1352 pr_err("Failed to register pci driver.\n"); 1353 return ret; 1354 } 1355 1356 return 0; 1357 } 1358 1359 static void __exit sec_exit(void) 1360 { 1361 pci_unregister_driver(&sec_pci_driver); 1362 sec_unregister_debugfs(); 1363 } 1364 1365 module_init(sec_init); 1366 module_exit(sec_exit); 1367 1368 MODULE_LICENSE("GPL v2"); 1369 MODULE_AUTHOR("Zaibo Xu <xuzaibo@huawei.com>"); 1370 MODULE_AUTHOR("Longfang Liu <liulongfang@huawei.com>"); 1371 MODULE_AUTHOR("Kai Ye <yekai13@huawei.com>"); 1372 MODULE_AUTHOR("Wei Zhang <zhangwei375@huawei.com>"); 1373 MODULE_DESCRIPTION("Driver for HiSilicon SEC accelerator"); 1374