1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2019 HiSilicon Limited. */ 3 4 #include <linux/acpi.h> 5 #include <linux/aer.h> 6 #include <linux/bitops.h> 7 #include <linux/debugfs.h> 8 #include <linux/init.h> 9 #include <linux/io.h> 10 #include <linux/iommu.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/pci.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/seq_file.h> 16 #include <linux/topology.h> 17 #include <linux/uacce.h> 18 19 #include "sec.h" 20 21 #define SEC_VF_NUM 63 22 #define SEC_QUEUE_NUM_V1 4096 23 #define PCI_DEVICE_ID_HUAWEI_SEC_PF 0xa255 24 25 #define SEC_BD_ERR_CHK_EN0 0xEFFFFFFF 26 #define SEC_BD_ERR_CHK_EN1 0x7ffff7fd 27 #define SEC_BD_ERR_CHK_EN3 0xffffbfff 28 29 #define SEC_SQE_SIZE 128 30 #define SEC_PF_DEF_Q_NUM 256 31 #define SEC_PF_DEF_Q_BASE 0 32 #define SEC_CTX_Q_NUM_DEF 2 33 #define SEC_CTX_Q_NUM_MAX 32 34 35 #define SEC_CTRL_CNT_CLR_CE 0x301120 36 #define SEC_CTRL_CNT_CLR_CE_BIT BIT(0) 37 #define SEC_CORE_INT_SOURCE 0x301010 38 #define SEC_CORE_INT_MASK 0x301000 39 #define SEC_CORE_INT_STATUS 0x301008 40 #define SEC_CORE_SRAM_ECC_ERR_INFO 0x301C14 41 #define SEC_ECC_NUM 16 42 #define SEC_ECC_MASH 0xFF 43 #define SEC_CORE_INT_DISABLE 0x0 44 45 #define SEC_RAS_CE_REG 0x301050 46 #define SEC_RAS_FE_REG 0x301054 47 #define SEC_RAS_NFE_REG 0x301058 48 #define SEC_RAS_FE_ENB_MSK 0x0 49 #define SEC_OOO_SHUTDOWN_SEL 0x301014 50 #define SEC_RAS_DISABLE 0x0 51 #define SEC_MEM_START_INIT_REG 0x301100 52 #define SEC_MEM_INIT_DONE_REG 0x301104 53 54 /* clock gating */ 55 #define SEC_CONTROL_REG 0x301200 56 #define SEC_DYNAMIC_GATE_REG 0x30121c 57 #define SEC_CORE_AUTO_GATE 0x30212c 58 #define SEC_DYNAMIC_GATE_EN 0x7fff 59 #define SEC_CORE_AUTO_GATE_EN GENMASK(3, 0) 60 #define SEC_CLK_GATE_ENABLE BIT(3) 61 #define SEC_CLK_GATE_DISABLE (~BIT(3)) 62 63 #define SEC_TRNG_EN_SHIFT 8 64 #define SEC_AXI_SHUTDOWN_ENABLE BIT(12) 65 #define SEC_AXI_SHUTDOWN_DISABLE 0xFFFFEFFF 66 67 #define SEC_INTERFACE_USER_CTRL0_REG 0x301220 68 #define SEC_INTERFACE_USER_CTRL1_REG 0x301224 69 #define SEC_SAA_EN_REG 0x301270 70 #define SEC_BD_ERR_CHK_EN_REG0 0x301380 71 #define SEC_BD_ERR_CHK_EN_REG1 0x301384 72 #define SEC_BD_ERR_CHK_EN_REG3 0x30138c 73 74 #define SEC_USER0_SMMU_NORMAL (BIT(23) | BIT(15)) 75 #define SEC_USER1_SMMU_NORMAL (BIT(31) | BIT(23) | BIT(15) | BIT(7)) 76 #define SEC_USER1_ENABLE_CONTEXT_SSV BIT(24) 77 #define SEC_USER1_ENABLE_DATA_SSV BIT(16) 78 #define SEC_USER1_WB_CONTEXT_SSV BIT(8) 79 #define SEC_USER1_WB_DATA_SSV BIT(0) 80 #define SEC_USER1_SVA_SET (SEC_USER1_ENABLE_CONTEXT_SSV | \ 81 SEC_USER1_ENABLE_DATA_SSV | \ 82 SEC_USER1_WB_CONTEXT_SSV | \ 83 SEC_USER1_WB_DATA_SSV) 84 #define SEC_USER1_SMMU_SVA (SEC_USER1_SMMU_NORMAL | SEC_USER1_SVA_SET) 85 #define SEC_USER1_SMMU_MASK (~SEC_USER1_SVA_SET) 86 #define SEC_INTERFACE_USER_CTRL0_REG_V3 0x302220 87 #define SEC_INTERFACE_USER_CTRL1_REG_V3 0x302224 88 #define SEC_USER1_SMMU_NORMAL_V3 (BIT(23) | BIT(17) | BIT(11) | BIT(5)) 89 #define SEC_USER1_SMMU_MASK_V3 0xFF79E79E 90 #define SEC_CORE_INT_STATUS_M_ECC BIT(2) 91 92 #define SEC_PREFETCH_CFG 0x301130 93 #define SEC_SVA_TRANS 0x301EC4 94 #define SEC_PREFETCH_ENABLE (~(BIT(0) | BIT(1) | BIT(11))) 95 #define SEC_PREFETCH_DISABLE BIT(1) 96 #define SEC_SVA_DISABLE_READY (BIT(7) | BIT(11)) 97 98 #define SEC_DELAY_10_US 10 99 #define SEC_POLL_TIMEOUT_US 1000 100 #define SEC_DBGFS_VAL_MAX_LEN 20 101 #define SEC_SINGLE_PORT_MAX_TRANS 0x2060 102 103 #define SEC_SQE_MASK_OFFSET 64 104 #define SEC_SQE_MASK_LEN 48 105 #define SEC_SHAPER_TYPE_RATE 400 106 107 #define SEC_DFX_BASE 0x301000 108 #define SEC_DFX_CORE 0x302100 109 #define SEC_DFX_COMMON1 0x301600 110 #define SEC_DFX_COMMON2 0x301C00 111 #define SEC_DFX_BASE_LEN 0x9D 112 #define SEC_DFX_CORE_LEN 0x32B 113 #define SEC_DFX_COMMON1_LEN 0x45 114 #define SEC_DFX_COMMON2_LEN 0xBA 115 116 #define SEC_ALG_BITMAP_SHIFT 32 117 118 #define SEC_CIPHER_BITMAP (GENMASK_ULL(5, 0) | GENMASK_ULL(16, 12) | \ 119 GENMASK(24, 21)) 120 #define SEC_DIGEST_BITMAP (GENMASK_ULL(11, 8) | GENMASK_ULL(20, 19) | \ 121 GENMASK_ULL(42, 25)) 122 #define SEC_AEAD_BITMAP (GENMASK_ULL(7, 6) | GENMASK_ULL(18, 17) | \ 123 GENMASK_ULL(45, 43)) 124 #define SEC_DEV_ALG_MAX_LEN 256 125 126 struct sec_hw_error { 127 u32 int_msk; 128 const char *msg; 129 }; 130 131 struct sec_dfx_item { 132 const char *name; 133 u32 offset; 134 }; 135 136 struct sec_dev_alg { 137 u64 alg_msk; 138 const char *algs; 139 }; 140 141 static const char sec_name[] = "hisi_sec2"; 142 static struct dentry *sec_debugfs_root; 143 144 static struct hisi_qm_list sec_devices = { 145 .register_to_crypto = sec_register_to_crypto, 146 .unregister_from_crypto = sec_unregister_from_crypto, 147 }; 148 149 static const struct hisi_qm_cap_info sec_basic_info[] = { 150 {SEC_QM_NFE_MASK_CAP, 0x3124, 0, GENMASK(31, 0), 0x0, 0x1C77, 0x7C77}, 151 {SEC_QM_RESET_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0xC77, 0x6C77}, 152 {SEC_QM_OOO_SHUTDOWN_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0x4, 0x6C77}, 153 {SEC_QM_CE_MASK_CAP, 0x312C, 0, GENMASK(31, 0), 0x0, 0x8, 0x8}, 154 {SEC_NFE_MASK_CAP, 0x3130, 0, GENMASK(31, 0), 0x0, 0x177, 0x60177}, 155 {SEC_RESET_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x177, 0x177}, 156 {SEC_OOO_SHUTDOWN_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x4, 0x177}, 157 {SEC_CE_MASK_CAP, 0x3138, 0, GENMASK(31, 0), 0x0, 0x88, 0xC088}, 158 {SEC_CLUSTER_NUM_CAP, 0x313c, 20, GENMASK(3, 0), 0x1, 0x1, 0x1}, 159 {SEC_CORE_TYPE_NUM_CAP, 0x313c, 16, GENMASK(3, 0), 0x1, 0x1, 0x1}, 160 {SEC_CORE_NUM_CAP, 0x313c, 8, GENMASK(7, 0), 0x4, 0x4, 0x4}, 161 {SEC_CORES_PER_CLUSTER_NUM_CAP, 0x313c, 0, GENMASK(7, 0), 0x4, 0x4, 0x4}, 162 {SEC_CORE_ENABLE_BITMAP, 0x3140, 32, GENMASK(31, 0), 0x17F, 0x17F, 0xF}, 163 {SEC_DRV_ALG_BITMAP_LOW, 0x3144, 0, GENMASK(31, 0), 0x18050CB, 0x18050CB, 0x187F0FF}, 164 {SEC_DRV_ALG_BITMAP_HIGH, 0x3148, 0, GENMASK(31, 0), 0x395C, 0x395C, 0x395C}, 165 {SEC_DEV_ALG_BITMAP_LOW, 0x314c, 0, GENMASK(31, 0), 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}, 166 {SEC_DEV_ALG_BITMAP_HIGH, 0x3150, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF}, 167 {SEC_CORE1_ALG_BITMAP_LOW, 0x3154, 0, GENMASK(31, 0), 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}, 168 {SEC_CORE1_ALG_BITMAP_HIGH, 0x3158, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF}, 169 {SEC_CORE2_ALG_BITMAP_LOW, 0x315c, 0, GENMASK(31, 0), 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}, 170 {SEC_CORE2_ALG_BITMAP_HIGH, 0x3160, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF}, 171 {SEC_CORE3_ALG_BITMAP_LOW, 0x3164, 0, GENMASK(31, 0), 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}, 172 {SEC_CORE3_ALG_BITMAP_HIGH, 0x3168, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF}, 173 {SEC_CORE4_ALG_BITMAP_LOW, 0x316c, 0, GENMASK(31, 0), 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}, 174 {SEC_CORE4_ALG_BITMAP_HIGH, 0x3170, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF}, 175 }; 176 177 static const struct sec_dev_alg sec_dev_algs[] = { { 178 .alg_msk = SEC_CIPHER_BITMAP, 179 .algs = "cipher\n", 180 }, { 181 .alg_msk = SEC_DIGEST_BITMAP, 182 .algs = "digest\n", 183 }, { 184 .alg_msk = SEC_AEAD_BITMAP, 185 .algs = "aead\n", 186 }, 187 }; 188 189 static const struct sec_hw_error sec_hw_errors[] = { 190 { 191 .int_msk = BIT(0), 192 .msg = "sec_axi_rresp_err_rint" 193 }, 194 { 195 .int_msk = BIT(1), 196 .msg = "sec_axi_bresp_err_rint" 197 }, 198 { 199 .int_msk = BIT(2), 200 .msg = "sec_ecc_2bit_err_rint" 201 }, 202 { 203 .int_msk = BIT(3), 204 .msg = "sec_ecc_1bit_err_rint" 205 }, 206 { 207 .int_msk = BIT(4), 208 .msg = "sec_req_trng_timeout_rint" 209 }, 210 { 211 .int_msk = BIT(5), 212 .msg = "sec_fsm_hbeat_rint" 213 }, 214 { 215 .int_msk = BIT(6), 216 .msg = "sec_channel_req_rng_timeout_rint" 217 }, 218 { 219 .int_msk = BIT(7), 220 .msg = "sec_bd_err_rint" 221 }, 222 { 223 .int_msk = BIT(8), 224 .msg = "sec_chain_buff_err_rint" 225 }, 226 { 227 .int_msk = BIT(14), 228 .msg = "sec_no_secure_access" 229 }, 230 { 231 .int_msk = BIT(15), 232 .msg = "sec_wrapping_key_auth_err" 233 }, 234 { 235 .int_msk = BIT(16), 236 .msg = "sec_km_key_crc_fail" 237 }, 238 { 239 .int_msk = BIT(17), 240 .msg = "sec_axi_poison_err" 241 }, 242 { 243 .int_msk = BIT(18), 244 .msg = "sec_sva_err" 245 }, 246 {} 247 }; 248 249 static const char * const sec_dbg_file_name[] = { 250 [SEC_CLEAR_ENABLE] = "clear_enable", 251 }; 252 253 static struct sec_dfx_item sec_dfx_labels[] = { 254 {"send_cnt", offsetof(struct sec_dfx, send_cnt)}, 255 {"recv_cnt", offsetof(struct sec_dfx, recv_cnt)}, 256 {"send_busy_cnt", offsetof(struct sec_dfx, send_busy_cnt)}, 257 {"recv_busy_cnt", offsetof(struct sec_dfx, recv_busy_cnt)}, 258 {"err_bd_cnt", offsetof(struct sec_dfx, err_bd_cnt)}, 259 {"invalid_req_cnt", offsetof(struct sec_dfx, invalid_req_cnt)}, 260 {"done_flag_cnt", offsetof(struct sec_dfx, done_flag_cnt)}, 261 }; 262 263 static const struct debugfs_reg32 sec_dfx_regs[] = { 264 {"SEC_PF_ABNORMAL_INT_SOURCE ", 0x301010}, 265 {"SEC_SAA_EN ", 0x301270}, 266 {"SEC_BD_LATENCY_MIN ", 0x301600}, 267 {"SEC_BD_LATENCY_MAX ", 0x301608}, 268 {"SEC_BD_LATENCY_AVG ", 0x30160C}, 269 {"SEC_BD_NUM_IN_SAA0 ", 0x301670}, 270 {"SEC_BD_NUM_IN_SAA1 ", 0x301674}, 271 {"SEC_BD_NUM_IN_SEC ", 0x301680}, 272 {"SEC_ECC_1BIT_CNT ", 0x301C00}, 273 {"SEC_ECC_1BIT_INFO ", 0x301C04}, 274 {"SEC_ECC_2BIT_CNT ", 0x301C10}, 275 {"SEC_ECC_2BIT_INFO ", 0x301C14}, 276 {"SEC_BD_SAA0 ", 0x301C20}, 277 {"SEC_BD_SAA1 ", 0x301C24}, 278 {"SEC_BD_SAA2 ", 0x301C28}, 279 {"SEC_BD_SAA3 ", 0x301C2C}, 280 {"SEC_BD_SAA4 ", 0x301C30}, 281 {"SEC_BD_SAA5 ", 0x301C34}, 282 {"SEC_BD_SAA6 ", 0x301C38}, 283 {"SEC_BD_SAA7 ", 0x301C3C}, 284 {"SEC_BD_SAA8 ", 0x301C40}, 285 }; 286 287 /* define the SEC's dfx regs region and region length */ 288 static struct dfx_diff_registers sec_diff_regs[] = { 289 { 290 .reg_offset = SEC_DFX_BASE, 291 .reg_len = SEC_DFX_BASE_LEN, 292 }, { 293 .reg_offset = SEC_DFX_COMMON1, 294 .reg_len = SEC_DFX_COMMON1_LEN, 295 }, { 296 .reg_offset = SEC_DFX_COMMON2, 297 .reg_len = SEC_DFX_COMMON2_LEN, 298 }, { 299 .reg_offset = SEC_DFX_CORE, 300 .reg_len = SEC_DFX_CORE_LEN, 301 }, 302 }; 303 304 static int sec_diff_regs_show(struct seq_file *s, void *unused) 305 { 306 struct hisi_qm *qm = s->private; 307 308 hisi_qm_acc_diff_regs_dump(qm, s, qm->debug.acc_diff_regs, 309 ARRAY_SIZE(sec_diff_regs)); 310 311 return 0; 312 } 313 DEFINE_SHOW_ATTRIBUTE(sec_diff_regs); 314 315 static int sec_pf_q_num_set(const char *val, const struct kernel_param *kp) 316 { 317 return q_num_set(val, kp, PCI_DEVICE_ID_HUAWEI_SEC_PF); 318 } 319 320 static const struct kernel_param_ops sec_pf_q_num_ops = { 321 .set = sec_pf_q_num_set, 322 .get = param_get_int, 323 }; 324 325 static u32 pf_q_num = SEC_PF_DEF_Q_NUM; 326 module_param_cb(pf_q_num, &sec_pf_q_num_ops, &pf_q_num, 0444); 327 MODULE_PARM_DESC(pf_q_num, "Number of queues in PF(v1 2-4096, v2 2-1024)"); 328 329 static int sec_ctx_q_num_set(const char *val, const struct kernel_param *kp) 330 { 331 u32 ctx_q_num; 332 int ret; 333 334 if (!val) 335 return -EINVAL; 336 337 ret = kstrtou32(val, 10, &ctx_q_num); 338 if (ret) 339 return -EINVAL; 340 341 if (!ctx_q_num || ctx_q_num > SEC_CTX_Q_NUM_MAX || ctx_q_num & 0x1) { 342 pr_err("ctx queue num[%u] is invalid!\n", ctx_q_num); 343 return -EINVAL; 344 } 345 346 return param_set_int(val, kp); 347 } 348 349 static const struct kernel_param_ops sec_ctx_q_num_ops = { 350 .set = sec_ctx_q_num_set, 351 .get = param_get_int, 352 }; 353 static u32 ctx_q_num = SEC_CTX_Q_NUM_DEF; 354 module_param_cb(ctx_q_num, &sec_ctx_q_num_ops, &ctx_q_num, 0444); 355 MODULE_PARM_DESC(ctx_q_num, "Queue num in ctx (2 default, 2, 4, ..., 32)"); 356 357 static const struct kernel_param_ops vfs_num_ops = { 358 .set = vfs_num_set, 359 .get = param_get_int, 360 }; 361 362 static u32 vfs_num; 363 module_param_cb(vfs_num, &vfs_num_ops, &vfs_num, 0444); 364 MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63), 0(default)"); 365 366 void sec_destroy_qps(struct hisi_qp **qps, int qp_num) 367 { 368 hisi_qm_free_qps(qps, qp_num); 369 kfree(qps); 370 } 371 372 struct hisi_qp **sec_create_qps(void) 373 { 374 int node = cpu_to_node(smp_processor_id()); 375 u32 ctx_num = ctx_q_num; 376 struct hisi_qp **qps; 377 int ret; 378 379 qps = kcalloc(ctx_num, sizeof(struct hisi_qp *), GFP_KERNEL); 380 if (!qps) 381 return NULL; 382 383 ret = hisi_qm_alloc_qps_node(&sec_devices, ctx_num, 0, node, qps); 384 if (!ret) 385 return qps; 386 387 kfree(qps); 388 return NULL; 389 } 390 391 u64 sec_get_alg_bitmap(struct hisi_qm *qm, u32 high, u32 low) 392 { 393 u32 cap_val_h, cap_val_l; 394 395 cap_val_h = hisi_qm_get_hw_info(qm, sec_basic_info, high, qm->cap_ver); 396 cap_val_l = hisi_qm_get_hw_info(qm, sec_basic_info, low, qm->cap_ver); 397 398 return ((u64)cap_val_h << SEC_ALG_BITMAP_SHIFT) | (u64)cap_val_l; 399 } 400 401 static const struct kernel_param_ops sec_uacce_mode_ops = { 402 .set = uacce_mode_set, 403 .get = param_get_int, 404 }; 405 406 /* 407 * uacce_mode = 0 means sec only register to crypto, 408 * uacce_mode = 1 means sec both register to crypto and uacce. 409 */ 410 static u32 uacce_mode = UACCE_MODE_NOUACCE; 411 module_param_cb(uacce_mode, &sec_uacce_mode_ops, &uacce_mode, 0444); 412 MODULE_PARM_DESC(uacce_mode, UACCE_MODE_DESC); 413 414 static const struct pci_device_id sec_dev_ids[] = { 415 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_SEC_PF) }, 416 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_SEC_VF) }, 417 { 0, } 418 }; 419 MODULE_DEVICE_TABLE(pci, sec_dev_ids); 420 421 static void sec_set_endian(struct hisi_qm *qm) 422 { 423 u32 reg; 424 425 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG); 426 reg &= ~(BIT(1) | BIT(0)); 427 if (!IS_ENABLED(CONFIG_64BIT)) 428 reg |= BIT(1); 429 430 if (!IS_ENABLED(CONFIG_CPU_LITTLE_ENDIAN)) 431 reg |= BIT(0); 432 433 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG); 434 } 435 436 static void sec_engine_sva_config(struct hisi_qm *qm) 437 { 438 u32 reg; 439 440 if (qm->ver > QM_HW_V2) { 441 reg = readl_relaxed(qm->io_base + 442 SEC_INTERFACE_USER_CTRL0_REG_V3); 443 reg |= SEC_USER0_SMMU_NORMAL; 444 writel_relaxed(reg, qm->io_base + 445 SEC_INTERFACE_USER_CTRL0_REG_V3); 446 447 reg = readl_relaxed(qm->io_base + 448 SEC_INTERFACE_USER_CTRL1_REG_V3); 449 reg &= SEC_USER1_SMMU_MASK_V3; 450 reg |= SEC_USER1_SMMU_NORMAL_V3; 451 writel_relaxed(reg, qm->io_base + 452 SEC_INTERFACE_USER_CTRL1_REG_V3); 453 } else { 454 reg = readl_relaxed(qm->io_base + 455 SEC_INTERFACE_USER_CTRL0_REG); 456 reg |= SEC_USER0_SMMU_NORMAL; 457 writel_relaxed(reg, qm->io_base + 458 SEC_INTERFACE_USER_CTRL0_REG); 459 reg = readl_relaxed(qm->io_base + 460 SEC_INTERFACE_USER_CTRL1_REG); 461 reg &= SEC_USER1_SMMU_MASK; 462 if (qm->use_sva) 463 reg |= SEC_USER1_SMMU_SVA; 464 else 465 reg |= SEC_USER1_SMMU_NORMAL; 466 writel_relaxed(reg, qm->io_base + 467 SEC_INTERFACE_USER_CTRL1_REG); 468 } 469 } 470 471 static void sec_open_sva_prefetch(struct hisi_qm *qm) 472 { 473 u32 val; 474 int ret; 475 476 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps)) 477 return; 478 479 /* Enable prefetch */ 480 val = readl_relaxed(qm->io_base + SEC_PREFETCH_CFG); 481 val &= SEC_PREFETCH_ENABLE; 482 writel(val, qm->io_base + SEC_PREFETCH_CFG); 483 484 ret = readl_relaxed_poll_timeout(qm->io_base + SEC_PREFETCH_CFG, 485 val, !(val & SEC_PREFETCH_DISABLE), 486 SEC_DELAY_10_US, SEC_POLL_TIMEOUT_US); 487 if (ret) 488 pci_err(qm->pdev, "failed to open sva prefetch\n"); 489 } 490 491 static void sec_close_sva_prefetch(struct hisi_qm *qm) 492 { 493 u32 val; 494 int ret; 495 496 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps)) 497 return; 498 499 val = readl_relaxed(qm->io_base + SEC_PREFETCH_CFG); 500 val |= SEC_PREFETCH_DISABLE; 501 writel(val, qm->io_base + SEC_PREFETCH_CFG); 502 503 ret = readl_relaxed_poll_timeout(qm->io_base + SEC_SVA_TRANS, 504 val, !(val & SEC_SVA_DISABLE_READY), 505 SEC_DELAY_10_US, SEC_POLL_TIMEOUT_US); 506 if (ret) 507 pci_err(qm->pdev, "failed to close sva prefetch\n"); 508 } 509 510 static void sec_enable_clock_gate(struct hisi_qm *qm) 511 { 512 u32 val; 513 514 if (qm->ver < QM_HW_V3) 515 return; 516 517 val = readl_relaxed(qm->io_base + SEC_CONTROL_REG); 518 val |= SEC_CLK_GATE_ENABLE; 519 writel_relaxed(val, qm->io_base + SEC_CONTROL_REG); 520 521 val = readl(qm->io_base + SEC_DYNAMIC_GATE_REG); 522 val |= SEC_DYNAMIC_GATE_EN; 523 writel(val, qm->io_base + SEC_DYNAMIC_GATE_REG); 524 525 val = readl(qm->io_base + SEC_CORE_AUTO_GATE); 526 val |= SEC_CORE_AUTO_GATE_EN; 527 writel(val, qm->io_base + SEC_CORE_AUTO_GATE); 528 } 529 530 static void sec_disable_clock_gate(struct hisi_qm *qm) 531 { 532 u32 val; 533 534 /* Kunpeng920 needs to close clock gating */ 535 val = readl_relaxed(qm->io_base + SEC_CONTROL_REG); 536 val &= SEC_CLK_GATE_DISABLE; 537 writel_relaxed(val, qm->io_base + SEC_CONTROL_REG); 538 } 539 540 static int sec_engine_init(struct hisi_qm *qm) 541 { 542 int ret; 543 u32 reg; 544 545 /* disable clock gate control before mem init */ 546 sec_disable_clock_gate(qm); 547 548 writel_relaxed(0x1, qm->io_base + SEC_MEM_START_INIT_REG); 549 550 ret = readl_relaxed_poll_timeout(qm->io_base + SEC_MEM_INIT_DONE_REG, 551 reg, reg & 0x1, SEC_DELAY_10_US, 552 SEC_POLL_TIMEOUT_US); 553 if (ret) { 554 pci_err(qm->pdev, "fail to init sec mem\n"); 555 return ret; 556 } 557 558 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG); 559 reg |= (0x1 << SEC_TRNG_EN_SHIFT); 560 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG); 561 562 sec_engine_sva_config(qm); 563 564 writel(SEC_SINGLE_PORT_MAX_TRANS, 565 qm->io_base + AM_CFG_SINGLE_PORT_MAX_TRANS); 566 567 reg = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_CORE_ENABLE_BITMAP, qm->cap_ver); 568 writel(reg, qm->io_base + SEC_SAA_EN_REG); 569 570 if (qm->ver < QM_HW_V3) { 571 /* HW V2 enable sm4 extra mode, as ctr/ecb */ 572 writel_relaxed(SEC_BD_ERR_CHK_EN0, 573 qm->io_base + SEC_BD_ERR_CHK_EN_REG0); 574 575 /* HW V2 enable sm4 xts mode multiple iv */ 576 writel_relaxed(SEC_BD_ERR_CHK_EN1, 577 qm->io_base + SEC_BD_ERR_CHK_EN_REG1); 578 writel_relaxed(SEC_BD_ERR_CHK_EN3, 579 qm->io_base + SEC_BD_ERR_CHK_EN_REG3); 580 } 581 582 /* config endian */ 583 sec_set_endian(qm); 584 585 sec_enable_clock_gate(qm); 586 587 return 0; 588 } 589 590 static int sec_set_user_domain_and_cache(struct hisi_qm *qm) 591 { 592 /* qm user domain */ 593 writel(AXUSER_BASE, qm->io_base + QM_ARUSER_M_CFG_1); 594 writel(ARUSER_M_CFG_ENABLE, qm->io_base + QM_ARUSER_M_CFG_ENABLE); 595 writel(AXUSER_BASE, qm->io_base + QM_AWUSER_M_CFG_1); 596 writel(AWUSER_M_CFG_ENABLE, qm->io_base + QM_AWUSER_M_CFG_ENABLE); 597 writel(WUSER_M_CFG_ENABLE, qm->io_base + QM_WUSER_M_CFG_ENABLE); 598 599 /* qm cache */ 600 writel(AXI_M_CFG, qm->io_base + QM_AXI_M_CFG); 601 writel(AXI_M_CFG_ENABLE, qm->io_base + QM_AXI_M_CFG_ENABLE); 602 603 /* disable FLR triggered by BME(bus master enable) */ 604 writel(PEH_AXUSER_CFG, qm->io_base + QM_PEH_AXUSER_CFG); 605 writel(PEH_AXUSER_CFG_ENABLE, qm->io_base + QM_PEH_AXUSER_CFG_ENABLE); 606 607 /* enable sqc,cqc writeback */ 608 writel(SQC_CACHE_ENABLE | CQC_CACHE_ENABLE | SQC_CACHE_WB_ENABLE | 609 CQC_CACHE_WB_ENABLE | FIELD_PREP(SQC_CACHE_WB_THRD, 1) | 610 FIELD_PREP(CQC_CACHE_WB_THRD, 1), qm->io_base + QM_CACHE_CTL); 611 612 return sec_engine_init(qm); 613 } 614 615 /* sec_debug_regs_clear() - clear the sec debug regs */ 616 static void sec_debug_regs_clear(struct hisi_qm *qm) 617 { 618 int i; 619 620 /* clear sec dfx regs */ 621 writel(0x1, qm->io_base + SEC_CTRL_CNT_CLR_CE); 622 for (i = 0; i < ARRAY_SIZE(sec_dfx_regs); i++) 623 readl(qm->io_base + sec_dfx_regs[i].offset); 624 625 /* clear rdclr_en */ 626 writel(0x0, qm->io_base + SEC_CTRL_CNT_CLR_CE); 627 628 hisi_qm_debug_regs_clear(qm); 629 } 630 631 static void sec_master_ooo_ctrl(struct hisi_qm *qm, bool enable) 632 { 633 u32 val1, val2; 634 635 val1 = readl(qm->io_base + SEC_CONTROL_REG); 636 if (enable) { 637 val1 |= SEC_AXI_SHUTDOWN_ENABLE; 638 val2 = hisi_qm_get_hw_info(qm, sec_basic_info, 639 SEC_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 640 } else { 641 val1 &= SEC_AXI_SHUTDOWN_DISABLE; 642 val2 = 0x0; 643 } 644 645 if (qm->ver > QM_HW_V2) 646 writel(val2, qm->io_base + SEC_OOO_SHUTDOWN_SEL); 647 648 writel(val1, qm->io_base + SEC_CONTROL_REG); 649 } 650 651 static void sec_hw_error_enable(struct hisi_qm *qm) 652 { 653 u32 ce, nfe; 654 655 if (qm->ver == QM_HW_V1) { 656 writel(SEC_CORE_INT_DISABLE, qm->io_base + SEC_CORE_INT_MASK); 657 pci_info(qm->pdev, "V1 not support hw error handle\n"); 658 return; 659 } 660 661 ce = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_CE_MASK_CAP, qm->cap_ver); 662 nfe = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_NFE_MASK_CAP, qm->cap_ver); 663 664 /* clear SEC hw error source if having */ 665 writel(ce | nfe | SEC_RAS_FE_ENB_MSK, qm->io_base + SEC_CORE_INT_SOURCE); 666 667 /* enable RAS int */ 668 writel(ce, qm->io_base + SEC_RAS_CE_REG); 669 writel(SEC_RAS_FE_ENB_MSK, qm->io_base + SEC_RAS_FE_REG); 670 writel(nfe, qm->io_base + SEC_RAS_NFE_REG); 671 672 /* enable SEC block master OOO when nfe occurs on Kunpeng930 */ 673 sec_master_ooo_ctrl(qm, true); 674 675 /* enable SEC hw error interrupts */ 676 writel(ce | nfe | SEC_RAS_FE_ENB_MSK, qm->io_base + SEC_CORE_INT_MASK); 677 } 678 679 static void sec_hw_error_disable(struct hisi_qm *qm) 680 { 681 /* disable SEC hw error interrupts */ 682 writel(SEC_CORE_INT_DISABLE, qm->io_base + SEC_CORE_INT_MASK); 683 684 /* disable SEC block master OOO when nfe occurs on Kunpeng930 */ 685 sec_master_ooo_ctrl(qm, false); 686 687 /* disable RAS int */ 688 writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_CE_REG); 689 writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_FE_REG); 690 writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_NFE_REG); 691 } 692 693 static u32 sec_clear_enable_read(struct hisi_qm *qm) 694 { 695 return readl(qm->io_base + SEC_CTRL_CNT_CLR_CE) & 696 SEC_CTRL_CNT_CLR_CE_BIT; 697 } 698 699 static int sec_clear_enable_write(struct hisi_qm *qm, u32 val) 700 { 701 u32 tmp; 702 703 if (val != 1 && val) 704 return -EINVAL; 705 706 tmp = (readl(qm->io_base + SEC_CTRL_CNT_CLR_CE) & 707 ~SEC_CTRL_CNT_CLR_CE_BIT) | val; 708 writel(tmp, qm->io_base + SEC_CTRL_CNT_CLR_CE); 709 710 return 0; 711 } 712 713 static ssize_t sec_debug_read(struct file *filp, char __user *buf, 714 size_t count, loff_t *pos) 715 { 716 struct sec_debug_file *file = filp->private_data; 717 char tbuf[SEC_DBGFS_VAL_MAX_LEN]; 718 struct hisi_qm *qm = file->qm; 719 u32 val; 720 int ret; 721 722 ret = hisi_qm_get_dfx_access(qm); 723 if (ret) 724 return ret; 725 726 spin_lock_irq(&file->lock); 727 728 switch (file->index) { 729 case SEC_CLEAR_ENABLE: 730 val = sec_clear_enable_read(qm); 731 break; 732 default: 733 goto err_input; 734 } 735 736 spin_unlock_irq(&file->lock); 737 738 hisi_qm_put_dfx_access(qm); 739 ret = snprintf(tbuf, SEC_DBGFS_VAL_MAX_LEN, "%u\n", val); 740 return simple_read_from_buffer(buf, count, pos, tbuf, ret); 741 742 err_input: 743 spin_unlock_irq(&file->lock); 744 hisi_qm_put_dfx_access(qm); 745 return -EINVAL; 746 } 747 748 static ssize_t sec_debug_write(struct file *filp, const char __user *buf, 749 size_t count, loff_t *pos) 750 { 751 struct sec_debug_file *file = filp->private_data; 752 char tbuf[SEC_DBGFS_VAL_MAX_LEN]; 753 struct hisi_qm *qm = file->qm; 754 unsigned long val; 755 int len, ret; 756 757 if (*pos != 0) 758 return 0; 759 760 if (count >= SEC_DBGFS_VAL_MAX_LEN) 761 return -ENOSPC; 762 763 len = simple_write_to_buffer(tbuf, SEC_DBGFS_VAL_MAX_LEN - 1, 764 pos, buf, count); 765 if (len < 0) 766 return len; 767 768 tbuf[len] = '\0'; 769 if (kstrtoul(tbuf, 0, &val)) 770 return -EFAULT; 771 772 ret = hisi_qm_get_dfx_access(qm); 773 if (ret) 774 return ret; 775 776 spin_lock_irq(&file->lock); 777 778 switch (file->index) { 779 case SEC_CLEAR_ENABLE: 780 ret = sec_clear_enable_write(qm, val); 781 if (ret) 782 goto err_input; 783 break; 784 default: 785 ret = -EINVAL; 786 goto err_input; 787 } 788 789 ret = count; 790 791 err_input: 792 spin_unlock_irq(&file->lock); 793 hisi_qm_put_dfx_access(qm); 794 return ret; 795 } 796 797 static const struct file_operations sec_dbg_fops = { 798 .owner = THIS_MODULE, 799 .open = simple_open, 800 .read = sec_debug_read, 801 .write = sec_debug_write, 802 }; 803 804 static int sec_debugfs_atomic64_get(void *data, u64 *val) 805 { 806 *val = atomic64_read((atomic64_t *)data); 807 808 return 0; 809 } 810 811 static int sec_debugfs_atomic64_set(void *data, u64 val) 812 { 813 if (val) 814 return -EINVAL; 815 816 atomic64_set((atomic64_t *)data, 0); 817 818 return 0; 819 } 820 821 DEFINE_DEBUGFS_ATTRIBUTE(sec_atomic64_ops, sec_debugfs_atomic64_get, 822 sec_debugfs_atomic64_set, "%lld\n"); 823 824 static int sec_regs_show(struct seq_file *s, void *unused) 825 { 826 hisi_qm_regs_dump(s, s->private); 827 828 return 0; 829 } 830 831 DEFINE_SHOW_ATTRIBUTE(sec_regs); 832 833 static int sec_core_debug_init(struct hisi_qm *qm) 834 { 835 struct dfx_diff_registers *sec_regs = qm->debug.acc_diff_regs; 836 struct sec_dev *sec = container_of(qm, struct sec_dev, qm); 837 struct device *dev = &qm->pdev->dev; 838 struct sec_dfx *dfx = &sec->debug.dfx; 839 struct debugfs_regset32 *regset; 840 struct dentry *tmp_d; 841 int i; 842 843 tmp_d = debugfs_create_dir("sec_dfx", qm->debug.debug_root); 844 845 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); 846 if (!regset) 847 return -ENOMEM; 848 849 regset->regs = sec_dfx_regs; 850 regset->nregs = ARRAY_SIZE(sec_dfx_regs); 851 regset->base = qm->io_base; 852 regset->dev = dev; 853 854 if (qm->pdev->device == PCI_DEVICE_ID_HUAWEI_SEC_PF) 855 debugfs_create_file("regs", 0444, tmp_d, regset, &sec_regs_fops); 856 if (qm->fun_type == QM_HW_PF && sec_regs) 857 debugfs_create_file("diff_regs", 0444, tmp_d, 858 qm, &sec_diff_regs_fops); 859 860 for (i = 0; i < ARRAY_SIZE(sec_dfx_labels); i++) { 861 atomic64_t *data = (atomic64_t *)((uintptr_t)dfx + 862 sec_dfx_labels[i].offset); 863 debugfs_create_file(sec_dfx_labels[i].name, 0644, 864 tmp_d, data, &sec_atomic64_ops); 865 } 866 867 return 0; 868 } 869 870 static int sec_debug_init(struct hisi_qm *qm) 871 { 872 struct sec_dev *sec = container_of(qm, struct sec_dev, qm); 873 int i; 874 875 if (qm->pdev->device == PCI_DEVICE_ID_HUAWEI_SEC_PF) { 876 for (i = SEC_CLEAR_ENABLE; i < SEC_DEBUG_FILE_NUM; i++) { 877 spin_lock_init(&sec->debug.files[i].lock); 878 sec->debug.files[i].index = i; 879 sec->debug.files[i].qm = qm; 880 881 debugfs_create_file(sec_dbg_file_name[i], 0600, 882 qm->debug.debug_root, 883 sec->debug.files + i, 884 &sec_dbg_fops); 885 } 886 } 887 888 return sec_core_debug_init(qm); 889 } 890 891 static int sec_debugfs_init(struct hisi_qm *qm) 892 { 893 struct device *dev = &qm->pdev->dev; 894 int ret; 895 896 qm->debug.debug_root = debugfs_create_dir(dev_name(dev), 897 sec_debugfs_root); 898 qm->debug.sqe_mask_offset = SEC_SQE_MASK_OFFSET; 899 qm->debug.sqe_mask_len = SEC_SQE_MASK_LEN; 900 901 ret = hisi_qm_regs_debugfs_init(qm, sec_diff_regs, ARRAY_SIZE(sec_diff_regs)); 902 if (ret) { 903 dev_warn(dev, "Failed to init SEC diff regs!\n"); 904 goto debugfs_remove; 905 } 906 907 hisi_qm_debug_init(qm); 908 909 ret = sec_debug_init(qm); 910 if (ret) 911 goto failed_to_create; 912 913 return 0; 914 915 failed_to_create: 916 hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(sec_diff_regs)); 917 debugfs_remove: 918 debugfs_remove_recursive(sec_debugfs_root); 919 return ret; 920 } 921 922 static void sec_debugfs_exit(struct hisi_qm *qm) 923 { 924 hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(sec_diff_regs)); 925 926 debugfs_remove_recursive(qm->debug.debug_root); 927 } 928 929 static int sec_show_last_regs_init(struct hisi_qm *qm) 930 { 931 struct qm_debug *debug = &qm->debug; 932 int i; 933 934 debug->last_words = kcalloc(ARRAY_SIZE(sec_dfx_regs), 935 sizeof(unsigned int), GFP_KERNEL); 936 if (!debug->last_words) 937 return -ENOMEM; 938 939 for (i = 0; i < ARRAY_SIZE(sec_dfx_regs); i++) 940 debug->last_words[i] = readl_relaxed(qm->io_base + 941 sec_dfx_regs[i].offset); 942 943 return 0; 944 } 945 946 static void sec_show_last_regs_uninit(struct hisi_qm *qm) 947 { 948 struct qm_debug *debug = &qm->debug; 949 950 if (qm->fun_type == QM_HW_VF || !debug->last_words) 951 return; 952 953 kfree(debug->last_words); 954 debug->last_words = NULL; 955 } 956 957 static void sec_show_last_dfx_regs(struct hisi_qm *qm) 958 { 959 struct qm_debug *debug = &qm->debug; 960 struct pci_dev *pdev = qm->pdev; 961 u32 val; 962 int i; 963 964 if (qm->fun_type == QM_HW_VF || !debug->last_words) 965 return; 966 967 /* dumps last word of the debugging registers during controller reset */ 968 for (i = 0; i < ARRAY_SIZE(sec_dfx_regs); i++) { 969 val = readl_relaxed(qm->io_base + sec_dfx_regs[i].offset); 970 if (val != debug->last_words[i]) 971 pci_info(pdev, "%s \t= 0x%08x => 0x%08x\n", 972 sec_dfx_regs[i].name, debug->last_words[i], val); 973 } 974 } 975 976 static void sec_log_hw_error(struct hisi_qm *qm, u32 err_sts) 977 { 978 const struct sec_hw_error *errs = sec_hw_errors; 979 struct device *dev = &qm->pdev->dev; 980 u32 err_val; 981 982 while (errs->msg) { 983 if (errs->int_msk & err_sts) { 984 dev_err(dev, "%s [error status=0x%x] found\n", 985 errs->msg, errs->int_msk); 986 987 if (SEC_CORE_INT_STATUS_M_ECC & errs->int_msk) { 988 err_val = readl(qm->io_base + 989 SEC_CORE_SRAM_ECC_ERR_INFO); 990 dev_err(dev, "multi ecc sram num=0x%x\n", 991 ((err_val) >> SEC_ECC_NUM) & 992 SEC_ECC_MASH); 993 } 994 } 995 errs++; 996 } 997 } 998 999 static u32 sec_get_hw_err_status(struct hisi_qm *qm) 1000 { 1001 return readl(qm->io_base + SEC_CORE_INT_STATUS); 1002 } 1003 1004 static void sec_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts) 1005 { 1006 u32 nfe; 1007 1008 writel(err_sts, qm->io_base + SEC_CORE_INT_SOURCE); 1009 nfe = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_NFE_MASK_CAP, qm->cap_ver); 1010 writel(nfe, qm->io_base + SEC_RAS_NFE_REG); 1011 } 1012 1013 static void sec_open_axi_master_ooo(struct hisi_qm *qm) 1014 { 1015 u32 val; 1016 1017 val = readl(qm->io_base + SEC_CONTROL_REG); 1018 writel(val & SEC_AXI_SHUTDOWN_DISABLE, qm->io_base + SEC_CONTROL_REG); 1019 writel(val | SEC_AXI_SHUTDOWN_ENABLE, qm->io_base + SEC_CONTROL_REG); 1020 } 1021 1022 static void sec_err_info_init(struct hisi_qm *qm) 1023 { 1024 struct hisi_qm_err_info *err_info = &qm->err_info; 1025 1026 err_info->fe = SEC_RAS_FE_ENB_MSK; 1027 err_info->ce = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_QM_CE_MASK_CAP, qm->cap_ver); 1028 err_info->nfe = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_QM_NFE_MASK_CAP, qm->cap_ver); 1029 err_info->ecc_2bits_mask = SEC_CORE_INT_STATUS_M_ECC; 1030 err_info->qm_shutdown_mask = hisi_qm_get_hw_info(qm, sec_basic_info, 1031 SEC_QM_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 1032 err_info->dev_shutdown_mask = hisi_qm_get_hw_info(qm, sec_basic_info, 1033 SEC_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 1034 err_info->qm_reset_mask = hisi_qm_get_hw_info(qm, sec_basic_info, 1035 SEC_QM_RESET_MASK_CAP, qm->cap_ver); 1036 err_info->dev_reset_mask = hisi_qm_get_hw_info(qm, sec_basic_info, 1037 SEC_RESET_MASK_CAP, qm->cap_ver); 1038 err_info->msi_wr_port = BIT(0); 1039 err_info->acpi_rst = "SRST"; 1040 } 1041 1042 static const struct hisi_qm_err_ini sec_err_ini = { 1043 .hw_init = sec_set_user_domain_and_cache, 1044 .hw_err_enable = sec_hw_error_enable, 1045 .hw_err_disable = sec_hw_error_disable, 1046 .get_dev_hw_err_status = sec_get_hw_err_status, 1047 .clear_dev_hw_err_status = sec_clear_hw_err_status, 1048 .log_dev_hw_err = sec_log_hw_error, 1049 .open_axi_master_ooo = sec_open_axi_master_ooo, 1050 .open_sva_prefetch = sec_open_sva_prefetch, 1051 .close_sva_prefetch = sec_close_sva_prefetch, 1052 .show_last_dfx_regs = sec_show_last_dfx_regs, 1053 .err_info_init = sec_err_info_init, 1054 }; 1055 1056 static int sec_pf_probe_init(struct sec_dev *sec) 1057 { 1058 struct hisi_qm *qm = &sec->qm; 1059 int ret; 1060 1061 qm->err_ini = &sec_err_ini; 1062 qm->err_ini->err_info_init(qm); 1063 1064 ret = sec_set_user_domain_and_cache(qm); 1065 if (ret) 1066 return ret; 1067 1068 sec_open_sva_prefetch(qm); 1069 hisi_qm_dev_err_init(qm); 1070 sec_debug_regs_clear(qm); 1071 ret = sec_show_last_regs_init(qm); 1072 if (ret) 1073 pci_err(qm->pdev, "Failed to init last word regs!\n"); 1074 1075 return ret; 1076 } 1077 1078 static int sec_set_qm_algs(struct hisi_qm *qm) 1079 { 1080 struct device *dev = &qm->pdev->dev; 1081 char *algs, *ptr; 1082 u64 alg_mask; 1083 int i; 1084 1085 if (!qm->use_sva) 1086 return 0; 1087 1088 algs = devm_kzalloc(dev, SEC_DEV_ALG_MAX_LEN * sizeof(char), GFP_KERNEL); 1089 if (!algs) 1090 return -ENOMEM; 1091 1092 alg_mask = sec_get_alg_bitmap(qm, SEC_DEV_ALG_BITMAP_HIGH, SEC_DEV_ALG_BITMAP_LOW); 1093 1094 for (i = 0; i < ARRAY_SIZE(sec_dev_algs); i++) 1095 if (alg_mask & sec_dev_algs[i].alg_msk) 1096 strcat(algs, sec_dev_algs[i].algs); 1097 1098 ptr = strrchr(algs, '\n'); 1099 if (ptr) 1100 *ptr = '\0'; 1101 1102 qm->uacce->algs = algs; 1103 1104 return 0; 1105 } 1106 1107 static int sec_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) 1108 { 1109 int ret; 1110 1111 qm->pdev = pdev; 1112 qm->ver = pdev->revision; 1113 qm->mode = uacce_mode; 1114 qm->sqe_size = SEC_SQE_SIZE; 1115 qm->dev_name = sec_name; 1116 1117 qm->fun_type = (pdev->device == PCI_DEVICE_ID_HUAWEI_SEC_PF) ? 1118 QM_HW_PF : QM_HW_VF; 1119 if (qm->fun_type == QM_HW_PF) { 1120 qm->qp_base = SEC_PF_DEF_Q_BASE; 1121 qm->qp_num = pf_q_num; 1122 qm->debug.curr_qm_qp_num = pf_q_num; 1123 qm->qm_list = &sec_devices; 1124 } else if (qm->fun_type == QM_HW_VF && qm->ver == QM_HW_V1) { 1125 /* 1126 * have no way to get qm configure in VM in v1 hardware, 1127 * so currently force PF to uses SEC_PF_DEF_Q_NUM, and force 1128 * to trigger only one VF in v1 hardware. 1129 * v2 hardware has no such problem. 1130 */ 1131 qm->qp_base = SEC_PF_DEF_Q_NUM; 1132 qm->qp_num = SEC_QUEUE_NUM_V1 - SEC_PF_DEF_Q_NUM; 1133 } 1134 1135 ret = hisi_qm_init(qm); 1136 if (ret) { 1137 pci_err(qm->pdev, "Failed to init sec qm configures!\n"); 1138 return ret; 1139 } 1140 1141 ret = sec_set_qm_algs(qm); 1142 if (ret) { 1143 pci_err(qm->pdev, "Failed to set sec algs!\n"); 1144 hisi_qm_uninit(qm); 1145 } 1146 1147 return ret; 1148 } 1149 1150 static void sec_qm_uninit(struct hisi_qm *qm) 1151 { 1152 hisi_qm_uninit(qm); 1153 } 1154 1155 static int sec_probe_init(struct sec_dev *sec) 1156 { 1157 u32 type_rate = SEC_SHAPER_TYPE_RATE; 1158 struct hisi_qm *qm = &sec->qm; 1159 int ret; 1160 1161 if (qm->fun_type == QM_HW_PF) { 1162 ret = sec_pf_probe_init(sec); 1163 if (ret) 1164 return ret; 1165 /* enable shaper type 0 */ 1166 if (qm->ver >= QM_HW_V3) { 1167 type_rate |= QM_SHAPER_ENABLE; 1168 qm->type_rate = type_rate; 1169 } 1170 } 1171 1172 return 0; 1173 } 1174 1175 static void sec_probe_uninit(struct hisi_qm *qm) 1176 { 1177 hisi_qm_dev_err_uninit(qm); 1178 } 1179 1180 static void sec_iommu_used_check(struct sec_dev *sec) 1181 { 1182 struct iommu_domain *domain; 1183 struct device *dev = &sec->qm.pdev->dev; 1184 1185 domain = iommu_get_domain_for_dev(dev); 1186 1187 /* Check if iommu is used */ 1188 sec->iommu_used = false; 1189 if (domain) { 1190 if (domain->type & __IOMMU_DOMAIN_PAGING) 1191 sec->iommu_used = true; 1192 dev_info(dev, "SMMU Opened, the iommu type = %u\n", 1193 domain->type); 1194 } 1195 } 1196 1197 static int sec_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1198 { 1199 struct sec_dev *sec; 1200 struct hisi_qm *qm; 1201 int ret; 1202 1203 sec = devm_kzalloc(&pdev->dev, sizeof(*sec), GFP_KERNEL); 1204 if (!sec) 1205 return -ENOMEM; 1206 1207 qm = &sec->qm; 1208 ret = sec_qm_init(qm, pdev); 1209 if (ret) { 1210 pci_err(pdev, "Failed to init SEC QM (%d)!\n", ret); 1211 return ret; 1212 } 1213 1214 sec->ctx_q_num = ctx_q_num; 1215 sec_iommu_used_check(sec); 1216 1217 ret = sec_probe_init(sec); 1218 if (ret) { 1219 pci_err(pdev, "Failed to probe!\n"); 1220 goto err_qm_uninit; 1221 } 1222 1223 ret = hisi_qm_start(qm); 1224 if (ret) { 1225 pci_err(pdev, "Failed to start sec qm!\n"); 1226 goto err_probe_uninit; 1227 } 1228 1229 ret = sec_debugfs_init(qm); 1230 if (ret) 1231 pci_warn(pdev, "Failed to init debugfs!\n"); 1232 1233 if (qm->qp_num >= ctx_q_num) { 1234 ret = hisi_qm_alg_register(qm, &sec_devices); 1235 if (ret < 0) { 1236 pr_err("Failed to register driver to crypto.\n"); 1237 goto err_qm_stop; 1238 } 1239 } else { 1240 pci_warn(qm->pdev, 1241 "Failed to use kernel mode, qp not enough!\n"); 1242 } 1243 1244 if (qm->uacce) { 1245 ret = uacce_register(qm->uacce); 1246 if (ret) { 1247 pci_err(pdev, "failed to register uacce (%d)!\n", ret); 1248 goto err_alg_unregister; 1249 } 1250 } 1251 1252 if (qm->fun_type == QM_HW_PF && vfs_num) { 1253 ret = hisi_qm_sriov_enable(pdev, vfs_num); 1254 if (ret < 0) 1255 goto err_alg_unregister; 1256 } 1257 1258 hisi_qm_pm_init(qm); 1259 1260 return 0; 1261 1262 err_alg_unregister: 1263 if (qm->qp_num >= ctx_q_num) 1264 hisi_qm_alg_unregister(qm, &sec_devices); 1265 err_qm_stop: 1266 sec_debugfs_exit(qm); 1267 hisi_qm_stop(qm, QM_NORMAL); 1268 err_probe_uninit: 1269 sec_show_last_regs_uninit(qm); 1270 sec_probe_uninit(qm); 1271 err_qm_uninit: 1272 sec_qm_uninit(qm); 1273 return ret; 1274 } 1275 1276 static void sec_remove(struct pci_dev *pdev) 1277 { 1278 struct hisi_qm *qm = pci_get_drvdata(pdev); 1279 1280 hisi_qm_pm_uninit(qm); 1281 hisi_qm_wait_task_finish(qm, &sec_devices); 1282 if (qm->qp_num >= ctx_q_num) 1283 hisi_qm_alg_unregister(qm, &sec_devices); 1284 1285 if (qm->fun_type == QM_HW_PF && qm->vfs_num) 1286 hisi_qm_sriov_disable(pdev, true); 1287 1288 sec_debugfs_exit(qm); 1289 1290 (void)hisi_qm_stop(qm, QM_NORMAL); 1291 1292 if (qm->fun_type == QM_HW_PF) 1293 sec_debug_regs_clear(qm); 1294 sec_show_last_regs_uninit(qm); 1295 1296 sec_probe_uninit(qm); 1297 1298 sec_qm_uninit(qm); 1299 } 1300 1301 static const struct dev_pm_ops sec_pm_ops = { 1302 SET_RUNTIME_PM_OPS(hisi_qm_suspend, hisi_qm_resume, NULL) 1303 }; 1304 1305 static const struct pci_error_handlers sec_err_handler = { 1306 .error_detected = hisi_qm_dev_err_detected, 1307 .slot_reset = hisi_qm_dev_slot_reset, 1308 .reset_prepare = hisi_qm_reset_prepare, 1309 .reset_done = hisi_qm_reset_done, 1310 }; 1311 1312 static struct pci_driver sec_pci_driver = { 1313 .name = "hisi_sec2", 1314 .id_table = sec_dev_ids, 1315 .probe = sec_probe, 1316 .remove = sec_remove, 1317 .err_handler = &sec_err_handler, 1318 .sriov_configure = hisi_qm_sriov_configure, 1319 .shutdown = hisi_qm_dev_shutdown, 1320 .driver.pm = &sec_pm_ops, 1321 }; 1322 1323 struct pci_driver *hisi_sec_get_pf_driver(void) 1324 { 1325 return &sec_pci_driver; 1326 } 1327 EXPORT_SYMBOL_GPL(hisi_sec_get_pf_driver); 1328 1329 static void sec_register_debugfs(void) 1330 { 1331 if (!debugfs_initialized()) 1332 return; 1333 1334 sec_debugfs_root = debugfs_create_dir("hisi_sec2", NULL); 1335 } 1336 1337 static void sec_unregister_debugfs(void) 1338 { 1339 debugfs_remove_recursive(sec_debugfs_root); 1340 } 1341 1342 static int __init sec_init(void) 1343 { 1344 int ret; 1345 1346 hisi_qm_init_list(&sec_devices); 1347 sec_register_debugfs(); 1348 1349 ret = pci_register_driver(&sec_pci_driver); 1350 if (ret < 0) { 1351 sec_unregister_debugfs(); 1352 pr_err("Failed to register pci driver.\n"); 1353 return ret; 1354 } 1355 1356 return 0; 1357 } 1358 1359 static void __exit sec_exit(void) 1360 { 1361 pci_unregister_driver(&sec_pci_driver); 1362 sec_unregister_debugfs(); 1363 } 1364 1365 module_init(sec_init); 1366 module_exit(sec_exit); 1367 1368 MODULE_LICENSE("GPL v2"); 1369 MODULE_AUTHOR("Zaibo Xu <xuzaibo@huawei.com>"); 1370 MODULE_AUTHOR("Longfang Liu <liulongfang@huawei.com>"); 1371 MODULE_AUTHOR("Kai Ye <yekai13@huawei.com>"); 1372 MODULE_AUTHOR("Wei Zhang <zhangwei375@huawei.com>"); 1373 MODULE_DESCRIPTION("Driver for HiSilicon SEC accelerator"); 1374