1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2022 HiSilicon Limited. */ 3 #ifndef QM_COMMON_H 4 #define QM_COMMON_H 5 6 #define QM_DBG_READ_LEN 256 7 #define QM_RESETTING 2 8 9 struct qm_cqe { 10 __le32 rsvd0; 11 __le16 cmd_id; 12 __le16 rsvd1; 13 __le16 sq_head; 14 __le16 sq_num; 15 __le16 rsvd2; 16 __le16 w7; 17 }; 18 19 struct qm_eqe { 20 __le32 dw0; 21 }; 22 23 struct qm_aeqe { 24 __le32 dw0; 25 }; 26 27 struct qm_sqc { 28 __le16 head; 29 __le16 tail; 30 __le32 base_l; 31 __le32 base_h; 32 __le32 dw3; 33 __le16 w8; 34 __le16 rsvd0; 35 __le16 pasid; 36 __le16 w11; 37 __le16 cq_num; 38 __le16 w13; 39 __le32 rsvd1; 40 }; 41 42 struct qm_cqc { 43 __le16 head; 44 __le16 tail; 45 __le32 base_l; 46 __le32 base_h; 47 __le32 dw3; 48 __le16 w8; 49 __le16 rsvd0; 50 __le16 pasid; 51 __le16 w11; 52 __le32 dw6; 53 __le32 rsvd1; 54 }; 55 56 struct qm_eqc { 57 __le16 head; 58 __le16 tail; 59 __le32 base_l; 60 __le32 base_h; 61 __le32 dw3; 62 __le32 rsvd[2]; 63 __le32 dw6; 64 }; 65 66 struct qm_aeqc { 67 __le16 head; 68 __le16 tail; 69 __le32 base_l; 70 __le32 base_h; 71 __le32 dw3; 72 __le32 rsvd[2]; 73 __le32 dw6; 74 }; 75 76 static const char * const qm_s[] = { 77 "init", "start", "close", "stop", 78 }; 79 80 void *hisi_qm_ctx_alloc(struct hisi_qm *qm, size_t ctx_size, 81 dma_addr_t *dma_addr); 82 void hisi_qm_ctx_free(struct hisi_qm *qm, size_t ctx_size, 83 const void *ctx_addr, dma_addr_t *dma_addr); 84 void hisi_qm_show_last_dfx_regs(struct hisi_qm *qm); 85 void hisi_qm_set_algqos_init(struct hisi_qm *qm); 86 87 #endif 88