1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018-2019 HiSilicon Limited. */ 3 #include <linux/acpi.h> 4 #include <linux/bitops.h> 5 #include <linux/debugfs.h> 6 #include <linux/init.h> 7 #include <linux/io.h> 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/pci.h> 11 #include <linux/pm_runtime.h> 12 #include <linux/topology.h> 13 #include <linux/uacce.h> 14 #include "hpre.h" 15 16 #define HPRE_QM_ABNML_INT_MASK 0x100004 17 #define HPRE_CTRL_CNT_CLR_CE_BIT BIT(0) 18 #define HPRE_COMM_CNT_CLR_CE 0x0 19 #define HPRE_CTRL_CNT_CLR_CE 0x301000 20 #define HPRE_FSM_MAX_CNT 0x301008 21 #define HPRE_VFG_AXQOS 0x30100c 22 #define HPRE_VFG_AXCACHE 0x301010 23 #define HPRE_RDCHN_INI_CFG 0x301014 24 #define HPRE_AWUSR_FP_CFG 0x301018 25 #define HPRE_BD_ENDIAN 0x301020 26 #define HPRE_ECC_BYPASS 0x301024 27 #define HPRE_RAS_WIDTH_CFG 0x301028 28 #define HPRE_POISON_BYPASS 0x30102c 29 #define HPRE_BD_ARUSR_CFG 0x301030 30 #define HPRE_BD_AWUSR_CFG 0x301034 31 #define HPRE_TYPES_ENB 0x301038 32 #define HPRE_RSA_ENB BIT(0) 33 #define HPRE_ECC_ENB BIT(1) 34 #define HPRE_DATA_RUSER_CFG 0x30103c 35 #define HPRE_DATA_WUSER_CFG 0x301040 36 #define HPRE_INT_MASK 0x301400 37 #define HPRE_INT_STATUS 0x301800 38 #define HPRE_HAC_INT_MSK 0x301400 39 #define HPRE_HAC_RAS_CE_ENB 0x301410 40 #define HPRE_HAC_RAS_NFE_ENB 0x301414 41 #define HPRE_HAC_RAS_FE_ENB 0x301418 42 #define HPRE_HAC_INT_SET 0x301500 43 #define HPRE_RNG_TIMEOUT_NUM 0x301A34 44 #define HPRE_CORE_INT_ENABLE 0 45 #define HPRE_CORE_INT_DISABLE GENMASK(21, 0) 46 #define HPRE_RDCHN_INI_ST 0x301a00 47 #define HPRE_CLSTR_BASE 0x302000 48 #define HPRE_CORE_EN_OFFSET 0x04 49 #define HPRE_CORE_INI_CFG_OFFSET 0x20 50 #define HPRE_CORE_INI_STATUS_OFFSET 0x80 51 #define HPRE_CORE_HTBT_WARN_OFFSET 0x8c 52 #define HPRE_CORE_IS_SCHD_OFFSET 0x90 53 54 #define HPRE_RAS_CE_ENB 0x301410 55 #define HPRE_RAS_NFE_ENB 0x301414 56 #define HPRE_RAS_FE_ENB 0x301418 57 #define HPRE_OOO_SHUTDOWN_SEL 0x301a3c 58 #define HPRE_HAC_RAS_FE_ENABLE 0 59 60 #define HPRE_CORE_ENB (HPRE_CLSTR_BASE + HPRE_CORE_EN_OFFSET) 61 #define HPRE_CORE_INI_CFG (HPRE_CLSTR_BASE + HPRE_CORE_INI_CFG_OFFSET) 62 #define HPRE_CORE_INI_STATUS (HPRE_CLSTR_BASE + HPRE_CORE_INI_STATUS_OFFSET) 63 #define HPRE_HAC_ECC1_CNT 0x301a04 64 #define HPRE_HAC_ECC2_CNT 0x301a08 65 #define HPRE_HAC_SOURCE_INT 0x301600 66 #define HPRE_CLSTR_ADDR_INTRVL 0x1000 67 #define HPRE_CLUSTER_INQURY 0x100 68 #define HPRE_CLSTR_ADDR_INQRY_RSLT 0x104 69 #define HPRE_TIMEOUT_ABNML_BIT 6 70 #define HPRE_PASID_EN_BIT 9 71 #define HPRE_REG_RD_INTVRL_US 10 72 #define HPRE_REG_RD_TMOUT_US 1000 73 #define HPRE_DBGFS_VAL_MAX_LEN 20 74 #define PCI_DEVICE_ID_HUAWEI_HPRE_PF 0xa258 75 #define HPRE_QM_USR_CFG_MASK GENMASK(31, 1) 76 #define HPRE_QM_AXI_CFG_MASK GENMASK(15, 0) 77 #define HPRE_QM_VFG_AX_MASK GENMASK(7, 0) 78 #define HPRE_BD_USR_MASK GENMASK(1, 0) 79 #define HPRE_PREFETCH_CFG 0x301130 80 #define HPRE_SVA_PREFTCH_DFX 0x30115C 81 #define HPRE_PREFETCH_ENABLE (~(BIT(0) | BIT(30))) 82 #define HPRE_PREFETCH_DISABLE BIT(30) 83 #define HPRE_SVA_DISABLE_READY (BIT(4) | BIT(8)) 84 85 /* clock gate */ 86 #define HPRE_CLKGATE_CTL 0x301a10 87 #define HPRE_PEH_CFG_AUTO_GATE 0x301a2c 88 #define HPRE_CLUSTER_DYN_CTL 0x302010 89 #define HPRE_CORE_SHB_CFG 0x302088 90 #define HPRE_CLKGATE_CTL_EN BIT(0) 91 #define HPRE_PEH_CFG_AUTO_GATE_EN BIT(0) 92 #define HPRE_CLUSTER_DYN_CTL_EN BIT(0) 93 #define HPRE_CORE_GATE_EN (BIT(30) | BIT(31)) 94 95 #define HPRE_AM_OOO_SHUTDOWN_ENB 0x301044 96 #define HPRE_AM_OOO_SHUTDOWN_ENABLE BIT(0) 97 #define HPRE_WR_MSI_PORT BIT(2) 98 99 #define HPRE_CORE_ECC_2BIT_ERR BIT(1) 100 #define HPRE_OOO_ECC_2BIT_ERR BIT(5) 101 102 #define HPRE_QM_BME_FLR BIT(7) 103 #define HPRE_QM_PM_FLR BIT(11) 104 #define HPRE_QM_SRIOV_FLR BIT(12) 105 106 #define HPRE_SHAPER_TYPE_RATE 640 107 #define HPRE_VIA_MSI_DSM 1 108 #define HPRE_SQE_MASK_OFFSET 8 109 #define HPRE_SQE_MASK_LEN 24 110 #define HPRE_CTX_Q_NUM_DEF 1 111 112 #define HPRE_DFX_BASE 0x301000 113 #define HPRE_DFX_COMMON1 0x301400 114 #define HPRE_DFX_COMMON2 0x301A00 115 #define HPRE_DFX_CORE 0x302000 116 #define HPRE_DFX_BASE_LEN 0x55 117 #define HPRE_DFX_COMMON1_LEN 0x41 118 #define HPRE_DFX_COMMON2_LEN 0xE 119 #define HPRE_DFX_CORE_LEN 0x43 120 121 #define HPRE_DEV_ALG_MAX_LEN 256 122 123 static const char hpre_name[] = "hisi_hpre"; 124 static struct dentry *hpre_debugfs_root; 125 static const struct pci_device_id hpre_dev_ids[] = { 126 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_HPRE_PF) }, 127 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_HPRE_VF) }, 128 { 0, } 129 }; 130 131 MODULE_DEVICE_TABLE(pci, hpre_dev_ids); 132 133 struct hpre_hw_error { 134 u32 int_msk; 135 const char *msg; 136 }; 137 138 struct hpre_dev_alg { 139 u32 alg_msk; 140 const char *alg; 141 }; 142 143 static const struct hpre_dev_alg hpre_dev_algs[] = { 144 { 145 .alg_msk = BIT(0), 146 .alg = "rsa\n" 147 }, { 148 .alg_msk = BIT(1), 149 .alg = "dh\n" 150 }, { 151 .alg_msk = BIT(2), 152 .alg = "ecdh\n" 153 }, { 154 .alg_msk = BIT(3), 155 .alg = "ecdsa\n" 156 }, { 157 .alg_msk = BIT(4), 158 .alg = "sm2\n" 159 }, { 160 .alg_msk = BIT(5), 161 .alg = "x25519\n" 162 }, { 163 .alg_msk = BIT(6), 164 .alg = "x448\n" 165 }, { 166 /* sentinel */ 167 } 168 }; 169 170 static struct hisi_qm_list hpre_devices = { 171 .register_to_crypto = hpre_algs_register, 172 .unregister_from_crypto = hpre_algs_unregister, 173 }; 174 175 static const char * const hpre_debug_file_name[] = { 176 [HPRE_CLEAR_ENABLE] = "rdclr_en", 177 [HPRE_CLUSTER_CTRL] = "cluster_ctrl", 178 }; 179 180 enum hpre_cap_type { 181 HPRE_QM_NFE_MASK_CAP, 182 HPRE_QM_RESET_MASK_CAP, 183 HPRE_QM_OOO_SHUTDOWN_MASK_CAP, 184 HPRE_QM_CE_MASK_CAP, 185 HPRE_NFE_MASK_CAP, 186 HPRE_RESET_MASK_CAP, 187 HPRE_OOO_SHUTDOWN_MASK_CAP, 188 HPRE_CE_MASK_CAP, 189 HPRE_CLUSTER_NUM_CAP, 190 HPRE_CORE_TYPE_NUM_CAP, 191 HPRE_CORE_NUM_CAP, 192 HPRE_CLUSTER_CORE_NUM_CAP, 193 HPRE_CORE_ENABLE_BITMAP_CAP, 194 HPRE_DRV_ALG_BITMAP_CAP, 195 HPRE_DEV_ALG_BITMAP_CAP, 196 HPRE_CORE1_ALG_BITMAP_CAP, 197 HPRE_CORE2_ALG_BITMAP_CAP, 198 HPRE_CORE3_ALG_BITMAP_CAP, 199 HPRE_CORE4_ALG_BITMAP_CAP, 200 HPRE_CORE5_ALG_BITMAP_CAP, 201 HPRE_CORE6_ALG_BITMAP_CAP, 202 HPRE_CORE7_ALG_BITMAP_CAP, 203 HPRE_CORE8_ALG_BITMAP_CAP, 204 HPRE_CORE9_ALG_BITMAP_CAP, 205 HPRE_CORE10_ALG_BITMAP_CAP 206 }; 207 208 static const struct hisi_qm_cap_info hpre_basic_info[] = { 209 {HPRE_QM_NFE_MASK_CAP, 0x3124, 0, GENMASK(31, 0), 0x0, 0x1C37, 0x7C37}, 210 {HPRE_QM_RESET_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0xC37, 0x6C37}, 211 {HPRE_QM_OOO_SHUTDOWN_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0x4, 0x6C37}, 212 {HPRE_QM_CE_MASK_CAP, 0x312C, 0, GENMASK(31, 0), 0x0, 0x8, 0x8}, 213 {HPRE_NFE_MASK_CAP, 0x3130, 0, GENMASK(31, 0), 0x0, 0x3FFFFE, 0x1FFFFFE}, 214 {HPRE_RESET_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x3FFFFE, 0xBFFFFE}, 215 {HPRE_OOO_SHUTDOWN_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x22, 0xBFFFFE}, 216 {HPRE_CE_MASK_CAP, 0x3138, 0, GENMASK(31, 0), 0x0, 0x1, 0x1}, 217 {HPRE_CLUSTER_NUM_CAP, 0x313c, 20, GENMASK(3, 0), 0x0, 0x4, 0x1}, 218 {HPRE_CORE_TYPE_NUM_CAP, 0x313c, 16, GENMASK(3, 0), 0x0, 0x2, 0x2}, 219 {HPRE_CORE_NUM_CAP, 0x313c, 8, GENMASK(7, 0), 0x0, 0x8, 0xA}, 220 {HPRE_CLUSTER_CORE_NUM_CAP, 0x313c, 0, GENMASK(7, 0), 0x0, 0x2, 0xA}, 221 {HPRE_CORE_ENABLE_BITMAP_CAP, 0x3140, 0, GENMASK(31, 0), 0x0, 0xF, 0x3FF}, 222 {HPRE_DRV_ALG_BITMAP_CAP, 0x3144, 0, GENMASK(31, 0), 0x0, 0x03, 0x27}, 223 {HPRE_DEV_ALG_BITMAP_CAP, 0x3148, 0, GENMASK(31, 0), 0x0, 0x03, 0x7F}, 224 {HPRE_CORE1_ALG_BITMAP_CAP, 0x314c, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F}, 225 {HPRE_CORE2_ALG_BITMAP_CAP, 0x3150, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F}, 226 {HPRE_CORE3_ALG_BITMAP_CAP, 0x3154, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F}, 227 {HPRE_CORE4_ALG_BITMAP_CAP, 0x3158, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F}, 228 {HPRE_CORE5_ALG_BITMAP_CAP, 0x315c, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F}, 229 {HPRE_CORE6_ALG_BITMAP_CAP, 0x3160, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F}, 230 {HPRE_CORE7_ALG_BITMAP_CAP, 0x3164, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F}, 231 {HPRE_CORE8_ALG_BITMAP_CAP, 0x3168, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F}, 232 {HPRE_CORE9_ALG_BITMAP_CAP, 0x316c, 0, GENMASK(31, 0), 0x0, 0x10, 0x10}, 233 {HPRE_CORE10_ALG_BITMAP_CAP, 0x3170, 0, GENMASK(31, 0), 0x0, 0x10, 0x10} 234 }; 235 236 static const struct hpre_hw_error hpre_hw_errors[] = { 237 { 238 .int_msk = BIT(0), 239 .msg = "core_ecc_1bit_err_int_set" 240 }, { 241 .int_msk = BIT(1), 242 .msg = "core_ecc_2bit_err_int_set" 243 }, { 244 .int_msk = BIT(2), 245 .msg = "dat_wb_poison_int_set" 246 }, { 247 .int_msk = BIT(3), 248 .msg = "dat_rd_poison_int_set" 249 }, { 250 .int_msk = BIT(4), 251 .msg = "bd_rd_poison_int_set" 252 }, { 253 .int_msk = BIT(5), 254 .msg = "ooo_ecc_2bit_err_int_set" 255 }, { 256 .int_msk = BIT(6), 257 .msg = "cluster1_shb_timeout_int_set" 258 }, { 259 .int_msk = BIT(7), 260 .msg = "cluster2_shb_timeout_int_set" 261 }, { 262 .int_msk = BIT(8), 263 .msg = "cluster3_shb_timeout_int_set" 264 }, { 265 .int_msk = BIT(9), 266 .msg = "cluster4_shb_timeout_int_set" 267 }, { 268 .int_msk = GENMASK(15, 10), 269 .msg = "ooo_rdrsp_err_int_set" 270 }, { 271 .int_msk = GENMASK(21, 16), 272 .msg = "ooo_wrrsp_err_int_set" 273 }, { 274 .int_msk = BIT(22), 275 .msg = "pt_rng_timeout_int_set" 276 }, { 277 .int_msk = BIT(23), 278 .msg = "sva_fsm_timeout_int_set" 279 }, { 280 .int_msk = BIT(24), 281 .msg = "sva_int_set" 282 }, { 283 /* sentinel */ 284 } 285 }; 286 287 static const u64 hpre_cluster_offsets[] = { 288 [HPRE_CLUSTER0] = 289 HPRE_CLSTR_BASE + HPRE_CLUSTER0 * HPRE_CLSTR_ADDR_INTRVL, 290 [HPRE_CLUSTER1] = 291 HPRE_CLSTR_BASE + HPRE_CLUSTER1 * HPRE_CLSTR_ADDR_INTRVL, 292 [HPRE_CLUSTER2] = 293 HPRE_CLSTR_BASE + HPRE_CLUSTER2 * HPRE_CLSTR_ADDR_INTRVL, 294 [HPRE_CLUSTER3] = 295 HPRE_CLSTR_BASE + HPRE_CLUSTER3 * HPRE_CLSTR_ADDR_INTRVL, 296 }; 297 298 static const struct debugfs_reg32 hpre_cluster_dfx_regs[] = { 299 {"CORES_EN_STATUS ", HPRE_CORE_EN_OFFSET}, 300 {"CORES_INI_CFG ", HPRE_CORE_INI_CFG_OFFSET}, 301 {"CORES_INI_STATUS ", HPRE_CORE_INI_STATUS_OFFSET}, 302 {"CORES_HTBT_WARN ", HPRE_CORE_HTBT_WARN_OFFSET}, 303 {"CORES_IS_SCHD ", HPRE_CORE_IS_SCHD_OFFSET}, 304 }; 305 306 static const struct debugfs_reg32 hpre_com_dfx_regs[] = { 307 {"READ_CLR_EN ", HPRE_CTRL_CNT_CLR_CE}, 308 {"AXQOS ", HPRE_VFG_AXQOS}, 309 {"AWUSR_CFG ", HPRE_AWUSR_FP_CFG}, 310 {"BD_ENDIAN ", HPRE_BD_ENDIAN}, 311 {"ECC_CHECK_CTRL ", HPRE_ECC_BYPASS}, 312 {"RAS_INT_WIDTH ", HPRE_RAS_WIDTH_CFG}, 313 {"POISON_BYPASS ", HPRE_POISON_BYPASS}, 314 {"BD_ARUSER ", HPRE_BD_ARUSR_CFG}, 315 {"BD_AWUSER ", HPRE_BD_AWUSR_CFG}, 316 {"DATA_ARUSER ", HPRE_DATA_RUSER_CFG}, 317 {"DATA_AWUSER ", HPRE_DATA_WUSER_CFG}, 318 {"INT_STATUS ", HPRE_INT_STATUS}, 319 {"INT_MASK ", HPRE_HAC_INT_MSK}, 320 {"RAS_CE_ENB ", HPRE_HAC_RAS_CE_ENB}, 321 {"RAS_NFE_ENB ", HPRE_HAC_RAS_NFE_ENB}, 322 {"RAS_FE_ENB ", HPRE_HAC_RAS_FE_ENB}, 323 {"INT_SET ", HPRE_HAC_INT_SET}, 324 {"RNG_TIMEOUT_NUM ", HPRE_RNG_TIMEOUT_NUM}, 325 }; 326 327 static const char *hpre_dfx_files[HPRE_DFX_FILE_NUM] = { 328 "send_cnt", 329 "recv_cnt", 330 "send_fail_cnt", 331 "send_busy_cnt", 332 "over_thrhld_cnt", 333 "overtime_thrhld", 334 "invalid_req_cnt" 335 }; 336 337 /* define the HPRE's dfx regs region and region length */ 338 static struct dfx_diff_registers hpre_diff_regs[] = { 339 { 340 .reg_offset = HPRE_DFX_BASE, 341 .reg_len = HPRE_DFX_BASE_LEN, 342 }, { 343 .reg_offset = HPRE_DFX_COMMON1, 344 .reg_len = HPRE_DFX_COMMON1_LEN, 345 }, { 346 .reg_offset = HPRE_DFX_COMMON2, 347 .reg_len = HPRE_DFX_COMMON2_LEN, 348 }, { 349 .reg_offset = HPRE_DFX_CORE, 350 .reg_len = HPRE_DFX_CORE_LEN, 351 }, 352 }; 353 354 bool hpre_check_alg_support(struct hisi_qm *qm, u32 alg) 355 { 356 u32 cap_val; 357 358 cap_val = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_DRV_ALG_BITMAP_CAP, qm->cap_ver); 359 if (alg & cap_val) 360 return true; 361 362 return false; 363 } 364 365 static int hpre_set_qm_algs(struct hisi_qm *qm) 366 { 367 struct device *dev = &qm->pdev->dev; 368 char *algs, *ptr; 369 u32 alg_msk; 370 int i; 371 372 if (!qm->use_sva) 373 return 0; 374 375 algs = devm_kzalloc(dev, HPRE_DEV_ALG_MAX_LEN * sizeof(char), GFP_KERNEL); 376 if (!algs) 377 return -ENOMEM; 378 379 alg_msk = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_DEV_ALG_BITMAP_CAP, qm->cap_ver); 380 381 for (i = 0; i < ARRAY_SIZE(hpre_dev_algs); i++) 382 if (alg_msk & hpre_dev_algs[i].alg_msk) 383 strcat(algs, hpre_dev_algs[i].alg); 384 385 ptr = strrchr(algs, '\n'); 386 if (ptr) 387 *ptr = '\0'; 388 389 qm->uacce->algs = algs; 390 391 return 0; 392 } 393 394 static int hpre_diff_regs_show(struct seq_file *s, void *unused) 395 { 396 struct hisi_qm *qm = s->private; 397 398 hisi_qm_acc_diff_regs_dump(qm, s, qm->debug.acc_diff_regs, 399 ARRAY_SIZE(hpre_diff_regs)); 400 401 return 0; 402 } 403 404 DEFINE_SHOW_ATTRIBUTE(hpre_diff_regs); 405 406 static int hpre_com_regs_show(struct seq_file *s, void *unused) 407 { 408 hisi_qm_regs_dump(s, s->private); 409 410 return 0; 411 } 412 413 DEFINE_SHOW_ATTRIBUTE(hpre_com_regs); 414 415 static int hpre_cluster_regs_show(struct seq_file *s, void *unused) 416 { 417 hisi_qm_regs_dump(s, s->private); 418 419 return 0; 420 } 421 422 DEFINE_SHOW_ATTRIBUTE(hpre_cluster_regs); 423 424 static const struct kernel_param_ops hpre_uacce_mode_ops = { 425 .set = uacce_mode_set, 426 .get = param_get_int, 427 }; 428 429 /* 430 * uacce_mode = 0 means hpre only register to crypto, 431 * uacce_mode = 1 means hpre both register to crypto and uacce. 432 */ 433 static u32 uacce_mode = UACCE_MODE_NOUACCE; 434 module_param_cb(uacce_mode, &hpre_uacce_mode_ops, &uacce_mode, 0444); 435 MODULE_PARM_DESC(uacce_mode, UACCE_MODE_DESC); 436 437 static bool pf_q_num_flag; 438 static int pf_q_num_set(const char *val, const struct kernel_param *kp) 439 { 440 pf_q_num_flag = true; 441 442 return q_num_set(val, kp, PCI_DEVICE_ID_HUAWEI_HPRE_PF); 443 } 444 445 static const struct kernel_param_ops hpre_pf_q_num_ops = { 446 .set = pf_q_num_set, 447 .get = param_get_int, 448 }; 449 450 static u32 pf_q_num = HPRE_PF_DEF_Q_NUM; 451 module_param_cb(pf_q_num, &hpre_pf_q_num_ops, &pf_q_num, 0444); 452 MODULE_PARM_DESC(pf_q_num, "Number of queues in PF of CS(2-1024)"); 453 454 static const struct kernel_param_ops vfs_num_ops = { 455 .set = vfs_num_set, 456 .get = param_get_int, 457 }; 458 459 static u32 vfs_num; 460 module_param_cb(vfs_num, &vfs_num_ops, &vfs_num, 0444); 461 MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63), 0(default)"); 462 463 static inline int hpre_cluster_num(struct hisi_qm *qm) 464 { 465 return hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_CLUSTER_NUM_CAP, qm->cap_ver); 466 } 467 468 static inline int hpre_cluster_core_mask(struct hisi_qm *qm) 469 { 470 return hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_CORE_ENABLE_BITMAP_CAP, qm->cap_ver); 471 } 472 473 struct hisi_qp *hpre_create_qp(u8 type) 474 { 475 int node = cpu_to_node(smp_processor_id()); 476 struct hisi_qp *qp = NULL; 477 int ret; 478 479 if (type != HPRE_V2_ALG_TYPE && type != HPRE_V3_ECC_ALG_TYPE) 480 return NULL; 481 482 /* 483 * type: 0 - RSA/DH. algorithm supported in V2, 484 * 1 - ECC algorithm in V3. 485 */ 486 ret = hisi_qm_alloc_qps_node(&hpre_devices, 1, type, node, &qp); 487 if (!ret) 488 return qp; 489 490 return NULL; 491 } 492 493 static void hpre_config_pasid(struct hisi_qm *qm) 494 { 495 u32 val1, val2; 496 497 if (qm->ver >= QM_HW_V3) 498 return; 499 500 val1 = readl_relaxed(qm->io_base + HPRE_DATA_RUSER_CFG); 501 val2 = readl_relaxed(qm->io_base + HPRE_DATA_WUSER_CFG); 502 if (qm->use_sva) { 503 val1 |= BIT(HPRE_PASID_EN_BIT); 504 val2 |= BIT(HPRE_PASID_EN_BIT); 505 } else { 506 val1 &= ~BIT(HPRE_PASID_EN_BIT); 507 val2 &= ~BIT(HPRE_PASID_EN_BIT); 508 } 509 writel_relaxed(val1, qm->io_base + HPRE_DATA_RUSER_CFG); 510 writel_relaxed(val2, qm->io_base + HPRE_DATA_WUSER_CFG); 511 } 512 513 static int hpre_cfg_by_dsm(struct hisi_qm *qm) 514 { 515 struct device *dev = &qm->pdev->dev; 516 union acpi_object *obj; 517 guid_t guid; 518 519 if (guid_parse("b06b81ab-0134-4a45-9b0c-483447b95fa7", &guid)) { 520 dev_err(dev, "Hpre GUID failed\n"); 521 return -EINVAL; 522 } 523 524 /* Switch over to MSI handling due to non-standard PCI implementation */ 525 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &guid, 526 0, HPRE_VIA_MSI_DSM, NULL); 527 if (!obj) { 528 dev_err(dev, "ACPI handle failed!\n"); 529 return -EIO; 530 } 531 532 ACPI_FREE(obj); 533 534 return 0; 535 } 536 537 static int hpre_set_cluster(struct hisi_qm *qm) 538 { 539 u32 cluster_core_mask = hpre_cluster_core_mask(qm); 540 u8 clusters_num = hpre_cluster_num(qm); 541 struct device *dev = &qm->pdev->dev; 542 unsigned long offset; 543 u32 val = 0; 544 int ret, i; 545 546 for (i = 0; i < clusters_num; i++) { 547 offset = i * HPRE_CLSTR_ADDR_INTRVL; 548 549 /* clusters initiating */ 550 writel(cluster_core_mask, 551 qm->io_base + offset + HPRE_CORE_ENB); 552 writel(0x1, qm->io_base + offset + HPRE_CORE_INI_CFG); 553 ret = readl_relaxed_poll_timeout(qm->io_base + offset + 554 HPRE_CORE_INI_STATUS, val, 555 ((val & cluster_core_mask) == 556 cluster_core_mask), 557 HPRE_REG_RD_INTVRL_US, 558 HPRE_REG_RD_TMOUT_US); 559 if (ret) { 560 dev_err(dev, 561 "cluster %d int st status timeout!\n", i); 562 return -ETIMEDOUT; 563 } 564 } 565 566 return 0; 567 } 568 569 /* 570 * For Kunpeng 920, we should disable FLR triggered by hardware (BME/PM/SRIOV). 571 * Or it may stay in D3 state when we bind and unbind hpre quickly, 572 * as it does FLR triggered by hardware. 573 */ 574 static void disable_flr_of_bme(struct hisi_qm *qm) 575 { 576 u32 val; 577 578 val = readl(qm->io_base + QM_PEH_AXUSER_CFG); 579 val &= ~(HPRE_QM_BME_FLR | HPRE_QM_SRIOV_FLR); 580 val |= HPRE_QM_PM_FLR; 581 writel(val, qm->io_base + QM_PEH_AXUSER_CFG); 582 writel(PEH_AXUSER_CFG_ENABLE, qm->io_base + QM_PEH_AXUSER_CFG_ENABLE); 583 } 584 585 static void hpre_open_sva_prefetch(struct hisi_qm *qm) 586 { 587 u32 val; 588 int ret; 589 590 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps)) 591 return; 592 593 /* Enable prefetch */ 594 val = readl_relaxed(qm->io_base + HPRE_PREFETCH_CFG); 595 val &= HPRE_PREFETCH_ENABLE; 596 writel(val, qm->io_base + HPRE_PREFETCH_CFG); 597 598 ret = readl_relaxed_poll_timeout(qm->io_base + HPRE_PREFETCH_CFG, 599 val, !(val & HPRE_PREFETCH_DISABLE), 600 HPRE_REG_RD_INTVRL_US, 601 HPRE_REG_RD_TMOUT_US); 602 if (ret) 603 pci_err(qm->pdev, "failed to open sva prefetch\n"); 604 } 605 606 static void hpre_close_sva_prefetch(struct hisi_qm *qm) 607 { 608 u32 val; 609 int ret; 610 611 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps)) 612 return; 613 614 val = readl_relaxed(qm->io_base + HPRE_PREFETCH_CFG); 615 val |= HPRE_PREFETCH_DISABLE; 616 writel(val, qm->io_base + HPRE_PREFETCH_CFG); 617 618 ret = readl_relaxed_poll_timeout(qm->io_base + HPRE_SVA_PREFTCH_DFX, 619 val, !(val & HPRE_SVA_DISABLE_READY), 620 HPRE_REG_RD_INTVRL_US, 621 HPRE_REG_RD_TMOUT_US); 622 if (ret) 623 pci_err(qm->pdev, "failed to close sva prefetch\n"); 624 } 625 626 static void hpre_enable_clock_gate(struct hisi_qm *qm) 627 { 628 u32 val; 629 630 if (qm->ver < QM_HW_V3) 631 return; 632 633 val = readl(qm->io_base + HPRE_CLKGATE_CTL); 634 val |= HPRE_CLKGATE_CTL_EN; 635 writel(val, qm->io_base + HPRE_CLKGATE_CTL); 636 637 val = readl(qm->io_base + HPRE_PEH_CFG_AUTO_GATE); 638 val |= HPRE_PEH_CFG_AUTO_GATE_EN; 639 writel(val, qm->io_base + HPRE_PEH_CFG_AUTO_GATE); 640 641 val = readl(qm->io_base + HPRE_CLUSTER_DYN_CTL); 642 val |= HPRE_CLUSTER_DYN_CTL_EN; 643 writel(val, qm->io_base + HPRE_CLUSTER_DYN_CTL); 644 645 val = readl_relaxed(qm->io_base + HPRE_CORE_SHB_CFG); 646 val |= HPRE_CORE_GATE_EN; 647 writel(val, qm->io_base + HPRE_CORE_SHB_CFG); 648 } 649 650 static void hpre_disable_clock_gate(struct hisi_qm *qm) 651 { 652 u32 val; 653 654 if (qm->ver < QM_HW_V3) 655 return; 656 657 val = readl(qm->io_base + HPRE_CLKGATE_CTL); 658 val &= ~HPRE_CLKGATE_CTL_EN; 659 writel(val, qm->io_base + HPRE_CLKGATE_CTL); 660 661 val = readl(qm->io_base + HPRE_PEH_CFG_AUTO_GATE); 662 val &= ~HPRE_PEH_CFG_AUTO_GATE_EN; 663 writel(val, qm->io_base + HPRE_PEH_CFG_AUTO_GATE); 664 665 val = readl(qm->io_base + HPRE_CLUSTER_DYN_CTL); 666 val &= ~HPRE_CLUSTER_DYN_CTL_EN; 667 writel(val, qm->io_base + HPRE_CLUSTER_DYN_CTL); 668 669 val = readl_relaxed(qm->io_base + HPRE_CORE_SHB_CFG); 670 val &= ~HPRE_CORE_GATE_EN; 671 writel(val, qm->io_base + HPRE_CORE_SHB_CFG); 672 } 673 674 static int hpre_set_user_domain_and_cache(struct hisi_qm *qm) 675 { 676 struct device *dev = &qm->pdev->dev; 677 u32 val; 678 int ret; 679 680 /* disabel dynamic clock gate before sram init */ 681 hpre_disable_clock_gate(qm); 682 683 writel(HPRE_QM_USR_CFG_MASK, qm->io_base + QM_ARUSER_M_CFG_ENABLE); 684 writel(HPRE_QM_USR_CFG_MASK, qm->io_base + QM_AWUSER_M_CFG_ENABLE); 685 writel_relaxed(HPRE_QM_AXI_CFG_MASK, qm->io_base + QM_AXI_M_CFG); 686 687 /* HPRE need more time, we close this interrupt */ 688 val = readl_relaxed(qm->io_base + HPRE_QM_ABNML_INT_MASK); 689 val |= BIT(HPRE_TIMEOUT_ABNML_BIT); 690 writel_relaxed(val, qm->io_base + HPRE_QM_ABNML_INT_MASK); 691 692 if (qm->ver >= QM_HW_V3) 693 writel(HPRE_RSA_ENB | HPRE_ECC_ENB, 694 qm->io_base + HPRE_TYPES_ENB); 695 else 696 writel(HPRE_RSA_ENB, qm->io_base + HPRE_TYPES_ENB); 697 698 writel(HPRE_QM_VFG_AX_MASK, qm->io_base + HPRE_VFG_AXCACHE); 699 writel(0x0, qm->io_base + HPRE_BD_ENDIAN); 700 writel(0x0, qm->io_base + HPRE_INT_MASK); 701 writel(0x0, qm->io_base + HPRE_POISON_BYPASS); 702 writel(0x0, qm->io_base + HPRE_COMM_CNT_CLR_CE); 703 writel(0x0, qm->io_base + HPRE_ECC_BYPASS); 704 705 writel(HPRE_BD_USR_MASK, qm->io_base + HPRE_BD_ARUSR_CFG); 706 writel(HPRE_BD_USR_MASK, qm->io_base + HPRE_BD_AWUSR_CFG); 707 writel(0x1, qm->io_base + HPRE_RDCHN_INI_CFG); 708 ret = readl_relaxed_poll_timeout(qm->io_base + HPRE_RDCHN_INI_ST, val, 709 val & BIT(0), 710 HPRE_REG_RD_INTVRL_US, 711 HPRE_REG_RD_TMOUT_US); 712 if (ret) { 713 dev_err(dev, "read rd channel timeout fail!\n"); 714 return -ETIMEDOUT; 715 } 716 717 ret = hpre_set_cluster(qm); 718 if (ret) 719 return -ETIMEDOUT; 720 721 /* This setting is only needed by Kunpeng 920. */ 722 if (qm->ver == QM_HW_V2) { 723 ret = hpre_cfg_by_dsm(qm); 724 if (ret) 725 return ret; 726 727 disable_flr_of_bme(qm); 728 } 729 730 /* Config data buffer pasid needed by Kunpeng 920 */ 731 hpre_config_pasid(qm); 732 733 hpre_enable_clock_gate(qm); 734 735 return ret; 736 } 737 738 static void hpre_cnt_regs_clear(struct hisi_qm *qm) 739 { 740 u8 clusters_num = hpre_cluster_num(qm); 741 unsigned long offset; 742 int i; 743 744 /* clear clusterX/cluster_ctrl */ 745 for (i = 0; i < clusters_num; i++) { 746 offset = HPRE_CLSTR_BASE + i * HPRE_CLSTR_ADDR_INTRVL; 747 writel(0x0, qm->io_base + offset + HPRE_CLUSTER_INQURY); 748 } 749 750 /* clear rdclr_en */ 751 writel(0x0, qm->io_base + HPRE_CTRL_CNT_CLR_CE); 752 753 hisi_qm_debug_regs_clear(qm); 754 } 755 756 static void hpre_master_ooo_ctrl(struct hisi_qm *qm, bool enable) 757 { 758 u32 val1, val2; 759 760 val1 = readl(qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB); 761 if (enable) { 762 val1 |= HPRE_AM_OOO_SHUTDOWN_ENABLE; 763 val2 = hisi_qm_get_hw_info(qm, hpre_basic_info, 764 HPRE_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 765 } else { 766 val1 &= ~HPRE_AM_OOO_SHUTDOWN_ENABLE; 767 val2 = 0x0; 768 } 769 770 if (qm->ver > QM_HW_V2) 771 writel(val2, qm->io_base + HPRE_OOO_SHUTDOWN_SEL); 772 773 writel(val1, qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB); 774 } 775 776 static void hpre_hw_error_disable(struct hisi_qm *qm) 777 { 778 u32 ce, nfe; 779 780 ce = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_CE_MASK_CAP, qm->cap_ver); 781 nfe = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_NFE_MASK_CAP, qm->cap_ver); 782 783 /* disable hpre hw error interrupts */ 784 writel(ce | nfe | HPRE_HAC_RAS_FE_ENABLE, qm->io_base + HPRE_INT_MASK); 785 /* disable HPRE block master OOO when nfe occurs on Kunpeng930 */ 786 hpre_master_ooo_ctrl(qm, false); 787 } 788 789 static void hpre_hw_error_enable(struct hisi_qm *qm) 790 { 791 u32 ce, nfe; 792 793 ce = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_CE_MASK_CAP, qm->cap_ver); 794 nfe = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_NFE_MASK_CAP, qm->cap_ver); 795 796 /* clear HPRE hw error source if having */ 797 writel(ce | nfe | HPRE_HAC_RAS_FE_ENABLE, qm->io_base + HPRE_HAC_SOURCE_INT); 798 799 /* configure error type */ 800 writel(ce, qm->io_base + HPRE_RAS_CE_ENB); 801 writel(nfe, qm->io_base + HPRE_RAS_NFE_ENB); 802 writel(HPRE_HAC_RAS_FE_ENABLE, qm->io_base + HPRE_RAS_FE_ENB); 803 804 /* enable HPRE block master OOO when nfe occurs on Kunpeng930 */ 805 hpre_master_ooo_ctrl(qm, true); 806 807 /* enable hpre hw error interrupts */ 808 writel(HPRE_CORE_INT_ENABLE, qm->io_base + HPRE_INT_MASK); 809 } 810 811 static inline struct hisi_qm *hpre_file_to_qm(struct hpre_debugfs_file *file) 812 { 813 struct hpre *hpre = container_of(file->debug, struct hpre, debug); 814 815 return &hpre->qm; 816 } 817 818 static u32 hpre_clear_enable_read(struct hpre_debugfs_file *file) 819 { 820 struct hisi_qm *qm = hpre_file_to_qm(file); 821 822 return readl(qm->io_base + HPRE_CTRL_CNT_CLR_CE) & 823 HPRE_CTRL_CNT_CLR_CE_BIT; 824 } 825 826 static int hpre_clear_enable_write(struct hpre_debugfs_file *file, u32 val) 827 { 828 struct hisi_qm *qm = hpre_file_to_qm(file); 829 u32 tmp; 830 831 if (val != 1 && val != 0) 832 return -EINVAL; 833 834 tmp = (readl(qm->io_base + HPRE_CTRL_CNT_CLR_CE) & 835 ~HPRE_CTRL_CNT_CLR_CE_BIT) | val; 836 writel(tmp, qm->io_base + HPRE_CTRL_CNT_CLR_CE); 837 838 return 0; 839 } 840 841 static u32 hpre_cluster_inqry_read(struct hpre_debugfs_file *file) 842 { 843 struct hisi_qm *qm = hpre_file_to_qm(file); 844 int cluster_index = file->index - HPRE_CLUSTER_CTRL; 845 unsigned long offset = HPRE_CLSTR_BASE + 846 cluster_index * HPRE_CLSTR_ADDR_INTRVL; 847 848 return readl(qm->io_base + offset + HPRE_CLSTR_ADDR_INQRY_RSLT); 849 } 850 851 static void hpre_cluster_inqry_write(struct hpre_debugfs_file *file, u32 val) 852 { 853 struct hisi_qm *qm = hpre_file_to_qm(file); 854 int cluster_index = file->index - HPRE_CLUSTER_CTRL; 855 unsigned long offset = HPRE_CLSTR_BASE + cluster_index * 856 HPRE_CLSTR_ADDR_INTRVL; 857 858 writel(val, qm->io_base + offset + HPRE_CLUSTER_INQURY); 859 } 860 861 static ssize_t hpre_ctrl_debug_read(struct file *filp, char __user *buf, 862 size_t count, loff_t *pos) 863 { 864 struct hpre_debugfs_file *file = filp->private_data; 865 struct hisi_qm *qm = hpre_file_to_qm(file); 866 char tbuf[HPRE_DBGFS_VAL_MAX_LEN]; 867 u32 val; 868 int ret; 869 870 ret = hisi_qm_get_dfx_access(qm); 871 if (ret) 872 return ret; 873 874 spin_lock_irq(&file->lock); 875 switch (file->type) { 876 case HPRE_CLEAR_ENABLE: 877 val = hpre_clear_enable_read(file); 878 break; 879 case HPRE_CLUSTER_CTRL: 880 val = hpre_cluster_inqry_read(file); 881 break; 882 default: 883 goto err_input; 884 } 885 spin_unlock_irq(&file->lock); 886 887 hisi_qm_put_dfx_access(qm); 888 ret = snprintf(tbuf, HPRE_DBGFS_VAL_MAX_LEN, "%u\n", val); 889 return simple_read_from_buffer(buf, count, pos, tbuf, ret); 890 891 err_input: 892 spin_unlock_irq(&file->lock); 893 hisi_qm_put_dfx_access(qm); 894 return -EINVAL; 895 } 896 897 static ssize_t hpre_ctrl_debug_write(struct file *filp, const char __user *buf, 898 size_t count, loff_t *pos) 899 { 900 struct hpre_debugfs_file *file = filp->private_data; 901 struct hisi_qm *qm = hpre_file_to_qm(file); 902 char tbuf[HPRE_DBGFS_VAL_MAX_LEN]; 903 unsigned long val; 904 int len, ret; 905 906 if (*pos != 0) 907 return 0; 908 909 if (count >= HPRE_DBGFS_VAL_MAX_LEN) 910 return -ENOSPC; 911 912 len = simple_write_to_buffer(tbuf, HPRE_DBGFS_VAL_MAX_LEN - 1, 913 pos, buf, count); 914 if (len < 0) 915 return len; 916 917 tbuf[len] = '\0'; 918 if (kstrtoul(tbuf, 0, &val)) 919 return -EFAULT; 920 921 ret = hisi_qm_get_dfx_access(qm); 922 if (ret) 923 return ret; 924 925 spin_lock_irq(&file->lock); 926 switch (file->type) { 927 case HPRE_CLEAR_ENABLE: 928 ret = hpre_clear_enable_write(file, val); 929 if (ret) 930 goto err_input; 931 break; 932 case HPRE_CLUSTER_CTRL: 933 hpre_cluster_inqry_write(file, val); 934 break; 935 default: 936 ret = -EINVAL; 937 goto err_input; 938 } 939 940 ret = count; 941 942 err_input: 943 spin_unlock_irq(&file->lock); 944 hisi_qm_put_dfx_access(qm); 945 return ret; 946 } 947 948 static const struct file_operations hpre_ctrl_debug_fops = { 949 .owner = THIS_MODULE, 950 .open = simple_open, 951 .read = hpre_ctrl_debug_read, 952 .write = hpre_ctrl_debug_write, 953 }; 954 955 static int hpre_debugfs_atomic64_get(void *data, u64 *val) 956 { 957 struct hpre_dfx *dfx_item = data; 958 959 *val = atomic64_read(&dfx_item->value); 960 961 return 0; 962 } 963 964 static int hpre_debugfs_atomic64_set(void *data, u64 val) 965 { 966 struct hpre_dfx *dfx_item = data; 967 struct hpre_dfx *hpre_dfx = NULL; 968 969 if (dfx_item->type == HPRE_OVERTIME_THRHLD) { 970 hpre_dfx = dfx_item - HPRE_OVERTIME_THRHLD; 971 atomic64_set(&hpre_dfx[HPRE_OVER_THRHLD_CNT].value, 0); 972 } else if (val) { 973 return -EINVAL; 974 } 975 976 atomic64_set(&dfx_item->value, val); 977 978 return 0; 979 } 980 981 DEFINE_DEBUGFS_ATTRIBUTE(hpre_atomic64_ops, hpre_debugfs_atomic64_get, 982 hpre_debugfs_atomic64_set, "%llu\n"); 983 984 static int hpre_create_debugfs_file(struct hisi_qm *qm, struct dentry *dir, 985 enum hpre_ctrl_dbgfs_file type, int indx) 986 { 987 struct hpre *hpre = container_of(qm, struct hpre, qm); 988 struct hpre_debug *dbg = &hpre->debug; 989 struct dentry *file_dir; 990 991 if (dir) 992 file_dir = dir; 993 else 994 file_dir = qm->debug.debug_root; 995 996 if (type >= HPRE_DEBUG_FILE_NUM) 997 return -EINVAL; 998 999 spin_lock_init(&dbg->files[indx].lock); 1000 dbg->files[indx].debug = dbg; 1001 dbg->files[indx].type = type; 1002 dbg->files[indx].index = indx; 1003 debugfs_create_file(hpre_debug_file_name[type], 0600, file_dir, 1004 dbg->files + indx, &hpre_ctrl_debug_fops); 1005 1006 return 0; 1007 } 1008 1009 static int hpre_pf_comm_regs_debugfs_init(struct hisi_qm *qm) 1010 { 1011 struct device *dev = &qm->pdev->dev; 1012 struct debugfs_regset32 *regset; 1013 1014 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); 1015 if (!regset) 1016 return -ENOMEM; 1017 1018 regset->regs = hpre_com_dfx_regs; 1019 regset->nregs = ARRAY_SIZE(hpre_com_dfx_regs); 1020 regset->base = qm->io_base; 1021 regset->dev = dev; 1022 1023 debugfs_create_file("regs", 0444, qm->debug.debug_root, 1024 regset, &hpre_com_regs_fops); 1025 1026 return 0; 1027 } 1028 1029 static int hpre_cluster_debugfs_init(struct hisi_qm *qm) 1030 { 1031 u8 clusters_num = hpre_cluster_num(qm); 1032 struct device *dev = &qm->pdev->dev; 1033 char buf[HPRE_DBGFS_VAL_MAX_LEN]; 1034 struct debugfs_regset32 *regset; 1035 struct dentry *tmp_d; 1036 int i, ret; 1037 1038 for (i = 0; i < clusters_num; i++) { 1039 ret = snprintf(buf, HPRE_DBGFS_VAL_MAX_LEN, "cluster%d", i); 1040 if (ret >= HPRE_DBGFS_VAL_MAX_LEN) 1041 return -EINVAL; 1042 tmp_d = debugfs_create_dir(buf, qm->debug.debug_root); 1043 1044 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); 1045 if (!regset) 1046 return -ENOMEM; 1047 1048 regset->regs = hpre_cluster_dfx_regs; 1049 regset->nregs = ARRAY_SIZE(hpre_cluster_dfx_regs); 1050 regset->base = qm->io_base + hpre_cluster_offsets[i]; 1051 regset->dev = dev; 1052 1053 debugfs_create_file("regs", 0444, tmp_d, regset, 1054 &hpre_cluster_regs_fops); 1055 ret = hpre_create_debugfs_file(qm, tmp_d, HPRE_CLUSTER_CTRL, 1056 i + HPRE_CLUSTER_CTRL); 1057 if (ret) 1058 return ret; 1059 } 1060 1061 return 0; 1062 } 1063 1064 static int hpre_ctrl_debug_init(struct hisi_qm *qm) 1065 { 1066 int ret; 1067 1068 ret = hpre_create_debugfs_file(qm, NULL, HPRE_CLEAR_ENABLE, 1069 HPRE_CLEAR_ENABLE); 1070 if (ret) 1071 return ret; 1072 1073 ret = hpre_pf_comm_regs_debugfs_init(qm); 1074 if (ret) 1075 return ret; 1076 1077 return hpre_cluster_debugfs_init(qm); 1078 } 1079 1080 static void hpre_dfx_debug_init(struct hisi_qm *qm) 1081 { 1082 struct dfx_diff_registers *hpre_regs = qm->debug.acc_diff_regs; 1083 struct hpre *hpre = container_of(qm, struct hpre, qm); 1084 struct hpre_dfx *dfx = hpre->debug.dfx; 1085 struct dentry *parent; 1086 int i; 1087 1088 parent = debugfs_create_dir("hpre_dfx", qm->debug.debug_root); 1089 for (i = 0; i < HPRE_DFX_FILE_NUM; i++) { 1090 dfx[i].type = i; 1091 debugfs_create_file(hpre_dfx_files[i], 0644, parent, &dfx[i], 1092 &hpre_atomic64_ops); 1093 } 1094 1095 if (qm->fun_type == QM_HW_PF && hpre_regs) 1096 debugfs_create_file("diff_regs", 0444, parent, 1097 qm, &hpre_diff_regs_fops); 1098 } 1099 1100 static int hpre_debugfs_init(struct hisi_qm *qm) 1101 { 1102 struct device *dev = &qm->pdev->dev; 1103 int ret; 1104 1105 qm->debug.debug_root = debugfs_create_dir(dev_name(dev), 1106 hpre_debugfs_root); 1107 1108 qm->debug.sqe_mask_offset = HPRE_SQE_MASK_OFFSET; 1109 qm->debug.sqe_mask_len = HPRE_SQE_MASK_LEN; 1110 ret = hisi_qm_regs_debugfs_init(qm, hpre_diff_regs, ARRAY_SIZE(hpre_diff_regs)); 1111 if (ret) { 1112 dev_warn(dev, "Failed to init HPRE diff regs!\n"); 1113 goto debugfs_remove; 1114 } 1115 1116 hisi_qm_debug_init(qm); 1117 1118 if (qm->pdev->device == PCI_DEVICE_ID_HUAWEI_HPRE_PF) { 1119 ret = hpre_ctrl_debug_init(qm); 1120 if (ret) 1121 goto failed_to_create; 1122 } 1123 1124 hpre_dfx_debug_init(qm); 1125 1126 return 0; 1127 1128 failed_to_create: 1129 hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(hpre_diff_regs)); 1130 debugfs_remove: 1131 debugfs_remove_recursive(qm->debug.debug_root); 1132 return ret; 1133 } 1134 1135 static void hpre_debugfs_exit(struct hisi_qm *qm) 1136 { 1137 hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(hpre_diff_regs)); 1138 1139 debugfs_remove_recursive(qm->debug.debug_root); 1140 } 1141 1142 static int hpre_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) 1143 { 1144 int ret; 1145 1146 if (pdev->revision == QM_HW_V1) { 1147 pci_warn(pdev, "HPRE version 1 is not supported!\n"); 1148 return -EINVAL; 1149 } 1150 1151 qm->mode = uacce_mode; 1152 qm->pdev = pdev; 1153 qm->ver = pdev->revision; 1154 qm->sqe_size = HPRE_SQE_SIZE; 1155 qm->dev_name = hpre_name; 1156 1157 qm->fun_type = (pdev->device == PCI_DEVICE_ID_HUAWEI_HPRE_PF) ? 1158 QM_HW_PF : QM_HW_VF; 1159 if (qm->fun_type == QM_HW_PF) { 1160 qm->qp_base = HPRE_PF_DEF_Q_BASE; 1161 qm->qp_num = pf_q_num; 1162 qm->debug.curr_qm_qp_num = pf_q_num; 1163 qm->qm_list = &hpre_devices; 1164 if (pf_q_num_flag) 1165 set_bit(QM_MODULE_PARAM, &qm->misc_ctl); 1166 } 1167 1168 ret = hisi_qm_init(qm); 1169 if (ret) { 1170 pci_err(pdev, "Failed to init hpre qm configures!\n"); 1171 return ret; 1172 } 1173 1174 ret = hpre_set_qm_algs(qm); 1175 if (ret) { 1176 pci_err(pdev, "Failed to set hpre algs!\n"); 1177 hisi_qm_uninit(qm); 1178 } 1179 1180 return ret; 1181 } 1182 1183 static int hpre_show_last_regs_init(struct hisi_qm *qm) 1184 { 1185 int cluster_dfx_regs_num = ARRAY_SIZE(hpre_cluster_dfx_regs); 1186 int com_dfx_regs_num = ARRAY_SIZE(hpre_com_dfx_regs); 1187 u8 clusters_num = hpre_cluster_num(qm); 1188 struct qm_debug *debug = &qm->debug; 1189 void __iomem *io_base; 1190 int i, j, idx; 1191 1192 debug->last_words = kcalloc(cluster_dfx_regs_num * clusters_num + 1193 com_dfx_regs_num, sizeof(unsigned int), GFP_KERNEL); 1194 if (!debug->last_words) 1195 return -ENOMEM; 1196 1197 for (i = 0; i < com_dfx_regs_num; i++) 1198 debug->last_words[i] = readl_relaxed(qm->io_base + 1199 hpre_com_dfx_regs[i].offset); 1200 1201 for (i = 0; i < clusters_num; i++) { 1202 io_base = qm->io_base + hpre_cluster_offsets[i]; 1203 for (j = 0; j < cluster_dfx_regs_num; j++) { 1204 idx = com_dfx_regs_num + i * cluster_dfx_regs_num + j; 1205 debug->last_words[idx] = readl_relaxed( 1206 io_base + hpre_cluster_dfx_regs[j].offset); 1207 } 1208 } 1209 1210 return 0; 1211 } 1212 1213 static void hpre_show_last_regs_uninit(struct hisi_qm *qm) 1214 { 1215 struct qm_debug *debug = &qm->debug; 1216 1217 if (qm->fun_type == QM_HW_VF || !debug->last_words) 1218 return; 1219 1220 kfree(debug->last_words); 1221 debug->last_words = NULL; 1222 } 1223 1224 static void hpre_show_last_dfx_regs(struct hisi_qm *qm) 1225 { 1226 int cluster_dfx_regs_num = ARRAY_SIZE(hpre_cluster_dfx_regs); 1227 int com_dfx_regs_num = ARRAY_SIZE(hpre_com_dfx_regs); 1228 u8 clusters_num = hpre_cluster_num(qm); 1229 struct qm_debug *debug = &qm->debug; 1230 struct pci_dev *pdev = qm->pdev; 1231 void __iomem *io_base; 1232 int i, j, idx; 1233 u32 val; 1234 1235 if (qm->fun_type == QM_HW_VF || !debug->last_words) 1236 return; 1237 1238 /* dumps last word of the debugging registers during controller reset */ 1239 for (i = 0; i < com_dfx_regs_num; i++) { 1240 val = readl_relaxed(qm->io_base + hpre_com_dfx_regs[i].offset); 1241 if (debug->last_words[i] != val) 1242 pci_info(pdev, "Common_core:%s \t= 0x%08x => 0x%08x\n", 1243 hpre_com_dfx_regs[i].name, debug->last_words[i], val); 1244 } 1245 1246 for (i = 0; i < clusters_num; i++) { 1247 io_base = qm->io_base + hpre_cluster_offsets[i]; 1248 for (j = 0; j < cluster_dfx_regs_num; j++) { 1249 val = readl_relaxed(io_base + 1250 hpre_cluster_dfx_regs[j].offset); 1251 idx = com_dfx_regs_num + i * cluster_dfx_regs_num + j; 1252 if (debug->last_words[idx] != val) 1253 pci_info(pdev, "cluster-%d:%s \t= 0x%08x => 0x%08x\n", 1254 i, hpre_cluster_dfx_regs[j].name, debug->last_words[idx], val); 1255 } 1256 } 1257 } 1258 1259 static void hpre_log_hw_error(struct hisi_qm *qm, u32 err_sts) 1260 { 1261 const struct hpre_hw_error *err = hpre_hw_errors; 1262 struct device *dev = &qm->pdev->dev; 1263 1264 while (err->msg) { 1265 if (err->int_msk & err_sts) 1266 dev_warn(dev, "%s [error status=0x%x] found\n", 1267 err->msg, err->int_msk); 1268 err++; 1269 } 1270 } 1271 1272 static u32 hpre_get_hw_err_status(struct hisi_qm *qm) 1273 { 1274 return readl(qm->io_base + HPRE_INT_STATUS); 1275 } 1276 1277 static void hpre_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts) 1278 { 1279 u32 nfe; 1280 1281 writel(err_sts, qm->io_base + HPRE_HAC_SOURCE_INT); 1282 nfe = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_NFE_MASK_CAP, qm->cap_ver); 1283 writel(nfe, qm->io_base + HPRE_RAS_NFE_ENB); 1284 } 1285 1286 static void hpre_open_axi_master_ooo(struct hisi_qm *qm) 1287 { 1288 u32 value; 1289 1290 value = readl(qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB); 1291 writel(value & ~HPRE_AM_OOO_SHUTDOWN_ENABLE, 1292 qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB); 1293 writel(value | HPRE_AM_OOO_SHUTDOWN_ENABLE, 1294 qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB); 1295 } 1296 1297 static void hpre_err_info_init(struct hisi_qm *qm) 1298 { 1299 struct hisi_qm_err_info *err_info = &qm->err_info; 1300 1301 err_info->fe = HPRE_HAC_RAS_FE_ENABLE; 1302 err_info->ce = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_QM_CE_MASK_CAP, qm->cap_ver); 1303 err_info->nfe = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_QM_NFE_MASK_CAP, qm->cap_ver); 1304 err_info->ecc_2bits_mask = HPRE_CORE_ECC_2BIT_ERR | HPRE_OOO_ECC_2BIT_ERR; 1305 err_info->dev_shutdown_mask = hisi_qm_get_hw_info(qm, hpre_basic_info, 1306 HPRE_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 1307 err_info->qm_shutdown_mask = hisi_qm_get_hw_info(qm, hpre_basic_info, 1308 HPRE_QM_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 1309 err_info->qm_reset_mask = hisi_qm_get_hw_info(qm, hpre_basic_info, 1310 HPRE_QM_RESET_MASK_CAP, qm->cap_ver); 1311 err_info->dev_reset_mask = hisi_qm_get_hw_info(qm, hpre_basic_info, 1312 HPRE_RESET_MASK_CAP, qm->cap_ver); 1313 err_info->msi_wr_port = HPRE_WR_MSI_PORT; 1314 err_info->acpi_rst = "HRST"; 1315 } 1316 1317 static const struct hisi_qm_err_ini hpre_err_ini = { 1318 .hw_init = hpre_set_user_domain_and_cache, 1319 .hw_err_enable = hpre_hw_error_enable, 1320 .hw_err_disable = hpre_hw_error_disable, 1321 .get_dev_hw_err_status = hpre_get_hw_err_status, 1322 .clear_dev_hw_err_status = hpre_clear_hw_err_status, 1323 .log_dev_hw_err = hpre_log_hw_error, 1324 .open_axi_master_ooo = hpre_open_axi_master_ooo, 1325 .open_sva_prefetch = hpre_open_sva_prefetch, 1326 .close_sva_prefetch = hpre_close_sva_prefetch, 1327 .show_last_dfx_regs = hpre_show_last_dfx_regs, 1328 .err_info_init = hpre_err_info_init, 1329 }; 1330 1331 static int hpre_pf_probe_init(struct hpre *hpre) 1332 { 1333 struct hisi_qm *qm = &hpre->qm; 1334 int ret; 1335 1336 ret = hpre_set_user_domain_and_cache(qm); 1337 if (ret) 1338 return ret; 1339 1340 hpre_open_sva_prefetch(qm); 1341 1342 qm->err_ini = &hpre_err_ini; 1343 qm->err_ini->err_info_init(qm); 1344 hisi_qm_dev_err_init(qm); 1345 ret = hpre_show_last_regs_init(qm); 1346 if (ret) 1347 pci_err(qm->pdev, "Failed to init last word regs!\n"); 1348 1349 return ret; 1350 } 1351 1352 static int hpre_probe_init(struct hpre *hpre) 1353 { 1354 u32 type_rate = HPRE_SHAPER_TYPE_RATE; 1355 struct hisi_qm *qm = &hpre->qm; 1356 int ret; 1357 1358 if (qm->fun_type == QM_HW_PF) { 1359 ret = hpre_pf_probe_init(hpre); 1360 if (ret) 1361 return ret; 1362 /* Enable shaper type 0 */ 1363 if (qm->ver >= QM_HW_V3) { 1364 type_rate |= QM_SHAPER_ENABLE; 1365 qm->type_rate = type_rate; 1366 } 1367 } 1368 1369 return 0; 1370 } 1371 1372 static int hpre_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1373 { 1374 struct hisi_qm *qm; 1375 struct hpre *hpre; 1376 int ret; 1377 1378 hpre = devm_kzalloc(&pdev->dev, sizeof(*hpre), GFP_KERNEL); 1379 if (!hpre) 1380 return -ENOMEM; 1381 1382 qm = &hpre->qm; 1383 ret = hpre_qm_init(qm, pdev); 1384 if (ret) { 1385 pci_err(pdev, "Failed to init HPRE QM (%d)!\n", ret); 1386 return ret; 1387 } 1388 1389 ret = hpre_probe_init(hpre); 1390 if (ret) { 1391 pci_err(pdev, "Failed to probe (%d)!\n", ret); 1392 goto err_with_qm_init; 1393 } 1394 1395 ret = hisi_qm_start(qm); 1396 if (ret) 1397 goto err_with_err_init; 1398 1399 ret = hpre_debugfs_init(qm); 1400 if (ret) 1401 dev_warn(&pdev->dev, "init debugfs fail!\n"); 1402 1403 hisi_qm_add_list(qm, &hpre_devices); 1404 ret = hisi_qm_alg_register(qm, &hpre_devices, HPRE_CTX_Q_NUM_DEF); 1405 if (ret < 0) { 1406 pci_err(pdev, "fail to register algs to crypto!\n"); 1407 goto err_qm_del_list; 1408 } 1409 1410 if (qm->uacce) { 1411 ret = uacce_register(qm->uacce); 1412 if (ret) { 1413 pci_err(pdev, "failed to register uacce (%d)!\n", ret); 1414 goto err_with_alg_register; 1415 } 1416 } 1417 1418 if (qm->fun_type == QM_HW_PF && vfs_num) { 1419 ret = hisi_qm_sriov_enable(pdev, vfs_num); 1420 if (ret < 0) 1421 goto err_with_alg_register; 1422 } 1423 1424 hisi_qm_pm_init(qm); 1425 1426 return 0; 1427 1428 err_with_alg_register: 1429 hisi_qm_alg_unregister(qm, &hpre_devices, HPRE_CTX_Q_NUM_DEF); 1430 1431 err_qm_del_list: 1432 hisi_qm_del_list(qm, &hpre_devices); 1433 hpre_debugfs_exit(qm); 1434 hisi_qm_stop(qm, QM_NORMAL); 1435 1436 err_with_err_init: 1437 hpre_show_last_regs_uninit(qm); 1438 hisi_qm_dev_err_uninit(qm); 1439 1440 err_with_qm_init: 1441 hisi_qm_uninit(qm); 1442 1443 return ret; 1444 } 1445 1446 static void hpre_remove(struct pci_dev *pdev) 1447 { 1448 struct hisi_qm *qm = pci_get_drvdata(pdev); 1449 1450 hisi_qm_pm_uninit(qm); 1451 hisi_qm_wait_task_finish(qm, &hpre_devices); 1452 hisi_qm_alg_unregister(qm, &hpre_devices, HPRE_CTX_Q_NUM_DEF); 1453 hisi_qm_del_list(qm, &hpre_devices); 1454 if (qm->fun_type == QM_HW_PF && qm->vfs_num) 1455 hisi_qm_sriov_disable(pdev, true); 1456 1457 hpre_debugfs_exit(qm); 1458 hisi_qm_stop(qm, QM_NORMAL); 1459 1460 if (qm->fun_type == QM_HW_PF) { 1461 hpre_cnt_regs_clear(qm); 1462 qm->debug.curr_qm_qp_num = 0; 1463 hpre_show_last_regs_uninit(qm); 1464 hisi_qm_dev_err_uninit(qm); 1465 } 1466 1467 hisi_qm_uninit(qm); 1468 } 1469 1470 static const struct dev_pm_ops hpre_pm_ops = { 1471 SET_RUNTIME_PM_OPS(hisi_qm_suspend, hisi_qm_resume, NULL) 1472 }; 1473 1474 static const struct pci_error_handlers hpre_err_handler = { 1475 .error_detected = hisi_qm_dev_err_detected, 1476 .slot_reset = hisi_qm_dev_slot_reset, 1477 .reset_prepare = hisi_qm_reset_prepare, 1478 .reset_done = hisi_qm_reset_done, 1479 }; 1480 1481 static struct pci_driver hpre_pci_driver = { 1482 .name = hpre_name, 1483 .id_table = hpre_dev_ids, 1484 .probe = hpre_probe, 1485 .remove = hpre_remove, 1486 .sriov_configure = IS_ENABLED(CONFIG_PCI_IOV) ? 1487 hisi_qm_sriov_configure : NULL, 1488 .err_handler = &hpre_err_handler, 1489 .shutdown = hisi_qm_dev_shutdown, 1490 .driver.pm = &hpre_pm_ops, 1491 }; 1492 1493 struct pci_driver *hisi_hpre_get_pf_driver(void) 1494 { 1495 return &hpre_pci_driver; 1496 } 1497 EXPORT_SYMBOL_GPL(hisi_hpre_get_pf_driver); 1498 1499 static void hpre_register_debugfs(void) 1500 { 1501 if (!debugfs_initialized()) 1502 return; 1503 1504 hpre_debugfs_root = debugfs_create_dir(hpre_name, NULL); 1505 } 1506 1507 static void hpre_unregister_debugfs(void) 1508 { 1509 debugfs_remove_recursive(hpre_debugfs_root); 1510 } 1511 1512 static int __init hpre_init(void) 1513 { 1514 int ret; 1515 1516 hisi_qm_init_list(&hpre_devices); 1517 hpre_register_debugfs(); 1518 1519 ret = pci_register_driver(&hpre_pci_driver); 1520 if (ret) { 1521 hpre_unregister_debugfs(); 1522 pr_err("hpre: can't register hisi hpre driver.\n"); 1523 } 1524 1525 return ret; 1526 } 1527 1528 static void __exit hpre_exit(void) 1529 { 1530 pci_unregister_driver(&hpre_pci_driver); 1531 hpre_unregister_debugfs(); 1532 } 1533 1534 module_init(hpre_init); 1535 module_exit(hpre_exit); 1536 1537 MODULE_LICENSE("GPL v2"); 1538 MODULE_AUTHOR("Zaibo Xu <xuzaibo@huawei.com>"); 1539 MODULE_AUTHOR("Meng Yu <yumeng18@huawei.com>"); 1540 MODULE_DESCRIPTION("Driver for HiSilicon HPRE accelerator"); 1541