1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018-2019 HiSilicon Limited. */ 3 #include <linux/acpi.h> 4 #include <linux/bitops.h> 5 #include <linux/debugfs.h> 6 #include <linux/init.h> 7 #include <linux/io.h> 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/pci.h> 11 #include <linux/pm_runtime.h> 12 #include <linux/topology.h> 13 #include <linux/uacce.h> 14 #include "hpre.h" 15 16 #define HPRE_CTRL_CNT_CLR_CE_BIT BIT(0) 17 #define HPRE_CTRL_CNT_CLR_CE 0x301000 18 #define HPRE_FSM_MAX_CNT 0x301008 19 #define HPRE_VFG_AXQOS 0x30100c 20 #define HPRE_VFG_AXCACHE 0x301010 21 #define HPRE_RDCHN_INI_CFG 0x301014 22 #define HPRE_AWUSR_FP_CFG 0x301018 23 #define HPRE_BD_ENDIAN 0x301020 24 #define HPRE_ECC_BYPASS 0x301024 25 #define HPRE_RAS_WIDTH_CFG 0x301028 26 #define HPRE_POISON_BYPASS 0x30102c 27 #define HPRE_BD_ARUSR_CFG 0x301030 28 #define HPRE_BD_AWUSR_CFG 0x301034 29 #define HPRE_TYPES_ENB 0x301038 30 #define HPRE_RSA_ENB BIT(0) 31 #define HPRE_ECC_ENB BIT(1) 32 #define HPRE_DATA_RUSER_CFG 0x30103c 33 #define HPRE_DATA_WUSER_CFG 0x301040 34 #define HPRE_INT_MASK 0x301400 35 #define HPRE_INT_STATUS 0x301800 36 #define HPRE_HAC_INT_MSK 0x301400 37 #define HPRE_HAC_RAS_CE_ENB 0x301410 38 #define HPRE_HAC_RAS_NFE_ENB 0x301414 39 #define HPRE_HAC_RAS_FE_ENB 0x301418 40 #define HPRE_HAC_INT_SET 0x301500 41 #define HPRE_RNG_TIMEOUT_NUM 0x301A34 42 #define HPRE_CORE_INT_ENABLE 0 43 #define HPRE_RDCHN_INI_ST 0x301a00 44 #define HPRE_CLSTR_BASE 0x302000 45 #define HPRE_CORE_EN_OFFSET 0x04 46 #define HPRE_CORE_INI_CFG_OFFSET 0x20 47 #define HPRE_CORE_INI_STATUS_OFFSET 0x80 48 #define HPRE_CORE_HTBT_WARN_OFFSET 0x8c 49 #define HPRE_CORE_IS_SCHD_OFFSET 0x90 50 51 #define HPRE_RAS_CE_ENB 0x301410 52 #define HPRE_RAS_NFE_ENB 0x301414 53 #define HPRE_RAS_FE_ENB 0x301418 54 #define HPRE_OOO_SHUTDOWN_SEL 0x301a3c 55 #define HPRE_HAC_RAS_FE_ENABLE 0 56 57 #define HPRE_CORE_ENB (HPRE_CLSTR_BASE + HPRE_CORE_EN_OFFSET) 58 #define HPRE_CORE_INI_CFG (HPRE_CLSTR_BASE + HPRE_CORE_INI_CFG_OFFSET) 59 #define HPRE_CORE_INI_STATUS (HPRE_CLSTR_BASE + HPRE_CORE_INI_STATUS_OFFSET) 60 #define HPRE_HAC_ECC1_CNT 0x301a04 61 #define HPRE_HAC_ECC2_CNT 0x301a08 62 #define HPRE_HAC_SOURCE_INT 0x301600 63 #define HPRE_CLSTR_ADDR_INTRVL 0x1000 64 #define HPRE_CLUSTER_INQURY 0x100 65 #define HPRE_CLSTR_ADDR_INQRY_RSLT 0x104 66 #define HPRE_PASID_EN_BIT 9 67 #define HPRE_REG_RD_INTVRL_US 10 68 #define HPRE_REG_RD_TMOUT_US 1000 69 #define HPRE_DBGFS_VAL_MAX_LEN 20 70 #define PCI_DEVICE_ID_HUAWEI_HPRE_PF 0xa258 71 #define HPRE_QM_USR_CFG_MASK GENMASK(31, 1) 72 #define HPRE_QM_AXI_CFG_MASK GENMASK(15, 0) 73 #define HPRE_QM_VFG_AX_MASK GENMASK(7, 0) 74 #define HPRE_BD_USR_MASK GENMASK(1, 0) 75 #define HPRE_PREFETCH_CFG 0x301130 76 #define HPRE_SVA_PREFTCH_DFX 0x30115C 77 #define HPRE_PREFETCH_ENABLE (~(BIT(0) | BIT(30))) 78 #define HPRE_PREFETCH_DISABLE BIT(30) 79 #define HPRE_SVA_DISABLE_READY (BIT(4) | BIT(8)) 80 81 /* clock gate */ 82 #define HPRE_CLKGATE_CTL 0x301a10 83 #define HPRE_PEH_CFG_AUTO_GATE 0x301a2c 84 #define HPRE_CLUSTER_DYN_CTL 0x302010 85 #define HPRE_CORE_SHB_CFG 0x302088 86 #define HPRE_CLKGATE_CTL_EN BIT(0) 87 #define HPRE_PEH_CFG_AUTO_GATE_EN BIT(0) 88 #define HPRE_CLUSTER_DYN_CTL_EN BIT(0) 89 #define HPRE_CORE_GATE_EN (BIT(30) | BIT(31)) 90 91 #define HPRE_AM_OOO_SHUTDOWN_ENB 0x301044 92 #define HPRE_AM_OOO_SHUTDOWN_ENABLE BIT(0) 93 #define HPRE_WR_MSI_PORT BIT(2) 94 95 #define HPRE_CORE_ECC_2BIT_ERR BIT(1) 96 #define HPRE_OOO_ECC_2BIT_ERR BIT(5) 97 98 #define HPRE_QM_BME_FLR BIT(7) 99 #define HPRE_QM_PM_FLR BIT(11) 100 #define HPRE_QM_SRIOV_FLR BIT(12) 101 102 #define HPRE_SHAPER_TYPE_RATE 640 103 #define HPRE_VIA_MSI_DSM 1 104 #define HPRE_SQE_MASK_OFFSET 8 105 #define HPRE_SQE_MASK_LEN 44 106 #define HPRE_CTX_Q_NUM_DEF 1 107 108 #define HPRE_DFX_BASE 0x301000 109 #define HPRE_DFX_COMMON1 0x301400 110 #define HPRE_DFX_COMMON2 0x301A00 111 #define HPRE_DFX_CORE 0x302000 112 #define HPRE_DFX_BASE_LEN 0x55 113 #define HPRE_DFX_COMMON1_LEN 0x41 114 #define HPRE_DFX_COMMON2_LEN 0xE 115 #define HPRE_DFX_CORE_LEN 0x43 116 117 static const char hpre_name[] = "hisi_hpre"; 118 static struct dentry *hpre_debugfs_root; 119 static const struct pci_device_id hpre_dev_ids[] = { 120 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_HPRE_PF) }, 121 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_HPRE_VF) }, 122 { 0, } 123 }; 124 125 MODULE_DEVICE_TABLE(pci, hpre_dev_ids); 126 127 struct hpre_hw_error { 128 u32 int_msk; 129 const char *msg; 130 }; 131 132 static const struct qm_dev_alg hpre_dev_algs[] = { 133 { 134 .alg_msk = BIT(0), 135 .alg = "rsa\n" 136 }, { 137 .alg_msk = BIT(1), 138 .alg = "dh\n" 139 }, { 140 .alg_msk = BIT(2), 141 .alg = "ecdh\n" 142 }, { 143 .alg_msk = BIT(3), 144 .alg = "ecdsa\n" 145 }, { 146 .alg_msk = BIT(4), 147 .alg = "sm2\n" 148 }, { 149 .alg_msk = BIT(5), 150 .alg = "x25519\n" 151 }, { 152 .alg_msk = BIT(6), 153 .alg = "x448\n" 154 }, { 155 /* sentinel */ 156 } 157 }; 158 159 static struct hisi_qm_list hpre_devices = { 160 .register_to_crypto = hpre_algs_register, 161 .unregister_from_crypto = hpre_algs_unregister, 162 }; 163 164 static const char * const hpre_debug_file_name[] = { 165 [HPRE_CLEAR_ENABLE] = "rdclr_en", 166 [HPRE_CLUSTER_CTRL] = "cluster_ctrl", 167 }; 168 169 enum hpre_cap_type { 170 HPRE_QM_NFE_MASK_CAP, 171 HPRE_QM_RESET_MASK_CAP, 172 HPRE_QM_OOO_SHUTDOWN_MASK_CAP, 173 HPRE_QM_CE_MASK_CAP, 174 HPRE_NFE_MASK_CAP, 175 HPRE_RESET_MASK_CAP, 176 HPRE_OOO_SHUTDOWN_MASK_CAP, 177 HPRE_CE_MASK_CAP, 178 HPRE_CLUSTER_NUM_CAP, 179 HPRE_CORE_TYPE_NUM_CAP, 180 HPRE_CORE_NUM_CAP, 181 HPRE_CLUSTER_CORE_NUM_CAP, 182 HPRE_CORE_ENABLE_BITMAP_CAP, 183 HPRE_DRV_ALG_BITMAP_CAP, 184 HPRE_DEV_ALG_BITMAP_CAP, 185 HPRE_CORE1_ALG_BITMAP_CAP, 186 HPRE_CORE2_ALG_BITMAP_CAP, 187 HPRE_CORE3_ALG_BITMAP_CAP, 188 HPRE_CORE4_ALG_BITMAP_CAP, 189 HPRE_CORE5_ALG_BITMAP_CAP, 190 HPRE_CORE6_ALG_BITMAP_CAP, 191 HPRE_CORE7_ALG_BITMAP_CAP, 192 HPRE_CORE8_ALG_BITMAP_CAP, 193 HPRE_CORE9_ALG_BITMAP_CAP, 194 HPRE_CORE10_ALG_BITMAP_CAP 195 }; 196 197 static const struct hisi_qm_cap_info hpre_basic_info[] = { 198 {HPRE_QM_NFE_MASK_CAP, 0x3124, 0, GENMASK(31, 0), 0x0, 0x1C37, 0x7C37}, 199 {HPRE_QM_RESET_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0xC37, 0x6C37}, 200 {HPRE_QM_OOO_SHUTDOWN_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0x4, 0x6C37}, 201 {HPRE_QM_CE_MASK_CAP, 0x312C, 0, GENMASK(31, 0), 0x0, 0x8, 0x8}, 202 {HPRE_NFE_MASK_CAP, 0x3130, 0, GENMASK(31, 0), 0x0, 0x3FFFFE, 0x1FFFC3E}, 203 {HPRE_RESET_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x3FFFFE, 0xBFFC3E}, 204 {HPRE_OOO_SHUTDOWN_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x22, 0xBFFC3E}, 205 {HPRE_CE_MASK_CAP, 0x3138, 0, GENMASK(31, 0), 0x0, 0x1, 0x1}, 206 {HPRE_CLUSTER_NUM_CAP, 0x313c, 20, GENMASK(3, 0), 0x0, 0x4, 0x1}, 207 {HPRE_CORE_TYPE_NUM_CAP, 0x313c, 16, GENMASK(3, 0), 0x0, 0x2, 0x2}, 208 {HPRE_CORE_NUM_CAP, 0x313c, 8, GENMASK(7, 0), 0x0, 0x8, 0xA}, 209 {HPRE_CLUSTER_CORE_NUM_CAP, 0x313c, 0, GENMASK(7, 0), 0x0, 0x2, 0xA}, 210 {HPRE_CORE_ENABLE_BITMAP_CAP, 0x3140, 0, GENMASK(31, 0), 0x0, 0xF, 0x3FF}, 211 {HPRE_DRV_ALG_BITMAP_CAP, 0x3144, 0, GENMASK(31, 0), 0x0, 0x03, 0x27}, 212 {HPRE_DEV_ALG_BITMAP_CAP, 0x3148, 0, GENMASK(31, 0), 0x0, 0x03, 0x7F}, 213 {HPRE_CORE1_ALG_BITMAP_CAP, 0x314c, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F}, 214 {HPRE_CORE2_ALG_BITMAP_CAP, 0x3150, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F}, 215 {HPRE_CORE3_ALG_BITMAP_CAP, 0x3154, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F}, 216 {HPRE_CORE4_ALG_BITMAP_CAP, 0x3158, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F}, 217 {HPRE_CORE5_ALG_BITMAP_CAP, 0x315c, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F}, 218 {HPRE_CORE6_ALG_BITMAP_CAP, 0x3160, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F}, 219 {HPRE_CORE7_ALG_BITMAP_CAP, 0x3164, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F}, 220 {HPRE_CORE8_ALG_BITMAP_CAP, 0x3168, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F}, 221 {HPRE_CORE9_ALG_BITMAP_CAP, 0x316c, 0, GENMASK(31, 0), 0x0, 0x10, 0x10}, 222 {HPRE_CORE10_ALG_BITMAP_CAP, 0x3170, 0, GENMASK(31, 0), 0x0, 0x10, 0x10} 223 }; 224 225 enum hpre_pre_store_cap_idx { 226 HPRE_CLUSTER_NUM_CAP_IDX = 0x0, 227 HPRE_CORE_ENABLE_BITMAP_CAP_IDX, 228 HPRE_DRV_ALG_BITMAP_CAP_IDX, 229 HPRE_DEV_ALG_BITMAP_CAP_IDX, 230 }; 231 232 static const u32 hpre_pre_store_caps[] = { 233 HPRE_CLUSTER_NUM_CAP, 234 HPRE_CORE_ENABLE_BITMAP_CAP, 235 HPRE_DRV_ALG_BITMAP_CAP, 236 HPRE_DEV_ALG_BITMAP_CAP, 237 }; 238 239 static const struct hpre_hw_error hpre_hw_errors[] = { 240 { 241 .int_msk = BIT(0), 242 .msg = "core_ecc_1bit_err_int_set" 243 }, { 244 .int_msk = BIT(1), 245 .msg = "core_ecc_2bit_err_int_set" 246 }, { 247 .int_msk = BIT(2), 248 .msg = "dat_wb_poison_int_set" 249 }, { 250 .int_msk = BIT(3), 251 .msg = "dat_rd_poison_int_set" 252 }, { 253 .int_msk = BIT(4), 254 .msg = "bd_rd_poison_int_set" 255 }, { 256 .int_msk = BIT(5), 257 .msg = "ooo_ecc_2bit_err_int_set" 258 }, { 259 .int_msk = BIT(6), 260 .msg = "cluster1_shb_timeout_int_set" 261 }, { 262 .int_msk = BIT(7), 263 .msg = "cluster2_shb_timeout_int_set" 264 }, { 265 .int_msk = BIT(8), 266 .msg = "cluster3_shb_timeout_int_set" 267 }, { 268 .int_msk = BIT(9), 269 .msg = "cluster4_shb_timeout_int_set" 270 }, { 271 .int_msk = GENMASK(15, 10), 272 .msg = "ooo_rdrsp_err_int_set" 273 }, { 274 .int_msk = GENMASK(21, 16), 275 .msg = "ooo_wrrsp_err_int_set" 276 }, { 277 .int_msk = BIT(22), 278 .msg = "pt_rng_timeout_int_set" 279 }, { 280 .int_msk = BIT(23), 281 .msg = "sva_fsm_timeout_int_set" 282 }, { 283 .int_msk = BIT(24), 284 .msg = "sva_int_set" 285 }, { 286 /* sentinel */ 287 } 288 }; 289 290 static const u64 hpre_cluster_offsets[] = { 291 [HPRE_CLUSTER0] = 292 HPRE_CLSTR_BASE + HPRE_CLUSTER0 * HPRE_CLSTR_ADDR_INTRVL, 293 [HPRE_CLUSTER1] = 294 HPRE_CLSTR_BASE + HPRE_CLUSTER1 * HPRE_CLSTR_ADDR_INTRVL, 295 [HPRE_CLUSTER2] = 296 HPRE_CLSTR_BASE + HPRE_CLUSTER2 * HPRE_CLSTR_ADDR_INTRVL, 297 [HPRE_CLUSTER3] = 298 HPRE_CLSTR_BASE + HPRE_CLUSTER3 * HPRE_CLSTR_ADDR_INTRVL, 299 }; 300 301 static const struct debugfs_reg32 hpre_cluster_dfx_regs[] = { 302 {"CORES_EN_STATUS ", HPRE_CORE_EN_OFFSET}, 303 {"CORES_INI_CFG ", HPRE_CORE_INI_CFG_OFFSET}, 304 {"CORES_INI_STATUS ", HPRE_CORE_INI_STATUS_OFFSET}, 305 {"CORES_HTBT_WARN ", HPRE_CORE_HTBT_WARN_OFFSET}, 306 {"CORES_IS_SCHD ", HPRE_CORE_IS_SCHD_OFFSET}, 307 }; 308 309 static const struct debugfs_reg32 hpre_com_dfx_regs[] = { 310 {"READ_CLR_EN ", HPRE_CTRL_CNT_CLR_CE}, 311 {"AXQOS ", HPRE_VFG_AXQOS}, 312 {"AWUSR_CFG ", HPRE_AWUSR_FP_CFG}, 313 {"BD_ENDIAN ", HPRE_BD_ENDIAN}, 314 {"ECC_CHECK_CTRL ", HPRE_ECC_BYPASS}, 315 {"RAS_INT_WIDTH ", HPRE_RAS_WIDTH_CFG}, 316 {"POISON_BYPASS ", HPRE_POISON_BYPASS}, 317 {"BD_ARUSER ", HPRE_BD_ARUSR_CFG}, 318 {"BD_AWUSER ", HPRE_BD_AWUSR_CFG}, 319 {"DATA_ARUSER ", HPRE_DATA_RUSER_CFG}, 320 {"DATA_AWUSER ", HPRE_DATA_WUSER_CFG}, 321 {"INT_STATUS ", HPRE_INT_STATUS}, 322 {"INT_MASK ", HPRE_HAC_INT_MSK}, 323 {"RAS_CE_ENB ", HPRE_HAC_RAS_CE_ENB}, 324 {"RAS_NFE_ENB ", HPRE_HAC_RAS_NFE_ENB}, 325 {"RAS_FE_ENB ", HPRE_HAC_RAS_FE_ENB}, 326 {"INT_SET ", HPRE_HAC_INT_SET}, 327 {"RNG_TIMEOUT_NUM ", HPRE_RNG_TIMEOUT_NUM}, 328 }; 329 330 static const char *hpre_dfx_files[HPRE_DFX_FILE_NUM] = { 331 "send_cnt", 332 "recv_cnt", 333 "send_fail_cnt", 334 "send_busy_cnt", 335 "over_thrhld_cnt", 336 "overtime_thrhld", 337 "invalid_req_cnt" 338 }; 339 340 /* define the HPRE's dfx regs region and region length */ 341 static struct dfx_diff_registers hpre_diff_regs[] = { 342 { 343 .reg_offset = HPRE_DFX_BASE, 344 .reg_len = HPRE_DFX_BASE_LEN, 345 }, { 346 .reg_offset = HPRE_DFX_COMMON1, 347 .reg_len = HPRE_DFX_COMMON1_LEN, 348 }, { 349 .reg_offset = HPRE_DFX_COMMON2, 350 .reg_len = HPRE_DFX_COMMON2_LEN, 351 }, { 352 .reg_offset = HPRE_DFX_CORE, 353 .reg_len = HPRE_DFX_CORE_LEN, 354 }, 355 }; 356 357 static const struct hisi_qm_err_ini hpre_err_ini; 358 359 bool hpre_check_alg_support(struct hisi_qm *qm, u32 alg) 360 { 361 u32 cap_val; 362 363 cap_val = qm->cap_tables.dev_cap_table[HPRE_DRV_ALG_BITMAP_CAP_IDX].cap_val; 364 if (alg & cap_val) 365 return true; 366 367 return false; 368 } 369 370 static int hpre_diff_regs_show(struct seq_file *s, void *unused) 371 { 372 struct hisi_qm *qm = s->private; 373 374 hisi_qm_acc_diff_regs_dump(qm, s, qm->debug.acc_diff_regs, 375 ARRAY_SIZE(hpre_diff_regs)); 376 377 return 0; 378 } 379 380 DEFINE_SHOW_ATTRIBUTE(hpre_diff_regs); 381 382 static int hpre_com_regs_show(struct seq_file *s, void *unused) 383 { 384 hisi_qm_regs_dump(s, s->private); 385 386 return 0; 387 } 388 389 DEFINE_SHOW_ATTRIBUTE(hpre_com_regs); 390 391 static int hpre_cluster_regs_show(struct seq_file *s, void *unused) 392 { 393 hisi_qm_regs_dump(s, s->private); 394 395 return 0; 396 } 397 398 DEFINE_SHOW_ATTRIBUTE(hpre_cluster_regs); 399 400 static const struct kernel_param_ops hpre_uacce_mode_ops = { 401 .set = uacce_mode_set, 402 .get = param_get_int, 403 }; 404 405 /* 406 * uacce_mode = 0 means hpre only register to crypto, 407 * uacce_mode = 1 means hpre both register to crypto and uacce. 408 */ 409 static u32 uacce_mode = UACCE_MODE_NOUACCE; 410 module_param_cb(uacce_mode, &hpre_uacce_mode_ops, &uacce_mode, 0444); 411 MODULE_PARM_DESC(uacce_mode, UACCE_MODE_DESC); 412 413 static bool pf_q_num_flag; 414 static int pf_q_num_set(const char *val, const struct kernel_param *kp) 415 { 416 pf_q_num_flag = true; 417 418 return q_num_set(val, kp, PCI_DEVICE_ID_HUAWEI_HPRE_PF); 419 } 420 421 static const struct kernel_param_ops hpre_pf_q_num_ops = { 422 .set = pf_q_num_set, 423 .get = param_get_int, 424 }; 425 426 static u32 pf_q_num = HPRE_PF_DEF_Q_NUM; 427 module_param_cb(pf_q_num, &hpre_pf_q_num_ops, &pf_q_num, 0444); 428 MODULE_PARM_DESC(pf_q_num, "Number of queues in PF of CS(2-1024)"); 429 430 static const struct kernel_param_ops vfs_num_ops = { 431 .set = vfs_num_set, 432 .get = param_get_int, 433 }; 434 435 static u32 vfs_num; 436 module_param_cb(vfs_num, &vfs_num_ops, &vfs_num, 0444); 437 MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63), 0(default)"); 438 439 struct hisi_qp *hpre_create_qp(u8 type) 440 { 441 int node = cpu_to_node(raw_smp_processor_id()); 442 struct hisi_qp *qp = NULL; 443 int ret; 444 445 if (type != HPRE_V2_ALG_TYPE && type != HPRE_V3_ECC_ALG_TYPE) 446 return NULL; 447 448 /* 449 * type: 0 - RSA/DH. algorithm supported in V2, 450 * 1 - ECC algorithm in V3. 451 */ 452 ret = hisi_qm_alloc_qps_node(&hpre_devices, 1, type, node, &qp); 453 if (!ret) 454 return qp; 455 456 return NULL; 457 } 458 459 static void hpre_config_pasid(struct hisi_qm *qm) 460 { 461 u32 val1, val2; 462 463 if (qm->ver >= QM_HW_V3) 464 return; 465 466 val1 = readl_relaxed(qm->io_base + HPRE_DATA_RUSER_CFG); 467 val2 = readl_relaxed(qm->io_base + HPRE_DATA_WUSER_CFG); 468 if (qm->use_sva) { 469 val1 |= BIT(HPRE_PASID_EN_BIT); 470 val2 |= BIT(HPRE_PASID_EN_BIT); 471 } else { 472 val1 &= ~BIT(HPRE_PASID_EN_BIT); 473 val2 &= ~BIT(HPRE_PASID_EN_BIT); 474 } 475 writel_relaxed(val1, qm->io_base + HPRE_DATA_RUSER_CFG); 476 writel_relaxed(val2, qm->io_base + HPRE_DATA_WUSER_CFG); 477 } 478 479 static int hpre_cfg_by_dsm(struct hisi_qm *qm) 480 { 481 struct device *dev = &qm->pdev->dev; 482 union acpi_object *obj; 483 guid_t guid; 484 485 if (guid_parse("b06b81ab-0134-4a45-9b0c-483447b95fa7", &guid)) { 486 dev_err(dev, "Hpre GUID failed\n"); 487 return -EINVAL; 488 } 489 490 /* Switch over to MSI handling due to non-standard PCI implementation */ 491 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &guid, 492 0, HPRE_VIA_MSI_DSM, NULL); 493 if (!obj) { 494 dev_err(dev, "ACPI handle failed!\n"); 495 return -EIO; 496 } 497 498 ACPI_FREE(obj); 499 500 return 0; 501 } 502 503 static int hpre_set_cluster(struct hisi_qm *qm) 504 { 505 struct device *dev = &qm->pdev->dev; 506 unsigned long offset; 507 u32 cluster_core_mask; 508 u8 clusters_num; 509 u32 val = 0; 510 int ret, i; 511 512 cluster_core_mask = qm->cap_tables.dev_cap_table[HPRE_CORE_ENABLE_BITMAP_CAP_IDX].cap_val; 513 clusters_num = qm->cap_tables.dev_cap_table[HPRE_CLUSTER_NUM_CAP_IDX].cap_val; 514 for (i = 0; i < clusters_num; i++) { 515 offset = i * HPRE_CLSTR_ADDR_INTRVL; 516 517 /* clusters initiating */ 518 writel(cluster_core_mask, 519 qm->io_base + offset + HPRE_CORE_ENB); 520 writel(0x1, qm->io_base + offset + HPRE_CORE_INI_CFG); 521 ret = readl_relaxed_poll_timeout(qm->io_base + offset + 522 HPRE_CORE_INI_STATUS, val, 523 ((val & cluster_core_mask) == 524 cluster_core_mask), 525 HPRE_REG_RD_INTVRL_US, 526 HPRE_REG_RD_TMOUT_US); 527 if (ret) { 528 dev_err(dev, 529 "cluster %d int st status timeout!\n", i); 530 return -ETIMEDOUT; 531 } 532 } 533 534 return 0; 535 } 536 537 /* 538 * For Kunpeng 920, we should disable FLR triggered by hardware (BME/PM/SRIOV). 539 * Or it may stay in D3 state when we bind and unbind hpre quickly, 540 * as it does FLR triggered by hardware. 541 */ 542 static void disable_flr_of_bme(struct hisi_qm *qm) 543 { 544 u32 val; 545 546 val = readl(qm->io_base + QM_PEH_AXUSER_CFG); 547 val &= ~(HPRE_QM_BME_FLR | HPRE_QM_SRIOV_FLR); 548 val |= HPRE_QM_PM_FLR; 549 writel(val, qm->io_base + QM_PEH_AXUSER_CFG); 550 writel(PEH_AXUSER_CFG_ENABLE, qm->io_base + QM_PEH_AXUSER_CFG_ENABLE); 551 } 552 553 static void hpre_open_sva_prefetch(struct hisi_qm *qm) 554 { 555 u32 val; 556 int ret; 557 558 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps)) 559 return; 560 561 /* Enable prefetch */ 562 val = readl_relaxed(qm->io_base + HPRE_PREFETCH_CFG); 563 val &= HPRE_PREFETCH_ENABLE; 564 writel(val, qm->io_base + HPRE_PREFETCH_CFG); 565 566 ret = readl_relaxed_poll_timeout(qm->io_base + HPRE_PREFETCH_CFG, 567 val, !(val & HPRE_PREFETCH_DISABLE), 568 HPRE_REG_RD_INTVRL_US, 569 HPRE_REG_RD_TMOUT_US); 570 if (ret) 571 pci_err(qm->pdev, "failed to open sva prefetch\n"); 572 } 573 574 static void hpre_close_sva_prefetch(struct hisi_qm *qm) 575 { 576 u32 val; 577 int ret; 578 579 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps)) 580 return; 581 582 val = readl_relaxed(qm->io_base + HPRE_PREFETCH_CFG); 583 val |= HPRE_PREFETCH_DISABLE; 584 writel(val, qm->io_base + HPRE_PREFETCH_CFG); 585 586 ret = readl_relaxed_poll_timeout(qm->io_base + HPRE_SVA_PREFTCH_DFX, 587 val, !(val & HPRE_SVA_DISABLE_READY), 588 HPRE_REG_RD_INTVRL_US, 589 HPRE_REG_RD_TMOUT_US); 590 if (ret) 591 pci_err(qm->pdev, "failed to close sva prefetch\n"); 592 } 593 594 static void hpre_enable_clock_gate(struct hisi_qm *qm) 595 { 596 unsigned long offset; 597 u8 clusters_num, i; 598 u32 val; 599 600 if (qm->ver < QM_HW_V3) 601 return; 602 603 val = readl(qm->io_base + HPRE_CLKGATE_CTL); 604 val |= HPRE_CLKGATE_CTL_EN; 605 writel(val, qm->io_base + HPRE_CLKGATE_CTL); 606 607 val = readl(qm->io_base + HPRE_PEH_CFG_AUTO_GATE); 608 val |= HPRE_PEH_CFG_AUTO_GATE_EN; 609 writel(val, qm->io_base + HPRE_PEH_CFG_AUTO_GATE); 610 611 clusters_num = qm->cap_tables.dev_cap_table[HPRE_CLUSTER_NUM_CAP_IDX].cap_val; 612 for (i = 0; i < clusters_num; i++) { 613 offset = (unsigned long)i * HPRE_CLSTR_ADDR_INTRVL; 614 val = readl(qm->io_base + offset + HPRE_CLUSTER_DYN_CTL); 615 val |= HPRE_CLUSTER_DYN_CTL_EN; 616 writel(val, qm->io_base + offset + HPRE_CLUSTER_DYN_CTL); 617 618 val = readl(qm->io_base + offset + HPRE_CORE_SHB_CFG); 619 val |= HPRE_CORE_GATE_EN; 620 writel(val, qm->io_base + offset + HPRE_CORE_SHB_CFG); 621 } 622 } 623 624 static void hpre_disable_clock_gate(struct hisi_qm *qm) 625 { 626 unsigned long offset; 627 u8 clusters_num, i; 628 u32 val; 629 630 if (qm->ver < QM_HW_V3) 631 return; 632 633 val = readl(qm->io_base + HPRE_CLKGATE_CTL); 634 val &= ~HPRE_CLKGATE_CTL_EN; 635 writel(val, qm->io_base + HPRE_CLKGATE_CTL); 636 637 val = readl(qm->io_base + HPRE_PEH_CFG_AUTO_GATE); 638 val &= ~HPRE_PEH_CFG_AUTO_GATE_EN; 639 writel(val, qm->io_base + HPRE_PEH_CFG_AUTO_GATE); 640 641 clusters_num = qm->cap_tables.dev_cap_table[HPRE_CLUSTER_NUM_CAP_IDX].cap_val; 642 for (i = 0; i < clusters_num; i++) { 643 offset = (unsigned long)i * HPRE_CLSTR_ADDR_INTRVL; 644 val = readl(qm->io_base + offset + HPRE_CLUSTER_DYN_CTL); 645 val &= ~HPRE_CLUSTER_DYN_CTL_EN; 646 writel(val, qm->io_base + offset + HPRE_CLUSTER_DYN_CTL); 647 648 val = readl(qm->io_base + offset + HPRE_CORE_SHB_CFG); 649 val &= ~HPRE_CORE_GATE_EN; 650 writel(val, qm->io_base + offset + HPRE_CORE_SHB_CFG); 651 } 652 } 653 654 static int hpre_set_user_domain_and_cache(struct hisi_qm *qm) 655 { 656 struct device *dev = &qm->pdev->dev; 657 u32 val; 658 int ret; 659 660 /* disabel dynamic clock gate before sram init */ 661 hpre_disable_clock_gate(qm); 662 663 writel(HPRE_QM_USR_CFG_MASK, qm->io_base + QM_ARUSER_M_CFG_ENABLE); 664 writel(HPRE_QM_USR_CFG_MASK, qm->io_base + QM_AWUSER_M_CFG_ENABLE); 665 writel_relaxed(HPRE_QM_AXI_CFG_MASK, qm->io_base + QM_AXI_M_CFG); 666 667 if (qm->ver >= QM_HW_V3) 668 writel(HPRE_RSA_ENB | HPRE_ECC_ENB, 669 qm->io_base + HPRE_TYPES_ENB); 670 else 671 writel(HPRE_RSA_ENB, qm->io_base + HPRE_TYPES_ENB); 672 673 writel(HPRE_QM_VFG_AX_MASK, qm->io_base + HPRE_VFG_AXCACHE); 674 writel(0x0, qm->io_base + HPRE_BD_ENDIAN); 675 writel(0x0, qm->io_base + HPRE_POISON_BYPASS); 676 writel(0x0, qm->io_base + HPRE_ECC_BYPASS); 677 678 writel(HPRE_BD_USR_MASK, qm->io_base + HPRE_BD_ARUSR_CFG); 679 writel(HPRE_BD_USR_MASK, qm->io_base + HPRE_BD_AWUSR_CFG); 680 writel(0x1, qm->io_base + HPRE_RDCHN_INI_CFG); 681 ret = readl_relaxed_poll_timeout(qm->io_base + HPRE_RDCHN_INI_ST, val, 682 val & BIT(0), 683 HPRE_REG_RD_INTVRL_US, 684 HPRE_REG_RD_TMOUT_US); 685 if (ret) { 686 dev_err(dev, "read rd channel timeout fail!\n"); 687 return -ETIMEDOUT; 688 } 689 690 ret = hpre_set_cluster(qm); 691 if (ret) 692 return -ETIMEDOUT; 693 694 /* This setting is only needed by Kunpeng 920. */ 695 if (qm->ver == QM_HW_V2) { 696 ret = hpre_cfg_by_dsm(qm); 697 if (ret) 698 return ret; 699 700 disable_flr_of_bme(qm); 701 } 702 703 /* Config data buffer pasid needed by Kunpeng 920 */ 704 hpre_config_pasid(qm); 705 706 hpre_enable_clock_gate(qm); 707 708 return ret; 709 } 710 711 static void hpre_cnt_regs_clear(struct hisi_qm *qm) 712 { 713 unsigned long offset; 714 u8 clusters_num; 715 int i; 716 717 /* clear clusterX/cluster_ctrl */ 718 clusters_num = qm->cap_tables.dev_cap_table[HPRE_CLUSTER_NUM_CAP_IDX].cap_val; 719 for (i = 0; i < clusters_num; i++) { 720 offset = HPRE_CLSTR_BASE + i * HPRE_CLSTR_ADDR_INTRVL; 721 writel(0x0, qm->io_base + offset + HPRE_CLUSTER_INQURY); 722 } 723 724 /* clear rdclr_en */ 725 writel(0x0, qm->io_base + HPRE_CTRL_CNT_CLR_CE); 726 727 hisi_qm_debug_regs_clear(qm); 728 } 729 730 static void hpre_master_ooo_ctrl(struct hisi_qm *qm, bool enable) 731 { 732 u32 val1, val2; 733 734 val1 = readl(qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB); 735 if (enable) { 736 val1 |= HPRE_AM_OOO_SHUTDOWN_ENABLE; 737 val2 = hisi_qm_get_hw_info(qm, hpre_basic_info, 738 HPRE_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 739 } else { 740 val1 &= ~HPRE_AM_OOO_SHUTDOWN_ENABLE; 741 val2 = 0x0; 742 } 743 744 if (qm->ver > QM_HW_V2) 745 writel(val2, qm->io_base + HPRE_OOO_SHUTDOWN_SEL); 746 747 writel(val1, qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB); 748 } 749 750 static void hpre_hw_error_disable(struct hisi_qm *qm) 751 { 752 u32 ce, nfe; 753 754 ce = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_CE_MASK_CAP, qm->cap_ver); 755 nfe = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_NFE_MASK_CAP, qm->cap_ver); 756 757 /* disable hpre hw error interrupts */ 758 writel(ce | nfe | HPRE_HAC_RAS_FE_ENABLE, qm->io_base + HPRE_INT_MASK); 759 /* disable HPRE block master OOO when nfe occurs on Kunpeng930 */ 760 hpre_master_ooo_ctrl(qm, false); 761 } 762 763 static void hpre_hw_error_enable(struct hisi_qm *qm) 764 { 765 u32 ce, nfe, err_en; 766 767 ce = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_CE_MASK_CAP, qm->cap_ver); 768 nfe = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_NFE_MASK_CAP, qm->cap_ver); 769 770 /* clear HPRE hw error source if having */ 771 writel(ce | nfe | HPRE_HAC_RAS_FE_ENABLE, qm->io_base + HPRE_HAC_SOURCE_INT); 772 773 /* configure error type */ 774 writel(ce, qm->io_base + HPRE_RAS_CE_ENB); 775 writel(nfe, qm->io_base + HPRE_RAS_NFE_ENB); 776 writel(HPRE_HAC_RAS_FE_ENABLE, qm->io_base + HPRE_RAS_FE_ENB); 777 778 /* enable HPRE block master OOO when nfe occurs on Kunpeng930 */ 779 hpre_master_ooo_ctrl(qm, true); 780 781 /* enable hpre hw error interrupts */ 782 err_en = ce | nfe | HPRE_HAC_RAS_FE_ENABLE; 783 writel(~err_en, qm->io_base + HPRE_INT_MASK); 784 } 785 786 static inline struct hisi_qm *hpre_file_to_qm(struct hpre_debugfs_file *file) 787 { 788 struct hpre *hpre = container_of(file->debug, struct hpre, debug); 789 790 return &hpre->qm; 791 } 792 793 static u32 hpre_clear_enable_read(struct hpre_debugfs_file *file) 794 { 795 struct hisi_qm *qm = hpre_file_to_qm(file); 796 797 return readl(qm->io_base + HPRE_CTRL_CNT_CLR_CE) & 798 HPRE_CTRL_CNT_CLR_CE_BIT; 799 } 800 801 static int hpre_clear_enable_write(struct hpre_debugfs_file *file, u32 val) 802 { 803 struct hisi_qm *qm = hpre_file_to_qm(file); 804 u32 tmp; 805 806 if (val != 1 && val != 0) 807 return -EINVAL; 808 809 tmp = (readl(qm->io_base + HPRE_CTRL_CNT_CLR_CE) & 810 ~HPRE_CTRL_CNT_CLR_CE_BIT) | val; 811 writel(tmp, qm->io_base + HPRE_CTRL_CNT_CLR_CE); 812 813 return 0; 814 } 815 816 static u32 hpre_cluster_inqry_read(struct hpre_debugfs_file *file) 817 { 818 struct hisi_qm *qm = hpre_file_to_qm(file); 819 int cluster_index = file->index - HPRE_CLUSTER_CTRL; 820 unsigned long offset = HPRE_CLSTR_BASE + 821 cluster_index * HPRE_CLSTR_ADDR_INTRVL; 822 823 return readl(qm->io_base + offset + HPRE_CLSTR_ADDR_INQRY_RSLT); 824 } 825 826 static void hpre_cluster_inqry_write(struct hpre_debugfs_file *file, u32 val) 827 { 828 struct hisi_qm *qm = hpre_file_to_qm(file); 829 int cluster_index = file->index - HPRE_CLUSTER_CTRL; 830 unsigned long offset = HPRE_CLSTR_BASE + cluster_index * 831 HPRE_CLSTR_ADDR_INTRVL; 832 833 writel(val, qm->io_base + offset + HPRE_CLUSTER_INQURY); 834 } 835 836 static ssize_t hpre_ctrl_debug_read(struct file *filp, char __user *buf, 837 size_t count, loff_t *pos) 838 { 839 struct hpre_debugfs_file *file = filp->private_data; 840 struct hisi_qm *qm = hpre_file_to_qm(file); 841 char tbuf[HPRE_DBGFS_VAL_MAX_LEN]; 842 u32 val; 843 int ret; 844 845 ret = hisi_qm_get_dfx_access(qm); 846 if (ret) 847 return ret; 848 849 spin_lock_irq(&file->lock); 850 switch (file->type) { 851 case HPRE_CLEAR_ENABLE: 852 val = hpre_clear_enable_read(file); 853 break; 854 case HPRE_CLUSTER_CTRL: 855 val = hpre_cluster_inqry_read(file); 856 break; 857 default: 858 goto err_input; 859 } 860 spin_unlock_irq(&file->lock); 861 862 hisi_qm_put_dfx_access(qm); 863 ret = snprintf(tbuf, HPRE_DBGFS_VAL_MAX_LEN, "%u\n", val); 864 return simple_read_from_buffer(buf, count, pos, tbuf, ret); 865 866 err_input: 867 spin_unlock_irq(&file->lock); 868 hisi_qm_put_dfx_access(qm); 869 return -EINVAL; 870 } 871 872 static ssize_t hpre_ctrl_debug_write(struct file *filp, const char __user *buf, 873 size_t count, loff_t *pos) 874 { 875 struct hpre_debugfs_file *file = filp->private_data; 876 struct hisi_qm *qm = hpre_file_to_qm(file); 877 char tbuf[HPRE_DBGFS_VAL_MAX_LEN]; 878 unsigned long val; 879 int len, ret; 880 881 if (*pos != 0) 882 return 0; 883 884 if (count >= HPRE_DBGFS_VAL_MAX_LEN) 885 return -ENOSPC; 886 887 len = simple_write_to_buffer(tbuf, HPRE_DBGFS_VAL_MAX_LEN - 1, 888 pos, buf, count); 889 if (len < 0) 890 return len; 891 892 tbuf[len] = '\0'; 893 if (kstrtoul(tbuf, 0, &val)) 894 return -EFAULT; 895 896 ret = hisi_qm_get_dfx_access(qm); 897 if (ret) 898 return ret; 899 900 spin_lock_irq(&file->lock); 901 switch (file->type) { 902 case HPRE_CLEAR_ENABLE: 903 ret = hpre_clear_enable_write(file, val); 904 if (ret) 905 goto err_input; 906 break; 907 case HPRE_CLUSTER_CTRL: 908 hpre_cluster_inqry_write(file, val); 909 break; 910 default: 911 ret = -EINVAL; 912 goto err_input; 913 } 914 915 ret = count; 916 917 err_input: 918 spin_unlock_irq(&file->lock); 919 hisi_qm_put_dfx_access(qm); 920 return ret; 921 } 922 923 static const struct file_operations hpre_ctrl_debug_fops = { 924 .owner = THIS_MODULE, 925 .open = simple_open, 926 .read = hpre_ctrl_debug_read, 927 .write = hpre_ctrl_debug_write, 928 }; 929 930 static int hpre_debugfs_atomic64_get(void *data, u64 *val) 931 { 932 struct hpre_dfx *dfx_item = data; 933 934 *val = atomic64_read(&dfx_item->value); 935 936 return 0; 937 } 938 939 static int hpre_debugfs_atomic64_set(void *data, u64 val) 940 { 941 struct hpre_dfx *dfx_item = data; 942 struct hpre_dfx *hpre_dfx = NULL; 943 944 if (dfx_item->type == HPRE_OVERTIME_THRHLD) { 945 hpre_dfx = dfx_item - HPRE_OVERTIME_THRHLD; 946 atomic64_set(&hpre_dfx[HPRE_OVER_THRHLD_CNT].value, 0); 947 } else if (val) { 948 return -EINVAL; 949 } 950 951 atomic64_set(&dfx_item->value, val); 952 953 return 0; 954 } 955 956 DEFINE_DEBUGFS_ATTRIBUTE(hpre_atomic64_ops, hpre_debugfs_atomic64_get, 957 hpre_debugfs_atomic64_set, "%llu\n"); 958 959 static int hpre_create_debugfs_file(struct hisi_qm *qm, struct dentry *dir, 960 enum hpre_ctrl_dbgfs_file type, int indx) 961 { 962 struct hpre *hpre = container_of(qm, struct hpre, qm); 963 struct hpre_debug *dbg = &hpre->debug; 964 struct dentry *file_dir; 965 966 if (dir) 967 file_dir = dir; 968 else 969 file_dir = qm->debug.debug_root; 970 971 if (type >= HPRE_DEBUG_FILE_NUM) 972 return -EINVAL; 973 974 spin_lock_init(&dbg->files[indx].lock); 975 dbg->files[indx].debug = dbg; 976 dbg->files[indx].type = type; 977 dbg->files[indx].index = indx; 978 debugfs_create_file(hpre_debug_file_name[type], 0600, file_dir, 979 dbg->files + indx, &hpre_ctrl_debug_fops); 980 981 return 0; 982 } 983 984 static int hpre_pf_comm_regs_debugfs_init(struct hisi_qm *qm) 985 { 986 struct device *dev = &qm->pdev->dev; 987 struct debugfs_regset32 *regset; 988 989 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); 990 if (!regset) 991 return -ENOMEM; 992 993 regset->regs = hpre_com_dfx_regs; 994 regset->nregs = ARRAY_SIZE(hpre_com_dfx_regs); 995 regset->base = qm->io_base; 996 regset->dev = dev; 997 998 debugfs_create_file("regs", 0444, qm->debug.debug_root, 999 regset, &hpre_com_regs_fops); 1000 1001 return 0; 1002 } 1003 1004 static int hpre_cluster_debugfs_init(struct hisi_qm *qm) 1005 { 1006 struct device *dev = &qm->pdev->dev; 1007 char buf[HPRE_DBGFS_VAL_MAX_LEN]; 1008 struct debugfs_regset32 *regset; 1009 struct dentry *tmp_d; 1010 u8 clusters_num; 1011 int i, ret; 1012 1013 clusters_num = qm->cap_tables.dev_cap_table[HPRE_CLUSTER_NUM_CAP_IDX].cap_val; 1014 for (i = 0; i < clusters_num; i++) { 1015 ret = snprintf(buf, HPRE_DBGFS_VAL_MAX_LEN, "cluster%d", i); 1016 if (ret >= HPRE_DBGFS_VAL_MAX_LEN) 1017 return -EINVAL; 1018 tmp_d = debugfs_create_dir(buf, qm->debug.debug_root); 1019 1020 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); 1021 if (!regset) 1022 return -ENOMEM; 1023 1024 regset->regs = hpre_cluster_dfx_regs; 1025 regset->nregs = ARRAY_SIZE(hpre_cluster_dfx_regs); 1026 regset->base = qm->io_base + hpre_cluster_offsets[i]; 1027 regset->dev = dev; 1028 1029 debugfs_create_file("regs", 0444, tmp_d, regset, 1030 &hpre_cluster_regs_fops); 1031 ret = hpre_create_debugfs_file(qm, tmp_d, HPRE_CLUSTER_CTRL, 1032 i + HPRE_CLUSTER_CTRL); 1033 if (ret) 1034 return ret; 1035 } 1036 1037 return 0; 1038 } 1039 1040 static int hpre_ctrl_debug_init(struct hisi_qm *qm) 1041 { 1042 int ret; 1043 1044 ret = hpre_create_debugfs_file(qm, NULL, HPRE_CLEAR_ENABLE, 1045 HPRE_CLEAR_ENABLE); 1046 if (ret) 1047 return ret; 1048 1049 ret = hpre_pf_comm_regs_debugfs_init(qm); 1050 if (ret) 1051 return ret; 1052 1053 return hpre_cluster_debugfs_init(qm); 1054 } 1055 1056 static void hpre_dfx_debug_init(struct hisi_qm *qm) 1057 { 1058 struct dfx_diff_registers *hpre_regs = qm->debug.acc_diff_regs; 1059 struct hpre *hpre = container_of(qm, struct hpre, qm); 1060 struct hpre_dfx *dfx = hpre->debug.dfx; 1061 struct dentry *parent; 1062 int i; 1063 1064 parent = debugfs_create_dir("hpre_dfx", qm->debug.debug_root); 1065 for (i = 0; i < HPRE_DFX_FILE_NUM; i++) { 1066 dfx[i].type = i; 1067 debugfs_create_file(hpre_dfx_files[i], 0644, parent, &dfx[i], 1068 &hpre_atomic64_ops); 1069 } 1070 1071 if (qm->fun_type == QM_HW_PF && hpre_regs) 1072 debugfs_create_file("diff_regs", 0444, parent, 1073 qm, &hpre_diff_regs_fops); 1074 } 1075 1076 static int hpre_debugfs_init(struct hisi_qm *qm) 1077 { 1078 struct device *dev = &qm->pdev->dev; 1079 int ret; 1080 1081 ret = hisi_qm_regs_debugfs_init(qm, hpre_diff_regs, ARRAY_SIZE(hpre_diff_regs)); 1082 if (ret) { 1083 dev_warn(dev, "Failed to init HPRE diff regs!\n"); 1084 return ret; 1085 } 1086 1087 qm->debug.debug_root = debugfs_create_dir(dev_name(dev), 1088 hpre_debugfs_root); 1089 qm->debug.sqe_mask_offset = HPRE_SQE_MASK_OFFSET; 1090 qm->debug.sqe_mask_len = HPRE_SQE_MASK_LEN; 1091 1092 hisi_qm_debug_init(qm); 1093 1094 if (qm->pdev->device == PCI_DEVICE_ID_HUAWEI_HPRE_PF) { 1095 ret = hpre_ctrl_debug_init(qm); 1096 if (ret) 1097 goto debugfs_remove; 1098 } 1099 1100 hpre_dfx_debug_init(qm); 1101 1102 return 0; 1103 1104 debugfs_remove: 1105 debugfs_remove_recursive(qm->debug.debug_root); 1106 hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(hpre_diff_regs)); 1107 return ret; 1108 } 1109 1110 static void hpre_debugfs_exit(struct hisi_qm *qm) 1111 { 1112 debugfs_remove_recursive(qm->debug.debug_root); 1113 1114 hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(hpre_diff_regs)); 1115 } 1116 1117 static int hpre_pre_store_cap_reg(struct hisi_qm *qm) 1118 { 1119 struct hisi_qm_cap_record *hpre_cap; 1120 struct device *dev = &qm->pdev->dev; 1121 size_t i, size; 1122 1123 size = ARRAY_SIZE(hpre_pre_store_caps); 1124 hpre_cap = devm_kzalloc(dev, sizeof(*hpre_cap) * size, GFP_KERNEL); 1125 if (!hpre_cap) 1126 return -ENOMEM; 1127 1128 for (i = 0; i < size; i++) { 1129 hpre_cap[i].type = hpre_pre_store_caps[i]; 1130 hpre_cap[i].cap_val = hisi_qm_get_hw_info(qm, hpre_basic_info, 1131 hpre_pre_store_caps[i], qm->cap_ver); 1132 } 1133 1134 if (hpre_cap[HPRE_CLUSTER_NUM_CAP_IDX].cap_val > HPRE_CLUSTERS_NUM_MAX) { 1135 dev_err(dev, "Device cluster num %u is out of range for driver supports %d!\n", 1136 hpre_cap[HPRE_CLUSTER_NUM_CAP_IDX].cap_val, HPRE_CLUSTERS_NUM_MAX); 1137 return -EINVAL; 1138 } 1139 1140 qm->cap_tables.dev_cap_table = hpre_cap; 1141 1142 return 0; 1143 } 1144 1145 static int hpre_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) 1146 { 1147 u64 alg_msk; 1148 int ret; 1149 1150 if (pdev->revision == QM_HW_V1) { 1151 pci_warn(pdev, "HPRE version 1 is not supported!\n"); 1152 return -EINVAL; 1153 } 1154 1155 qm->mode = uacce_mode; 1156 qm->pdev = pdev; 1157 qm->ver = pdev->revision; 1158 qm->sqe_size = HPRE_SQE_SIZE; 1159 qm->dev_name = hpre_name; 1160 1161 qm->fun_type = (pdev->device == PCI_DEVICE_ID_HUAWEI_HPRE_PF) ? 1162 QM_HW_PF : QM_HW_VF; 1163 if (qm->fun_type == QM_HW_PF) { 1164 qm->qp_base = HPRE_PF_DEF_Q_BASE; 1165 qm->qp_num = pf_q_num; 1166 qm->debug.curr_qm_qp_num = pf_q_num; 1167 qm->qm_list = &hpre_devices; 1168 qm->err_ini = &hpre_err_ini; 1169 if (pf_q_num_flag) 1170 set_bit(QM_MODULE_PARAM, &qm->misc_ctl); 1171 } 1172 1173 ret = hisi_qm_init(qm); 1174 if (ret) { 1175 pci_err(pdev, "Failed to init hpre qm configures!\n"); 1176 return ret; 1177 } 1178 1179 /* Fetch and save the value of capability registers */ 1180 ret = hpre_pre_store_cap_reg(qm); 1181 if (ret) { 1182 pci_err(pdev, "Failed to pre-store capability registers!\n"); 1183 hisi_qm_uninit(qm); 1184 return ret; 1185 } 1186 1187 alg_msk = qm->cap_tables.dev_cap_table[HPRE_DEV_ALG_BITMAP_CAP_IDX].cap_val; 1188 ret = hisi_qm_set_algs(qm, alg_msk, hpre_dev_algs, ARRAY_SIZE(hpre_dev_algs)); 1189 if (ret) { 1190 pci_err(pdev, "Failed to set hpre algs!\n"); 1191 hisi_qm_uninit(qm); 1192 } 1193 1194 return ret; 1195 } 1196 1197 static int hpre_show_last_regs_init(struct hisi_qm *qm) 1198 { 1199 int cluster_dfx_regs_num = ARRAY_SIZE(hpre_cluster_dfx_regs); 1200 int com_dfx_regs_num = ARRAY_SIZE(hpre_com_dfx_regs); 1201 struct qm_debug *debug = &qm->debug; 1202 void __iomem *io_base; 1203 u8 clusters_num; 1204 int i, j, idx; 1205 1206 clusters_num = qm->cap_tables.dev_cap_table[HPRE_CLUSTER_NUM_CAP_IDX].cap_val; 1207 debug->last_words = kcalloc(cluster_dfx_regs_num * clusters_num + 1208 com_dfx_regs_num, sizeof(unsigned int), GFP_KERNEL); 1209 if (!debug->last_words) 1210 return -ENOMEM; 1211 1212 for (i = 0; i < com_dfx_regs_num; i++) 1213 debug->last_words[i] = readl_relaxed(qm->io_base + 1214 hpre_com_dfx_regs[i].offset); 1215 1216 for (i = 0; i < clusters_num; i++) { 1217 io_base = qm->io_base + hpre_cluster_offsets[i]; 1218 for (j = 0; j < cluster_dfx_regs_num; j++) { 1219 idx = com_dfx_regs_num + i * cluster_dfx_regs_num + j; 1220 debug->last_words[idx] = readl_relaxed( 1221 io_base + hpre_cluster_dfx_regs[j].offset); 1222 } 1223 } 1224 1225 return 0; 1226 } 1227 1228 static void hpre_show_last_regs_uninit(struct hisi_qm *qm) 1229 { 1230 struct qm_debug *debug = &qm->debug; 1231 1232 if (qm->fun_type == QM_HW_VF || !debug->last_words) 1233 return; 1234 1235 kfree(debug->last_words); 1236 debug->last_words = NULL; 1237 } 1238 1239 static void hpre_show_last_dfx_regs(struct hisi_qm *qm) 1240 { 1241 int cluster_dfx_regs_num = ARRAY_SIZE(hpre_cluster_dfx_regs); 1242 int com_dfx_regs_num = ARRAY_SIZE(hpre_com_dfx_regs); 1243 struct qm_debug *debug = &qm->debug; 1244 struct pci_dev *pdev = qm->pdev; 1245 void __iomem *io_base; 1246 u8 clusters_num; 1247 int i, j, idx; 1248 u32 val; 1249 1250 if (qm->fun_type == QM_HW_VF || !debug->last_words) 1251 return; 1252 1253 /* dumps last word of the debugging registers during controller reset */ 1254 for (i = 0; i < com_dfx_regs_num; i++) { 1255 val = readl_relaxed(qm->io_base + hpre_com_dfx_regs[i].offset); 1256 if (debug->last_words[i] != val) 1257 pci_info(pdev, "Common_core:%s \t= 0x%08x => 0x%08x\n", 1258 hpre_com_dfx_regs[i].name, debug->last_words[i], val); 1259 } 1260 1261 clusters_num = qm->cap_tables.dev_cap_table[HPRE_CLUSTER_NUM_CAP_IDX].cap_val; 1262 for (i = 0; i < clusters_num; i++) { 1263 io_base = qm->io_base + hpre_cluster_offsets[i]; 1264 for (j = 0; j < cluster_dfx_regs_num; j++) { 1265 val = readl_relaxed(io_base + 1266 hpre_cluster_dfx_regs[j].offset); 1267 idx = com_dfx_regs_num + i * cluster_dfx_regs_num + j; 1268 if (debug->last_words[idx] != val) 1269 pci_info(pdev, "cluster-%d:%s \t= 0x%08x => 0x%08x\n", 1270 i, hpre_cluster_dfx_regs[j].name, debug->last_words[idx], val); 1271 } 1272 } 1273 } 1274 1275 static void hpre_log_hw_error(struct hisi_qm *qm, u32 err_sts) 1276 { 1277 const struct hpre_hw_error *err = hpre_hw_errors; 1278 struct device *dev = &qm->pdev->dev; 1279 1280 while (err->msg) { 1281 if (err->int_msk & err_sts) 1282 dev_warn(dev, "%s [error status=0x%x] found\n", 1283 err->msg, err->int_msk); 1284 err++; 1285 } 1286 } 1287 1288 static u32 hpre_get_hw_err_status(struct hisi_qm *qm) 1289 { 1290 return readl(qm->io_base + HPRE_INT_STATUS); 1291 } 1292 1293 static void hpre_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts) 1294 { 1295 u32 nfe; 1296 1297 writel(err_sts, qm->io_base + HPRE_HAC_SOURCE_INT); 1298 nfe = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_NFE_MASK_CAP, qm->cap_ver); 1299 writel(nfe, qm->io_base + HPRE_RAS_NFE_ENB); 1300 } 1301 1302 static void hpre_open_axi_master_ooo(struct hisi_qm *qm) 1303 { 1304 u32 value; 1305 1306 value = readl(qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB); 1307 writel(value & ~HPRE_AM_OOO_SHUTDOWN_ENABLE, 1308 qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB); 1309 writel(value | HPRE_AM_OOO_SHUTDOWN_ENABLE, 1310 qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB); 1311 } 1312 1313 static void hpre_err_info_init(struct hisi_qm *qm) 1314 { 1315 struct hisi_qm_err_info *err_info = &qm->err_info; 1316 1317 err_info->fe = HPRE_HAC_RAS_FE_ENABLE; 1318 err_info->ce = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_QM_CE_MASK_CAP, qm->cap_ver); 1319 err_info->nfe = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_QM_NFE_MASK_CAP, qm->cap_ver); 1320 err_info->ecc_2bits_mask = HPRE_CORE_ECC_2BIT_ERR | HPRE_OOO_ECC_2BIT_ERR; 1321 err_info->dev_shutdown_mask = hisi_qm_get_hw_info(qm, hpre_basic_info, 1322 HPRE_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 1323 err_info->qm_shutdown_mask = hisi_qm_get_hw_info(qm, hpre_basic_info, 1324 HPRE_QM_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 1325 err_info->qm_reset_mask = hisi_qm_get_hw_info(qm, hpre_basic_info, 1326 HPRE_QM_RESET_MASK_CAP, qm->cap_ver); 1327 err_info->dev_reset_mask = hisi_qm_get_hw_info(qm, hpre_basic_info, 1328 HPRE_RESET_MASK_CAP, qm->cap_ver); 1329 err_info->msi_wr_port = HPRE_WR_MSI_PORT; 1330 err_info->acpi_rst = "HRST"; 1331 } 1332 1333 static const struct hisi_qm_err_ini hpre_err_ini = { 1334 .hw_init = hpre_set_user_domain_and_cache, 1335 .hw_err_enable = hpre_hw_error_enable, 1336 .hw_err_disable = hpre_hw_error_disable, 1337 .get_dev_hw_err_status = hpre_get_hw_err_status, 1338 .clear_dev_hw_err_status = hpre_clear_hw_err_status, 1339 .log_dev_hw_err = hpre_log_hw_error, 1340 .open_axi_master_ooo = hpre_open_axi_master_ooo, 1341 .open_sva_prefetch = hpre_open_sva_prefetch, 1342 .close_sva_prefetch = hpre_close_sva_prefetch, 1343 .show_last_dfx_regs = hpre_show_last_dfx_regs, 1344 .err_info_init = hpre_err_info_init, 1345 }; 1346 1347 static int hpre_pf_probe_init(struct hpre *hpre) 1348 { 1349 struct hisi_qm *qm = &hpre->qm; 1350 int ret; 1351 1352 ret = hpre_set_user_domain_and_cache(qm); 1353 if (ret) 1354 return ret; 1355 1356 hpre_open_sva_prefetch(qm); 1357 1358 hisi_qm_dev_err_init(qm); 1359 ret = hpre_show_last_regs_init(qm); 1360 if (ret) 1361 pci_err(qm->pdev, "Failed to init last word regs!\n"); 1362 1363 return ret; 1364 } 1365 1366 static int hpre_probe_init(struct hpre *hpre) 1367 { 1368 u32 type_rate = HPRE_SHAPER_TYPE_RATE; 1369 struct hisi_qm *qm = &hpre->qm; 1370 int ret; 1371 1372 if (qm->fun_type == QM_HW_PF) { 1373 ret = hpre_pf_probe_init(hpre); 1374 if (ret) 1375 return ret; 1376 /* Enable shaper type 0 */ 1377 if (qm->ver >= QM_HW_V3) { 1378 type_rate |= QM_SHAPER_ENABLE; 1379 qm->type_rate = type_rate; 1380 } 1381 } 1382 1383 return 0; 1384 } 1385 1386 static void hpre_probe_uninit(struct hisi_qm *qm) 1387 { 1388 if (qm->fun_type == QM_HW_VF) 1389 return; 1390 1391 hpre_cnt_regs_clear(qm); 1392 qm->debug.curr_qm_qp_num = 0; 1393 hpre_show_last_regs_uninit(qm); 1394 hpre_close_sva_prefetch(qm); 1395 hisi_qm_dev_err_uninit(qm); 1396 } 1397 1398 static int hpre_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1399 { 1400 struct hisi_qm *qm; 1401 struct hpre *hpre; 1402 int ret; 1403 1404 hpre = devm_kzalloc(&pdev->dev, sizeof(*hpre), GFP_KERNEL); 1405 if (!hpre) 1406 return -ENOMEM; 1407 1408 qm = &hpre->qm; 1409 ret = hpre_qm_init(qm, pdev); 1410 if (ret) { 1411 pci_err(pdev, "Failed to init HPRE QM (%d)!\n", ret); 1412 return ret; 1413 } 1414 1415 ret = hpre_probe_init(hpre); 1416 if (ret) { 1417 pci_err(pdev, "Failed to probe (%d)!\n", ret); 1418 goto err_with_qm_init; 1419 } 1420 1421 ret = hisi_qm_start(qm); 1422 if (ret) 1423 goto err_with_probe_init; 1424 1425 ret = hpre_debugfs_init(qm); 1426 if (ret) 1427 dev_warn(&pdev->dev, "init debugfs fail!\n"); 1428 1429 hisi_qm_add_list(qm, &hpre_devices); 1430 ret = hisi_qm_alg_register(qm, &hpre_devices, HPRE_CTX_Q_NUM_DEF); 1431 if (ret < 0) { 1432 pci_err(pdev, "fail to register algs to crypto!\n"); 1433 goto err_qm_del_list; 1434 } 1435 1436 if (qm->uacce) { 1437 ret = uacce_register(qm->uacce); 1438 if (ret) { 1439 pci_err(pdev, "failed to register uacce (%d)!\n", ret); 1440 goto err_with_alg_register; 1441 } 1442 } 1443 1444 if (qm->fun_type == QM_HW_PF && vfs_num) { 1445 ret = hisi_qm_sriov_enable(pdev, vfs_num); 1446 if (ret < 0) 1447 goto err_with_alg_register; 1448 } 1449 1450 hisi_qm_pm_init(qm); 1451 1452 return 0; 1453 1454 err_with_alg_register: 1455 hisi_qm_alg_unregister(qm, &hpre_devices, HPRE_CTX_Q_NUM_DEF); 1456 1457 err_qm_del_list: 1458 hisi_qm_del_list(qm, &hpre_devices); 1459 hpre_debugfs_exit(qm); 1460 hisi_qm_stop(qm, QM_NORMAL); 1461 1462 err_with_probe_init: 1463 hpre_probe_uninit(qm); 1464 1465 err_with_qm_init: 1466 hisi_qm_uninit(qm); 1467 1468 return ret; 1469 } 1470 1471 static void hpre_remove(struct pci_dev *pdev) 1472 { 1473 struct hisi_qm *qm = pci_get_drvdata(pdev); 1474 1475 hisi_qm_pm_uninit(qm); 1476 hisi_qm_wait_task_finish(qm, &hpre_devices); 1477 hisi_qm_alg_unregister(qm, &hpre_devices, HPRE_CTX_Q_NUM_DEF); 1478 hisi_qm_del_list(qm, &hpre_devices); 1479 if (qm->fun_type == QM_HW_PF && qm->vfs_num) 1480 hisi_qm_sriov_disable(pdev, true); 1481 1482 hpre_debugfs_exit(qm); 1483 hisi_qm_stop(qm, QM_NORMAL); 1484 1485 hpre_probe_uninit(qm); 1486 hisi_qm_uninit(qm); 1487 } 1488 1489 static const struct dev_pm_ops hpre_pm_ops = { 1490 SET_RUNTIME_PM_OPS(hisi_qm_suspend, hisi_qm_resume, NULL) 1491 }; 1492 1493 static const struct pci_error_handlers hpre_err_handler = { 1494 .error_detected = hisi_qm_dev_err_detected, 1495 .slot_reset = hisi_qm_dev_slot_reset, 1496 .reset_prepare = hisi_qm_reset_prepare, 1497 .reset_done = hisi_qm_reset_done, 1498 }; 1499 1500 static struct pci_driver hpre_pci_driver = { 1501 .name = hpre_name, 1502 .id_table = hpre_dev_ids, 1503 .probe = hpre_probe, 1504 .remove = hpre_remove, 1505 .sriov_configure = IS_ENABLED(CONFIG_PCI_IOV) ? 1506 hisi_qm_sriov_configure : NULL, 1507 .err_handler = &hpre_err_handler, 1508 .shutdown = hisi_qm_dev_shutdown, 1509 .driver.pm = &hpre_pm_ops, 1510 }; 1511 1512 struct pci_driver *hisi_hpre_get_pf_driver(void) 1513 { 1514 return &hpre_pci_driver; 1515 } 1516 EXPORT_SYMBOL_GPL(hisi_hpre_get_pf_driver); 1517 1518 static void hpre_register_debugfs(void) 1519 { 1520 if (!debugfs_initialized()) 1521 return; 1522 1523 hpre_debugfs_root = debugfs_create_dir(hpre_name, NULL); 1524 } 1525 1526 static void hpre_unregister_debugfs(void) 1527 { 1528 debugfs_remove_recursive(hpre_debugfs_root); 1529 } 1530 1531 static int __init hpre_init(void) 1532 { 1533 int ret; 1534 1535 hisi_qm_init_list(&hpre_devices); 1536 hpre_register_debugfs(); 1537 1538 ret = pci_register_driver(&hpre_pci_driver); 1539 if (ret) { 1540 hpre_unregister_debugfs(); 1541 pr_err("hpre: can't register hisi hpre driver.\n"); 1542 } 1543 1544 return ret; 1545 } 1546 1547 static void __exit hpre_exit(void) 1548 { 1549 pci_unregister_driver(&hpre_pci_driver); 1550 hpre_unregister_debugfs(); 1551 } 1552 1553 module_init(hpre_init); 1554 module_exit(hpre_exit); 1555 1556 MODULE_LICENSE("GPL v2"); 1557 MODULE_AUTHOR("Zaibo Xu <xuzaibo@huawei.com>"); 1558 MODULE_AUTHOR("Meng Yu <yumeng18@huawei.com>"); 1559 MODULE_DESCRIPTION("Driver for HiSilicon HPRE accelerator"); 1560