1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (C) 2012-2019 ARM Limited or its affiliates. */ 3 4 #ifndef __CC_HOST_H__ 5 #define __CC_HOST_H__ 6 7 // -------------------------------------- 8 // BLOCK: HOST_P 9 // -------------------------------------- 10 11 12 /* IRR */ 13 #define CC_HOST_IRR_REG_OFFSET 0xA00UL 14 #define CC_HOST_IRR_REE_OP_ABORTED_AES_0_INT_BIT_SHIFT 0x1UL 15 #define CC_HOST_IRR_REE_OP_ABORTED_AES_0_INT_BIT_SIZE 0x1UL 16 #define CC_HOST_IRR_DSCRPTR_COMPLETION_LOW_INT_BIT_SHIFT 0x2UL 17 #define CC_HOST_IRR_DSCRPTR_COMPLETION_LOW_INT_BIT_SIZE 0x1UL 18 #define CC_HOST_IRR_REE_OP_ABORTED_AES_1_INT_BIT_SHIFT 0x3UL 19 #define CC_HOST_IRR_REE_OP_ABORTED_AES_1_INT_BIT_SIZE 0x1UL 20 #define CC_HOST_IRR_REE_OP_ABORTED_AES_2_INT_BIT_SHIFT 0x4UL 21 #define CC_HOST_IRR_REE_OP_ABORTED_AES_2_INT_BIT_SIZE 0x1UL 22 #define CC_HOST_IRR_REE_OP_ABORTED_AES_3_INT_BIT_SHIFT 0x5UL 23 #define CC_HOST_IRR_REE_OP_ABORTED_AES_3_INT_BIT_SIZE 0x1UL 24 #define CC_HOST_IRR_REE_OP_ABORTED_AES_4_INT_BIT_SHIFT 0x6UL 25 #define CC_HOST_IRR_REE_OP_ABORTED_AES_4_INT_BIT_SIZE 0x1UL 26 #define CC_HOST_IRR_REE_OP_ABORTED_AES_5_INT_BIT_SHIFT 0x7UL 27 #define CC_HOST_IRR_REE_OP_ABORTED_AES_5_INT_BIT_SIZE 0x1UL 28 #define CC_HOST_IRR_AXI_ERR_INT_BIT_SHIFT 0x8UL 29 #define CC_HOST_IRR_AXI_ERR_INT_BIT_SIZE 0x1UL 30 #define CC_HOST_IRR_REE_OP_ABORTED_AES_6_INT_BIT_SHIFT 0x9UL 31 #define CC_HOST_IRR_REE_OP_ABORTED_AES_6_INT_BIT_SIZE 0x1UL 32 #define CC_HOST_IRR_REE_OP_ABORTED_AES_7_INT_BIT_SHIFT 0xAUL 33 #define CC_HOST_IRR_REE_OP_ABORTED_AES_7_INT_BIT_SIZE 0x1UL 34 #define CC_HOST_IRR_GPR0_BIT_SHIFT 0xBUL 35 #define CC_HOST_IRR_GPR0_BIT_SIZE 0x1UL 36 #define CC_HOST_IRR_REE_OP_ABORTED_SM_0_INT_BIT_SHIFT 0xCUL 37 #define CC_HOST_IRR_REE_OP_ABORTED_SM_0_INT_BIT_SIZE 0x1UL 38 #define CC_HOST_IRR_REE_OP_ABORTED_SM_1_INT_BIT_SHIFT 0xDUL 39 #define CC_HOST_IRR_REE_OP_ABORTED_SM_1_INT_BIT_SIZE 0x1UL 40 #define CC_HOST_IRR_REE_OP_ABORTED_SM_2_INT_BIT_SHIFT 0xEUL 41 #define CC_HOST_IRR_REE_OP_ABORTED_SM_2_INT_BIT_SIZE 0x1UL 42 #define CC_HOST_IRR_REE_OP_ABORTED_SM_3_INT_BIT_SHIFT 0xFUL 43 #define CC_HOST_IRR_REE_OP_ABORTED_SM_3_INT_BIT_SIZE 0x1UL 44 #define CC_HOST_IRR_REE_OP_ABORTED_SM_4_INT_BIT_SHIFT 0x10UL 45 #define CC_HOST_IRR_REE_OP_ABORTED_SM_4_INT_BIT_SIZE 0x1UL 46 #define CC_HOST_IRR_REE_OP_ABORTED_SM_5_INT_BIT_SHIFT 0x11UL 47 #define CC_HOST_IRR_REE_OP_ABORTED_SM_5_INT_BIT_SIZE 0x1UL 48 #define CC_HOST_IRR_REE_OP_ABORTED_SM_6_INT_BIT_SHIFT 0x12UL 49 #define CC_HOST_IRR_REE_OP_ABORTED_SM_6_INT_BIT_SIZE 0x1UL 50 #define CC_HOST_IRR_DSCRPTR_WATERMARK_INT_BIT_SHIFT 0x13UL 51 #define CC_HOST_IRR_DSCRPTR_WATERMARK_INT_BIT_SIZE 0x1UL 52 #define CC_HOST_IRR_REE_OP_ABORTED_SM_7_INT_BIT_SHIFT 0x14UL 53 #define CC_HOST_IRR_REE_OP_ABORTED_SM_7_INT_BIT_SIZE 0x1UL 54 #define CC_HOST_IRR_AXIM_COMP_INT_BIT_SHIFT 0x17UL 55 #define CC_HOST_IRR_AXIM_COMP_INT_BIT_SIZE 0x1UL 56 #define CC_HOST_SEP_SRAM_THRESHOLD_REG_OFFSET 0xA10UL 57 #define CC_HOST_SEP_SRAM_THRESHOLD_VALUE_BIT_SHIFT 0x0UL 58 #define CC_HOST_SEP_SRAM_THRESHOLD_VALUE_BIT_SIZE 0xCUL 59 60 /* IMR */ 61 #define CC_HOST_IMR_REG_OFFSET 0x0A04UL 62 #define CC_HOST_IMR_REE_OP_ABORTED_AES_0_MASK_BIT_SHIFT 0x1UL 63 #define CC_HOST_IMR_REE_OP_ABORTED_AES_0_MASK_BIT_SIZE 0x1UL 64 #define CC_HOST_IMR_DSCRPTR_COMPLETION_MASK_BIT_SHIFT 0x2UL 65 #define CC_HOST_IMR_DSCRPTR_COMPLETION_MASK_BIT_SIZE 0x1UL 66 #define CC_HOST_IMR_REE_OP_ABORTED_AES_1_MASK_BIT_SHIFT 0x3UL 67 #define CC_HOST_IMR_REE_OP_ABORTED_AES_1_MASK_BIT_SIZE 0x1UL 68 #define CC_HOST_IMR_REE_OP_ABORTED_AES_2_MASK_BIT_SHIFT 0x4UL 69 #define CC_HOST_IMR_REE_OP_ABORTED_AES_2_MASK_BIT_SIZE 0x1UL 70 #define CC_HOST_IMR_REE_OP_ABORTED_AES_3_MASK_BIT_SHIFT 0x5UL 71 #define CC_HOST_IMR_REE_OP_ABORTED_AES_3_MASK_BIT_SIZE 0x1UL 72 #define CC_HOST_IMR_REE_OP_ABORTED_AES_4_MASK_BIT_SHIFT 0x6UL 73 #define CC_HOST_IMR_REE_OP_ABORTED_AES_4_MASK_BIT_SIZE 0x1UL 74 #define CC_HOST_IMR_REE_OP_ABORTED_AES_5_MASK_BIT_SHIFT 0x7UL 75 #define CC_HOST_IMR_REE_OP_ABORTED_AES_5_MASK_BIT_SIZE 0x1UL 76 #define CC_HOST_IMR_AXI_ERR_MASK_BIT_SHIFT 0x8UL 77 #define CC_HOST_IMR_AXI_ERR_MASK_BIT_SIZE 0x1UL 78 #define CC_HOST_IMR_REE_OP_ABORTED_AES_6_MASK_BIT_SHIFT 0x9UL 79 #define CC_HOST_IMR_REE_OP_ABORTED_AES_6_MASK_BIT_SIZE 0x1UL 80 #define CC_HOST_IMR_REE_OP_ABORTED_AES_7_MASK_BIT_SHIFT 0xAUL 81 #define CC_HOST_IMR_REE_OP_ABORTED_AES_7_MASK_BIT_SIZE 0x1UL 82 #define CC_HOST_IMR_GPR0_BIT_SHIFT 0xBUL 83 #define CC_HOST_IMR_GPR0_BIT_SIZE 0x1UL 84 #define CC_HOST_IMR_REE_OP_ABORTED_SM_0_MASK_BIT_SHIFT 0xCUL 85 #define CC_HOST_IMR_REE_OP_ABORTED_SM_0_MASK_BIT_SIZE 0x1UL 86 #define CC_HOST_IMR_REE_OP_ABORTED_SM_1_MASK_BIT_SHIFT 0xDUL 87 #define CC_HOST_IMR_REE_OP_ABORTED_SM_1_MASK_BIT_SIZE 0x1UL 88 #define CC_HOST_IMR_REE_OP_ABORTED_SM_2_MASK_BIT_SHIFT 0xEUL 89 #define CC_HOST_IMR_REE_OP_ABORTED_SM_2_MASK_BIT_SIZE 0x1UL 90 #define CC_HOST_IMR_REE_OP_ABORTED_SM_3_MASK_BIT_SHIFT 0xFUL 91 #define CC_HOST_IMR_REE_OP_ABORTED_SM_3_MASK_BIT_SIZE 0x1UL 92 #define CC_HOST_IMR_REE_OP_ABORTED_SM_4_MASK_BIT_SHIFT 0x10UL 93 #define CC_HOST_IMR_REE_OP_ABORTED_SM_4_MASK_BIT_SIZE 0x1UL 94 #define CC_HOST_IMR_REE_OP_ABORTED_SM_5_MASK_BIT_SHIFT 0x11UL 95 #define CC_HOST_IMR_REE_OP_ABORTED_SM_5_MASK_BIT_SIZE 0x1UL 96 #define CC_HOST_IMR_REE_OP_ABORTED_SM_6_MASK_BIT_SHIFT 0x12UL 97 #define CC_HOST_IMR_REE_OP_ABORTED_SM_6_MASK_BIT_SIZE 0x1UL 98 #define CC_HOST_IMR_DSCRPTR_WATERMARK_MASK0_BIT_SHIFT 0x13UL 99 #define CC_HOST_IMR_DSCRPTR_WATERMARK_MASK0_BIT_SIZE 0x1UL 100 #define CC_HOST_IMR_REE_OP_ABORTED_SM_7_MASK_BIT_SHIFT 0x14UL 101 #define CC_HOST_IMR_REE_OP_ABORTED_SM_7_MASK_BIT_SIZE 0x1UL 102 #define CC_HOST_IMR_AXIM_COMP_INT_MASK_BIT_SHIFT 0x17UL 103 #define CC_HOST_IMR_AXIM_COMP_INT_MASK_BIT_SIZE 0x1UL 104 105 /* ICR */ 106 #define CC_HOST_ICR_REG_OFFSET 0xA08UL 107 #define CC_HOST_ICR_DSCRPTR_COMPLETION_BIT_SHIFT 0x2UL 108 #define CC_HOST_ICR_DSCRPTR_COMPLETION_BIT_SIZE 0x1UL 109 #define CC_HOST_ICR_AXI_ERR_CLEAR_BIT_SHIFT 0x8UL 110 #define CC_HOST_ICR_AXI_ERR_CLEAR_BIT_SIZE 0x1UL 111 #define CC_HOST_ICR_GPR_INT_CLEAR_BIT_SHIFT 0xBUL 112 #define CC_HOST_ICR_GPR_INT_CLEAR_BIT_SIZE 0x1UL 113 #define CC_HOST_ICR_DSCRPTR_WATERMARK_QUEUE0_CLEAR_BIT_SHIFT 0x13UL 114 #define CC_HOST_ICR_DSCRPTR_WATERMARK_QUEUE0_CLEAR_BIT_SIZE 0x1UL 115 #define CC_HOST_ICR_AXIM_COMP_INT_CLEAR_BIT_SHIFT 0x17UL 116 #define CC_HOST_ICR_AXIM_COMP_INT_CLEAR_BIT_SIZE 0x1UL 117 #define CC_NVM_IS_IDLE_REG_OFFSET 0x0A10UL 118 #define CC_NVM_IS_IDLE_VALUE_BIT_SHIFT 0x0UL 119 #define CC_NVM_IS_IDLE_VALUE_BIT_SIZE 0x1UL 120 #define CC_SECURITY_DISABLED_REG_OFFSET 0x0A1CUL 121 #define CC_SECURITY_DISABLED_VALUE_BIT_SHIFT 0x0UL 122 #define CC_SECURITY_DISABLED_VALUE_BIT_SIZE 0x1UL 123 #define CC_HOST_SIGNATURE_712_REG_OFFSET 0xA24UL 124 #define CC_HOST_SIGNATURE_630_REG_OFFSET 0xAC8UL 125 #define CC_HOST_SIGNATURE_VALUE_BIT_SHIFT 0x0UL 126 #define CC_HOST_SIGNATURE_VALUE_BIT_SIZE 0x20UL 127 #define CC_HOST_BOOT_REG_OFFSET 0xA28UL 128 #define CC_HOST_BOOT_SYNTHESIS_CONFIG_BIT_SHIFT 0x0UL 129 #define CC_HOST_BOOT_SYNTHESIS_CONFIG_BIT_SIZE 0x1UL 130 #define CC_HOST_BOOT_LARGE_RKEK_LOCAL_BIT_SHIFT 0x1UL 131 #define CC_HOST_BOOT_LARGE_RKEK_LOCAL_BIT_SIZE 0x1UL 132 #define CC_HOST_BOOT_HASH_IN_FUSES_LOCAL_BIT_SHIFT 0x2UL 133 #define CC_HOST_BOOT_HASH_IN_FUSES_LOCAL_BIT_SIZE 0x1UL 134 #define CC_HOST_BOOT_EXT_MEM_SECURED_LOCAL_BIT_SHIFT 0x3UL 135 #define CC_HOST_BOOT_EXT_MEM_SECURED_LOCAL_BIT_SIZE 0x1UL 136 #define CC_HOST_BOOT_RKEK_ECC_EXISTS_LOCAL_N_BIT_SHIFT 0x5UL 137 #define CC_HOST_BOOT_RKEK_ECC_EXISTS_LOCAL_N_BIT_SIZE 0x1UL 138 #define CC_HOST_BOOT_SRAM_SIZE_LOCAL_BIT_SHIFT 0x6UL 139 #define CC_HOST_BOOT_SRAM_SIZE_LOCAL_BIT_SIZE 0x3UL 140 #define CC_HOST_BOOT_DSCRPTR_EXISTS_LOCAL_BIT_SHIFT 0x9UL 141 #define CC_HOST_BOOT_DSCRPTR_EXISTS_LOCAL_BIT_SIZE 0x1UL 142 #define CC_HOST_BOOT_PAU_EXISTS_LOCAL_BIT_SHIFT 0xAUL 143 #define CC_HOST_BOOT_PAU_EXISTS_LOCAL_BIT_SIZE 0x1UL 144 #define CC_HOST_BOOT_RNG_EXISTS_LOCAL_BIT_SHIFT 0xBUL 145 #define CC_HOST_BOOT_RNG_EXISTS_LOCAL_BIT_SIZE 0x1UL 146 #define CC_HOST_BOOT_PKA_EXISTS_LOCAL_BIT_SHIFT 0xCUL 147 #define CC_HOST_BOOT_PKA_EXISTS_LOCAL_BIT_SIZE 0x1UL 148 #define CC_HOST_BOOT_RC4_EXISTS_LOCAL_BIT_SHIFT 0xDUL 149 #define CC_HOST_BOOT_RC4_EXISTS_LOCAL_BIT_SIZE 0x1UL 150 #define CC_HOST_BOOT_SHA_512_PRSNT_LOCAL_BIT_SHIFT 0xEUL 151 #define CC_HOST_BOOT_SHA_512_PRSNT_LOCAL_BIT_SIZE 0x1UL 152 #define CC_HOST_BOOT_SHA_256_PRSNT_LOCAL_BIT_SHIFT 0xFUL 153 #define CC_HOST_BOOT_SHA_256_PRSNT_LOCAL_BIT_SIZE 0x1UL 154 #define CC_HOST_BOOT_MD5_PRSNT_LOCAL_BIT_SHIFT 0x10UL 155 #define CC_HOST_BOOT_MD5_PRSNT_LOCAL_BIT_SIZE 0x1UL 156 #define CC_HOST_BOOT_HASH_EXISTS_LOCAL_BIT_SHIFT 0x11UL 157 #define CC_HOST_BOOT_HASH_EXISTS_LOCAL_BIT_SIZE 0x1UL 158 #define CC_HOST_BOOT_C2_EXISTS_LOCAL_BIT_SHIFT 0x12UL 159 #define CC_HOST_BOOT_C2_EXISTS_LOCAL_BIT_SIZE 0x1UL 160 #define CC_HOST_BOOT_DES_EXISTS_LOCAL_BIT_SHIFT 0x13UL 161 #define CC_HOST_BOOT_DES_EXISTS_LOCAL_BIT_SIZE 0x1UL 162 #define CC_HOST_BOOT_AES_XCBC_MAC_EXISTS_LOCAL_BIT_SHIFT 0x14UL 163 #define CC_HOST_BOOT_AES_XCBC_MAC_EXISTS_LOCAL_BIT_SIZE 0x1UL 164 #define CC_HOST_BOOT_AES_CMAC_EXISTS_LOCAL_BIT_SHIFT 0x15UL 165 #define CC_HOST_BOOT_AES_CMAC_EXISTS_LOCAL_BIT_SIZE 0x1UL 166 #define CC_HOST_BOOT_AES_CCM_EXISTS_LOCAL_BIT_SHIFT 0x16UL 167 #define CC_HOST_BOOT_AES_CCM_EXISTS_LOCAL_BIT_SIZE 0x1UL 168 #define CC_HOST_BOOT_AES_XEX_HW_T_CALC_LOCAL_BIT_SHIFT 0x17UL 169 #define CC_HOST_BOOT_AES_XEX_HW_T_CALC_LOCAL_BIT_SIZE 0x1UL 170 #define CC_HOST_BOOT_AES_XEX_EXISTS_LOCAL_BIT_SHIFT 0x18UL 171 #define CC_HOST_BOOT_AES_XEX_EXISTS_LOCAL_BIT_SIZE 0x1UL 172 #define CC_HOST_BOOT_CTR_EXISTS_LOCAL_BIT_SHIFT 0x19UL 173 #define CC_HOST_BOOT_CTR_EXISTS_LOCAL_BIT_SIZE 0x1UL 174 #define CC_HOST_BOOT_AES_DIN_BYTE_RESOLUTION_LOCAL_BIT_SHIFT 0x1AUL 175 #define CC_HOST_BOOT_AES_DIN_BYTE_RESOLUTION_LOCAL_BIT_SIZE 0x1UL 176 #define CC_HOST_BOOT_TUNNELING_ENB_LOCAL_BIT_SHIFT 0x1BUL 177 #define CC_HOST_BOOT_TUNNELING_ENB_LOCAL_BIT_SIZE 0x1UL 178 #define CC_HOST_BOOT_SUPPORT_256_192_KEY_LOCAL_BIT_SHIFT 0x1CUL 179 #define CC_HOST_BOOT_SUPPORT_256_192_KEY_LOCAL_BIT_SIZE 0x1UL 180 #define CC_HOST_BOOT_ONLY_ENCRYPT_LOCAL_BIT_SHIFT 0x1DUL 181 #define CC_HOST_BOOT_ONLY_ENCRYPT_LOCAL_BIT_SIZE 0x1UL 182 #define CC_HOST_BOOT_AES_EXISTS_LOCAL_BIT_SHIFT 0x1EUL 183 #define CC_HOST_BOOT_AES_EXISTS_LOCAL_BIT_SIZE 0x1UL 184 #define CC_HOST_VERSION_712_REG_OFFSET 0xA40UL 185 #define CC_HOST_VERSION_630_REG_OFFSET 0xAD8UL 186 #define CC_HOST_VERSION_VALUE_BIT_SHIFT 0x0UL 187 #define CC_HOST_VERSION_VALUE_BIT_SIZE 0x20UL 188 #define CC_HOST_KFDE0_VALID_REG_OFFSET 0xA60UL 189 #define CC_HOST_KFDE0_VALID_VALUE_BIT_SHIFT 0x0UL 190 #define CC_HOST_KFDE0_VALID_VALUE_BIT_SIZE 0x1UL 191 #define CC_HOST_KFDE1_VALID_REG_OFFSET 0xA64UL 192 #define CC_HOST_KFDE1_VALID_VALUE_BIT_SHIFT 0x0UL 193 #define CC_HOST_KFDE1_VALID_VALUE_BIT_SIZE 0x1UL 194 #define CC_HOST_KFDE2_VALID_REG_OFFSET 0xA68UL 195 #define CC_HOST_KFDE2_VALID_VALUE_BIT_SHIFT 0x0UL 196 #define CC_HOST_KFDE2_VALID_VALUE_BIT_SIZE 0x1UL 197 #define CC_HOST_KFDE3_VALID_REG_OFFSET 0xA6CUL 198 #define CC_HOST_KFDE3_VALID_VALUE_BIT_SHIFT 0x0UL 199 #define CC_HOST_KFDE3_VALID_VALUE_BIT_SIZE 0x1UL 200 #define CC_HOST_GPR0_REG_OFFSET 0xA70UL 201 #define CC_HOST_GPR0_VALUE_BIT_SHIFT 0x0UL 202 #define CC_HOST_GPR0_VALUE_BIT_SIZE 0x20UL 203 #define CC_GPR_HOST_REG_OFFSET 0xA74UL 204 #define CC_GPR_HOST_VALUE_BIT_SHIFT 0x0UL 205 #define CC_GPR_HOST_VALUE_BIT_SIZE 0x20UL 206 #define CC_HOST_POWER_DOWN_EN_REG_OFFSET 0xA78UL 207 #define CC_HOST_POWER_DOWN_EN_VALUE_BIT_SHIFT 0x0UL 208 #define CC_HOST_POWER_DOWN_EN_VALUE_BIT_SIZE 0x1UL 209 #define CC_HOST_REMOVE_INPUT_PINS_REG_OFFSET 0x0A7CUL 210 #define CC_HOST_REMOVE_INPUT_PINS_REMOVE_AES_ENGINE_BIT_SHIFT 0x0UL 211 #define CC_HOST_REMOVE_INPUT_PINS_REMOVE_AES_ENGINE_BIT_SIZE 0x1UL 212 #define CC_HOST_REMOVE_INPUT_PINS_REMOVE_AES_MAC_ENGINE_BIT_SHIFT 0x1UL 213 #define CC_HOST_REMOVE_INPUT_PINS_REMOVE_AES_MAC_ENGINE_BIT_SIZE 0x1UL 214 #define CC_HOST_REMOVE_INPUT_PINS_REMOVE_GHASH_ENGINE_BIT_SHIFT 0x2UL 215 #define CC_HOST_REMOVE_INPUT_PINS_REMOVE_GHASH_ENGINE_BIT_SIZE 0x1UL 216 #define CC_HOST_REMOVE_INPUT_PINS_REMOVE_DES_ENGINE_BIT_SHIFT 0x3UL 217 #define CC_HOST_REMOVE_INPUT_PINS_REMOVE_DES_ENGINE_BIT_SIZE 0x1UL 218 #define CC_HOST_REMOVE_INPUT_PINS_REMOVE_HASH_ENGINE_BIT_SHIFT 0x4UL 219 #define CC_HOST_REMOVE_INPUT_PINS_REMOVE_HASH_ENGINE_BIT_SIZE 0x1UL 220 #define CC_HOST_REMOVE_INPUT_PINS_REMOVE_SM3_ENGINE_BIT_SHIFT 0x5UL 221 #define CC_HOST_REMOVE_INPUT_PINS_REMOVE_SM3_ENGINE_BIT_SIZE 0x1UL 222 #define CC_HOST_REMOVE_INPUT_PINS_REMOVE_SM4_ENGINE_BIT_SHIFT 0x6UL 223 #define CC_HOST_REMOVE_INPUT_PINS_REMOVE_SM4_ENGINE_BIT_SIZE 0x1UL 224 #define CC_HOST_REMOVE_INPUT_PINS_OTP_DISCONNECTED_BIT_SHIFT 0x7UL 225 #define CC_HOST_REMOVE_INPUT_PINS_OTP_DISCONNECTED_BIT_SIZE 0x1UL 226 // -------------------------------------- 227 // BLOCK: ID_REGISTERS 228 // -------------------------------------- 229 #define CC_PERIPHERAL_ID_4_REG_OFFSET 0x0FD0UL 230 #define CC_PERIPHERAL_ID_4_VALUE_BIT_SHIFT 0x0UL 231 #define CC_PERIPHERAL_ID_4_VALUE_BIT_SIZE 0x4UL 232 #define CC_PIDRESERVED0_REG_OFFSET 0x0FD4UL 233 #define CC_PIDRESERVED1_REG_OFFSET 0x0FD8UL 234 #define CC_PIDRESERVED2_REG_OFFSET 0x0FDCUL 235 #define CC_PERIPHERAL_ID_0_REG_OFFSET 0x0FE0UL 236 #define CC_PERIPHERAL_ID_0_VALUE_BIT_SHIFT 0x0UL 237 #define CC_PERIPHERAL_ID_0_VALUE_BIT_SIZE 0x8UL 238 #define CC_PERIPHERAL_ID_1_REG_OFFSET 0x0FE4UL 239 #define CC_PERIPHERAL_ID_1_PART_1_BIT_SHIFT 0x0UL 240 #define CC_PERIPHERAL_ID_1_PART_1_BIT_SIZE 0x4UL 241 #define CC_PERIPHERAL_ID_1_DES_0_JEP106_BIT_SHIFT 0x4UL 242 #define CC_PERIPHERAL_ID_1_DES_0_JEP106_BIT_SIZE 0x4UL 243 #define CC_PERIPHERAL_ID_2_REG_OFFSET 0x0FE8UL 244 #define CC_PERIPHERAL_ID_2_DES_1_JEP106_BIT_SHIFT 0x0UL 245 #define CC_PERIPHERAL_ID_2_DES_1_JEP106_BIT_SIZE 0x3UL 246 #define CC_PERIPHERAL_ID_2_JEDEC_BIT_SHIFT 0x3UL 247 #define CC_PERIPHERAL_ID_2_JEDEC_BIT_SIZE 0x1UL 248 #define CC_PERIPHERAL_ID_2_REVISION_BIT_SHIFT 0x4UL 249 #define CC_PERIPHERAL_ID_2_REVISION_BIT_SIZE 0x4UL 250 #define CC_PERIPHERAL_ID_3_REG_OFFSET 0x0FECUL 251 #define CC_PERIPHERAL_ID_3_CMOD_BIT_SHIFT 0x0UL 252 #define CC_PERIPHERAL_ID_3_CMOD_BIT_SIZE 0x4UL 253 #define CC_PERIPHERAL_ID_3_REVAND_BIT_SHIFT 0x4UL 254 #define CC_PERIPHERAL_ID_3_REVAND_BIT_SIZE 0x4UL 255 #define CC_COMPONENT_ID_0_REG_OFFSET 0x0FF0UL 256 #define CC_COMPONENT_ID_0_VALUE_BIT_SHIFT 0x0UL 257 #define CC_COMPONENT_ID_0_VALUE_BIT_SIZE 0x8UL 258 #define CC_COMPONENT_ID_1_REG_OFFSET 0x0FF4UL 259 #define CC_COMPONENT_ID_1_PRMBL_1_BIT_SHIFT 0x0UL 260 #define CC_COMPONENT_ID_1_PRMBL_1_BIT_SIZE 0x4UL 261 #define CC_COMPONENT_ID_1_CLASS_BIT_SHIFT 0x4UL 262 #define CC_COMPONENT_ID_1_CLASS_BIT_SIZE 0x4UL 263 #define CC_COMPONENT_ID_2_REG_OFFSET 0x0FF8UL 264 #define CC_COMPONENT_ID_2_VALUE_BIT_SHIFT 0x0UL 265 #define CC_COMPONENT_ID_2_VALUE_BIT_SIZE 0x8UL 266 #define CC_COMPONENT_ID_3_REG_OFFSET 0x0FFCUL 267 #define CC_COMPONENT_ID_3_VALUE_BIT_SHIFT 0x0UL 268 #define CC_COMPONENT_ID_3_VALUE_BIT_SIZE 0x8UL 269 // -------------------------------------- 270 // BLOCK: HOST_SRAM 271 // -------------------------------------- 272 #define CC_SRAM_DATA_REG_OFFSET 0xF00UL 273 #define CC_SRAM_DATA_VALUE_BIT_SHIFT 0x0UL 274 #define CC_SRAM_DATA_VALUE_BIT_SIZE 0x20UL 275 #define CC_SRAM_ADDR_REG_OFFSET 0xF04UL 276 #define CC_SRAM_ADDR_VALUE_BIT_SHIFT 0x0UL 277 #define CC_SRAM_ADDR_VALUE_BIT_SIZE 0xFUL 278 #define CC_SRAM_DATA_READY_REG_OFFSET 0xF08UL 279 #define CC_SRAM_DATA_READY_VALUE_BIT_SHIFT 0x0UL 280 #define CC_SRAM_DATA_READY_VALUE_BIT_SIZE 0x1UL 281 282 #endif //__CC_HOST_H__ 283