xref: /linux/drivers/crypto/ccp/psp-dev.h (revision 2697b79a469b68e3ad3640f55284359c1396278d)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * AMD Platform Security Processor (PSP) interface driver
4  *
5  * Copyright (C) 2017-2019 Advanced Micro Devices, Inc.
6  *
7  * Author: Brijesh Singh <brijesh.singh@amd.com>
8  */
9 
10 #ifndef __PSP_DEV_H__
11 #define __PSP_DEV_H__
12 
13 #include <linux/device.h>
14 #include <linux/list.h>
15 #include <linux/bits.h>
16 #include <linux/interrupt.h>
17 #include <linux/mutex.h>
18 #include <linux/psp.h>
19 #include <linux/psp-platform-access.h>
20 
21 #include "sp-dev.h"
22 
23 #define MAX_PSP_NAME_LEN		16
24 
25 extern struct psp_device *psp_master;
26 
27 typedef void (*psp_irq_handler_t)(int, void *, unsigned int);
28 
29 struct psp_device {
30 	struct list_head entry;
31 
32 	struct psp_vdata *vdata;
33 	char name[MAX_PSP_NAME_LEN];
34 
35 	struct device *dev;
36 	struct sp_device *sp;
37 
38 	void __iomem *io_regs;
39 	struct mutex mailbox_mutex;
40 
41 	psp_irq_handler_t sev_irq_handler;
42 	void *sev_irq_data;
43 
44 	void *sev_data;
45 	void *tee_data;
46 	void *platform_access_data;
47 	void *dbc_data;
48 
49 	unsigned int capability;
50 };
51 
52 void psp_set_sev_irq_handler(struct psp_device *psp, psp_irq_handler_t handler,
53 			     void *data);
54 void psp_clear_sev_irq_handler(struct psp_device *psp);
55 
56 struct psp_device *psp_get_master_device(void);
57 
58 #define PSP_CAPABILITY_SEV			BIT(0)
59 #define PSP_CAPABILITY_TEE			BIT(1)
60 #define PSP_CAPABILITY_DBC_THRU_EXT		BIT(2)
61 #define PSP_CAPABILITY_PSP_SECURITY_REPORTING	BIT(7)
62 
63 #define PSP_CAPABILITY_PSP_SECURITY_OFFSET	8
64 /*
65  * The PSP doesn't directly store these bits in the capability register
66  * but instead copies them from the results of query command.
67  *
68  * The offsets from the query command are below, and shifted when used.
69  */
70 #define PSP_SECURITY_FUSED_PART			BIT(0)
71 #define PSP_SECURITY_DEBUG_LOCK_ON		BIT(2)
72 #define PSP_SECURITY_TSME_STATUS		BIT(5)
73 #define PSP_SECURITY_ANTI_ROLLBACK_STATUS	BIT(7)
74 #define PSP_SECURITY_RPMC_PRODUCTION_ENABLED	BIT(8)
75 #define PSP_SECURITY_RPMC_SPIROM_AVAILABLE	BIT(9)
76 #define PSP_SECURITY_HSP_TPM_AVAILABLE		BIT(10)
77 #define PSP_SECURITY_ROM_ARMOR_ENFORCED		BIT(11)
78 
79 /**
80  * enum psp_cmd - PSP mailbox commands
81  * @PSP_CMD_TEE_RING_INIT:	Initialize TEE ring buffer
82  * @PSP_CMD_TEE_RING_DESTROY:	Destroy TEE ring buffer
83  * @PSP_CMD_TEE_EXTENDED_CMD:	Extended command
84  * @PSP_CMD_MAX:		Maximum command id
85  */
86 enum psp_cmd {
87 	PSP_CMD_TEE_RING_INIT		= 1,
88 	PSP_CMD_TEE_RING_DESTROY	= 2,
89 	PSP_CMD_TEE_EXTENDED_CMD	= 14,
90 	PSP_CMD_MAX			= 15,
91 };
92 
93 int psp_mailbox_command(struct psp_device *psp, enum psp_cmd cmd, void *cmdbuff,
94 			unsigned int timeout_msecs, unsigned int *cmdresp);
95 
96 /**
97  * struct psp_ext_req_buffer_hdr - Structure of the extended command header
98  * @payload_size: total payload size
99  * @sub_cmd_id: extended command ID
100  * @status: status of command execution (out)
101  */
102 struct psp_ext_req_buffer_hdr {
103 	u32 payload_size;
104 	u32 sub_cmd_id;
105 	u32 status;
106 } __packed;
107 
108 struct psp_ext_request {
109 	struct psp_ext_req_buffer_hdr header;
110 	void *buf;
111 } __packed;
112 
113 /**
114  * enum psp_sub_cmd - PSP mailbox sub commands
115  * @PSP_SUB_CMD_DBC_GET_NONCE:		Get nonce from DBC
116  * @PSP_SUB_CMD_DBC_SET_UID:		Set UID for DBC
117  * @PSP_SUB_CMD_DBC_GET_PARAMETER:	Get parameter from DBC
118  * @PSP_SUB_CMD_DBC_SET_PARAMETER:	Set parameter for DBC
119  */
120 enum psp_sub_cmd {
121 	PSP_SUB_CMD_DBC_GET_NONCE	= PSP_DYNAMIC_BOOST_GET_NONCE,
122 	PSP_SUB_CMD_DBC_SET_UID		= PSP_DYNAMIC_BOOST_SET_UID,
123 	PSP_SUB_CMD_DBC_GET_PARAMETER	= PSP_DYNAMIC_BOOST_GET_PARAMETER,
124 	PSP_SUB_CMD_DBC_SET_PARAMETER	= PSP_DYNAMIC_BOOST_SET_PARAMETER,
125 };
126 
127 int psp_extended_mailbox_cmd(struct psp_device *psp, unsigned int timeout_msecs,
128 			     struct psp_ext_request *req);
129 #endif /* __PSP_DEV_H */
130