1 /* 2 * AMD Cryptographic Coprocessor (CCP) driver 3 * 4 * Copyright (C) 2013 Advanced Micro Devices, Inc. 5 * 6 * Author: Tom Lendacky <thomas.lendacky@amd.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #ifndef __CCP_DEV_H__ 14 #define __CCP_DEV_H__ 15 16 #include <linux/device.h> 17 #include <linux/pci.h> 18 #include <linux/spinlock.h> 19 #include <linux/mutex.h> 20 #include <linux/list.h> 21 #include <linux/wait.h> 22 #include <linux/dmapool.h> 23 #include <linux/hw_random.h> 24 25 26 #define IO_OFFSET 0x20000 27 28 #define MAX_DMAPOOL_NAME_LEN 32 29 30 #define MAX_HW_QUEUES 5 31 #define MAX_CMD_QLEN 100 32 33 #define TRNG_RETRIES 10 34 35 36 /****** Register Mappings ******/ 37 #define Q_MASK_REG 0x000 38 #define TRNG_OUT_REG 0x00c 39 #define IRQ_MASK_REG 0x040 40 #define IRQ_STATUS_REG 0x200 41 42 #define DEL_CMD_Q_JOB 0x124 43 #define DEL_Q_ACTIVE 0x00000200 44 #define DEL_Q_ID_SHIFT 6 45 46 #define CMD_REQ0 0x180 47 #define CMD_REQ_INCR 0x04 48 49 #define CMD_Q_STATUS_BASE 0x210 50 #define CMD_Q_INT_STATUS_BASE 0x214 51 #define CMD_Q_STATUS_INCR 0x20 52 53 #define CMD_Q_CACHE 0x228 54 #define CMD_Q_CACHE_INC 0x20 55 56 #define CMD_Q_ERROR(__qs) ((__qs) & 0x0000003f); 57 #define CMD_Q_DEPTH(__qs) (((__qs) >> 12) & 0x0000000f); 58 59 /****** REQ0 Related Values ******/ 60 #define REQ0_WAIT_FOR_WRITE 0x00000004 61 #define REQ0_INT_ON_COMPLETE 0x00000002 62 #define REQ0_STOP_ON_COMPLETE 0x00000001 63 64 #define REQ0_CMD_Q_SHIFT 9 65 #define REQ0_JOBID_SHIFT 3 66 67 /****** REQ1 Related Values ******/ 68 #define REQ1_PROTECT_SHIFT 27 69 #define REQ1_ENGINE_SHIFT 23 70 #define REQ1_KEY_KSB_SHIFT 2 71 72 #define REQ1_EOM 0x00000002 73 #define REQ1_INIT 0x00000001 74 75 /* AES Related Values */ 76 #define REQ1_AES_TYPE_SHIFT 21 77 #define REQ1_AES_MODE_SHIFT 18 78 #define REQ1_AES_ACTION_SHIFT 17 79 #define REQ1_AES_CFB_SIZE_SHIFT 10 80 81 /* XTS-AES Related Values */ 82 #define REQ1_XTS_AES_SIZE_SHIFT 10 83 84 /* SHA Related Values */ 85 #define REQ1_SHA_TYPE_SHIFT 21 86 87 /* RSA Related Values */ 88 #define REQ1_RSA_MOD_SIZE_SHIFT 10 89 90 /* Pass-Through Related Values */ 91 #define REQ1_PT_BW_SHIFT 12 92 #define REQ1_PT_BS_SHIFT 10 93 94 /* ECC Related Values */ 95 #define REQ1_ECC_AFFINE_CONVERT 0x00200000 96 #define REQ1_ECC_FUNCTION_SHIFT 18 97 98 /****** REQ4 Related Values ******/ 99 #define REQ4_KSB_SHIFT 18 100 #define REQ4_MEMTYPE_SHIFT 16 101 102 /****** REQ6 Related Values ******/ 103 #define REQ6_MEMTYPE_SHIFT 16 104 105 106 /****** Key Storage Block ******/ 107 #define KSB_START 77 108 #define KSB_END 127 109 #define KSB_COUNT (KSB_END - KSB_START + 1) 110 #define CCP_KSB_BITS 256 111 #define CCP_KSB_BYTES 32 112 113 #define CCP_JOBID_MASK 0x0000003f 114 115 #define CCP_DMAPOOL_MAX_SIZE 64 116 #define CCP_DMAPOOL_ALIGN (1 << 5) 117 118 #define CCP_REVERSE_BUF_SIZE 64 119 120 #define CCP_AES_KEY_KSB_COUNT 1 121 #define CCP_AES_CTX_KSB_COUNT 1 122 123 #define CCP_XTS_AES_KEY_KSB_COUNT 1 124 #define CCP_XTS_AES_CTX_KSB_COUNT 1 125 126 #define CCP_SHA_KSB_COUNT 1 127 128 #define CCP_RSA_MAX_WIDTH 4096 129 130 #define CCP_PASSTHRU_BLOCKSIZE 256 131 #define CCP_PASSTHRU_MASKSIZE 32 132 #define CCP_PASSTHRU_KSB_COUNT 1 133 134 #define CCP_ECC_MODULUS_BYTES 48 /* 384-bits */ 135 #define CCP_ECC_MAX_OPERANDS 6 136 #define CCP_ECC_MAX_OUTPUTS 3 137 #define CCP_ECC_SRC_BUF_SIZE 448 138 #define CCP_ECC_DST_BUF_SIZE 192 139 #define CCP_ECC_OPERAND_SIZE 64 140 #define CCP_ECC_OUTPUT_SIZE 64 141 #define CCP_ECC_RESULT_OFFSET 60 142 #define CCP_ECC_RESULT_SUCCESS 0x0001 143 144 145 struct ccp_device; 146 struct ccp_cmd; 147 148 struct ccp_cmd_queue { 149 struct ccp_device *ccp; 150 151 /* Queue identifier */ 152 u32 id; 153 154 /* Queue dma pool */ 155 struct dma_pool *dma_pool; 156 157 /* Queue reserved KSB regions */ 158 u32 ksb_key; 159 u32 ksb_ctx; 160 161 /* Queue processing thread */ 162 struct task_struct *kthread; 163 unsigned int active; 164 unsigned int suspended; 165 166 /* Number of free command slots available */ 167 unsigned int free_slots; 168 169 /* Interrupt masks */ 170 u32 int_ok; 171 u32 int_err; 172 173 /* Register addresses for queue */ 174 void __iomem *reg_status; 175 void __iomem *reg_int_status; 176 177 /* Status values from job */ 178 u32 int_status; 179 u32 q_status; 180 u32 q_int_status; 181 u32 cmd_error; 182 183 /* Interrupt wait queue */ 184 wait_queue_head_t int_queue; 185 unsigned int int_rcvd; 186 } ____cacheline_aligned; 187 188 struct ccp_device { 189 struct device *dev; 190 191 /* 192 * Bus specific device information 193 */ 194 void *dev_specific; 195 int (*get_irq)(struct ccp_device *ccp); 196 void (*free_irq)(struct ccp_device *ccp); 197 198 /* 199 * I/O area used for device communication. The register mapping 200 * starts at an offset into the mapped bar. 201 * The CMD_REQx registers and the Delete_Cmd_Queue_Job register 202 * need to be protected while a command queue thread is accessing 203 * them. 204 */ 205 struct mutex req_mutex ____cacheline_aligned; 206 void __iomem *io_map; 207 void __iomem *io_regs; 208 209 /* 210 * Master lists that all cmds are queued on. Because there can be 211 * more than one CCP command queue that can process a cmd a separate 212 * backlog list is neeeded so that the backlog completion call 213 * completes before the cmd is available for execution. 214 */ 215 spinlock_t cmd_lock ____cacheline_aligned; 216 unsigned int cmd_count; 217 struct list_head cmd; 218 struct list_head backlog; 219 220 /* 221 * The command queues. These represent the queues available on the 222 * CCP that are available for processing cmds 223 */ 224 struct ccp_cmd_queue cmd_q[MAX_HW_QUEUES]; 225 unsigned int cmd_q_count; 226 227 /* 228 * Support for the CCP True RNG 229 */ 230 struct hwrng hwrng; 231 unsigned int hwrng_retries; 232 233 /* 234 * A counter used to generate job-ids for cmds submitted to the CCP 235 */ 236 atomic_t current_id ____cacheline_aligned; 237 238 /* 239 * The CCP uses key storage blocks (KSB) to maintain context for certain 240 * operations. To prevent multiple cmds from using the same KSB range 241 * a command queue reserves a KSB range for the duration of the cmd. 242 * Each queue, will however, reserve 2 KSB blocks for operations that 243 * only require single KSB entries (eg. AES context/iv and key) in order 244 * to avoid allocation contention. This will reserve at most 10 KSB 245 * entries, leaving 40 KSB entries available for dynamic allocation. 246 */ 247 struct mutex ksb_mutex ____cacheline_aligned; 248 DECLARE_BITMAP(ksb, KSB_COUNT); 249 wait_queue_head_t ksb_queue; 250 unsigned int ksb_avail; 251 unsigned int ksb_count; 252 u32 ksb_start; 253 254 /* Suspend support */ 255 unsigned int suspending; 256 wait_queue_head_t suspend_queue; 257 }; 258 259 260 int ccp_pci_init(void); 261 void ccp_pci_exit(void); 262 263 struct ccp_device *ccp_alloc_struct(struct device *dev); 264 int ccp_init(struct ccp_device *ccp); 265 void ccp_destroy(struct ccp_device *ccp); 266 bool ccp_queues_suspended(struct ccp_device *ccp); 267 268 irqreturn_t ccp_irq_handler(int irq, void *data); 269 270 int ccp_run_cmd(struct ccp_cmd_queue *cmd_q, struct ccp_cmd *cmd); 271 272 #endif 273