1 /* 2 * AMD Cryptographic Coprocessor (CCP) driver 3 * 4 * Copyright (C) 2013,2016 Advanced Micro Devices, Inc. 5 * 6 * Author: Tom Lendacky <thomas.lendacky@amd.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #ifndef __CCP_DEV_H__ 14 #define __CCP_DEV_H__ 15 16 #include <linux/device.h> 17 #include <linux/pci.h> 18 #include <linux/spinlock.h> 19 #include <linux/mutex.h> 20 #include <linux/list.h> 21 #include <linux/wait.h> 22 #include <linux/dmapool.h> 23 #include <linux/hw_random.h> 24 #include <linux/bitops.h> 25 26 #define MAX_CCP_NAME_LEN 16 27 #define MAX_DMAPOOL_NAME_LEN 32 28 29 #define MAX_HW_QUEUES 5 30 #define MAX_CMD_QLEN 100 31 32 #define TRNG_RETRIES 10 33 34 #define CACHE_NONE 0x00 35 #define CACHE_WB_NO_ALLOC 0xb7 36 37 /****** Register Mappings ******/ 38 #define Q_MASK_REG 0x000 39 #define TRNG_OUT_REG 0x00c 40 #define IRQ_MASK_REG 0x040 41 #define IRQ_STATUS_REG 0x200 42 43 #define DEL_CMD_Q_JOB 0x124 44 #define DEL_Q_ACTIVE 0x00000200 45 #define DEL_Q_ID_SHIFT 6 46 47 #define CMD_REQ0 0x180 48 #define CMD_REQ_INCR 0x04 49 50 #define CMD_Q_STATUS_BASE 0x210 51 #define CMD_Q_INT_STATUS_BASE 0x214 52 #define CMD_Q_STATUS_INCR 0x20 53 54 #define CMD_Q_CACHE_BASE 0x228 55 #define CMD_Q_CACHE_INC 0x20 56 57 #define CMD_Q_ERROR(__qs) ((__qs) & 0x0000003f) 58 #define CMD_Q_DEPTH(__qs) (((__qs) >> 12) & 0x0000000f) 59 60 /****** REQ0 Related Values ******/ 61 #define REQ0_WAIT_FOR_WRITE 0x00000004 62 #define REQ0_INT_ON_COMPLETE 0x00000002 63 #define REQ0_STOP_ON_COMPLETE 0x00000001 64 65 #define REQ0_CMD_Q_SHIFT 9 66 #define REQ0_JOBID_SHIFT 3 67 68 /****** REQ1 Related Values ******/ 69 #define REQ1_PROTECT_SHIFT 27 70 #define REQ1_ENGINE_SHIFT 23 71 #define REQ1_KEY_KSB_SHIFT 2 72 73 #define REQ1_EOM 0x00000002 74 #define REQ1_INIT 0x00000001 75 76 /* AES Related Values */ 77 #define REQ1_AES_TYPE_SHIFT 21 78 #define REQ1_AES_MODE_SHIFT 18 79 #define REQ1_AES_ACTION_SHIFT 17 80 #define REQ1_AES_CFB_SIZE_SHIFT 10 81 82 /* XTS-AES Related Values */ 83 #define REQ1_XTS_AES_SIZE_SHIFT 10 84 85 /* SHA Related Values */ 86 #define REQ1_SHA_TYPE_SHIFT 21 87 88 /* RSA Related Values */ 89 #define REQ1_RSA_MOD_SIZE_SHIFT 10 90 91 /* Pass-Through Related Values */ 92 #define REQ1_PT_BW_SHIFT 12 93 #define REQ1_PT_BS_SHIFT 10 94 95 /* ECC Related Values */ 96 #define REQ1_ECC_AFFINE_CONVERT 0x00200000 97 #define REQ1_ECC_FUNCTION_SHIFT 18 98 99 /****** REQ4 Related Values ******/ 100 #define REQ4_KSB_SHIFT 18 101 #define REQ4_MEMTYPE_SHIFT 16 102 103 /****** REQ6 Related Values ******/ 104 #define REQ6_MEMTYPE_SHIFT 16 105 106 /****** Key Storage Block ******/ 107 #define KSB_START 77 108 #define KSB_END 127 109 #define KSB_COUNT (KSB_END - KSB_START + 1) 110 #define CCP_KSB_BITS 256 111 #define CCP_KSB_BYTES 32 112 113 #define CCP_JOBID_MASK 0x0000003f 114 115 #define CCP_DMAPOOL_MAX_SIZE 64 116 #define CCP_DMAPOOL_ALIGN BIT(5) 117 118 #define CCP_REVERSE_BUF_SIZE 64 119 120 #define CCP_AES_KEY_KSB_COUNT 1 121 #define CCP_AES_CTX_KSB_COUNT 1 122 123 #define CCP_XTS_AES_KEY_KSB_COUNT 1 124 #define CCP_XTS_AES_CTX_KSB_COUNT 1 125 126 #define CCP_SHA_KSB_COUNT 1 127 128 #define CCP_RSA_MAX_WIDTH 4096 129 130 #define CCP_PASSTHRU_BLOCKSIZE 256 131 #define CCP_PASSTHRU_MASKSIZE 32 132 #define CCP_PASSTHRU_KSB_COUNT 1 133 134 #define CCP_ECC_MODULUS_BYTES 48 /* 384-bits */ 135 #define CCP_ECC_MAX_OPERANDS 6 136 #define CCP_ECC_MAX_OUTPUTS 3 137 #define CCP_ECC_SRC_BUF_SIZE 448 138 #define CCP_ECC_DST_BUF_SIZE 192 139 #define CCP_ECC_OPERAND_SIZE 64 140 #define CCP_ECC_OUTPUT_SIZE 64 141 #define CCP_ECC_RESULT_OFFSET 60 142 #define CCP_ECC_RESULT_SUCCESS 0x0001 143 144 struct ccp_device; 145 struct ccp_cmd; 146 147 struct ccp_cmd_queue { 148 struct ccp_device *ccp; 149 150 /* Queue identifier */ 151 u32 id; 152 153 /* Queue dma pool */ 154 struct dma_pool *dma_pool; 155 156 /* Queue reserved KSB regions */ 157 u32 ksb_key; 158 u32 ksb_ctx; 159 160 /* Queue processing thread */ 161 struct task_struct *kthread; 162 unsigned int active; 163 unsigned int suspended; 164 165 /* Number of free command slots available */ 166 unsigned int free_slots; 167 168 /* Interrupt masks */ 169 u32 int_ok; 170 u32 int_err; 171 172 /* Register addresses for queue */ 173 void __iomem *reg_status; 174 void __iomem *reg_int_status; 175 176 /* Status values from job */ 177 u32 int_status; 178 u32 q_status; 179 u32 q_int_status; 180 u32 cmd_error; 181 182 /* Interrupt wait queue */ 183 wait_queue_head_t int_queue; 184 unsigned int int_rcvd; 185 } ____cacheline_aligned; 186 187 struct ccp_device { 188 struct list_head entry; 189 190 unsigned int ord; 191 char name[MAX_CCP_NAME_LEN]; 192 char rngname[MAX_CCP_NAME_LEN]; 193 194 struct device *dev; 195 196 /* 197 * Bus specific device information 198 */ 199 void *dev_specific; 200 int (*get_irq)(struct ccp_device *ccp); 201 void (*free_irq)(struct ccp_device *ccp); 202 unsigned int irq; 203 204 /* 205 * I/O area used for device communication. The register mapping 206 * starts at an offset into the mapped bar. 207 * The CMD_REQx registers and the Delete_Cmd_Queue_Job register 208 * need to be protected while a command queue thread is accessing 209 * them. 210 */ 211 struct mutex req_mutex ____cacheline_aligned; 212 void __iomem *io_map; 213 void __iomem *io_regs; 214 215 /* 216 * Master lists that all cmds are queued on. Because there can be 217 * more than one CCP command queue that can process a cmd a separate 218 * backlog list is neeeded so that the backlog completion call 219 * completes before the cmd is available for execution. 220 */ 221 spinlock_t cmd_lock ____cacheline_aligned; 222 unsigned int cmd_count; 223 struct list_head cmd; 224 struct list_head backlog; 225 226 /* 227 * The command queues. These represent the queues available on the 228 * CCP that are available for processing cmds 229 */ 230 struct ccp_cmd_queue cmd_q[MAX_HW_QUEUES]; 231 unsigned int cmd_q_count; 232 233 /* 234 * Support for the CCP True RNG 235 */ 236 struct hwrng hwrng; 237 unsigned int hwrng_retries; 238 239 /* 240 * A counter used to generate job-ids for cmds submitted to the CCP 241 */ 242 atomic_t current_id ____cacheline_aligned; 243 244 /* 245 * The CCP uses key storage blocks (KSB) to maintain context for certain 246 * operations. To prevent multiple cmds from using the same KSB range 247 * a command queue reserves a KSB range for the duration of the cmd. 248 * Each queue, will however, reserve 2 KSB blocks for operations that 249 * only require single KSB entries (eg. AES context/iv and key) in order 250 * to avoid allocation contention. This will reserve at most 10 KSB 251 * entries, leaving 40 KSB entries available for dynamic allocation. 252 */ 253 struct mutex ksb_mutex ____cacheline_aligned; 254 DECLARE_BITMAP(ksb, KSB_COUNT); 255 wait_queue_head_t ksb_queue; 256 unsigned int ksb_avail; 257 unsigned int ksb_count; 258 u32 ksb_start; 259 260 /* Suspend support */ 261 unsigned int suspending; 262 wait_queue_head_t suspend_queue; 263 264 /* DMA caching attribute support */ 265 unsigned int axcache; 266 }; 267 268 int ccp_pci_init(void); 269 void ccp_pci_exit(void); 270 271 int ccp_platform_init(void); 272 void ccp_platform_exit(void); 273 274 struct ccp_device *ccp_alloc_struct(struct device *dev); 275 int ccp_init(struct ccp_device *ccp); 276 void ccp_destroy(struct ccp_device *ccp); 277 bool ccp_queues_suspended(struct ccp_device *ccp); 278 279 irqreturn_t ccp_irq_handler(int irq, void *data); 280 281 int ccp_run_cmd(struct ccp_cmd_queue *cmd_q, struct ccp_cmd *cmd); 282 283 #endif 284