1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __NITROX_DEV_H 3 #define __NITROX_DEV_H 4 5 #include <linux/dma-mapping.h> 6 #include <linux/interrupt.h> 7 #include <linux/pci.h> 8 9 #define VERSION_LEN 32 10 11 struct nitrox_cmdq { 12 /* command queue lock */ 13 spinlock_t cmdq_lock; 14 /* response list lock */ 15 spinlock_t response_lock; 16 /* backlog list lock */ 17 spinlock_t backlog_lock; 18 19 /* request submitted to chip, in progress */ 20 struct list_head response_head; 21 /* hw queue full, hold in backlog list */ 22 struct list_head backlog_head; 23 24 /* doorbell address */ 25 u8 __iomem *dbell_csr_addr; 26 /* base address of the queue */ 27 u8 *head; 28 29 struct nitrox_device *ndev; 30 /* flush pending backlog commands */ 31 struct work_struct backlog_qflush; 32 33 /* requests posted waiting for completion */ 34 atomic_t pending_count; 35 /* requests in backlog queues */ 36 atomic_t backlog_count; 37 38 int write_idx; 39 /* command size 32B/64B */ 40 u8 instr_size; 41 u8 qno; 42 u32 qsize; 43 44 /* unaligned addresses */ 45 u8 *head_unaligned; 46 dma_addr_t dma_unaligned; 47 /* dma address of the base */ 48 dma_addr_t dma; 49 }; 50 51 struct nitrox_hw { 52 /* firmware version */ 53 char fw_name[VERSION_LEN]; 54 55 u16 vendor_id; 56 u16 device_id; 57 u8 revision_id; 58 59 /* CNN55XX cores */ 60 u8 se_cores; 61 u8 ae_cores; 62 u8 zip_cores; 63 }; 64 65 #define MAX_MSIX_VECTOR_NAME 20 66 /** 67 * vectors for queues (64 AE, 64 SE and 64 ZIP) and 68 * error condition/mailbox. 69 */ 70 #define MAX_MSIX_VECTORS 192 71 72 struct nitrox_msix { 73 struct msix_entry *entries; 74 char **names; 75 DECLARE_BITMAP(irqs, MAX_MSIX_VECTORS); 76 u32 nr_entries; 77 }; 78 79 struct bh_data { 80 /* slc port completion count address */ 81 u8 __iomem *completion_cnt_csr_addr; 82 83 struct nitrox_cmdq *cmdq; 84 struct tasklet_struct resp_handler; 85 }; 86 87 struct nitrox_bh { 88 struct bh_data *slc; 89 }; 90 91 /* 92 * NITROX Device states 93 */ 94 enum ndev_state { 95 __NDEV_NOT_READY, 96 __NDEV_READY, 97 __NDEV_IN_RESET, 98 }; 99 100 /* NITROX support modes for VF(s) */ 101 enum vf_mode { 102 __NDEV_MODE_PF, 103 __NDEV_MODE_VF16, 104 __NDEV_MODE_VF32, 105 __NDEV_MODE_VF64, 106 __NDEV_MODE_VF128, 107 }; 108 109 #define __NDEV_SRIOV_BIT 0 110 111 /* command queue size */ 112 #define DEFAULT_CMD_QLEN 2048 113 /* command timeout in milliseconds */ 114 #define CMD_TIMEOUT 2000 115 116 #define DEV(ndev) ((struct device *)(&(ndev)->pdev->dev)) 117 118 #define NITROX_CSR_ADDR(ndev, offset) \ 119 ((ndev)->bar_addr + (offset)) 120 121 /** 122 * struct nitrox_device - NITROX Device Information. 123 * @list: pointer to linked list of devices 124 * @bar_addr: iomap address 125 * @pdev: PCI device information 126 * @state: NITROX device state 127 * @flags: flags to indicate device the features 128 * @timeout: Request timeout in jiffies 129 * @refcnt: Device usage count 130 * @idx: device index (0..N) 131 * @node: NUMA node id attached 132 * @qlen: Command queue length 133 * @nr_queues: Number of command queues 134 * @mode: Device mode PF/VF 135 * @ctx_pool: DMA pool for crypto context 136 * @pkt_cmdqs: SE Command queues 137 * @msix: MSI-X information 138 * @bh: post processing work 139 * @hw: hardware information 140 * @debugfs_dir: debugfs directory 141 */ 142 struct nitrox_device { 143 struct list_head list; 144 145 u8 __iomem *bar_addr; 146 struct pci_dev *pdev; 147 148 atomic_t state; 149 unsigned long flags; 150 unsigned long timeout; 151 refcount_t refcnt; 152 153 u8 idx; 154 int node; 155 u16 qlen; 156 u16 nr_queues; 157 int num_vfs; 158 enum vf_mode mode; 159 160 struct dma_pool *ctx_pool; 161 struct nitrox_cmdq *pkt_cmdqs; 162 163 struct nitrox_msix msix; 164 struct nitrox_bh bh; 165 166 struct nitrox_hw hw; 167 #if IS_ENABLED(CONFIG_DEBUG_FS) 168 struct dentry *debugfs_dir; 169 #endif 170 }; 171 172 /** 173 * nitrox_read_csr - Read from device register 174 * @ndev: NITROX device 175 * @offset: offset of the register to read 176 * 177 * Returns: value read 178 */ 179 static inline u64 nitrox_read_csr(struct nitrox_device *ndev, u64 offset) 180 { 181 return readq(ndev->bar_addr + offset); 182 } 183 184 /** 185 * nitrox_write_csr - Write to device register 186 * @ndev: NITROX device 187 * @offset: offset of the register to write 188 * @value: value to write 189 */ 190 static inline void nitrox_write_csr(struct nitrox_device *ndev, u64 offset, 191 u64 value) 192 { 193 writeq(value, (ndev->bar_addr + offset)); 194 } 195 196 static inline bool nitrox_ready(struct nitrox_device *ndev) 197 { 198 return atomic_read(&ndev->state) == __NDEV_READY; 199 } 200 201 #endif /* __NITROX_DEV_H */ 202