1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __NITROX_DEV_H 3 #define __NITROX_DEV_H 4 5 #include <linux/dma-mapping.h> 6 #include <linux/interrupt.h> 7 #include <linux/pci.h> 8 #include <linux/if.h> 9 10 #define VERSION_LEN 32 11 /* Maximum queues in PF mode */ 12 #define MAX_PF_QUEUES 64 13 /* Maximum UCD Blocks */ 14 #define CNN55XX_MAX_UCD_BLOCKS 8 15 16 /** 17 * struct nitrox_cmdq - NITROX command queue 18 * @cmd_qlock: command queue lock 19 * @resp_qlock: response queue lock 20 * @backlog_qlock: backlog queue lock 21 * @ndev: NITROX device 22 * @response_head: submitted request list 23 * @backlog_head: backlog queue 24 * @dbell_csr_addr: doorbell register address for this queue 25 * @compl_cnt_csr_addr: completion count register address of the slc port 26 * @base: command queue base address 27 * @dma: dma address of the base 28 * @pending_count: request pending at device 29 * @backlog_count: backlog request count 30 * @write_idx: next write index for the command 31 * @instr_size: command size 32 * @qno: command queue number 33 * @qsize: command queue size 34 * @unalign_base: unaligned base address 35 * @unalign_dma: unaligned dma address 36 */ 37 struct nitrox_cmdq { 38 spinlock_t cmd_qlock; 39 spinlock_t resp_qlock; 40 spinlock_t backlog_qlock; 41 42 struct nitrox_device *ndev; 43 struct list_head response_head; 44 struct list_head backlog_head; 45 46 u8 __iomem *dbell_csr_addr; 47 u8 __iomem *compl_cnt_csr_addr; 48 u8 *base; 49 dma_addr_t dma; 50 51 struct work_struct backlog_qflush; 52 53 atomic_t pending_count; 54 atomic_t backlog_count; 55 56 int write_idx; 57 u8 instr_size; 58 u8 qno; 59 u32 qsize; 60 61 u8 *unalign_base; 62 dma_addr_t unalign_dma; 63 }; 64 65 /** 66 * struct nitrox_hw - NITROX hardware information 67 * @partname: partname ex: CNN55xxx-xxx 68 * @fw_name: firmware version 69 * @freq: NITROX frequency 70 * @vendor_id: vendor ID 71 * @device_id: device ID 72 * @revision_id: revision ID 73 * @se_cores: number of symmetric cores 74 * @ae_cores: number of asymmetric cores 75 * @zip_cores: number of zip cores 76 */ 77 struct nitrox_hw { 78 char partname[IFNAMSIZ * 2]; 79 char fw_name[CNN55XX_MAX_UCD_BLOCKS][VERSION_LEN]; 80 81 int freq; 82 u16 vendor_id; 83 u16 device_id; 84 u8 revision_id; 85 86 u8 se_cores; 87 u8 ae_cores; 88 u8 zip_cores; 89 }; 90 91 struct nitrox_stats { 92 atomic64_t posted; 93 atomic64_t completed; 94 atomic64_t dropped; 95 }; 96 97 #define IRQ_NAMESZ 32 98 99 struct nitrox_q_vector { 100 char name[IRQ_NAMESZ]; 101 bool valid; 102 int ring; 103 struct tasklet_struct resp_tasklet; 104 union { 105 struct nitrox_cmdq *cmdq; 106 struct nitrox_device *ndev; 107 }; 108 }; 109 110 /** 111 * mbox_msg - Mailbox message data 112 * @type: message type 113 * @opcode: message opcode 114 * @data: message data 115 */ 116 union mbox_msg { 117 u64 value; 118 struct { 119 u64 type: 2; 120 u64 opcode: 6; 121 u64 data: 58; 122 }; 123 struct { 124 u64 type: 2; 125 u64 opcode: 6; 126 u64 chipid: 8; 127 u64 vfid: 8; 128 } id; 129 }; 130 131 /** 132 * nitrox_vfdev - NITROX VF device instance in PF 133 * @state: VF device state 134 * @vfno: VF number 135 * @nr_queues: number of queues enabled in VF 136 * @ring: ring to communicate with VF 137 * @msg: Mailbox message data from VF 138 * @mbx_resp: Mailbox counters 139 */ 140 struct nitrox_vfdev { 141 atomic_t state; 142 int vfno; 143 int nr_queues; 144 int ring; 145 union mbox_msg msg; 146 atomic64_t mbx_resp; 147 }; 148 149 /** 150 * struct nitrox_iov - SR-IOV information 151 * @num_vfs: number of VF(s) enabled 152 * @max_vf_queues: Maximum number of queues allowed for VF 153 * @vfdev: VF(s) devices 154 * @pf2vf_wq: workqueue for PF2VF communication 155 * @msix: MSI-X entry for PF in SR-IOV case 156 */ 157 struct nitrox_iov { 158 int num_vfs; 159 int max_vf_queues; 160 struct nitrox_vfdev *vfdev; 161 struct workqueue_struct *pf2vf_wq; 162 struct msix_entry msix; 163 }; 164 165 /* 166 * NITROX Device states 167 */ 168 enum ndev_state { 169 __NDEV_NOT_READY, 170 __NDEV_READY, 171 __NDEV_IN_RESET, 172 }; 173 174 /* NITROX support modes for VF(s) */ 175 enum vf_mode { 176 __NDEV_MODE_PF, 177 __NDEV_MODE_VF16, 178 __NDEV_MODE_VF32, 179 __NDEV_MODE_VF64, 180 __NDEV_MODE_VF128, 181 }; 182 183 #define __NDEV_SRIOV_BIT 0 184 185 /* command queue size */ 186 #define DEFAULT_CMD_QLEN 2048 187 /* command timeout in milliseconds */ 188 #define CMD_TIMEOUT 2000 189 190 #define DEV(ndev) ((struct device *)(&(ndev)->pdev->dev)) 191 192 #define NITROX_CSR_ADDR(ndev, offset) \ 193 ((ndev)->bar_addr + (offset)) 194 195 /** 196 * struct nitrox_device - NITROX Device Information. 197 * @list: pointer to linked list of devices 198 * @bar_addr: iomap address 199 * @pdev: PCI device information 200 * @state: NITROX device state 201 * @flags: flags to indicate device the features 202 * @timeout: Request timeout in jiffies 203 * @refcnt: Device usage count 204 * @idx: device index (0..N) 205 * @node: NUMA node id attached 206 * @qlen: Command queue length 207 * @nr_queues: Number of command queues 208 * @mode: Device mode PF/VF 209 * @ctx_pool: DMA pool for crypto context 210 * @pkt_inq: Packet input rings 211 * @qvec: MSI-X queue vectors information 212 * @iov: SR-IOV informatin 213 * @num_vecs: number of MSI-X vectors 214 * @stats: request statistics 215 * @hw: hardware information 216 * @debugfs_dir: debugfs directory 217 */ 218 struct nitrox_device { 219 struct list_head list; 220 221 u8 __iomem *bar_addr; 222 struct pci_dev *pdev; 223 224 atomic_t state; 225 unsigned long flags; 226 unsigned long timeout; 227 refcount_t refcnt; 228 229 u8 idx; 230 int node; 231 u16 qlen; 232 u16 nr_queues; 233 enum vf_mode mode; 234 235 struct dma_pool *ctx_pool; 236 struct nitrox_cmdq *pkt_inq; 237 238 struct nitrox_q_vector *qvec; 239 struct nitrox_iov iov; 240 int num_vecs; 241 242 struct nitrox_stats stats; 243 struct nitrox_hw hw; 244 #if IS_ENABLED(CONFIG_DEBUG_FS) 245 struct dentry *debugfs_dir; 246 #endif 247 }; 248 249 /** 250 * nitrox_read_csr - Read from device register 251 * @ndev: NITROX device 252 * @offset: offset of the register to read 253 * 254 * Returns: value read 255 */ 256 static inline u64 nitrox_read_csr(struct nitrox_device *ndev, u64 offset) 257 { 258 return readq(ndev->bar_addr + offset); 259 } 260 261 /** 262 * nitrox_write_csr - Write to device register 263 * @ndev: NITROX device 264 * @offset: offset of the register to write 265 * @value: value to write 266 */ 267 static inline void nitrox_write_csr(struct nitrox_device *ndev, u64 offset, 268 u64 value) 269 { 270 writeq(value, (ndev->bar_addr + offset)); 271 } 272 273 static inline bool nitrox_ready(struct nitrox_device *ndev) 274 { 275 return atomic_read(&ndev->state) == __NDEV_READY; 276 } 277 278 static inline bool nitrox_vfdev_ready(struct nitrox_vfdev *vfdev) 279 { 280 return atomic_read(&vfdev->state) == __NDEV_READY; 281 } 282 283 #endif /* __NITROX_DEV_H */ 284