1 #ifndef __NITROX_CSR_H 2 #define __NITROX_CSR_H 3 4 #include <asm/byteorder.h> 5 #include <linux/types.h> 6 7 /* EMU clusters */ 8 #define NR_CLUSTERS 4 9 #define AE_CORES_PER_CLUSTER 20 10 #define SE_CORES_PER_CLUSTER 16 11 12 /* BIST registers */ 13 #define EMU_BIST_STATUSX(_i) (0x1402700 + ((_i) * 0x40000)) 14 #define UCD_BIST_STATUS 0x12C0070 15 #define NPS_CORE_BIST_REG 0x10000E8 16 #define NPS_CORE_NPC_BIST_REG 0x1000128 17 #define NPS_PKT_SLC_BIST_REG 0x1040088 18 #define NPS_PKT_IN_BIST_REG 0x1040100 19 #define POM_BIST_REG 0x11C0100 20 #define BMI_BIST_REG 0x1140080 21 #define EFL_CORE_BIST_REGX(_i) (0x1240100 + ((_i) * 0x400)) 22 #define EFL_TOP_BIST_STAT 0x1241090 23 #define BMO_BIST_REG 0x1180080 24 #define LBC_BIST_STATUS 0x1200020 25 #define PEM_BIST_STATUSX(_i) (0x1080468 | ((_i) << 18)) 26 27 /* EMU registers */ 28 #define EMU_SE_ENABLEX(_i) (0x1400000 + ((_i) * 0x40000)) 29 #define EMU_AE_ENABLEX(_i) (0x1400008 + ((_i) * 0x40000)) 30 #define EMU_WD_INT_ENA_W1SX(_i) (0x1402318 + ((_i) * 0x40000)) 31 #define EMU_GE_INT_ENA_W1SX(_i) (0x1402518 + ((_i) * 0x40000)) 32 #define EMU_FUSE_MAPX(_i) (0x1402708 + ((_i) * 0x40000)) 33 34 /* UCD registers */ 35 #define UCD_UCODE_LOAD_BLOCK_NUM 0x12C0010 36 #define UCD_UCODE_LOAD_IDX_DATAX(_i) (0x12C0018 + ((_i) * 0x20)) 37 #define UCD_SE_EID_UCODE_BLOCK_NUMX(_i) (0x12C0000 + ((_i) * 0x1000)) 38 39 /* NPS core registers */ 40 #define NPS_CORE_GBL_VFCFG 0x1000000 41 #define NPS_CORE_CONTROL 0x1000008 42 #define NPS_CORE_INT_ACTIVE 0x1000080 43 #define NPS_CORE_INT 0x10000A0 44 #define NPS_CORE_INT_ENA_W1S 0x10000B8 45 #define NPS_STATS_PKT_DMA_RD_CNT 0x1000180 46 #define NPS_STATS_PKT_DMA_WR_CNT 0x1000190 47 48 /* NPS packet registers */ 49 #define NPS_PKT_INT 0x1040018 50 #define NPS_PKT_IN_RERR_HI 0x1040108 51 #define NPS_PKT_IN_RERR_HI_ENA_W1S 0x1040120 52 #define NPS_PKT_IN_RERR_LO 0x1040128 53 #define NPS_PKT_IN_RERR_LO_ENA_W1S 0x1040140 54 #define NPS_PKT_IN_ERR_TYPE 0x1040148 55 #define NPS_PKT_IN_ERR_TYPE_ENA_W1S 0x1040160 56 #define NPS_PKT_IN_INSTR_CTLX(_i) (0x10060 + ((_i) * 0x40000)) 57 #define NPS_PKT_IN_INSTR_BADDRX(_i) (0x10068 + ((_i) * 0x40000)) 58 #define NPS_PKT_IN_INSTR_RSIZEX(_i) (0x10070 + ((_i) * 0x40000)) 59 #define NPS_PKT_IN_DONE_CNTSX(_i) (0x10080 + ((_i) * 0x40000)) 60 #define NPS_PKT_IN_INSTR_BAOFF_DBELLX(_i) (0x10078 + ((_i) * 0x40000)) 61 #define NPS_PKT_IN_INT_LEVELSX(_i) (0x10088 + ((_i) * 0x40000)) 62 63 #define NPS_PKT_SLC_RERR_HI 0x1040208 64 #define NPS_PKT_SLC_RERR_HI_ENA_W1S 0x1040220 65 #define NPS_PKT_SLC_RERR_LO 0x1040228 66 #define NPS_PKT_SLC_RERR_LO_ENA_W1S 0x1040240 67 #define NPS_PKT_SLC_ERR_TYPE 0x1040248 68 #define NPS_PKT_SLC_ERR_TYPE_ENA_W1S 0x1040260 69 #define NPS_PKT_SLC_CTLX(_i) (0x10000 + ((_i) * 0x40000)) 70 #define NPS_PKT_SLC_CNTSX(_i) (0x10008 + ((_i) * 0x40000)) 71 #define NPS_PKT_SLC_INT_LEVELSX(_i) (0x10010 + ((_i) * 0x40000)) 72 73 /* POM registers */ 74 #define POM_INT_ENA_W1S 0x11C0018 75 #define POM_GRP_EXECMASKX(_i) (0x11C1100 | ((_i) * 8)) 76 #define POM_INT 0x11C0000 77 #define POM_PERF_CTL 0x11CC400 78 79 /* BMI registers */ 80 #define BMI_INT 0x1140000 81 #define BMI_CTL 0x1140020 82 #define BMI_INT_ENA_W1S 0x1140018 83 #define BMI_NPS_PKT_CNT 0x1140070 84 85 /* EFL registers */ 86 #define EFL_CORE_INT_ENA_W1SX(_i) (0x1240018 + ((_i) * 0x400)) 87 #define EFL_CORE_VF_ERR_INT0X(_i) (0x1240050 + ((_i) * 0x400)) 88 #define EFL_CORE_VF_ERR_INT0_ENA_W1SX(_i) (0x1240068 + ((_i) * 0x400)) 89 #define EFL_CORE_VF_ERR_INT1X(_i) (0x1240070 + ((_i) * 0x400)) 90 #define EFL_CORE_VF_ERR_INT1_ENA_W1SX(_i) (0x1240088 + ((_i) * 0x400)) 91 #define EFL_CORE_SE_ERR_INTX(_i) (0x12400A0 + ((_i) * 0x400)) 92 #define EFL_RNM_CTL_STATUS 0x1241800 93 #define EFL_CORE_INTX(_i) (0x1240000 + ((_i) * 0x400)) 94 95 /* BMO registers */ 96 #define BMO_CTL2 0x1180028 97 #define BMO_NPS_SLC_PKT_CNT 0x1180078 98 99 /* LBC registers */ 100 #define LBC_INT 0x1200000 101 #define LBC_INVAL_CTL 0x1201010 102 #define LBC_PLM_VF1_64_INT 0x1202008 103 #define LBC_INVAL_STATUS 0x1202010 104 #define LBC_INT_ENA_W1S 0x1203000 105 #define LBC_PLM_VF1_64_INT_ENA_W1S 0x1205008 106 #define LBC_PLM_VF65_128_INT 0x1206008 107 #define LBC_ELM_VF1_64_INT 0x1208000 108 #define LBC_PLM_VF65_128_INT_ENA_W1S 0x1209008 109 #define LBC_ELM_VF1_64_INT_ENA_W1S 0x120B000 110 #define LBC_ELM_VF65_128_INT 0x120C000 111 #define LBC_ELM_VF65_128_INT_ENA_W1S 0x120F000 112 113 /* PEM registers */ 114 #define PEM0_INT 0x1080428 115 116 /** 117 * struct emu_fuse_map - EMU Fuse Map Registers 118 * @ae_fuse: Fuse settings for AE 19..0 119 * @se_fuse: Fuse settings for SE 15..0 120 * 121 * A set bit indicates the unit is fuse disabled. 122 */ 123 union emu_fuse_map { 124 u64 value; 125 struct { 126 #if (defined(__BIG_ENDIAN_BITFIELD)) 127 u64 valid : 1; 128 u64 raz_52_62 : 11; 129 u64 ae_fuse : 20; 130 u64 raz_16_31 : 16; 131 u64 se_fuse : 16; 132 #else 133 u64 se_fuse : 16; 134 u64 raz_16_31 : 16; 135 u64 ae_fuse : 20; 136 u64 raz_52_62 : 11; 137 u64 valid : 1; 138 #endif 139 } s; 140 }; 141 142 /** 143 * struct emu_se_enable - Symmetric Engine Enable Registers 144 * @enable: Individual enables for each of the clusters 145 * 16 symmetric engines. 146 */ 147 union emu_se_enable { 148 u64 value; 149 struct { 150 #if (defined(__BIG_ENDIAN_BITFIELD)) 151 u64 raz : 48; 152 u64 enable : 16; 153 #else 154 u64 enable : 16; 155 u64 raz : 48; 156 #endif 157 } s; 158 }; 159 160 /** 161 * struct emu_ae_enable - EMU Asymmetric engines. 162 * @enable: Individual enables for each of the cluster's 163 * 20 Asymmetric Engines. 164 */ 165 union emu_ae_enable { 166 u64 value; 167 struct { 168 #if (defined(__BIG_ENDIAN_BITFIELD)) 169 u64 raz : 44; 170 u64 enable : 20; 171 #else 172 u64 enable : 20; 173 u64 raz : 44; 174 #endif 175 } s; 176 }; 177 178 /** 179 * struct emu_wd_int_ena_w1s - EMU Interrupt Enable Registers 180 * @ae_wd: Reads or sets enable for EMU(0..3)_WD_INT[AE_WD] 181 * @se_wd: Reads or sets enable for EMU(0..3)_WD_INT[SE_WD] 182 */ 183 union emu_wd_int_ena_w1s { 184 u64 value; 185 struct { 186 #if (defined(__BIG_ENDIAN_BITFIELD)) 187 u64 raz2 : 12; 188 u64 ae_wd : 20; 189 u64 raz1 : 16; 190 u64 se_wd : 16; 191 #else 192 u64 se_wd : 16; 193 u64 raz1 : 16; 194 u64 ae_wd : 20; 195 u64 raz2 : 12; 196 #endif 197 } s; 198 }; 199 200 /** 201 * struct emu_ge_int_ena_w1s - EMU Interrupt Enable set registers 202 * @ae_ge: Reads or sets enable for EMU(0..3)_GE_INT[AE_GE] 203 * @se_ge: Reads or sets enable for EMU(0..3)_GE_INT[SE_GE] 204 */ 205 union emu_ge_int_ena_w1s { 206 u64 value; 207 struct { 208 #if (defined(__BIG_ENDIAN_BITFIELD)) 209 u64 raz_52_63 : 12; 210 u64 ae_ge : 20; 211 u64 raz_16_31: 16; 212 u64 se_ge : 16; 213 #else 214 u64 se_ge : 16; 215 u64 raz_16_31: 16; 216 u64 ae_ge : 20; 217 u64 raz_52_63 : 12; 218 #endif 219 } s; 220 }; 221 222 /** 223 * struct nps_pkt_slc_ctl - Solicited Packet Out Control Registers 224 * @rh: Indicates whether to remove or include the response header 225 * 1 = Include, 0 = Remove 226 * @z: If set, 8 trailing 0x00 bytes will be added to the end of the 227 * outgoing packet. 228 * @enb: Enable for this port. 229 */ 230 union nps_pkt_slc_ctl { 231 u64 value; 232 struct { 233 #if defined(__BIG_ENDIAN_BITFIELD) 234 u64 raz : 61; 235 u64 rh : 1; 236 u64 z : 1; 237 u64 enb : 1; 238 #else 239 u64 enb : 1; 240 u64 z : 1; 241 u64 rh : 1; 242 u64 raz : 61; 243 #endif 244 } s; 245 }; 246 247 /** 248 * struct nps_pkt_slc_cnts - Solicited Packet Out Count Registers 249 * @slc_int: Returns a 1 when: 250 * NPS_PKT_SLC(i)_CNTS[CNT] > NPS_PKT_SLC(i)_INT_LEVELS[CNT], or 251 * NPS_PKT_SLC(i)_CNTS[TIMER] > NPS_PKT_SLC(i)_INT_LEVELS[TIMET]. 252 * To clear the bit, the CNTS register must be written to clear. 253 * @in_int: Returns a 1 when: 254 * NPS_PKT_IN(i)_DONE_CNTS[CNT] > NPS_PKT_IN(i)_INT_LEVELS[CNT]. 255 * To clear the bit, the DONE_CNTS register must be written to clear. 256 * @mbox_int: Returns a 1 when: 257 * NPS_PKT_MBOX_PF_VF(i)_INT[INTR] is set. To clear the bit, 258 * write NPS_PKT_MBOX_PF_VF(i)_INT[INTR] with 1. 259 * @timer: Timer, incremented every 2048 coprocessor clock cycles 260 * when [CNT] is not zero. The hardware clears both [TIMER] and 261 * [INT] when [CNT] goes to 0. 262 * @cnt: Packet counter. Hardware adds to [CNT] as it sends packets out. 263 * On a write to this CSR, hardware subtracts the amount written to the 264 * [CNT] field from [CNT]. 265 */ 266 union nps_pkt_slc_cnts { 267 u64 value; 268 struct { 269 #if defined(__BIG_ENDIAN_BITFIELD) 270 u64 slc_int : 1; 271 u64 uns_int : 1; 272 u64 in_int : 1; 273 u64 mbox_int : 1; 274 u64 resend : 1; 275 u64 raz : 5; 276 u64 timer : 22; 277 u64 cnt : 32; 278 #else 279 u64 cnt : 32; 280 u64 timer : 22; 281 u64 raz : 5; 282 u64 resend : 1; 283 u64 mbox_int : 1; 284 u64 in_int : 1; 285 u64 uns_int : 1; 286 u64 slc_int : 1; 287 #endif 288 } s; 289 }; 290 291 /** 292 * struct nps_pkt_slc_int_levels - Solicited Packet Out Interrupt Levels 293 * Registers. 294 * @bmode: Determines whether NPS_PKT_SLC_CNTS[CNT] is a byte or 295 * packet counter. 296 * @timet: Output port counter time interrupt threshold. 297 * @cnt: Output port counter interrupt threshold. 298 */ 299 union nps_pkt_slc_int_levels { 300 u64 value; 301 struct { 302 #if defined(__BIG_ENDIAN_BITFIELD) 303 u64 bmode : 1; 304 u64 raz : 9; 305 u64 timet : 22; 306 u64 cnt : 32; 307 #else 308 u64 cnt : 32; 309 u64 timet : 22; 310 u64 raz : 9; 311 u64 bmode : 1; 312 #endif 313 } s; 314 }; 315 316 /** 317 * struct nps_pkt_inst - NPS Packet Interrupt Register 318 * @in_err: Set when any NPS_PKT_IN_RERR_HI/LO bit and 319 * corresponding NPS_PKT_IN_RERR_*_ENA_* bit are bot set. 320 * @uns_err: Set when any NSP_PKT_UNS_RERR_HI/LO bit and 321 * corresponding NPS_PKT_UNS_RERR_*_ENA_* bit are both set. 322 * @slc_er: Set when any NSP_PKT_SLC_RERR_HI/LO bit and 323 * corresponding NPS_PKT_SLC_RERR_*_ENA_* bit are both set. 324 */ 325 union nps_pkt_int { 326 u64 value; 327 struct { 328 #if defined(__BIG_ENDIAN_BITFIELD) 329 u64 raz : 54; 330 u64 uns_wto : 1; 331 u64 in_err : 1; 332 u64 uns_err : 1; 333 u64 slc_err : 1; 334 u64 in_dbe : 1; 335 u64 in_sbe : 1; 336 u64 uns_dbe : 1; 337 u64 uns_sbe : 1; 338 u64 slc_dbe : 1; 339 u64 slc_sbe : 1; 340 #else 341 u64 slc_sbe : 1; 342 u64 slc_dbe : 1; 343 u64 uns_sbe : 1; 344 u64 uns_dbe : 1; 345 u64 in_sbe : 1; 346 u64 in_dbe : 1; 347 u64 slc_err : 1; 348 u64 uns_err : 1; 349 u64 in_err : 1; 350 u64 uns_wto : 1; 351 u64 raz : 54; 352 #endif 353 } s; 354 }; 355 356 /** 357 * struct nps_pkt_in_done_cnts - Input instruction ring counts registers 358 * @slc_cnt: Returns a 1 when: 359 * NPS_PKT_SLC(i)_CNTS[CNT] > NPS_PKT_SLC(i)_INT_LEVELS[CNT], or 360 * NPS_PKT_SLC(i)_CNTS[TIMER] > NPS_PKT_SCL(i)_INT_LEVELS[TIMET] 361 * To clear the bit, the CNTS register must be 362 * written to clear the underlying condition 363 * @uns_int: Return a 1 when: 364 * NPS_PKT_UNS(i)_CNTS[CNT] > NPS_PKT_UNS(i)_INT_LEVELS[CNT], or 365 * NPS_PKT_UNS(i)_CNTS[TIMER] > NPS_PKT_UNS(i)_INT_LEVELS[TIMET] 366 * To clear the bit, the CNTS register must be 367 * written to clear the underlying condition 368 * @in_int: Returns a 1 when: 369 * NPS_PKT_IN(i)_DONE_CNTS[CNT] > NPS_PKT_IN(i)_INT_LEVELS[CNT] 370 * To clear the bit, the DONE_CNTS register 371 * must be written to clear the underlying condition 372 * @mbox_int: Returns a 1 when: 373 * NPS_PKT_MBOX_PF_VF(i)_INT[INTR] is set. 374 * To clear the bit, write NPS_PKT_MBOX_PF_VF(i)_INT[INTR] 375 * with 1. 376 * @resend: A write of 1 will resend an MSI-X interrupt message if any 377 * of the following conditions are true for this ring "i". 378 * NPS_PKT_SLC(i)_CNTS[CNT] > NPS_PKT_SLC(i)_INT_LEVELS[CNT] 379 * NPS_PKT_SLC(i)_CNTS[TIMER] > NPS_PKT_SLC(i)_INT_LEVELS[TIMET] 380 * NPS_PKT_UNS(i)_CNTS[CNT] > NPS_PKT_UNS(i)_INT_LEVELS[CNT] 381 * NPS_PKT_UNS(i)_CNTS[TIMER] > NPS_PKT_UNS(i)_INT_LEVELS[TIMET] 382 * NPS_PKT_IN(i)_DONE_CNTS[CNT] > NPS_PKT_IN(i)_INT_LEVELS[CNT] 383 * NPS_PKT_MBOX_PF_VF(i)_INT[INTR] is set 384 * @cnt: Packet counter. Hardware adds to [CNT] as it reads 385 * packets. On a write to this CSR, hardware substracts the 386 * amount written to the [CNT] field from [CNT], which will 387 * clear PKT_IN(i)_INT_STATUS[INTR] if [CNT] becomes <= 388 * NPS_PKT_IN(i)_INT_LEVELS[CNT]. This register should be 389 * cleared before enabling a ring by reading the current 390 * value and writing it back. 391 */ 392 union nps_pkt_in_done_cnts { 393 u64 value; 394 struct { 395 #if defined(__BIG_ENDIAN_BITFIELD) 396 u64 slc_int : 1; 397 u64 uns_int : 1; 398 u64 in_int : 1; 399 u64 mbox_int : 1; 400 u64 resend : 1; 401 u64 raz : 27; 402 u64 cnt : 32; 403 #else 404 u64 cnt : 32; 405 u64 raz : 27; 406 u64 resend : 1; 407 u64 mbox_int : 1; 408 u64 in_int : 1; 409 u64 uns_int : 1; 410 u64 slc_int : 1; 411 #endif 412 } s; 413 }; 414 415 /** 416 * struct nps_pkt_in_instr_ctl - Input Instruction Ring Control Registers. 417 * @is64b: If 1, the ring uses 64-byte instructions. If 0, the 418 * ring uses 32-byte instructions. 419 * @enb: Enable for the input ring. 420 */ 421 union nps_pkt_in_instr_ctl { 422 u64 value; 423 struct { 424 #if (defined(__BIG_ENDIAN_BITFIELD)) 425 u64 raz : 62; 426 u64 is64b : 1; 427 u64 enb : 1; 428 #else 429 u64 enb : 1; 430 u64 is64b : 1; 431 u64 raz : 62; 432 #endif 433 } s; 434 }; 435 436 /** 437 * struct nps_pkt_in_instr_rsize - Input instruction ring size registers 438 * @rsize: Ring size (number of instructions) 439 */ 440 union nps_pkt_in_instr_rsize { 441 u64 value; 442 struct { 443 #if (defined(__BIG_ENDIAN_BITFIELD)) 444 u64 raz : 32; 445 u64 rsize : 32; 446 #else 447 u64 rsize : 32; 448 u64 raz : 32; 449 #endif 450 } s; 451 }; 452 453 /** 454 * struct nps_pkt_in_instr_baoff_dbell - Input instruction ring 455 * base address offset and doorbell registers 456 * @aoff: Address offset. The offset from the NPS_PKT_IN_INSTR_BADDR 457 * where the next pointer is read. 458 * @dbell: Pointer list doorbell count. Write operations to this field 459 * increments the present value here. Read operations return the 460 * present value. 461 */ 462 union nps_pkt_in_instr_baoff_dbell { 463 u64 value; 464 struct { 465 #if (defined(__BIG_ENDIAN_BITFIELD)) 466 u64 aoff : 32; 467 u64 dbell : 32; 468 #else 469 u64 dbell : 32; 470 u64 aoff : 32; 471 #endif 472 } s; 473 }; 474 475 /** 476 * struct nps_core_int_ena_w1s - NPS core interrupt enable set register 477 * @host_nps_wr_err: Reads or sets enable for 478 * NPS_CORE_INT[HOST_NPS_WR_ERR]. 479 * @npco_dma_malform: Reads or sets enable for 480 * NPS_CORE_INT[NPCO_DMA_MALFORM]. 481 * @exec_wr_timeout: Reads or sets enable for 482 * NPS_CORE_INT[EXEC_WR_TIMEOUT]. 483 * @host_wr_timeout: Reads or sets enable for 484 * NPS_CORE_INT[HOST_WR_TIMEOUT]. 485 * @host_wr_err: Reads or sets enable for 486 * NPS_CORE_INT[HOST_WR_ERR] 487 */ 488 union nps_core_int_ena_w1s { 489 u64 value; 490 struct { 491 #if (defined(__BIG_ENDIAN_BITFIELD)) 492 u64 raz4 : 55; 493 u64 host_nps_wr_err : 1; 494 u64 npco_dma_malform : 1; 495 u64 exec_wr_timeout : 1; 496 u64 host_wr_timeout : 1; 497 u64 host_wr_err : 1; 498 u64 raz3 : 1; 499 u64 raz2 : 1; 500 u64 raz1 : 1; 501 u64 raz0 : 1; 502 #else 503 u64 raz0 : 1; 504 u64 raz1 : 1; 505 u64 raz2 : 1; 506 u64 raz3 : 1; 507 u64 host_wr_err : 1; 508 u64 host_wr_timeout : 1; 509 u64 exec_wr_timeout : 1; 510 u64 npco_dma_malform : 1; 511 u64 host_nps_wr_err : 1; 512 u64 raz4 : 55; 513 #endif 514 } s; 515 }; 516 517 /** 518 * struct nps_core_gbl_vfcfg - Global VF Configuration Register. 519 * @ilk_disable: When set, this bit indicates that the ILK interface has 520 * been disabled. 521 * @obaf: BMO allocation control 522 * 0 = allocate per queue 523 * 1 = allocate per VF 524 * @ibaf: BMI allocation control 525 * 0 = allocate per queue 526 * 1 = allocate per VF 527 * @zaf: ZIP allocation control 528 * 0 = allocate per queue 529 * 1 = allocate per VF 530 * @aeaf: AE allocation control 531 * 0 = allocate per queue 532 * 1 = allocate per VF 533 * @seaf: SE allocation control 534 * 0 = allocation per queue 535 * 1 = allocate per VF 536 * @cfg: VF/PF mode. 537 */ 538 union nps_core_gbl_vfcfg { 539 u64 value; 540 struct { 541 #if (defined(__BIG_ENDIAN_BITFIELD)) 542 u64 raz :55; 543 u64 ilk_disable :1; 544 u64 obaf :1; 545 u64 ibaf :1; 546 u64 zaf :1; 547 u64 aeaf :1; 548 u64 seaf :1; 549 u64 cfg :3; 550 #else 551 u64 cfg :3; 552 u64 seaf :1; 553 u64 aeaf :1; 554 u64 zaf :1; 555 u64 ibaf :1; 556 u64 obaf :1; 557 u64 ilk_disable :1; 558 u64 raz :55; 559 #endif 560 } s; 561 }; 562 563 /** 564 * struct nps_core_int_active - NPS Core Interrupt Active Register 565 * @resend: Resend MSI-X interrupt if needs to handle interrupts 566 * Sofware can set this bit and then exit the ISR. 567 * @ocla: Set when any OCLA(0)_INT and corresponding OCLA(0_INT_ENA_W1C 568 * bit are set 569 * @mbox: Set when any NPS_PKT_MBOX_INT_LO/HI and corresponding 570 * NPS_PKT_MBOX_INT_LO_ENA_W1C/HI_ENA_W1C bits are set 571 * @emu: bit i is set in [EMU] when any EMU(i)_INT bit is set 572 * @bmo: Set when any BMO_INT bit is set 573 * @bmi: Set when any BMI_INT bit is set or when any non-RO 574 * BMI_INT and corresponding BMI_INT_ENA_W1C bits are both set 575 * @aqm: Set when any AQM_INT bit is set 576 * @zqm: Set when any ZQM_INT bit is set 577 * @efl: Set when any EFL_INT RO bit is set or when any non-RO EFL_INT 578 * and corresponding EFL_INT_ENA_W1C bits are both set 579 * @ilk: Set when any ILK_INT bit is set 580 * @lbc: Set when any LBC_INT RO bit is set or when any non-RO LBC_INT 581 * and corresponding LBC_INT_ENA_W1C bits are bot set 582 * @pem: Set when any PEM(0)_INT RO bit is set or when any non-RO 583 * PEM(0)_INT and corresponding PEM(0)_INT_ENA_W1C bit are both set 584 * @ucd: Set when any UCD_INT bit is set 585 * @zctl: Set when any ZIP_INT RO bit is set or when any non-RO ZIP_INT 586 * and corresponding ZIP_INT_ENA_W1C bits are both set 587 * @lbm: Set when any LBM_INT bit is set 588 * @nps_pkt: Set when any NPS_PKT_INT bit is set 589 * @nps_core: Set when any NPS_CORE_INT RO bit is set or when non-RO 590 * NPS_CORE_INT and corresponding NSP_CORE_INT_ENA_W1C bits are both set 591 */ 592 union nps_core_int_active { 593 u64 value; 594 struct { 595 #if (defined(__BIG_ENDIAN_BITFIELD)) 596 u64 resend : 1; 597 u64 raz : 43; 598 u64 ocla : 1; 599 u64 mbox : 1; 600 u64 emu : 4; 601 u64 bmo : 1; 602 u64 bmi : 1; 603 u64 aqm : 1; 604 u64 zqm : 1; 605 u64 efl : 1; 606 u64 ilk : 1; 607 u64 lbc : 1; 608 u64 pem : 1; 609 u64 pom : 1; 610 u64 ucd : 1; 611 u64 zctl : 1; 612 u64 lbm : 1; 613 u64 nps_pkt : 1; 614 u64 nps_core : 1; 615 #else 616 u64 nps_core : 1; 617 u64 nps_pkt : 1; 618 u64 lbm : 1; 619 u64 zctl: 1; 620 u64 ucd : 1; 621 u64 pom : 1; 622 u64 pem : 1; 623 u64 lbc : 1; 624 u64 ilk : 1; 625 u64 efl : 1; 626 u64 zqm : 1; 627 u64 aqm : 1; 628 u64 bmi : 1; 629 u64 bmo : 1; 630 u64 emu : 4; 631 u64 mbox : 1; 632 u64 ocla : 1; 633 u64 raz : 43; 634 u64 resend : 1; 635 #endif 636 } s; 637 }; 638 639 /** 640 * struct efl_core_int - EFL Interrupt Registers 641 * @epci_decode_err: EPCI decoded a transacation that was unknown 642 * This error should only occurred when there is a micrcode/SE error 643 * and should be considered fatal 644 * @ae_err: An AE uncorrectable error occurred. 645 * See EFL_CORE(0..3)_AE_ERR_INT 646 * @se_err: An SE uncorrectable error occurred. 647 * See EFL_CORE(0..3)_SE_ERR_INT 648 * @dbe: Double-bit error occurred in EFL 649 * @sbe: Single-bit error occurred in EFL 650 * @d_left: Asserted when new POM-Header-BMI-data is 651 * being sent to an Exec, and that Exec has Not read all BMI 652 * data associated with the previous POM header 653 * @len_ovr: Asserted when an Exec-Read is issued that is more than 654 * 14 greater in length that the BMI data left to be read 655 */ 656 union efl_core_int { 657 u64 value; 658 struct { 659 #if (defined(__BIG_ENDIAN_BITFIELD)) 660 u64 raz : 57; 661 u64 epci_decode_err : 1; 662 u64 ae_err : 1; 663 u64 se_err : 1; 664 u64 dbe : 1; 665 u64 sbe : 1; 666 u64 d_left : 1; 667 u64 len_ovr : 1; 668 #else 669 u64 len_ovr : 1; 670 u64 d_left : 1; 671 u64 sbe : 1; 672 u64 dbe : 1; 673 u64 se_err : 1; 674 u64 ae_err : 1; 675 u64 epci_decode_err : 1; 676 u64 raz : 57; 677 #endif 678 } s; 679 }; 680 681 /** 682 * struct efl_core_int_ena_w1s - EFL core interrupt enable set register 683 * @epci_decode_err: Reads or sets enable for 684 * EFL_CORE(0..3)_INT[EPCI_DECODE_ERR]. 685 * @d_left: Reads or sets enable for 686 * EFL_CORE(0..3)_INT[D_LEFT]. 687 * @len_ovr: Reads or sets enable for 688 * EFL_CORE(0..3)_INT[LEN_OVR]. 689 */ 690 union efl_core_int_ena_w1s { 691 u64 value; 692 struct { 693 #if (defined(__BIG_ENDIAN_BITFIELD)) 694 u64 raz_7_63 : 57; 695 u64 epci_decode_err : 1; 696 u64 raz_2_5 : 4; 697 u64 d_left : 1; 698 u64 len_ovr : 1; 699 #else 700 u64 len_ovr : 1; 701 u64 d_left : 1; 702 u64 raz_2_5 : 4; 703 u64 epci_decode_err : 1; 704 u64 raz_7_63 : 57; 705 #endif 706 } s; 707 }; 708 709 /** 710 * struct efl_rnm_ctl_status - RNM Control and Status Register 711 * @ent_sel: Select input to RNM FIFO 712 * @exp_ent: Exported entropy enable for random number generator 713 * @rng_rst: Reset to RNG. Setting this bit to 1 cancels the generation 714 * of the current random number. 715 * @rnm_rst: Reset the RNM. Setting this bit to 1 clears all sorted numbers 716 * in the random number memory. 717 * @rng_en: Enabled the output of the RNG. 718 * @ent_en: Entropy enable for random number generator. 719 */ 720 union efl_rnm_ctl_status { 721 u64 value; 722 struct { 723 #if (defined(__BIG_ENDIAN_BITFIELD)) 724 u64 raz_9_63 : 55; 725 u64 ent_sel : 4; 726 u64 exp_ent : 1; 727 u64 rng_rst : 1; 728 u64 rnm_rst : 1; 729 u64 rng_en : 1; 730 u64 ent_en : 1; 731 #else 732 u64 ent_en : 1; 733 u64 rng_en : 1; 734 u64 rnm_rst : 1; 735 u64 rng_rst : 1; 736 u64 exp_ent : 1; 737 u64 ent_sel : 4; 738 u64 raz_9_63 : 55; 739 #endif 740 } s; 741 }; 742 743 /** 744 * struct bmi_ctl - BMI control register 745 * @ilk_hdrq_thrsh: Maximum number of header queue locations 746 * that ILK packets may consume. When the threshold is 747 * exceeded ILK_XOFF is sent to the BMI_X2P_ARB. 748 * @nps_hdrq_thrsh: Maximum number of header queue locations 749 * that NPS packets may consume. When the threshold is 750 * exceeded NPS_XOFF is sent to the BMI_X2P_ARB. 751 * @totl_hdrq_thrsh: Maximum number of header queue locations 752 * that the sum of ILK and NPS packets may consume. 753 * @ilk_free_thrsh: Maximum number of buffers that ILK packet 754 * flows may consume before ILK_XOFF is sent to the BMI_X2P_ARB. 755 * @nps_free_thrsh: Maximum number of buffers that NPS packet 756 * flows may consume before NPS XOFF is sent to the BMI_X2p_ARB. 757 * @totl_free_thrsh: Maximum number of buffers that bot ILK and NPS 758 * packet flows may consume before both NPS_XOFF and ILK_XOFF 759 * are asserted to the BMI_X2P_ARB. 760 * @max_pkt_len: Maximum packet length, integral number of 256B 761 * buffers. 762 */ 763 union bmi_ctl { 764 u64 value; 765 struct { 766 #if (defined(__BIG_ENDIAN_BITFIELD)) 767 u64 raz_56_63 : 8; 768 u64 ilk_hdrq_thrsh : 8; 769 u64 nps_hdrq_thrsh : 8; 770 u64 totl_hdrq_thrsh : 8; 771 u64 ilk_free_thrsh : 8; 772 u64 nps_free_thrsh : 8; 773 u64 totl_free_thrsh : 8; 774 u64 max_pkt_len : 8; 775 #else 776 u64 max_pkt_len : 8; 777 u64 totl_free_thrsh : 8; 778 u64 nps_free_thrsh : 8; 779 u64 ilk_free_thrsh : 8; 780 u64 totl_hdrq_thrsh : 8; 781 u64 nps_hdrq_thrsh : 8; 782 u64 ilk_hdrq_thrsh : 8; 783 u64 raz_56_63 : 8; 784 #endif 785 } s; 786 }; 787 788 /** 789 * struct bmi_int_ena_w1s - BMI interrupt enable set register 790 * @ilk_req_oflw: Reads or sets enable for 791 * BMI_INT[ILK_REQ_OFLW]. 792 * @nps_req_oflw: Reads or sets enable for 793 * BMI_INT[NPS_REQ_OFLW]. 794 * @fpf_undrrn: Reads or sets enable for 795 * BMI_INT[FPF_UNDRRN]. 796 * @eop_err_ilk: Reads or sets enable for 797 * BMI_INT[EOP_ERR_ILK]. 798 * @eop_err_nps: Reads or sets enable for 799 * BMI_INT[EOP_ERR_NPS]. 800 * @sop_err_ilk: Reads or sets enable for 801 * BMI_INT[SOP_ERR_ILK]. 802 * @sop_err_nps: Reads or sets enable for 803 * BMI_INT[SOP_ERR_NPS]. 804 * @pkt_rcv_err_ilk: Reads or sets enable for 805 * BMI_INT[PKT_RCV_ERR_ILK]. 806 * @pkt_rcv_err_nps: Reads or sets enable for 807 * BMI_INT[PKT_RCV_ERR_NPS]. 808 * @max_len_err_ilk: Reads or sets enable for 809 * BMI_INT[MAX_LEN_ERR_ILK]. 810 * @max_len_err_nps: Reads or sets enable for 811 * BMI_INT[MAX_LEN_ERR_NPS]. 812 */ 813 union bmi_int_ena_w1s { 814 u64 value; 815 struct { 816 #if (defined(__BIG_ENDIAN_BITFIELD)) 817 u64 raz_13_63 : 51; 818 u64 ilk_req_oflw : 1; 819 u64 nps_req_oflw : 1; 820 u64 raz_10 : 1; 821 u64 raz_9 : 1; 822 u64 fpf_undrrn : 1; 823 u64 eop_err_ilk : 1; 824 u64 eop_err_nps : 1; 825 u64 sop_err_ilk : 1; 826 u64 sop_err_nps : 1; 827 u64 pkt_rcv_err_ilk : 1; 828 u64 pkt_rcv_err_nps : 1; 829 u64 max_len_err_ilk : 1; 830 u64 max_len_err_nps : 1; 831 #else 832 u64 max_len_err_nps : 1; 833 u64 max_len_err_ilk : 1; 834 u64 pkt_rcv_err_nps : 1; 835 u64 pkt_rcv_err_ilk : 1; 836 u64 sop_err_nps : 1; 837 u64 sop_err_ilk : 1; 838 u64 eop_err_nps : 1; 839 u64 eop_err_ilk : 1; 840 u64 fpf_undrrn : 1; 841 u64 raz_9 : 1; 842 u64 raz_10 : 1; 843 u64 nps_req_oflw : 1; 844 u64 ilk_req_oflw : 1; 845 u64 raz_13_63 : 51; 846 #endif 847 } s; 848 }; 849 850 /** 851 * struct bmo_ctl2 - BMO Control2 Register 852 * @arb_sel: Determines P2X Arbitration 853 * @ilk_buf_thrsh: Maximum number of buffers that the 854 * ILK packet flows may consume before ILK XOFF is 855 * asserted to the POM. 856 * @nps_slc_buf_thrsh: Maximum number of buffers that the 857 * NPS_SLC packet flow may consume before NPS_SLC XOFF is 858 * asserted to the POM. 859 * @nps_uns_buf_thrsh: Maximum number of buffers that the 860 * NPS_UNS packet flow may consume before NPS_UNS XOFF is 861 * asserted to the POM. 862 * @totl_buf_thrsh: Maximum number of buffers that ILK, NPS_UNS and 863 * NPS_SLC packet flows may consume before NPS_UNS XOFF, NSP_SLC and 864 * ILK_XOFF are all asserted POM. 865 */ 866 union bmo_ctl2 { 867 u64 value; 868 struct { 869 #if (defined(__BIG_ENDIAN_BITFIELD)) 870 u64 arb_sel : 1; 871 u64 raz_32_62 : 31; 872 u64 ilk_buf_thrsh : 8; 873 u64 nps_slc_buf_thrsh : 8; 874 u64 nps_uns_buf_thrsh : 8; 875 u64 totl_buf_thrsh : 8; 876 #else 877 u64 totl_buf_thrsh : 8; 878 u64 nps_uns_buf_thrsh : 8; 879 u64 nps_slc_buf_thrsh : 8; 880 u64 ilk_buf_thrsh : 8; 881 u64 raz_32_62 : 31; 882 u64 arb_sel : 1; 883 #endif 884 } s; 885 }; 886 887 /** 888 * struct pom_int_ena_w1s - POM interrupt enable set register 889 * @illegal_intf: Reads or sets enable for POM_INT[ILLEGAL_INTF]. 890 * @illegal_dport: Reads or sets enable for POM_INT[ILLEGAL_DPORT]. 891 */ 892 union pom_int_ena_w1s { 893 u64 value; 894 struct { 895 #if (defined(__BIG_ENDIAN_BITFIELD)) 896 u64 raz2 : 60; 897 u64 illegal_intf : 1; 898 u64 illegal_dport : 1; 899 u64 raz1 : 1; 900 u64 raz0 : 1; 901 #else 902 u64 raz0 : 1; 903 u64 raz1 : 1; 904 u64 illegal_dport : 1; 905 u64 illegal_intf : 1; 906 u64 raz2 : 60; 907 #endif 908 } s; 909 }; 910 911 /** 912 * struct lbc_inval_ctl - LBC invalidation control register 913 * @wait_timer: Wait timer for wait state. [WAIT_TIMER] must 914 * always be written with its reset value. 915 * @cam_inval_start: Software should write [CAM_INVAL_START]=1 916 * to initiate an LBC cache invalidation. After this, software 917 * should read LBC_INVAL_STATUS until LBC_INVAL_STATUS[DONE] is set. 918 * LBC hardware clears [CAVM_INVAL_START] before software can 919 * observed LBC_INVAL_STATUS[DONE] to be set 920 */ 921 union lbc_inval_ctl { 922 u64 value; 923 struct { 924 #if (defined(__BIG_ENDIAN_BITFIELD)) 925 u64 raz2 : 48; 926 u64 wait_timer : 8; 927 u64 raz1 : 6; 928 u64 cam_inval_start : 1; 929 u64 raz0 : 1; 930 #else 931 u64 raz0 : 1; 932 u64 cam_inval_start : 1; 933 u64 raz1 : 6; 934 u64 wait_timer : 8; 935 u64 raz2 : 48; 936 #endif 937 } s; 938 }; 939 940 /** 941 * struct lbc_int_ena_w1s - LBC interrupt enable set register 942 * @cam_hard_err: Reads or sets enable for LBC_INT[CAM_HARD_ERR]. 943 * @cam_inval_abort: Reads or sets enable for LBC_INT[CAM_INVAL_ABORT]. 944 * @over_fetch_err: Reads or sets enable for LBC_INT[OVER_FETCH_ERR]. 945 * @cache_line_to_err: Reads or sets enable for 946 * LBC_INT[CACHE_LINE_TO_ERR]. 947 * @cam_soft_err: Reads or sets enable for 948 * LBC_INT[CAM_SOFT_ERR]. 949 * @dma_rd_err: Reads or sets enable for 950 * LBC_INT[DMA_RD_ERR]. 951 */ 952 union lbc_int_ena_w1s { 953 u64 value; 954 struct { 955 #if (defined(__BIG_ENDIAN_BITFIELD)) 956 u64 raz_10_63 : 54; 957 u64 cam_hard_err : 1; 958 u64 cam_inval_abort : 1; 959 u64 over_fetch_err : 1; 960 u64 cache_line_to_err : 1; 961 u64 raz_2_5 : 4; 962 u64 cam_soft_err : 1; 963 u64 dma_rd_err : 1; 964 #else 965 u64 dma_rd_err : 1; 966 u64 cam_soft_err : 1; 967 u64 raz_2_5 : 4; 968 u64 cache_line_to_err : 1; 969 u64 over_fetch_err : 1; 970 u64 cam_inval_abort : 1; 971 u64 cam_hard_err : 1; 972 u64 raz_10_63 : 54; 973 #endif 974 } s; 975 }; 976 977 /** 978 * struct lbc_int - LBC interrupt summary register 979 * @cam_hard_err: indicates a fatal hardware error. 980 * It requires system reset. 981 * When [CAM_HARD_ERR] is set, LBC stops logging any new information in 982 * LBC_POM_MISS_INFO_LOG, 983 * LBC_POM_MISS_ADDR_LOG, 984 * LBC_EFL_MISS_INFO_LOG, and 985 * LBC_EFL_MISS_ADDR_LOG. 986 * Software should sample them. 987 * @cam_inval_abort: indicates a fatal hardware error. 988 * System reset is required. 989 * @over_fetch_err: indicates a fatal hardware error 990 * System reset is required 991 * @cache_line_to_err: is a debug feature. 992 * This timeout interrupt bit tells the software that 993 * a cacheline in LBC has non-zero usage and the context 994 * has not been used for greater than the 995 * LBC_TO_CNT[TO_CNT] time interval. 996 * @sbe: Memory SBE error. This is recoverable via ECC. 997 * See LBC_ECC_INT for more details. 998 * @dbe: Memory DBE error. This is a fatal and requires a 999 * system reset. 1000 * @pref_dat_len_mismatch_err: Summary bit for context length 1001 * mismatch errors. 1002 * @rd_dat_len_mismatch_err: Summary bit for SE read data length 1003 * greater than data prefect length errors. 1004 * @cam_soft_err: is recoverable. Software must complete a 1005 * LBC_INVAL_CTL[CAM_INVAL_START] invalidation sequence and 1006 * then clear [CAM_SOFT_ERR]. 1007 * @dma_rd_err: A context prefect read of host memory returned with 1008 * a read error. 1009 */ 1010 union lbc_int { 1011 u64 value; 1012 struct { 1013 #if (defined(__BIG_ENDIAN_BITFIELD)) 1014 u64 raz_10_63 : 54; 1015 u64 cam_hard_err : 1; 1016 u64 cam_inval_abort : 1; 1017 u64 over_fetch_err : 1; 1018 u64 cache_line_to_err : 1; 1019 u64 sbe : 1; 1020 u64 dbe : 1; 1021 u64 pref_dat_len_mismatch_err : 1; 1022 u64 rd_dat_len_mismatch_err : 1; 1023 u64 cam_soft_err : 1; 1024 u64 dma_rd_err : 1; 1025 #else 1026 u64 dma_rd_err : 1; 1027 u64 cam_soft_err : 1; 1028 u64 rd_dat_len_mismatch_err : 1; 1029 u64 pref_dat_len_mismatch_err : 1; 1030 u64 dbe : 1; 1031 u64 sbe : 1; 1032 u64 cache_line_to_err : 1; 1033 u64 over_fetch_err : 1; 1034 u64 cam_inval_abort : 1; 1035 u64 cam_hard_err : 1; 1036 u64 raz_10_63 : 54; 1037 #endif 1038 } s; 1039 }; 1040 1041 /** 1042 * struct lbc_inval_status: LBC Invalidation status register 1043 * @cam_clean_entry_complete_cnt: The number of entries that are 1044 * cleaned up successfully. 1045 * @cam_clean_entry_cnt: The number of entries that have the CAM 1046 * inval command issued. 1047 * @cam_inval_state: cam invalidation FSM state 1048 * @cam_inval_abort: cam invalidation abort 1049 * @cam_rst_rdy: lbc_cam reset ready 1050 * @done: LBC clears [DONE] when 1051 * LBC_INVAL_CTL[CAM_INVAL_START] is written with a one, 1052 * and sets [DONE] when it completes the invalidation 1053 * sequence. 1054 */ 1055 union lbc_inval_status { 1056 u64 value; 1057 struct { 1058 #if (defined(__BIG_ENDIAN_BITFIELD)) 1059 u64 raz3 : 23; 1060 u64 cam_clean_entry_complete_cnt : 9; 1061 u64 raz2 : 7; 1062 u64 cam_clean_entry_cnt : 9; 1063 u64 raz1 : 5; 1064 u64 cam_inval_state : 3; 1065 u64 raz0 : 5; 1066 u64 cam_inval_abort : 1; 1067 u64 cam_rst_rdy : 1; 1068 u64 done : 1; 1069 #else 1070 u64 done : 1; 1071 u64 cam_rst_rdy : 1; 1072 u64 cam_inval_abort : 1; 1073 u64 raz0 : 5; 1074 u64 cam_inval_state : 3; 1075 u64 raz1 : 5; 1076 u64 cam_clean_entry_cnt : 9; 1077 u64 raz2 : 7; 1078 u64 cam_clean_entry_complete_cnt : 9; 1079 u64 raz3 : 23; 1080 #endif 1081 } s; 1082 }; 1083 1084 #endif /* __NITROX_CSR_H */ 1085