1 /* 2 * CAAM hardware register-level view 3 * 4 * Copyright 2008-2011 Freescale Semiconductor, Inc. 5 */ 6 7 #ifndef REGS_H 8 #define REGS_H 9 10 #include <linux/types.h> 11 #include <linux/bitops.h> 12 #include <linux/io.h> 13 14 /* 15 * Architecture-specific register access methods 16 * 17 * CAAM's bus-addressable registers are 64 bits internally. 18 * They have been wired to be safely accessible on 32-bit 19 * architectures, however. Registers were organized such 20 * that (a) they can be contained in 32 bits, (b) if not, then they 21 * can be treated as two 32-bit entities, or finally (c) if they 22 * must be treated as a single 64-bit value, then this can safely 23 * be done with two 32-bit cycles. 24 * 25 * For 32-bit operations on 64-bit values, CAAM follows the same 26 * 64-bit register access conventions as it's predecessors, in that 27 * writes are "triggered" by a write to the register at the numerically 28 * higher address, thus, a full 64-bit write cycle requires a write 29 * to the lower address, followed by a write to the higher address, 30 * which will latch/execute the write cycle. 31 * 32 * For example, let's assume a SW reset of CAAM through the master 33 * configuration register. 34 * - SWRST is in bit 31 of MCFG. 35 * - MCFG begins at base+0x0000. 36 * - Bits 63-32 are a 32-bit word at base+0x0000 (numerically-lower) 37 * - Bits 31-0 are a 32-bit word at base+0x0004 (numerically-higher) 38 * 39 * (and on Power, the convention is 0-31, 32-63, I know...) 40 * 41 * Assuming a 64-bit write to this MCFG to perform a software reset 42 * would then require a write of 0 to base+0x0000, followed by a 43 * write of 0x80000000 to base+0x0004, which would "execute" the 44 * reset. 45 * 46 * Of course, since MCFG 63-32 is all zero, we could cheat and simply 47 * write 0x8000000 to base+0x0004, and the reset would work fine. 48 * However, since CAAM does contain some write-and-read-intended 49 * 64-bit registers, this code defines 64-bit access methods for 50 * the sake of internal consistency and simplicity, and so that a 51 * clean transition to 64-bit is possible when it becomes necessary. 52 * 53 * There are limitations to this that the developer must recognize. 54 * 32-bit architectures cannot enforce an atomic-64 operation, 55 * Therefore: 56 * 57 * - On writes, since the HW is assumed to latch the cycle on the 58 * write of the higher-numeric-address word, then ordered 59 * writes work OK. 60 * 61 * - For reads, where a register contains a relevant value of more 62 * that 32 bits, the hardware employs logic to latch the other 63 * "half" of the data until read, ensuring an accurate value. 64 * This is of particular relevance when dealing with CAAM's 65 * performance counters. 66 * 67 */ 68 69 extern bool caam_little_end; 70 71 #define caam_to_cpu(len) \ 72 static inline u##len caam##len ## _to_cpu(u##len val) \ 73 { \ 74 if (caam_little_end) \ 75 return le##len ## _to_cpu(val); \ 76 else \ 77 return be##len ## _to_cpu(val); \ 78 } 79 80 #define cpu_to_caam(len) \ 81 static inline u##len cpu_to_caam##len(u##len val) \ 82 { \ 83 if (caam_little_end) \ 84 return cpu_to_le##len(val); \ 85 else \ 86 return cpu_to_be##len(val); \ 87 } 88 89 caam_to_cpu(16) 90 caam_to_cpu(32) 91 caam_to_cpu(64) 92 cpu_to_caam(16) 93 cpu_to_caam(32) 94 cpu_to_caam(64) 95 96 static inline void wr_reg32(void __iomem *reg, u32 data) 97 { 98 if (caam_little_end) 99 iowrite32(data, reg); 100 else 101 iowrite32be(data, reg); 102 } 103 104 static inline u32 rd_reg32(void __iomem *reg) 105 { 106 if (caam_little_end) 107 return ioread32(reg); 108 109 return ioread32be(reg); 110 } 111 112 static inline void clrsetbits_32(void __iomem *reg, u32 clear, u32 set) 113 { 114 if (caam_little_end) 115 iowrite32((ioread32(reg) & ~clear) | set, reg); 116 else 117 iowrite32be((ioread32be(reg) & ~clear) | set, reg); 118 } 119 120 /* 121 * The only users of these wr/rd_reg64 functions is the Job Ring (JR). 122 * The DMA address registers in the JR are handled differently depending on 123 * platform: 124 * 125 * 1. All BE CAAM platforms and i.MX platforms (LE CAAM): 126 * 127 * base + 0x0000 : most-significant 32 bits 128 * base + 0x0004 : least-significant 32 bits 129 * 130 * The 32-bit version of this core therefore has to write to base + 0x0004 131 * to set the 32-bit wide DMA address. 132 * 133 * 2. All other LE CAAM platforms (LS1021A etc.) 134 * base + 0x0000 : least-significant 32 bits 135 * base + 0x0004 : most-significant 32 bits 136 */ 137 #ifdef CONFIG_64BIT 138 static inline void wr_reg64(void __iomem *reg, u64 data) 139 { 140 if (caam_little_end) 141 iowrite64(data, reg); 142 else 143 iowrite64be(data, reg); 144 } 145 146 static inline u64 rd_reg64(void __iomem *reg) 147 { 148 if (caam_little_end) 149 return ioread64(reg); 150 else 151 return ioread64be(reg); 152 } 153 154 #else /* CONFIG_64BIT */ 155 static inline void wr_reg64(void __iomem *reg, u64 data) 156 { 157 #ifndef CONFIG_CRYPTO_DEV_FSL_CAAM_IMX 158 if (caam_little_end) { 159 wr_reg32((u32 __iomem *)(reg) + 1, data >> 32); 160 wr_reg32((u32 __iomem *)(reg), data); 161 } else 162 #endif 163 { 164 wr_reg32((u32 __iomem *)(reg), data >> 32); 165 wr_reg32((u32 __iomem *)(reg) + 1, data); 166 } 167 } 168 169 static inline u64 rd_reg64(void __iomem *reg) 170 { 171 #ifndef CONFIG_CRYPTO_DEV_FSL_CAAM_IMX 172 if (caam_little_end) 173 return ((u64)rd_reg32((u32 __iomem *)(reg) + 1) << 32 | 174 (u64)rd_reg32((u32 __iomem *)(reg))); 175 else 176 #endif 177 return ((u64)rd_reg32((u32 __iomem *)(reg)) << 32 | 178 (u64)rd_reg32((u32 __iomem *)(reg) + 1)); 179 } 180 #endif /* CONFIG_64BIT */ 181 182 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 183 #ifdef CONFIG_SOC_IMX7D 184 #define cpu_to_caam_dma(value) \ 185 (((u64)cpu_to_caam32(lower_32_bits(value)) << 32) | \ 186 (u64)cpu_to_caam32(upper_32_bits(value))) 187 #define caam_dma_to_cpu(value) \ 188 (((u64)caam32_to_cpu(lower_32_bits(value)) << 32) | \ 189 (u64)caam32_to_cpu(upper_32_bits(value))) 190 #else 191 #define cpu_to_caam_dma(value) cpu_to_caam64(value) 192 #define caam_dma_to_cpu(value) caam64_to_cpu(value) 193 #endif /* CONFIG_SOC_IMX7D */ 194 #else 195 #define cpu_to_caam_dma(value) cpu_to_caam32(value) 196 #define caam_dma_to_cpu(value) caam32_to_cpu(value) 197 #endif /* CONFIG_ARCH_DMA_ADDR_T_64BIT */ 198 199 /* 200 * jr_outentry 201 * Represents each entry in a JobR output ring 202 */ 203 struct jr_outentry { 204 dma_addr_t desc;/* Pointer to completed descriptor */ 205 u32 jrstatus; /* Status for completed descriptor */ 206 } __packed; 207 208 /* 209 * caam_perfmon - Performance Monitor/Secure Memory Status/ 210 * CAAM Global Status/Component Version IDs 211 * 212 * Spans f00-fff wherever instantiated 213 */ 214 215 /* Number of DECOs */ 216 #define CHA_NUM_MS_DECONUM_SHIFT 24 217 #define CHA_NUM_MS_DECONUM_MASK (0xfull << CHA_NUM_MS_DECONUM_SHIFT) 218 219 /* 220 * CHA version IDs / instantiation bitfields 221 * Defined for use with the cha_id fields in perfmon, but the same shift/mask 222 * selectors can be used to pull out the number of instantiated blocks within 223 * cha_num fields in perfmon because the locations are the same. 224 */ 225 #define CHA_ID_LS_AES_SHIFT 0 226 #define CHA_ID_LS_AES_MASK (0xfull << CHA_ID_LS_AES_SHIFT) 227 #define CHA_ID_LS_AES_LP (0x3ull << CHA_ID_LS_AES_SHIFT) 228 #define CHA_ID_LS_AES_HP (0x4ull << CHA_ID_LS_AES_SHIFT) 229 230 #define CHA_ID_LS_DES_SHIFT 4 231 #define CHA_ID_LS_DES_MASK (0xfull << CHA_ID_LS_DES_SHIFT) 232 233 #define CHA_ID_LS_ARC4_SHIFT 8 234 #define CHA_ID_LS_ARC4_MASK (0xfull << CHA_ID_LS_ARC4_SHIFT) 235 236 #define CHA_ID_LS_MD_SHIFT 12 237 #define CHA_ID_LS_MD_MASK (0xfull << CHA_ID_LS_MD_SHIFT) 238 #define CHA_ID_LS_MD_LP256 (0x0ull << CHA_ID_LS_MD_SHIFT) 239 #define CHA_ID_LS_MD_LP512 (0x1ull << CHA_ID_LS_MD_SHIFT) 240 #define CHA_ID_LS_MD_HP (0x2ull << CHA_ID_LS_MD_SHIFT) 241 242 #define CHA_ID_LS_RNG_SHIFT 16 243 #define CHA_ID_LS_RNG_MASK (0xfull << CHA_ID_LS_RNG_SHIFT) 244 245 #define CHA_ID_LS_SNW8_SHIFT 20 246 #define CHA_ID_LS_SNW8_MASK (0xfull << CHA_ID_LS_SNW8_SHIFT) 247 248 #define CHA_ID_LS_KAS_SHIFT 24 249 #define CHA_ID_LS_KAS_MASK (0xfull << CHA_ID_LS_KAS_SHIFT) 250 251 #define CHA_ID_LS_PK_SHIFT 28 252 #define CHA_ID_LS_PK_MASK (0xfull << CHA_ID_LS_PK_SHIFT) 253 254 #define CHA_ID_MS_CRC_SHIFT 0 255 #define CHA_ID_MS_CRC_MASK (0xfull << CHA_ID_MS_CRC_SHIFT) 256 257 #define CHA_ID_MS_SNW9_SHIFT 4 258 #define CHA_ID_MS_SNW9_MASK (0xfull << CHA_ID_MS_SNW9_SHIFT) 259 260 #define CHA_ID_MS_DECO_SHIFT 24 261 #define CHA_ID_MS_DECO_MASK (0xfull << CHA_ID_MS_DECO_SHIFT) 262 263 #define CHA_ID_MS_JR_SHIFT 28 264 #define CHA_ID_MS_JR_MASK (0xfull << CHA_ID_MS_JR_SHIFT) 265 266 struct sec_vid { 267 u16 ip_id; 268 u8 maj_rev; 269 u8 min_rev; 270 }; 271 272 struct caam_perfmon { 273 /* Performance Monitor Registers f00-f9f */ 274 u64 req_dequeued; /* PC_REQ_DEQ - Dequeued Requests */ 275 u64 ob_enc_req; /* PC_OB_ENC_REQ - Outbound Encrypt Requests */ 276 u64 ib_dec_req; /* PC_IB_DEC_REQ - Inbound Decrypt Requests */ 277 u64 ob_enc_bytes; /* PC_OB_ENCRYPT - Outbound Bytes Encrypted */ 278 u64 ob_prot_bytes; /* PC_OB_PROTECT - Outbound Bytes Protected */ 279 u64 ib_dec_bytes; /* PC_IB_DECRYPT - Inbound Bytes Decrypted */ 280 u64 ib_valid_bytes; /* PC_IB_VALIDATED Inbound Bytes Validated */ 281 u64 rsvd[13]; 282 283 /* CAAM Hardware Instantiation Parameters fa0-fbf */ 284 u32 cha_rev_ms; /* CRNR - CHA Rev No. Most significant half*/ 285 u32 cha_rev_ls; /* CRNR - CHA Rev No. Least significant half*/ 286 #define CTPR_MS_QI_SHIFT 25 287 #define CTPR_MS_QI_MASK (0x1ull << CTPR_MS_QI_SHIFT) 288 #define CTPR_MS_VIRT_EN_INCL 0x00000001 289 #define CTPR_MS_VIRT_EN_POR 0x00000002 290 #define CTPR_MS_PG_SZ_MASK 0x10 291 #define CTPR_MS_PG_SZ_SHIFT 4 292 u32 comp_parms_ms; /* CTPR - Compile Parameters Register */ 293 u32 comp_parms_ls; /* CTPR - Compile Parameters Register */ 294 u64 rsvd1[2]; 295 296 /* CAAM Global Status fc0-fdf */ 297 u64 faultaddr; /* FAR - Fault Address */ 298 u32 faultliodn; /* FALR - Fault Address LIODN */ 299 u32 faultdetail; /* FADR - Fault Addr Detail */ 300 u32 rsvd2; 301 #define CSTA_PLEND BIT(10) 302 #define CSTA_ALT_PLEND BIT(18) 303 u32 status; /* CSTA - CAAM Status */ 304 u64 rsvd3; 305 306 /* Component Instantiation Parameters fe0-fff */ 307 u32 rtic_id; /* RVID - RTIC Version ID */ 308 u32 ccb_id; /* CCBVID - CCB Version ID */ 309 u32 cha_id_ms; /* CHAVID - CHA Version ID Most Significant*/ 310 u32 cha_id_ls; /* CHAVID - CHA Version ID Least Significant*/ 311 u32 cha_num_ms; /* CHANUM - CHA Number Most Significant */ 312 u32 cha_num_ls; /* CHANUM - CHA Number Least Significant*/ 313 u32 caam_id_ms; /* CAAMVID - CAAM Version ID MS */ 314 u32 caam_id_ls; /* CAAMVID - CAAM Version ID LS */ 315 }; 316 317 /* LIODN programming for DMA configuration */ 318 #define MSTRID_LOCK_LIODN 0x80000000 319 #define MSTRID_LOCK_MAKETRUSTED 0x00010000 /* only for JR masterid */ 320 321 #define MSTRID_LIODN_MASK 0x0fff 322 struct masterid { 323 u32 liodn_ms; /* lock and make-trusted control bits */ 324 u32 liodn_ls; /* LIODN for non-sequence and seq access */ 325 }; 326 327 /* Partition ID for DMA configuration */ 328 struct partid { 329 u32 rsvd1; 330 u32 pidr; /* partition ID, DECO */ 331 }; 332 333 /* RNGB test mode (replicated twice in some configurations) */ 334 /* Padded out to 0x100 */ 335 struct rngtst { 336 u32 mode; /* RTSTMODEx - Test mode */ 337 u32 rsvd1[3]; 338 u32 reset; /* RTSTRESETx - Test reset control */ 339 u32 rsvd2[3]; 340 u32 status; /* RTSTSSTATUSx - Test status */ 341 u32 rsvd3; 342 u32 errstat; /* RTSTERRSTATx - Test error status */ 343 u32 rsvd4; 344 u32 errctl; /* RTSTERRCTLx - Test error control */ 345 u32 rsvd5; 346 u32 entropy; /* RTSTENTROPYx - Test entropy */ 347 u32 rsvd6[15]; 348 u32 verifctl; /* RTSTVERIFCTLx - Test verification control */ 349 u32 rsvd7; 350 u32 verifstat; /* RTSTVERIFSTATx - Test verification status */ 351 u32 rsvd8; 352 u32 verifdata; /* RTSTVERIFDx - Test verification data */ 353 u32 rsvd9; 354 u32 xkey; /* RTSTXKEYx - Test XKEY */ 355 u32 rsvd10; 356 u32 oscctctl; /* RTSTOSCCTCTLx - Test osc. counter control */ 357 u32 rsvd11; 358 u32 oscct; /* RTSTOSCCTx - Test oscillator counter */ 359 u32 rsvd12; 360 u32 oscctstat; /* RTSTODCCTSTATx - Test osc counter status */ 361 u32 rsvd13[2]; 362 u32 ofifo[4]; /* RTSTOFIFOx - Test output FIFO */ 363 u32 rsvd14[15]; 364 }; 365 366 /* RNG4 TRNG test registers */ 367 struct rng4tst { 368 #define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */ 369 #define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC 0 /* use von Neumann data in 370 both entropy shifter and 371 statistical checker */ 372 #define RTMCTL_SAMP_MODE_RAW_ES_SC 1 /* use raw data in both 373 entropy shifter and 374 statistical checker */ 375 #define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_RAW_SC 2 /* use von Neumann data in 376 entropy shifter, raw data 377 in statistical checker */ 378 #define RTMCTL_SAMP_MODE_INVALID 3 /* invalid combination */ 379 u32 rtmctl; /* misc. control register */ 380 u32 rtscmisc; /* statistical check misc. register */ 381 u32 rtpkrrng; /* poker range register */ 382 union { 383 u32 rtpkrmax; /* PRGM=1: poker max. limit register */ 384 u32 rtpkrsq; /* PRGM=0: poker square calc. result register */ 385 }; 386 #define RTSDCTL_ENT_DLY_SHIFT 16 387 #define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT) 388 #define RTSDCTL_ENT_DLY_MIN 3200 389 #define RTSDCTL_ENT_DLY_MAX 12800 390 u32 rtsdctl; /* seed control register */ 391 union { 392 u32 rtsblim; /* PRGM=1: sparse bit limit register */ 393 u32 rttotsam; /* PRGM=0: total samples register */ 394 }; 395 u32 rtfrqmin; /* frequency count min. limit register */ 396 #define RTFRQMAX_DISABLE (1 << 20) 397 union { 398 u32 rtfrqmax; /* PRGM=1: freq. count max. limit register */ 399 u32 rtfrqcnt; /* PRGM=0: freq. count register */ 400 }; 401 u32 rsvd1[40]; 402 #define RDSTA_SKVT 0x80000000 403 #define RDSTA_SKVN 0x40000000 404 #define RDSTA_IF0 0x00000001 405 #define RDSTA_IF1 0x00000002 406 #define RDSTA_IFMASK (RDSTA_IF1 | RDSTA_IF0) 407 u32 rdsta; 408 u32 rsvd2[15]; 409 }; 410 411 /* 412 * caam_ctrl - basic core configuration 413 * starts base + 0x0000 padded out to 0x1000 414 */ 415 416 #define KEK_KEY_SIZE 8 417 #define TKEK_KEY_SIZE 8 418 #define TDSK_KEY_SIZE 8 419 420 #define DECO_RESET 1 /* Use with DECO reset/availability regs */ 421 #define DECO_RESET_0 (DECO_RESET << 0) 422 #define DECO_RESET_1 (DECO_RESET << 1) 423 #define DECO_RESET_2 (DECO_RESET << 2) 424 #define DECO_RESET_3 (DECO_RESET << 3) 425 #define DECO_RESET_4 (DECO_RESET << 4) 426 427 struct caam_ctrl { 428 /* Basic Configuration Section 000-01f */ 429 /* Read/Writable */ 430 u32 rsvd1; 431 u32 mcr; /* MCFG Master Config Register */ 432 u32 rsvd2; 433 u32 scfgr; /* SCFGR, Security Config Register */ 434 435 /* Bus Access Configuration Section 010-11f */ 436 /* Read/Writable */ 437 struct masterid jr_mid[4]; /* JRxLIODNR - JobR LIODN setup */ 438 u32 rsvd3[11]; 439 u32 jrstart; /* JRSTART - Job Ring Start Register */ 440 struct masterid rtic_mid[4]; /* RTICxLIODNR - RTIC LIODN setup */ 441 u32 rsvd4[5]; 442 u32 deco_rsr; /* DECORSR - Deco Request Source */ 443 u32 rsvd11; 444 u32 deco_rq; /* DECORR - DECO Request */ 445 struct partid deco_mid[5]; /* DECOxLIODNR - 1 per DECO */ 446 u32 rsvd5[22]; 447 448 /* DECO Availability/Reset Section 120-3ff */ 449 u32 deco_avail; /* DAR - DECO availability */ 450 u32 deco_reset; /* DRR - DECO reset */ 451 u32 rsvd6[182]; 452 453 /* Key Encryption/Decryption Configuration 400-5ff */ 454 /* Read/Writable only while in Non-secure mode */ 455 u32 kek[KEK_KEY_SIZE]; /* JDKEKR - Key Encryption Key */ 456 u32 tkek[TKEK_KEY_SIZE]; /* TDKEKR - Trusted Desc KEK */ 457 u32 tdsk[TDSK_KEY_SIZE]; /* TDSKR - Trusted Desc Signing Key */ 458 u32 rsvd7[32]; 459 u64 sknonce; /* SKNR - Secure Key Nonce */ 460 u32 rsvd8[70]; 461 462 /* RNG Test/Verification/Debug Access 600-7ff */ 463 /* (Useful in Test/Debug modes only...) */ 464 union { 465 struct rngtst rtst[2]; 466 struct rng4tst r4tst[2]; 467 }; 468 469 u32 rsvd9[448]; 470 471 /* Performance Monitor f00-fff */ 472 struct caam_perfmon perfmon; 473 }; 474 475 /* 476 * Controller master config register defs 477 */ 478 #define MCFGR_SWRESET 0x80000000 /* software reset */ 479 #define MCFGR_WDENABLE 0x40000000 /* DECO watchdog enable */ 480 #define MCFGR_WDFAIL 0x20000000 /* DECO watchdog force-fail */ 481 #define MCFGR_DMA_RESET 0x10000000 482 #define MCFGR_LONG_PTR 0x00010000 /* Use >32-bit desc addressing */ 483 #define SCFGR_RDBENABLE 0x00000400 484 #define SCFGR_VIRT_EN 0x00008000 485 #define DECORR_RQD0ENABLE 0x00000001 /* Enable DECO0 for direct access */ 486 #define DECORSR_JR0 0x00000001 /* JR to supply TZ, SDID, ICID */ 487 #define DECORSR_VALID 0x80000000 488 #define DECORR_DEN0 0x00010000 /* DECO0 available for access*/ 489 490 /* AXI read cache control */ 491 #define MCFGR_ARCACHE_SHIFT 12 492 #define MCFGR_ARCACHE_MASK (0xf << MCFGR_ARCACHE_SHIFT) 493 #define MCFGR_ARCACHE_BUFF (0x1 << MCFGR_ARCACHE_SHIFT) 494 #define MCFGR_ARCACHE_CACH (0x2 << MCFGR_ARCACHE_SHIFT) 495 #define MCFGR_ARCACHE_RALL (0x4 << MCFGR_ARCACHE_SHIFT) 496 497 /* AXI write cache control */ 498 #define MCFGR_AWCACHE_SHIFT 8 499 #define MCFGR_AWCACHE_MASK (0xf << MCFGR_AWCACHE_SHIFT) 500 #define MCFGR_AWCACHE_BUFF (0x1 << MCFGR_AWCACHE_SHIFT) 501 #define MCFGR_AWCACHE_CACH (0x2 << MCFGR_AWCACHE_SHIFT) 502 #define MCFGR_AWCACHE_WALL (0x8 << MCFGR_AWCACHE_SHIFT) 503 504 /* AXI pipeline depth */ 505 #define MCFGR_AXIPIPE_SHIFT 4 506 #define MCFGR_AXIPIPE_MASK (0xf << MCFGR_AXIPIPE_SHIFT) 507 508 #define MCFGR_AXIPRI 0x00000008 /* Assert AXI priority sideband */ 509 #define MCFGR_LARGE_BURST 0x00000004 /* 128/256-byte burst size */ 510 #define MCFGR_BURST_64 0x00000001 /* 64-byte burst size */ 511 512 /* JRSTART register offsets */ 513 #define JRSTART_JR0_START 0x00000001 /* Start Job ring 0 */ 514 #define JRSTART_JR1_START 0x00000002 /* Start Job ring 1 */ 515 #define JRSTART_JR2_START 0x00000004 /* Start Job ring 2 */ 516 #define JRSTART_JR3_START 0x00000008 /* Start Job ring 3 */ 517 518 /* 519 * caam_job_ring - direct job ring setup 520 * 1-4 possible per instantiation, base + 1000/2000/3000/4000 521 * Padded out to 0x1000 522 */ 523 struct caam_job_ring { 524 /* Input ring */ 525 u64 inpring_base; /* IRBAx - Input desc ring baseaddr */ 526 u32 rsvd1; 527 u32 inpring_size; /* IRSx - Input ring size */ 528 u32 rsvd2; 529 u32 inpring_avail; /* IRSAx - Input ring room remaining */ 530 u32 rsvd3; 531 u32 inpring_jobadd; /* IRJAx - Input ring jobs added */ 532 533 /* Output Ring */ 534 u64 outring_base; /* ORBAx - Output status ring base addr */ 535 u32 rsvd4; 536 u32 outring_size; /* ORSx - Output ring size */ 537 u32 rsvd5; 538 u32 outring_rmvd; /* ORJRx - Output ring jobs removed */ 539 u32 rsvd6; 540 u32 outring_used; /* ORSFx - Output ring slots full */ 541 542 /* Status/Configuration */ 543 u32 rsvd7; 544 u32 jroutstatus; /* JRSTAx - JobR output status */ 545 u32 rsvd8; 546 u32 jrintstatus; /* JRINTx - JobR interrupt status */ 547 u32 rconfig_hi; /* JRxCFG - Ring configuration */ 548 u32 rconfig_lo; 549 550 /* Indices. CAAM maintains as "heads" of each queue */ 551 u32 rsvd9; 552 u32 inp_rdidx; /* IRRIx - Input ring read index */ 553 u32 rsvd10; 554 u32 out_wtidx; /* ORWIx - Output ring write index */ 555 556 /* Command/control */ 557 u32 rsvd11; 558 u32 jrcommand; /* JRCRx - JobR command */ 559 560 u32 rsvd12[932]; 561 562 /* Performance Monitor f00-fff */ 563 struct caam_perfmon perfmon; 564 }; 565 566 #define JR_RINGSIZE_MASK 0x03ff 567 /* 568 * jrstatus - Job Ring Output Status 569 * All values in lo word 570 * Also note, same values written out as status through QI 571 * in the command/status field of a frame descriptor 572 */ 573 #define JRSTA_SSRC_SHIFT 28 574 #define JRSTA_SSRC_MASK 0xf0000000 575 576 #define JRSTA_SSRC_NONE 0x00000000 577 #define JRSTA_SSRC_CCB_ERROR 0x20000000 578 #define JRSTA_SSRC_JUMP_HALT_USER 0x30000000 579 #define JRSTA_SSRC_DECO 0x40000000 580 #define JRSTA_SSRC_JRERROR 0x60000000 581 #define JRSTA_SSRC_JUMP_HALT_CC 0x70000000 582 583 #define JRSTA_DECOERR_JUMP 0x08000000 584 #define JRSTA_DECOERR_INDEX_SHIFT 8 585 #define JRSTA_DECOERR_INDEX_MASK 0xff00 586 #define JRSTA_DECOERR_ERROR_MASK 0x00ff 587 588 #define JRSTA_DECOERR_NONE 0x00 589 #define JRSTA_DECOERR_LINKLEN 0x01 590 #define JRSTA_DECOERR_LINKPTR 0x02 591 #define JRSTA_DECOERR_JRCTRL 0x03 592 #define JRSTA_DECOERR_DESCCMD 0x04 593 #define JRSTA_DECOERR_ORDER 0x05 594 #define JRSTA_DECOERR_KEYCMD 0x06 595 #define JRSTA_DECOERR_LOADCMD 0x07 596 #define JRSTA_DECOERR_STORECMD 0x08 597 #define JRSTA_DECOERR_OPCMD 0x09 598 #define JRSTA_DECOERR_FIFOLDCMD 0x0a 599 #define JRSTA_DECOERR_FIFOSTCMD 0x0b 600 #define JRSTA_DECOERR_MOVECMD 0x0c 601 #define JRSTA_DECOERR_JUMPCMD 0x0d 602 #define JRSTA_DECOERR_MATHCMD 0x0e 603 #define JRSTA_DECOERR_SHASHCMD 0x0f 604 #define JRSTA_DECOERR_SEQCMD 0x10 605 #define JRSTA_DECOERR_DECOINTERNAL 0x11 606 #define JRSTA_DECOERR_SHDESCHDR 0x12 607 #define JRSTA_DECOERR_HDRLEN 0x13 608 #define JRSTA_DECOERR_BURSTER 0x14 609 #define JRSTA_DECOERR_DESCSIGNATURE 0x15 610 #define JRSTA_DECOERR_DMA 0x16 611 #define JRSTA_DECOERR_BURSTFIFO 0x17 612 #define JRSTA_DECOERR_JRRESET 0x1a 613 #define JRSTA_DECOERR_JOBFAIL 0x1b 614 #define JRSTA_DECOERR_DNRERR 0x80 615 #define JRSTA_DECOERR_UNDEFPCL 0x81 616 #define JRSTA_DECOERR_PDBERR 0x82 617 #define JRSTA_DECOERR_ANRPLY_LATE 0x83 618 #define JRSTA_DECOERR_ANRPLY_REPLAY 0x84 619 #define JRSTA_DECOERR_SEQOVF 0x85 620 #define JRSTA_DECOERR_INVSIGN 0x86 621 #define JRSTA_DECOERR_DSASIGN 0x87 622 623 #define JRSTA_CCBERR_JUMP 0x08000000 624 #define JRSTA_CCBERR_INDEX_MASK 0xff00 625 #define JRSTA_CCBERR_INDEX_SHIFT 8 626 #define JRSTA_CCBERR_CHAID_MASK 0x00f0 627 #define JRSTA_CCBERR_CHAID_SHIFT 4 628 #define JRSTA_CCBERR_ERRID_MASK 0x000f 629 630 #define JRSTA_CCBERR_CHAID_AES (0x01 << JRSTA_CCBERR_CHAID_SHIFT) 631 #define JRSTA_CCBERR_CHAID_DES (0x02 << JRSTA_CCBERR_CHAID_SHIFT) 632 #define JRSTA_CCBERR_CHAID_ARC4 (0x03 << JRSTA_CCBERR_CHAID_SHIFT) 633 #define JRSTA_CCBERR_CHAID_MD (0x04 << JRSTA_CCBERR_CHAID_SHIFT) 634 #define JRSTA_CCBERR_CHAID_RNG (0x05 << JRSTA_CCBERR_CHAID_SHIFT) 635 #define JRSTA_CCBERR_CHAID_SNOW (0x06 << JRSTA_CCBERR_CHAID_SHIFT) 636 #define JRSTA_CCBERR_CHAID_KASUMI (0x07 << JRSTA_CCBERR_CHAID_SHIFT) 637 #define JRSTA_CCBERR_CHAID_PK (0x08 << JRSTA_CCBERR_CHAID_SHIFT) 638 #define JRSTA_CCBERR_CHAID_CRC (0x09 << JRSTA_CCBERR_CHAID_SHIFT) 639 640 #define JRSTA_CCBERR_ERRID_NONE 0x00 641 #define JRSTA_CCBERR_ERRID_MODE 0x01 642 #define JRSTA_CCBERR_ERRID_DATASIZ 0x02 643 #define JRSTA_CCBERR_ERRID_KEYSIZ 0x03 644 #define JRSTA_CCBERR_ERRID_PKAMEMSZ 0x04 645 #define JRSTA_CCBERR_ERRID_PKBMEMSZ 0x05 646 #define JRSTA_CCBERR_ERRID_SEQUENCE 0x06 647 #define JRSTA_CCBERR_ERRID_PKDIVZRO 0x07 648 #define JRSTA_CCBERR_ERRID_PKMODEVN 0x08 649 #define JRSTA_CCBERR_ERRID_KEYPARIT 0x09 650 #define JRSTA_CCBERR_ERRID_ICVCHK 0x0a 651 #define JRSTA_CCBERR_ERRID_HARDWARE 0x0b 652 #define JRSTA_CCBERR_ERRID_CCMAAD 0x0c 653 #define JRSTA_CCBERR_ERRID_INVCHA 0x0f 654 655 #define JRINT_ERR_INDEX_MASK 0x3fff0000 656 #define JRINT_ERR_INDEX_SHIFT 16 657 #define JRINT_ERR_TYPE_MASK 0xf00 658 #define JRINT_ERR_TYPE_SHIFT 8 659 #define JRINT_ERR_HALT_MASK 0xc 660 #define JRINT_ERR_HALT_SHIFT 2 661 #define JRINT_ERR_HALT_INPROGRESS 0x4 662 #define JRINT_ERR_HALT_COMPLETE 0x8 663 #define JRINT_JR_ERROR 0x02 664 #define JRINT_JR_INT 0x01 665 666 #define JRINT_ERR_TYPE_WRITE 1 667 #define JRINT_ERR_TYPE_BAD_INPADDR 3 668 #define JRINT_ERR_TYPE_BAD_OUTADDR 4 669 #define JRINT_ERR_TYPE_INV_INPWRT 5 670 #define JRINT_ERR_TYPE_INV_OUTWRT 6 671 #define JRINT_ERR_TYPE_RESET 7 672 #define JRINT_ERR_TYPE_REMOVE_OFL 8 673 #define JRINT_ERR_TYPE_ADD_OFL 9 674 675 #define JRCFG_SOE 0x04 676 #define JRCFG_ICEN 0x02 677 #define JRCFG_IMSK 0x01 678 #define JRCFG_ICDCT_SHIFT 8 679 #define JRCFG_ICTT_SHIFT 16 680 681 #define JRCR_RESET 0x01 682 683 /* 684 * caam_assurance - Assurance Controller View 685 * base + 0x6000 padded out to 0x1000 686 */ 687 688 struct rtic_element { 689 u64 address; 690 u32 rsvd; 691 u32 length; 692 }; 693 694 struct rtic_block { 695 struct rtic_element element[2]; 696 }; 697 698 struct rtic_memhash { 699 u32 memhash_be[32]; 700 u32 memhash_le[32]; 701 }; 702 703 struct caam_assurance { 704 /* Status/Command/Watchdog */ 705 u32 rsvd1; 706 u32 status; /* RSTA - Status */ 707 u32 rsvd2; 708 u32 cmd; /* RCMD - Command */ 709 u32 rsvd3; 710 u32 ctrl; /* RCTL - Control */ 711 u32 rsvd4; 712 u32 throttle; /* RTHR - Throttle */ 713 u32 rsvd5[2]; 714 u64 watchdog; /* RWDOG - Watchdog Timer */ 715 u32 rsvd6; 716 u32 rend; /* REND - Endian corrections */ 717 u32 rsvd7[50]; 718 719 /* Block access/configuration @ 100/110/120/130 */ 720 struct rtic_block memblk[4]; /* Memory Blocks A-D */ 721 u32 rsvd8[32]; 722 723 /* Block hashes @ 200/300/400/500 */ 724 struct rtic_memhash hash[4]; /* Block hash values A-D */ 725 u32 rsvd_3[640]; 726 }; 727 728 /* 729 * caam_queue_if - QI configuration and control 730 * starts base + 0x7000, padded out to 0x1000 long 731 */ 732 733 struct caam_queue_if { 734 u32 qi_control_hi; /* QICTL - QI Control */ 735 u32 qi_control_lo; 736 u32 rsvd1; 737 u32 qi_status; /* QISTA - QI Status */ 738 u32 qi_deq_cfg_hi; /* QIDQC - QI Dequeue Configuration */ 739 u32 qi_deq_cfg_lo; 740 u32 qi_enq_cfg_hi; /* QISEQC - QI Enqueue Command */ 741 u32 qi_enq_cfg_lo; 742 u32 rsvd2[1016]; 743 }; 744 745 /* QI control bits - low word */ 746 #define QICTL_DQEN 0x01 /* Enable frame pop */ 747 #define QICTL_STOP 0x02 /* Stop dequeue/enqueue */ 748 #define QICTL_SOE 0x04 /* Stop on error */ 749 750 /* QI control bits - high word */ 751 #define QICTL_MBSI 0x01 752 #define QICTL_MHWSI 0x02 753 #define QICTL_MWSI 0x04 754 #define QICTL_MDWSI 0x08 755 #define QICTL_CBSI 0x10 /* CtrlDataByteSwapInput */ 756 #define QICTL_CHWSI 0x20 /* CtrlDataHalfSwapInput */ 757 #define QICTL_CWSI 0x40 /* CtrlDataWordSwapInput */ 758 #define QICTL_CDWSI 0x80 /* CtrlDataDWordSwapInput */ 759 #define QICTL_MBSO 0x0100 760 #define QICTL_MHWSO 0x0200 761 #define QICTL_MWSO 0x0400 762 #define QICTL_MDWSO 0x0800 763 #define QICTL_CBSO 0x1000 /* CtrlDataByteSwapOutput */ 764 #define QICTL_CHWSO 0x2000 /* CtrlDataHalfSwapOutput */ 765 #define QICTL_CWSO 0x4000 /* CtrlDataWordSwapOutput */ 766 #define QICTL_CDWSO 0x8000 /* CtrlDataDWordSwapOutput */ 767 #define QICTL_DMBS 0x010000 768 #define QICTL_EPO 0x020000 769 770 /* QI status bits */ 771 #define QISTA_PHRDERR 0x01 /* PreHeader Read Error */ 772 #define QISTA_CFRDERR 0x02 /* Compound Frame Read Error */ 773 #define QISTA_OFWRERR 0x04 /* Output Frame Read Error */ 774 #define QISTA_BPDERR 0x08 /* Buffer Pool Depleted */ 775 #define QISTA_BTSERR 0x10 /* Buffer Undersize */ 776 #define QISTA_CFWRERR 0x20 /* Compound Frame Write Err */ 777 #define QISTA_STOPD 0x80000000 /* QI Stopped (see QICTL) */ 778 779 /* deco_sg_table - DECO view of scatter/gather table */ 780 struct deco_sg_table { 781 u64 addr; /* Segment Address */ 782 u32 elen; /* E, F bits + 30-bit length */ 783 u32 bpid_offset; /* Buffer Pool ID + 16-bit length */ 784 }; 785 786 /* 787 * caam_deco - descriptor controller - CHA cluster block 788 * 789 * Only accessible when direct DECO access is turned on 790 * (done in DECORR, via MID programmed in DECOxMID 791 * 792 * 5 typical, base + 0x8000/9000/a000/b000 793 * Padded out to 0x1000 long 794 */ 795 struct caam_deco { 796 u32 rsvd1; 797 u32 cls1_mode; /* CxC1MR - Class 1 Mode */ 798 u32 rsvd2; 799 u32 cls1_keysize; /* CxC1KSR - Class 1 Key Size */ 800 u32 cls1_datasize_hi; /* CxC1DSR - Class 1 Data Size */ 801 u32 cls1_datasize_lo; 802 u32 rsvd3; 803 u32 cls1_icvsize; /* CxC1ICVSR - Class 1 ICV size */ 804 u32 rsvd4[5]; 805 u32 cha_ctrl; /* CCTLR - CHA control */ 806 u32 rsvd5; 807 u32 irq_crtl; /* CxCIRQ - CCB interrupt done/error/clear */ 808 u32 rsvd6; 809 u32 clr_written; /* CxCWR - Clear-Written */ 810 u32 ccb_status_hi; /* CxCSTA - CCB Status/Error */ 811 u32 ccb_status_lo; 812 u32 rsvd7[3]; 813 u32 aad_size; /* CxAADSZR - Current AAD Size */ 814 u32 rsvd8; 815 u32 cls1_iv_size; /* CxC1IVSZR - Current Class 1 IV Size */ 816 u32 rsvd9[7]; 817 u32 pkha_a_size; /* PKASZRx - Size of PKHA A */ 818 u32 rsvd10; 819 u32 pkha_b_size; /* PKBSZRx - Size of PKHA B */ 820 u32 rsvd11; 821 u32 pkha_n_size; /* PKNSZRx - Size of PKHA N */ 822 u32 rsvd12; 823 u32 pkha_e_size; /* PKESZRx - Size of PKHA E */ 824 u32 rsvd13[24]; 825 u32 cls1_ctx[16]; /* CxC1CTXR - Class 1 Context @100 */ 826 u32 rsvd14[48]; 827 u32 cls1_key[8]; /* CxC1KEYR - Class 1 Key @200 */ 828 u32 rsvd15[121]; 829 u32 cls2_mode; /* CxC2MR - Class 2 Mode */ 830 u32 rsvd16; 831 u32 cls2_keysize; /* CxX2KSR - Class 2 Key Size */ 832 u32 cls2_datasize_hi; /* CxC2DSR - Class 2 Data Size */ 833 u32 cls2_datasize_lo; 834 u32 rsvd17; 835 u32 cls2_icvsize; /* CxC2ICVSZR - Class 2 ICV Size */ 836 u32 rsvd18[56]; 837 u32 cls2_ctx[18]; /* CxC2CTXR - Class 2 Context @500 */ 838 u32 rsvd19[46]; 839 u32 cls2_key[32]; /* CxC2KEYR - Class2 Key @600 */ 840 u32 rsvd20[84]; 841 u32 inp_infofifo_hi; /* CxIFIFO - Input Info FIFO @7d0 */ 842 u32 inp_infofifo_lo; 843 u32 rsvd21[2]; 844 u64 inp_datafifo; /* CxDFIFO - Input Data FIFO */ 845 u32 rsvd22[2]; 846 u64 out_datafifo; /* CxOFIFO - Output Data FIFO */ 847 u32 rsvd23[2]; 848 u32 jr_ctl_hi; /* CxJRR - JobR Control Register @800 */ 849 u32 jr_ctl_lo; 850 u64 jr_descaddr; /* CxDADR - JobR Descriptor Address */ 851 #define DECO_OP_STATUS_HI_ERR_MASK 0xF00000FF 852 u32 op_status_hi; /* DxOPSTA - DECO Operation Status */ 853 u32 op_status_lo; 854 u32 rsvd24[2]; 855 u32 liodn; /* DxLSR - DECO LIODN Status - non-seq */ 856 u32 td_liodn; /* DxLSR - DECO LIODN Status - trustdesc */ 857 u32 rsvd26[6]; 858 u64 math[4]; /* DxMTH - Math register */ 859 u32 rsvd27[8]; 860 struct deco_sg_table gthr_tbl[4]; /* DxGTR - Gather Tables */ 861 u32 rsvd28[16]; 862 struct deco_sg_table sctr_tbl[4]; /* DxSTR - Scatter Tables */ 863 u32 rsvd29[48]; 864 u32 descbuf[64]; /* DxDESB - Descriptor buffer */ 865 u32 rscvd30[193]; 866 #define DESC_DBG_DECO_STAT_HOST_ERR 0x00D00000 867 #define DESC_DBG_DECO_STAT_VALID 0x80000000 868 #define DESC_DBG_DECO_STAT_MASK 0x00F00000 869 u32 desc_dbg; /* DxDDR - DECO Debug Register */ 870 u32 rsvd31[126]; 871 }; 872 873 #define DECO_JQCR_WHL 0x20000000 874 #define DECO_JQCR_FOUR 0x10000000 875 876 #define JR_BLOCK_NUMBER 1 877 #define ASSURE_BLOCK_NUMBER 6 878 #define QI_BLOCK_NUMBER 7 879 #define DECO_BLOCK_NUMBER 8 880 #define PG_SIZE_4K 0x1000 881 #define PG_SIZE_64K 0x10000 882 #endif /* REGS_H */ 883