1 /* * CAAM control-plane driver backend 2 * Controller-level driver, kernel property detection, initialization 3 * 4 * Copyright 2008-2012 Freescale Semiconductor, Inc. 5 */ 6 7 #include <linux/device.h> 8 #include <linux/of_address.h> 9 #include <linux/of_irq.h> 10 #include <linux/sys_soc.h> 11 12 #include "compat.h" 13 #include "regs.h" 14 #include "intern.h" 15 #include "jr.h" 16 #include "desc_constr.h" 17 #include "ctrl.h" 18 19 bool caam_little_end; 20 EXPORT_SYMBOL(caam_little_end); 21 bool caam_dpaa2; 22 EXPORT_SYMBOL(caam_dpaa2); 23 bool caam_imx; 24 EXPORT_SYMBOL(caam_imx); 25 26 #ifdef CONFIG_CAAM_QI 27 #include "qi.h" 28 #endif 29 30 /* 31 * i.MX targets tend to have clock control subsystems that can 32 * enable/disable clocking to our device. 33 */ 34 static inline struct clk *caam_drv_identify_clk(struct device *dev, 35 char *clk_name) 36 { 37 return caam_imx ? devm_clk_get(dev, clk_name) : NULL; 38 } 39 40 /* 41 * Descriptor to instantiate RNG State Handle 0 in normal mode and 42 * load the JDKEK, TDKEK and TDSK registers 43 */ 44 static void build_instantiation_desc(u32 *desc, int handle, int do_sk) 45 { 46 u32 *jump_cmd, op_flags; 47 48 init_job_desc(desc, 0); 49 50 op_flags = OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG | 51 (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INIT; 52 53 /* INIT RNG in non-test mode */ 54 append_operation(desc, op_flags); 55 56 if (!handle && do_sk) { 57 /* 58 * For SH0, Secure Keys must be generated as well 59 */ 60 61 /* wait for done */ 62 jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1); 63 set_jump_tgt_here(desc, jump_cmd); 64 65 /* 66 * load 1 to clear written reg: 67 * resets the done interrrupt and returns the RNG to idle. 68 */ 69 append_load_imm_u32(desc, 1, LDST_SRCDST_WORD_CLRW); 70 71 /* Initialize State Handle */ 72 append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG | 73 OP_ALG_AAI_RNG4_SK); 74 } 75 76 append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT); 77 } 78 79 /* Descriptor for deinstantiation of State Handle 0 of the RNG block. */ 80 static void build_deinstantiation_desc(u32 *desc, int handle) 81 { 82 init_job_desc(desc, 0); 83 84 /* Uninstantiate State Handle 0 */ 85 append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG | 86 (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INITFINAL); 87 88 append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT); 89 } 90 91 /* 92 * run_descriptor_deco0 - runs a descriptor on DECO0, under direct control of 93 * the software (no JR/QI used). 94 * @ctrldev - pointer to device 95 * @status - descriptor status, after being run 96 * 97 * Return: - 0 if no error occurred 98 * - -ENODEV if the DECO couldn't be acquired 99 * - -EAGAIN if an error occurred while executing the descriptor 100 */ 101 static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc, 102 u32 *status) 103 { 104 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev); 105 struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl; 106 struct caam_deco __iomem *deco = ctrlpriv->deco; 107 unsigned int timeout = 100000; 108 u32 deco_dbg_reg, flags; 109 int i; 110 111 112 if (ctrlpriv->virt_en == 1) { 113 clrsetbits_32(&ctrl->deco_rsr, 0, DECORSR_JR0); 114 115 while (!(rd_reg32(&ctrl->deco_rsr) & DECORSR_VALID) && 116 --timeout) 117 cpu_relax(); 118 119 timeout = 100000; 120 } 121 122 clrsetbits_32(&ctrl->deco_rq, 0, DECORR_RQD0ENABLE); 123 124 while (!(rd_reg32(&ctrl->deco_rq) & DECORR_DEN0) && 125 --timeout) 126 cpu_relax(); 127 128 if (!timeout) { 129 dev_err(ctrldev, "failed to acquire DECO 0\n"); 130 clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0); 131 return -ENODEV; 132 } 133 134 for (i = 0; i < desc_len(desc); i++) 135 wr_reg32(&deco->descbuf[i], caam32_to_cpu(*(desc + i))); 136 137 flags = DECO_JQCR_WHL; 138 /* 139 * If the descriptor length is longer than 4 words, then the 140 * FOUR bit in JRCTRL register must be set. 141 */ 142 if (desc_len(desc) >= 4) 143 flags |= DECO_JQCR_FOUR; 144 145 /* Instruct the DECO to execute it */ 146 clrsetbits_32(&deco->jr_ctl_hi, 0, flags); 147 148 timeout = 10000000; 149 do { 150 deco_dbg_reg = rd_reg32(&deco->desc_dbg); 151 /* 152 * If an error occured in the descriptor, then 153 * the DECO status field will be set to 0x0D 154 */ 155 if ((deco_dbg_reg & DESC_DBG_DECO_STAT_MASK) == 156 DESC_DBG_DECO_STAT_HOST_ERR) 157 break; 158 cpu_relax(); 159 } while ((deco_dbg_reg & DESC_DBG_DECO_STAT_VALID) && --timeout); 160 161 *status = rd_reg32(&deco->op_status_hi) & 162 DECO_OP_STATUS_HI_ERR_MASK; 163 164 if (ctrlpriv->virt_en == 1) 165 clrsetbits_32(&ctrl->deco_rsr, DECORSR_JR0, 0); 166 167 /* Mark the DECO as free */ 168 clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0); 169 170 if (!timeout) 171 return -EAGAIN; 172 173 return 0; 174 } 175 176 /* 177 * instantiate_rng - builds and executes a descriptor on DECO0, 178 * which initializes the RNG block. 179 * @ctrldev - pointer to device 180 * @state_handle_mask - bitmask containing the instantiation status 181 * for the RNG4 state handles which exist in 182 * the RNG4 block: 1 if it's been instantiated 183 * by an external entry, 0 otherwise. 184 * @gen_sk - generate data to be loaded into the JDKEK, TDKEK and TDSK; 185 * Caution: this can be done only once; if the keys need to be 186 * regenerated, a POR is required 187 * 188 * Return: - 0 if no error occurred 189 * - -ENOMEM if there isn't enough memory to allocate the descriptor 190 * - -ENODEV if DECO0 couldn't be acquired 191 * - -EAGAIN if an error occurred when executing the descriptor 192 * f.i. there was a RNG hardware error due to not "good enough" 193 * entropy being aquired. 194 */ 195 static int instantiate_rng(struct device *ctrldev, int state_handle_mask, 196 int gen_sk) 197 { 198 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev); 199 struct caam_ctrl __iomem *ctrl; 200 u32 *desc, status = 0, rdsta_val; 201 int ret = 0, sh_idx; 202 203 ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl; 204 desc = kmalloc(CAAM_CMD_SZ * 7, GFP_KERNEL); 205 if (!desc) 206 return -ENOMEM; 207 208 for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) { 209 /* 210 * If the corresponding bit is set, this state handle 211 * was initialized by somebody else, so it's left alone. 212 */ 213 if ((1 << sh_idx) & state_handle_mask) 214 continue; 215 216 /* Create the descriptor for instantiating RNG State Handle */ 217 build_instantiation_desc(desc, sh_idx, gen_sk); 218 219 /* Try to run it through DECO0 */ 220 ret = run_descriptor_deco0(ctrldev, desc, &status); 221 222 /* 223 * If ret is not 0, or descriptor status is not 0, then 224 * something went wrong. No need to try the next state 225 * handle (if available), bail out here. 226 * Also, if for some reason, the State Handle didn't get 227 * instantiated although the descriptor has finished 228 * without any error (HW optimizations for later 229 * CAAM eras), then try again. 230 */ 231 if (ret) 232 break; 233 234 rdsta_val = rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_IFMASK; 235 if ((status && status != JRSTA_SSRC_JUMP_HALT_CC) || 236 !(rdsta_val & (1 << sh_idx))) { 237 ret = -EAGAIN; 238 break; 239 } 240 241 dev_info(ctrldev, "Instantiated RNG4 SH%d\n", sh_idx); 242 /* Clear the contents before recreating the descriptor */ 243 memset(desc, 0x00, CAAM_CMD_SZ * 7); 244 } 245 246 kfree(desc); 247 248 return ret; 249 } 250 251 /* 252 * deinstantiate_rng - builds and executes a descriptor on DECO0, 253 * which deinitializes the RNG block. 254 * @ctrldev - pointer to device 255 * @state_handle_mask - bitmask containing the instantiation status 256 * for the RNG4 state handles which exist in 257 * the RNG4 block: 1 if it's been instantiated 258 * 259 * Return: - 0 if no error occurred 260 * - -ENOMEM if there isn't enough memory to allocate the descriptor 261 * - -ENODEV if DECO0 couldn't be acquired 262 * - -EAGAIN if an error occurred when executing the descriptor 263 */ 264 static int deinstantiate_rng(struct device *ctrldev, int state_handle_mask) 265 { 266 u32 *desc, status; 267 int sh_idx, ret = 0; 268 269 desc = kmalloc(CAAM_CMD_SZ * 3, GFP_KERNEL); 270 if (!desc) 271 return -ENOMEM; 272 273 for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) { 274 /* 275 * If the corresponding bit is set, then it means the state 276 * handle was initialized by us, and thus it needs to be 277 * deinitialized as well 278 */ 279 if ((1 << sh_idx) & state_handle_mask) { 280 /* 281 * Create the descriptor for deinstantating this state 282 * handle 283 */ 284 build_deinstantiation_desc(desc, sh_idx); 285 286 /* Try to run it through DECO0 */ 287 ret = run_descriptor_deco0(ctrldev, desc, &status); 288 289 if (ret || 290 (status && status != JRSTA_SSRC_JUMP_HALT_CC)) { 291 dev_err(ctrldev, 292 "Failed to deinstantiate RNG4 SH%d\n", 293 sh_idx); 294 break; 295 } 296 dev_info(ctrldev, "Deinstantiated RNG4 SH%d\n", sh_idx); 297 } 298 } 299 300 kfree(desc); 301 302 return ret; 303 } 304 305 static int caam_remove(struct platform_device *pdev) 306 { 307 struct device *ctrldev; 308 struct caam_drv_private *ctrlpriv; 309 struct caam_ctrl __iomem *ctrl; 310 311 ctrldev = &pdev->dev; 312 ctrlpriv = dev_get_drvdata(ctrldev); 313 ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl; 314 315 /* Remove platform devices under the crypto node */ 316 of_platform_depopulate(ctrldev); 317 318 #ifdef CONFIG_CAAM_QI 319 if (ctrlpriv->qidev) 320 caam_qi_shutdown(ctrlpriv->qidev); 321 #endif 322 323 /* 324 * De-initialize RNG state handles initialized by this driver. 325 * In case of SoCs with Management Complex, RNG is managed by MC f/w. 326 */ 327 if (!ctrlpriv->mc_en && ctrlpriv->rng4_sh_init) 328 deinstantiate_rng(ctrldev, ctrlpriv->rng4_sh_init); 329 330 /* Shut down debug views */ 331 #ifdef CONFIG_DEBUG_FS 332 debugfs_remove_recursive(ctrlpriv->dfs_root); 333 #endif 334 335 /* Unmap controller region */ 336 iounmap(ctrl); 337 338 /* shut clocks off before finalizing shutdown */ 339 clk_disable_unprepare(ctrlpriv->caam_ipg); 340 if (ctrlpriv->caam_mem) 341 clk_disable_unprepare(ctrlpriv->caam_mem); 342 clk_disable_unprepare(ctrlpriv->caam_aclk); 343 if (ctrlpriv->caam_emi_slow) 344 clk_disable_unprepare(ctrlpriv->caam_emi_slow); 345 return 0; 346 } 347 348 /* 349 * kick_trng - sets the various parameters for enabling the initialization 350 * of the RNG4 block in CAAM 351 * @pdev - pointer to the platform device 352 * @ent_delay - Defines the length (in system clocks) of each entropy sample. 353 */ 354 static void kick_trng(struct platform_device *pdev, int ent_delay) 355 { 356 struct device *ctrldev = &pdev->dev; 357 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev); 358 struct caam_ctrl __iomem *ctrl; 359 struct rng4tst __iomem *r4tst; 360 u32 val; 361 362 ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl; 363 r4tst = &ctrl->r4tst[0]; 364 365 /* put RNG4 into program mode */ 366 clrsetbits_32(&r4tst->rtmctl, 0, RTMCTL_PRGM); 367 368 /* 369 * Performance-wise, it does not make sense to 370 * set the delay to a value that is lower 371 * than the last one that worked (i.e. the state handles 372 * were instantiated properly. Thus, instead of wasting 373 * time trying to set the values controlling the sample 374 * frequency, the function simply returns. 375 */ 376 val = (rd_reg32(&r4tst->rtsdctl) & RTSDCTL_ENT_DLY_MASK) 377 >> RTSDCTL_ENT_DLY_SHIFT; 378 if (ent_delay <= val) 379 goto start_rng; 380 381 val = rd_reg32(&r4tst->rtsdctl); 382 val = (val & ~RTSDCTL_ENT_DLY_MASK) | 383 (ent_delay << RTSDCTL_ENT_DLY_SHIFT); 384 wr_reg32(&r4tst->rtsdctl, val); 385 /* min. freq. count, equal to 1/4 of the entropy sample length */ 386 wr_reg32(&r4tst->rtfrqmin, ent_delay >> 2); 387 /* disable maximum frequency count */ 388 wr_reg32(&r4tst->rtfrqmax, RTFRQMAX_DISABLE); 389 /* read the control register */ 390 val = rd_reg32(&r4tst->rtmctl); 391 start_rng: 392 /* 393 * select raw sampling in both entropy shifter 394 * and statistical checker; ; put RNG4 into run mode 395 */ 396 clrsetbits_32(&r4tst->rtmctl, RTMCTL_PRGM, RTMCTL_SAMP_MODE_RAW_ES_SC); 397 } 398 399 static int caam_get_era_from_hw(struct caam_ctrl __iomem *ctrl) 400 { 401 static const struct { 402 u16 ip_id; 403 u8 maj_rev; 404 u8 era; 405 } id[] = { 406 {0x0A10, 1, 1}, 407 {0x0A10, 2, 2}, 408 {0x0A12, 1, 3}, 409 {0x0A14, 1, 3}, 410 {0x0A14, 2, 4}, 411 {0x0A16, 1, 4}, 412 {0x0A10, 3, 4}, 413 {0x0A11, 1, 4}, 414 {0x0A18, 1, 4}, 415 {0x0A11, 2, 5}, 416 {0x0A12, 2, 5}, 417 {0x0A13, 1, 5}, 418 {0x0A1C, 1, 5} 419 }; 420 u32 ccbvid, id_ms; 421 u8 maj_rev, era; 422 u16 ip_id; 423 int i; 424 425 ccbvid = rd_reg32(&ctrl->perfmon.ccb_id); 426 era = (ccbvid & CCBVID_ERA_MASK) >> CCBVID_ERA_SHIFT; 427 if (era) /* This is '0' prior to CAAM ERA-6 */ 428 return era; 429 430 id_ms = rd_reg32(&ctrl->perfmon.caam_id_ms); 431 ip_id = (id_ms & SECVID_MS_IPID_MASK) >> SECVID_MS_IPID_SHIFT; 432 maj_rev = (id_ms & SECVID_MS_MAJ_REV_MASK) >> SECVID_MS_MAJ_REV_SHIFT; 433 434 for (i = 0; i < ARRAY_SIZE(id); i++) 435 if (id[i].ip_id == ip_id && id[i].maj_rev == maj_rev) 436 return id[i].era; 437 438 return -ENOTSUPP; 439 } 440 441 /** 442 * caam_get_era() - Return the ERA of the SEC on SoC, based 443 * on "sec-era" optional property in the DTS. This property is updated 444 * by u-boot. 445 * In case this property is not passed an attempt to retrieve the CAAM 446 * era via register reads will be made. 447 **/ 448 static int caam_get_era(struct caam_ctrl __iomem *ctrl) 449 { 450 struct device_node *caam_node; 451 int ret; 452 u32 prop; 453 454 caam_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0"); 455 ret = of_property_read_u32(caam_node, "fsl,sec-era", &prop); 456 of_node_put(caam_node); 457 458 if (!ret) 459 return prop; 460 else 461 return caam_get_era_from_hw(ctrl); 462 } 463 464 static const struct of_device_id caam_match[] = { 465 { 466 .compatible = "fsl,sec-v4.0", 467 }, 468 { 469 .compatible = "fsl,sec4.0", 470 }, 471 {}, 472 }; 473 MODULE_DEVICE_TABLE(of, caam_match); 474 475 /* Probe routine for CAAM top (controller) level */ 476 static int caam_probe(struct platform_device *pdev) 477 { 478 int ret, ring, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN; 479 u64 caam_id; 480 static const struct soc_device_attribute imx_soc[] = { 481 {.family = "Freescale i.MX"}, 482 {}, 483 }; 484 struct device *dev; 485 struct device_node *nprop, *np; 486 struct caam_ctrl __iomem *ctrl; 487 struct caam_drv_private *ctrlpriv; 488 struct clk *clk; 489 #ifdef CONFIG_DEBUG_FS 490 struct caam_perfmon *perfmon; 491 #endif 492 u32 scfgr, comp_params; 493 u32 cha_vid_ls; 494 int pg_size; 495 int BLOCK_OFFSET = 0; 496 497 ctrlpriv = devm_kzalloc(&pdev->dev, sizeof(*ctrlpriv), GFP_KERNEL); 498 if (!ctrlpriv) 499 return -ENOMEM; 500 501 dev = &pdev->dev; 502 dev_set_drvdata(dev, ctrlpriv); 503 nprop = pdev->dev.of_node; 504 505 caam_imx = (bool)soc_device_match(imx_soc); 506 507 /* Enable clocking */ 508 clk = caam_drv_identify_clk(&pdev->dev, "ipg"); 509 if (IS_ERR(clk)) { 510 ret = PTR_ERR(clk); 511 dev_err(&pdev->dev, 512 "can't identify CAAM ipg clk: %d\n", ret); 513 return ret; 514 } 515 ctrlpriv->caam_ipg = clk; 516 517 if (!of_machine_is_compatible("fsl,imx7d") && 518 !of_machine_is_compatible("fsl,imx7s")) { 519 clk = caam_drv_identify_clk(&pdev->dev, "mem"); 520 if (IS_ERR(clk)) { 521 ret = PTR_ERR(clk); 522 dev_err(&pdev->dev, 523 "can't identify CAAM mem clk: %d\n", ret); 524 return ret; 525 } 526 ctrlpriv->caam_mem = clk; 527 } 528 529 clk = caam_drv_identify_clk(&pdev->dev, "aclk"); 530 if (IS_ERR(clk)) { 531 ret = PTR_ERR(clk); 532 dev_err(&pdev->dev, 533 "can't identify CAAM aclk clk: %d\n", ret); 534 return ret; 535 } 536 ctrlpriv->caam_aclk = clk; 537 538 if (!of_machine_is_compatible("fsl,imx6ul") && 539 !of_machine_is_compatible("fsl,imx7d") && 540 !of_machine_is_compatible("fsl,imx7s")) { 541 clk = caam_drv_identify_clk(&pdev->dev, "emi_slow"); 542 if (IS_ERR(clk)) { 543 ret = PTR_ERR(clk); 544 dev_err(&pdev->dev, 545 "can't identify CAAM emi_slow clk: %d\n", ret); 546 return ret; 547 } 548 ctrlpriv->caam_emi_slow = clk; 549 } 550 551 ret = clk_prepare_enable(ctrlpriv->caam_ipg); 552 if (ret < 0) { 553 dev_err(&pdev->dev, "can't enable CAAM ipg clock: %d\n", ret); 554 return ret; 555 } 556 557 if (ctrlpriv->caam_mem) { 558 ret = clk_prepare_enable(ctrlpriv->caam_mem); 559 if (ret < 0) { 560 dev_err(&pdev->dev, "can't enable CAAM secure mem clock: %d\n", 561 ret); 562 goto disable_caam_ipg; 563 } 564 } 565 566 ret = clk_prepare_enable(ctrlpriv->caam_aclk); 567 if (ret < 0) { 568 dev_err(&pdev->dev, "can't enable CAAM aclk clock: %d\n", ret); 569 goto disable_caam_mem; 570 } 571 572 if (ctrlpriv->caam_emi_slow) { 573 ret = clk_prepare_enable(ctrlpriv->caam_emi_slow); 574 if (ret < 0) { 575 dev_err(&pdev->dev, "can't enable CAAM emi slow clock: %d\n", 576 ret); 577 goto disable_caam_aclk; 578 } 579 } 580 581 /* Get configuration properties from device tree */ 582 /* First, get register page */ 583 ctrl = of_iomap(nprop, 0); 584 if (ctrl == NULL) { 585 dev_err(dev, "caam: of_iomap() failed\n"); 586 ret = -ENOMEM; 587 goto disable_caam_emi_slow; 588 } 589 590 caam_little_end = !(bool)(rd_reg32(&ctrl->perfmon.status) & 591 (CSTA_PLEND | CSTA_ALT_PLEND)); 592 593 /* Finding the page size for using the CTPR_MS register */ 594 comp_params = rd_reg32(&ctrl->perfmon.comp_parms_ms); 595 pg_size = (comp_params & CTPR_MS_PG_SZ_MASK) >> CTPR_MS_PG_SZ_SHIFT; 596 597 /* Allocating the BLOCK_OFFSET based on the supported page size on 598 * the platform 599 */ 600 if (pg_size == 0) 601 BLOCK_OFFSET = PG_SIZE_4K; 602 else 603 BLOCK_OFFSET = PG_SIZE_64K; 604 605 ctrlpriv->ctrl = (struct caam_ctrl __iomem __force *)ctrl; 606 ctrlpriv->assure = (struct caam_assurance __iomem __force *) 607 ((__force uint8_t *)ctrl + 608 BLOCK_OFFSET * ASSURE_BLOCK_NUMBER 609 ); 610 ctrlpriv->deco = (struct caam_deco __iomem __force *) 611 ((__force uint8_t *)ctrl + 612 BLOCK_OFFSET * DECO_BLOCK_NUMBER 613 ); 614 615 /* Get the IRQ of the controller (for security violations only) */ 616 ctrlpriv->secvio_irq = irq_of_parse_and_map(nprop, 0); 617 618 /* 619 * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel, 620 * long pointers in master configuration register. 621 * In case of SoCs with Management Complex, MC f/w performs 622 * the configuration. 623 */ 624 caam_dpaa2 = !!(comp_params & CTPR_MS_DPAA2); 625 np = of_find_compatible_node(NULL, NULL, "fsl,qoriq-mc"); 626 ctrlpriv->mc_en = !!np; 627 of_node_put(np); 628 629 if (!ctrlpriv->mc_en) 630 clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK | MCFGR_LONG_PTR, 631 MCFGR_AWCACHE_CACH | MCFGR_AWCACHE_BUFF | 632 MCFGR_WDENABLE | MCFGR_LARGE_BURST | 633 (sizeof(dma_addr_t) == sizeof(u64) ? 634 MCFGR_LONG_PTR : 0)); 635 636 /* 637 * Read the Compile Time paramters and SCFGR to determine 638 * if Virtualization is enabled for this platform 639 */ 640 scfgr = rd_reg32(&ctrl->scfgr); 641 642 ctrlpriv->virt_en = 0; 643 if (comp_params & CTPR_MS_VIRT_EN_INCL) { 644 /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or 645 * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SCFGR_VIRT_EN = 1 646 */ 647 if ((comp_params & CTPR_MS_VIRT_EN_POR) || 648 (!(comp_params & CTPR_MS_VIRT_EN_POR) && 649 (scfgr & SCFGR_VIRT_EN))) 650 ctrlpriv->virt_en = 1; 651 } else { 652 /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */ 653 if (comp_params & CTPR_MS_VIRT_EN_POR) 654 ctrlpriv->virt_en = 1; 655 } 656 657 if (ctrlpriv->virt_en == 1) 658 clrsetbits_32(&ctrl->jrstart, 0, JRSTART_JR0_START | 659 JRSTART_JR1_START | JRSTART_JR2_START | 660 JRSTART_JR3_START); 661 662 if (sizeof(dma_addr_t) == sizeof(u64)) { 663 if (caam_dpaa2) 664 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(49)); 665 else if (of_device_is_compatible(nprop, "fsl,sec-v5.0")) 666 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40)); 667 else 668 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36)); 669 } else { 670 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); 671 } 672 if (ret) { 673 dev_err(dev, "dma_set_mask_and_coherent failed (%d)\n", ret); 674 goto iounmap_ctrl; 675 } 676 677 ctrlpriv->era = caam_get_era(ctrl); 678 679 ret = of_platform_populate(nprop, caam_match, NULL, dev); 680 if (ret) { 681 dev_err(dev, "JR platform devices creation error\n"); 682 goto iounmap_ctrl; 683 } 684 685 #ifdef CONFIG_DEBUG_FS 686 /* 687 * FIXME: needs better naming distinction, as some amalgamation of 688 * "caam" and nprop->full_name. The OF name isn't distinctive, 689 * but does separate instances 690 */ 691 perfmon = (struct caam_perfmon __force *)&ctrl->perfmon; 692 693 ctrlpriv->dfs_root = debugfs_create_dir(dev_name(dev), NULL); 694 ctrlpriv->ctl = debugfs_create_dir("ctl", ctrlpriv->dfs_root); 695 #endif 696 697 ring = 0; 698 for_each_available_child_of_node(nprop, np) 699 if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") || 700 of_device_is_compatible(np, "fsl,sec4.0-job-ring")) { 701 ctrlpriv->jr[ring] = (struct caam_job_ring __iomem __force *) 702 ((__force uint8_t *)ctrl + 703 (ring + JR_BLOCK_NUMBER) * 704 BLOCK_OFFSET 705 ); 706 ctrlpriv->total_jobrs++; 707 ring++; 708 } 709 710 /* Check to see if (DPAA 1.x) QI present. If so, enable */ 711 ctrlpriv->qi_present = !!(comp_params & CTPR_MS_QI_MASK); 712 if (ctrlpriv->qi_present && !caam_dpaa2) { 713 ctrlpriv->qi = (struct caam_queue_if __iomem __force *) 714 ((__force uint8_t *)ctrl + 715 BLOCK_OFFSET * QI_BLOCK_NUMBER 716 ); 717 /* This is all that's required to physically enable QI */ 718 wr_reg32(&ctrlpriv->qi->qi_control_lo, QICTL_DQEN); 719 720 /* If QMAN driver is present, init CAAM-QI backend */ 721 #ifdef CONFIG_CAAM_QI 722 ret = caam_qi_init(pdev); 723 if (ret) 724 dev_err(dev, "caam qi i/f init failed: %d\n", ret); 725 #endif 726 } 727 728 /* If no QI and no rings specified, quit and go home */ 729 if ((!ctrlpriv->qi_present) && (!ctrlpriv->total_jobrs)) { 730 dev_err(dev, "no queues configured, terminating\n"); 731 ret = -ENOMEM; 732 goto caam_remove; 733 } 734 735 cha_vid_ls = rd_reg32(&ctrl->perfmon.cha_id_ls); 736 737 /* 738 * If SEC has RNG version >= 4 and RNG state handle has not been 739 * already instantiated, do RNG instantiation 740 * In case of SoCs with Management Complex, RNG is managed by MC f/w. 741 */ 742 if (!ctrlpriv->mc_en && 743 (cha_vid_ls & CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT >= 4) { 744 ctrlpriv->rng4_sh_init = 745 rd_reg32(&ctrl->r4tst[0].rdsta); 746 /* 747 * If the secure keys (TDKEK, JDKEK, TDSK), were already 748 * generated, signal this to the function that is instantiating 749 * the state handles. An error would occur if RNG4 attempts 750 * to regenerate these keys before the next POR. 751 */ 752 gen_sk = ctrlpriv->rng4_sh_init & RDSTA_SKVN ? 0 : 1; 753 ctrlpriv->rng4_sh_init &= RDSTA_IFMASK; 754 do { 755 int inst_handles = 756 rd_reg32(&ctrl->r4tst[0].rdsta) & 757 RDSTA_IFMASK; 758 /* 759 * If either SH were instantiated by somebody else 760 * (e.g. u-boot) then it is assumed that the entropy 761 * parameters are properly set and thus the function 762 * setting these (kick_trng(...)) is skipped. 763 * Also, if a handle was instantiated, do not change 764 * the TRNG parameters. 765 */ 766 if (!(ctrlpriv->rng4_sh_init || inst_handles)) { 767 dev_info(dev, 768 "Entropy delay = %u\n", 769 ent_delay); 770 kick_trng(pdev, ent_delay); 771 ent_delay += 400; 772 } 773 /* 774 * if instantiate_rng(...) fails, the loop will rerun 775 * and the kick_trng(...) function will modfiy the 776 * upper and lower limits of the entropy sampling 777 * interval, leading to a sucessful initialization of 778 * the RNG. 779 */ 780 ret = instantiate_rng(dev, inst_handles, 781 gen_sk); 782 if (ret == -EAGAIN) 783 /* 784 * if here, the loop will rerun, 785 * so don't hog the CPU 786 */ 787 cpu_relax(); 788 } while ((ret == -EAGAIN) && (ent_delay < RTSDCTL_ENT_DLY_MAX)); 789 if (ret) { 790 dev_err(dev, "failed to instantiate RNG"); 791 goto caam_remove; 792 } 793 /* 794 * Set handles init'ed by this module as the complement of the 795 * already initialized ones 796 */ 797 ctrlpriv->rng4_sh_init = ~ctrlpriv->rng4_sh_init & RDSTA_IFMASK; 798 799 /* Enable RDB bit so that RNG works faster */ 800 clrsetbits_32(&ctrl->scfgr, 0, SCFGR_RDBENABLE); 801 } 802 803 /* NOTE: RTIC detection ought to go here, around Si time */ 804 805 caam_id = (u64)rd_reg32(&ctrl->perfmon.caam_id_ms) << 32 | 806 (u64)rd_reg32(&ctrl->perfmon.caam_id_ls); 807 808 /* Report "alive" for developer to see */ 809 dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id, 810 ctrlpriv->era); 811 dev_info(dev, "job rings = %d, qi = %d\n", 812 ctrlpriv->total_jobrs, ctrlpriv->qi_present); 813 814 #ifdef CONFIG_DEBUG_FS 815 debugfs_create_file("rq_dequeued", S_IRUSR | S_IRGRP | S_IROTH, 816 ctrlpriv->ctl, &perfmon->req_dequeued, 817 &caam_fops_u64_ro); 818 debugfs_create_file("ob_rq_encrypted", S_IRUSR | S_IRGRP | S_IROTH, 819 ctrlpriv->ctl, &perfmon->ob_enc_req, 820 &caam_fops_u64_ro); 821 debugfs_create_file("ib_rq_decrypted", S_IRUSR | S_IRGRP | S_IROTH, 822 ctrlpriv->ctl, &perfmon->ib_dec_req, 823 &caam_fops_u64_ro); 824 debugfs_create_file("ob_bytes_encrypted", S_IRUSR | S_IRGRP | S_IROTH, 825 ctrlpriv->ctl, &perfmon->ob_enc_bytes, 826 &caam_fops_u64_ro); 827 debugfs_create_file("ob_bytes_protected", S_IRUSR | S_IRGRP | S_IROTH, 828 ctrlpriv->ctl, &perfmon->ob_prot_bytes, 829 &caam_fops_u64_ro); 830 debugfs_create_file("ib_bytes_decrypted", S_IRUSR | S_IRGRP | S_IROTH, 831 ctrlpriv->ctl, &perfmon->ib_dec_bytes, 832 &caam_fops_u64_ro); 833 debugfs_create_file("ib_bytes_validated", S_IRUSR | S_IRGRP | S_IROTH, 834 ctrlpriv->ctl, &perfmon->ib_valid_bytes, 835 &caam_fops_u64_ro); 836 837 /* Controller level - global status values */ 838 debugfs_create_file("fault_addr", S_IRUSR | S_IRGRP | S_IROTH, 839 ctrlpriv->ctl, &perfmon->faultaddr, 840 &caam_fops_u32_ro); 841 debugfs_create_file("fault_detail", S_IRUSR | S_IRGRP | S_IROTH, 842 ctrlpriv->ctl, &perfmon->faultdetail, 843 &caam_fops_u32_ro); 844 debugfs_create_file("fault_status", S_IRUSR | S_IRGRP | S_IROTH, 845 ctrlpriv->ctl, &perfmon->status, 846 &caam_fops_u32_ro); 847 848 /* Internal covering keys (useful in non-secure mode only) */ 849 ctrlpriv->ctl_kek_wrap.data = (__force void *)&ctrlpriv->ctrl->kek[0]; 850 ctrlpriv->ctl_kek_wrap.size = KEK_KEY_SIZE * sizeof(u32); 851 ctrlpriv->ctl_kek = debugfs_create_blob("kek", 852 S_IRUSR | 853 S_IRGRP | S_IROTH, 854 ctrlpriv->ctl, 855 &ctrlpriv->ctl_kek_wrap); 856 857 ctrlpriv->ctl_tkek_wrap.data = (__force void *)&ctrlpriv->ctrl->tkek[0]; 858 ctrlpriv->ctl_tkek_wrap.size = KEK_KEY_SIZE * sizeof(u32); 859 ctrlpriv->ctl_tkek = debugfs_create_blob("tkek", 860 S_IRUSR | 861 S_IRGRP | S_IROTH, 862 ctrlpriv->ctl, 863 &ctrlpriv->ctl_tkek_wrap); 864 865 ctrlpriv->ctl_tdsk_wrap.data = (__force void *)&ctrlpriv->ctrl->tdsk[0]; 866 ctrlpriv->ctl_tdsk_wrap.size = KEK_KEY_SIZE * sizeof(u32); 867 ctrlpriv->ctl_tdsk = debugfs_create_blob("tdsk", 868 S_IRUSR | 869 S_IRGRP | S_IROTH, 870 ctrlpriv->ctl, 871 &ctrlpriv->ctl_tdsk_wrap); 872 #endif 873 return 0; 874 875 caam_remove: 876 caam_remove(pdev); 877 return ret; 878 879 iounmap_ctrl: 880 iounmap(ctrl); 881 disable_caam_emi_slow: 882 if (ctrlpriv->caam_emi_slow) 883 clk_disable_unprepare(ctrlpriv->caam_emi_slow); 884 disable_caam_aclk: 885 clk_disable_unprepare(ctrlpriv->caam_aclk); 886 disable_caam_mem: 887 if (ctrlpriv->caam_mem) 888 clk_disable_unprepare(ctrlpriv->caam_mem); 889 disable_caam_ipg: 890 clk_disable_unprepare(ctrlpriv->caam_ipg); 891 return ret; 892 } 893 894 static struct platform_driver caam_driver = { 895 .driver = { 896 .name = "caam", 897 .of_match_table = caam_match, 898 }, 899 .probe = caam_probe, 900 .remove = caam_remove, 901 }; 902 903 module_platform_driver(caam_driver); 904 905 MODULE_LICENSE("GPL"); 906 MODULE_DESCRIPTION("FSL CAAM request backend"); 907 MODULE_AUTHOR("Freescale Semiconductor - NMG/STC"); 908