1 /* * CAAM control-plane driver backend 2 * Controller-level driver, kernel property detection, initialization 3 * 4 * Copyright 2008-2012 Freescale Semiconductor, Inc. 5 */ 6 7 #include <linux/device.h> 8 #include <linux/of_address.h> 9 #include <linux/of_irq.h> 10 11 #include "compat.h" 12 #include "regs.h" 13 #include "intern.h" 14 #include "jr.h" 15 #include "desc_constr.h" 16 #include "ctrl.h" 17 18 bool caam_little_end; 19 EXPORT_SYMBOL(caam_little_end); 20 21 #ifdef CONFIG_CAAM_QI 22 #include "qi.h" 23 #endif 24 25 /* 26 * i.MX targets tend to have clock control subsystems that can 27 * enable/disable clocking to our device. 28 */ 29 #ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_IMX 30 static inline struct clk *caam_drv_identify_clk(struct device *dev, 31 char *clk_name) 32 { 33 return devm_clk_get(dev, clk_name); 34 } 35 #else 36 static inline struct clk *caam_drv_identify_clk(struct device *dev, 37 char *clk_name) 38 { 39 return NULL; 40 } 41 #endif 42 43 /* 44 * Descriptor to instantiate RNG State Handle 0 in normal mode and 45 * load the JDKEK, TDKEK and TDSK registers 46 */ 47 static void build_instantiation_desc(u32 *desc, int handle, int do_sk) 48 { 49 u32 *jump_cmd, op_flags; 50 51 init_job_desc(desc, 0); 52 53 op_flags = OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG | 54 (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INIT; 55 56 /* INIT RNG in non-test mode */ 57 append_operation(desc, op_flags); 58 59 if (!handle && do_sk) { 60 /* 61 * For SH0, Secure Keys must be generated as well 62 */ 63 64 /* wait for done */ 65 jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1); 66 set_jump_tgt_here(desc, jump_cmd); 67 68 /* 69 * load 1 to clear written reg: 70 * resets the done interrrupt and returns the RNG to idle. 71 */ 72 append_load_imm_u32(desc, 1, LDST_SRCDST_WORD_CLRW); 73 74 /* Initialize State Handle */ 75 append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG | 76 OP_ALG_AAI_RNG4_SK); 77 } 78 79 append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT); 80 } 81 82 /* Descriptor for deinstantiation of State Handle 0 of the RNG block. */ 83 static void build_deinstantiation_desc(u32 *desc, int handle) 84 { 85 init_job_desc(desc, 0); 86 87 /* Uninstantiate State Handle 0 */ 88 append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG | 89 (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INITFINAL); 90 91 append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT); 92 } 93 94 /* 95 * run_descriptor_deco0 - runs a descriptor on DECO0, under direct control of 96 * the software (no JR/QI used). 97 * @ctrldev - pointer to device 98 * @status - descriptor status, after being run 99 * 100 * Return: - 0 if no error occurred 101 * - -ENODEV if the DECO couldn't be acquired 102 * - -EAGAIN if an error occurred while executing the descriptor 103 */ 104 static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc, 105 u32 *status) 106 { 107 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev); 108 struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl; 109 struct caam_deco __iomem *deco = ctrlpriv->deco; 110 unsigned int timeout = 100000; 111 u32 deco_dbg_reg, flags; 112 int i; 113 114 115 if (ctrlpriv->virt_en == 1) { 116 clrsetbits_32(&ctrl->deco_rsr, 0, DECORSR_JR0); 117 118 while (!(rd_reg32(&ctrl->deco_rsr) & DECORSR_VALID) && 119 --timeout) 120 cpu_relax(); 121 122 timeout = 100000; 123 } 124 125 clrsetbits_32(&ctrl->deco_rq, 0, DECORR_RQD0ENABLE); 126 127 while (!(rd_reg32(&ctrl->deco_rq) & DECORR_DEN0) && 128 --timeout) 129 cpu_relax(); 130 131 if (!timeout) { 132 dev_err(ctrldev, "failed to acquire DECO 0\n"); 133 clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0); 134 return -ENODEV; 135 } 136 137 for (i = 0; i < desc_len(desc); i++) 138 wr_reg32(&deco->descbuf[i], caam32_to_cpu(*(desc + i))); 139 140 flags = DECO_JQCR_WHL; 141 /* 142 * If the descriptor length is longer than 4 words, then the 143 * FOUR bit in JRCTRL register must be set. 144 */ 145 if (desc_len(desc) >= 4) 146 flags |= DECO_JQCR_FOUR; 147 148 /* Instruct the DECO to execute it */ 149 clrsetbits_32(&deco->jr_ctl_hi, 0, flags); 150 151 timeout = 10000000; 152 do { 153 deco_dbg_reg = rd_reg32(&deco->desc_dbg); 154 /* 155 * If an error occured in the descriptor, then 156 * the DECO status field will be set to 0x0D 157 */ 158 if ((deco_dbg_reg & DESC_DBG_DECO_STAT_MASK) == 159 DESC_DBG_DECO_STAT_HOST_ERR) 160 break; 161 cpu_relax(); 162 } while ((deco_dbg_reg & DESC_DBG_DECO_STAT_VALID) && --timeout); 163 164 *status = rd_reg32(&deco->op_status_hi) & 165 DECO_OP_STATUS_HI_ERR_MASK; 166 167 if (ctrlpriv->virt_en == 1) 168 clrsetbits_32(&ctrl->deco_rsr, DECORSR_JR0, 0); 169 170 /* Mark the DECO as free */ 171 clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0); 172 173 if (!timeout) 174 return -EAGAIN; 175 176 return 0; 177 } 178 179 /* 180 * instantiate_rng - builds and executes a descriptor on DECO0, 181 * which initializes the RNG block. 182 * @ctrldev - pointer to device 183 * @state_handle_mask - bitmask containing the instantiation status 184 * for the RNG4 state handles which exist in 185 * the RNG4 block: 1 if it's been instantiated 186 * by an external entry, 0 otherwise. 187 * @gen_sk - generate data to be loaded into the JDKEK, TDKEK and TDSK; 188 * Caution: this can be done only once; if the keys need to be 189 * regenerated, a POR is required 190 * 191 * Return: - 0 if no error occurred 192 * - -ENOMEM if there isn't enough memory to allocate the descriptor 193 * - -ENODEV if DECO0 couldn't be acquired 194 * - -EAGAIN if an error occurred when executing the descriptor 195 * f.i. there was a RNG hardware error due to not "good enough" 196 * entropy being aquired. 197 */ 198 static int instantiate_rng(struct device *ctrldev, int state_handle_mask, 199 int gen_sk) 200 { 201 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev); 202 struct caam_ctrl __iomem *ctrl; 203 u32 *desc, status = 0, rdsta_val; 204 int ret = 0, sh_idx; 205 206 ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl; 207 desc = kmalloc(CAAM_CMD_SZ * 7, GFP_KERNEL); 208 if (!desc) 209 return -ENOMEM; 210 211 for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) { 212 /* 213 * If the corresponding bit is set, this state handle 214 * was initialized by somebody else, so it's left alone. 215 */ 216 if ((1 << sh_idx) & state_handle_mask) 217 continue; 218 219 /* Create the descriptor for instantiating RNG State Handle */ 220 build_instantiation_desc(desc, sh_idx, gen_sk); 221 222 /* Try to run it through DECO0 */ 223 ret = run_descriptor_deco0(ctrldev, desc, &status); 224 225 /* 226 * If ret is not 0, or descriptor status is not 0, then 227 * something went wrong. No need to try the next state 228 * handle (if available), bail out here. 229 * Also, if for some reason, the State Handle didn't get 230 * instantiated although the descriptor has finished 231 * without any error (HW optimizations for later 232 * CAAM eras), then try again. 233 */ 234 rdsta_val = rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_IFMASK; 235 if ((status && status != JRSTA_SSRC_JUMP_HALT_CC) || 236 !(rdsta_val & (1 << sh_idx))) 237 ret = -EAGAIN; 238 if (ret) 239 break; 240 dev_info(ctrldev, "Instantiated RNG4 SH%d\n", sh_idx); 241 /* Clear the contents before recreating the descriptor */ 242 memset(desc, 0x00, CAAM_CMD_SZ * 7); 243 } 244 245 kfree(desc); 246 247 return ret; 248 } 249 250 /* 251 * deinstantiate_rng - builds and executes a descriptor on DECO0, 252 * which deinitializes the RNG block. 253 * @ctrldev - pointer to device 254 * @state_handle_mask - bitmask containing the instantiation status 255 * for the RNG4 state handles which exist in 256 * the RNG4 block: 1 if it's been instantiated 257 * 258 * Return: - 0 if no error occurred 259 * - -ENOMEM if there isn't enough memory to allocate the descriptor 260 * - -ENODEV if DECO0 couldn't be acquired 261 * - -EAGAIN if an error occurred when executing the descriptor 262 */ 263 static int deinstantiate_rng(struct device *ctrldev, int state_handle_mask) 264 { 265 u32 *desc, status; 266 int sh_idx, ret = 0; 267 268 desc = kmalloc(CAAM_CMD_SZ * 3, GFP_KERNEL); 269 if (!desc) 270 return -ENOMEM; 271 272 for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) { 273 /* 274 * If the corresponding bit is set, then it means the state 275 * handle was initialized by us, and thus it needs to be 276 * deinitialized as well 277 */ 278 if ((1 << sh_idx) & state_handle_mask) { 279 /* 280 * Create the descriptor for deinstantating this state 281 * handle 282 */ 283 build_deinstantiation_desc(desc, sh_idx); 284 285 /* Try to run it through DECO0 */ 286 ret = run_descriptor_deco0(ctrldev, desc, &status); 287 288 if (ret || status) { 289 dev_err(ctrldev, 290 "Failed to deinstantiate RNG4 SH%d\n", 291 sh_idx); 292 break; 293 } 294 dev_info(ctrldev, "Deinstantiated RNG4 SH%d\n", sh_idx); 295 } 296 } 297 298 kfree(desc); 299 300 return ret; 301 } 302 303 static int caam_remove(struct platform_device *pdev) 304 { 305 struct device *ctrldev; 306 struct caam_drv_private *ctrlpriv; 307 struct caam_ctrl __iomem *ctrl; 308 int ring; 309 310 ctrldev = &pdev->dev; 311 ctrlpriv = dev_get_drvdata(ctrldev); 312 ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl; 313 314 /* Remove platform devices for JobRs */ 315 for (ring = 0; ring < ctrlpriv->total_jobrs; ring++) 316 of_device_unregister(ctrlpriv->jrpdev[ring]); 317 318 #ifdef CONFIG_CAAM_QI 319 if (ctrlpriv->qidev) 320 caam_qi_shutdown(ctrlpriv->qidev); 321 #endif 322 323 /* De-initialize RNG state handles initialized by this driver. */ 324 if (ctrlpriv->rng4_sh_init) 325 deinstantiate_rng(ctrldev, ctrlpriv->rng4_sh_init); 326 327 /* Shut down debug views */ 328 #ifdef CONFIG_DEBUG_FS 329 debugfs_remove_recursive(ctrlpriv->dfs_root); 330 #endif 331 332 /* Unmap controller region */ 333 iounmap(ctrl); 334 335 /* shut clocks off before finalizing shutdown */ 336 clk_disable_unprepare(ctrlpriv->caam_ipg); 337 clk_disable_unprepare(ctrlpriv->caam_mem); 338 clk_disable_unprepare(ctrlpriv->caam_aclk); 339 if (ctrlpriv->caam_emi_slow) 340 clk_disable_unprepare(ctrlpriv->caam_emi_slow); 341 return 0; 342 } 343 344 /* 345 * kick_trng - sets the various parameters for enabling the initialization 346 * of the RNG4 block in CAAM 347 * @pdev - pointer to the platform device 348 * @ent_delay - Defines the length (in system clocks) of each entropy sample. 349 */ 350 static void kick_trng(struct platform_device *pdev, int ent_delay) 351 { 352 struct device *ctrldev = &pdev->dev; 353 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev); 354 struct caam_ctrl __iomem *ctrl; 355 struct rng4tst __iomem *r4tst; 356 u32 val; 357 358 ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl; 359 r4tst = &ctrl->r4tst[0]; 360 361 /* put RNG4 into program mode */ 362 clrsetbits_32(&r4tst->rtmctl, 0, RTMCTL_PRGM); 363 364 /* 365 * Performance-wise, it does not make sense to 366 * set the delay to a value that is lower 367 * than the last one that worked (i.e. the state handles 368 * were instantiated properly. Thus, instead of wasting 369 * time trying to set the values controlling the sample 370 * frequency, the function simply returns. 371 */ 372 val = (rd_reg32(&r4tst->rtsdctl) & RTSDCTL_ENT_DLY_MASK) 373 >> RTSDCTL_ENT_DLY_SHIFT; 374 if (ent_delay <= val) 375 goto start_rng; 376 377 val = rd_reg32(&r4tst->rtsdctl); 378 val = (val & ~RTSDCTL_ENT_DLY_MASK) | 379 (ent_delay << RTSDCTL_ENT_DLY_SHIFT); 380 wr_reg32(&r4tst->rtsdctl, val); 381 /* min. freq. count, equal to 1/4 of the entropy sample length */ 382 wr_reg32(&r4tst->rtfrqmin, ent_delay >> 2); 383 /* disable maximum frequency count */ 384 wr_reg32(&r4tst->rtfrqmax, RTFRQMAX_DISABLE); 385 /* read the control register */ 386 val = rd_reg32(&r4tst->rtmctl); 387 start_rng: 388 /* 389 * select raw sampling in both entropy shifter 390 * and statistical checker; ; put RNG4 into run mode 391 */ 392 clrsetbits_32(&r4tst->rtmctl, RTMCTL_PRGM, RTMCTL_SAMP_MODE_RAW_ES_SC); 393 } 394 395 /** 396 * caam_get_era() - Return the ERA of the SEC on SoC, based 397 * on "sec-era" propery in the DTS. This property is updated by u-boot. 398 **/ 399 int caam_get_era(void) 400 { 401 struct device_node *caam_node; 402 int ret; 403 u32 prop; 404 405 caam_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0"); 406 ret = of_property_read_u32(caam_node, "fsl,sec-era", &prop); 407 of_node_put(caam_node); 408 409 return ret ? -ENOTSUPP : prop; 410 } 411 EXPORT_SYMBOL(caam_get_era); 412 413 /* Probe routine for CAAM top (controller) level */ 414 static int caam_probe(struct platform_device *pdev) 415 { 416 int ret, ring, ridx, rspec, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN; 417 u64 caam_id; 418 struct device *dev; 419 struct device_node *nprop, *np; 420 struct caam_ctrl __iomem *ctrl; 421 struct caam_drv_private *ctrlpriv; 422 struct clk *clk; 423 #ifdef CONFIG_DEBUG_FS 424 struct caam_perfmon *perfmon; 425 #endif 426 u32 scfgr, comp_params; 427 u32 cha_vid_ls; 428 int pg_size; 429 int BLOCK_OFFSET = 0; 430 431 ctrlpriv = devm_kzalloc(&pdev->dev, sizeof(*ctrlpriv), GFP_KERNEL); 432 if (!ctrlpriv) 433 return -ENOMEM; 434 435 dev = &pdev->dev; 436 dev_set_drvdata(dev, ctrlpriv); 437 ctrlpriv->pdev = pdev; 438 nprop = pdev->dev.of_node; 439 440 /* Enable clocking */ 441 clk = caam_drv_identify_clk(&pdev->dev, "ipg"); 442 if (IS_ERR(clk)) { 443 ret = PTR_ERR(clk); 444 dev_err(&pdev->dev, 445 "can't identify CAAM ipg clk: %d\n", ret); 446 return ret; 447 } 448 ctrlpriv->caam_ipg = clk; 449 450 clk = caam_drv_identify_clk(&pdev->dev, "mem"); 451 if (IS_ERR(clk)) { 452 ret = PTR_ERR(clk); 453 dev_err(&pdev->dev, 454 "can't identify CAAM mem clk: %d\n", ret); 455 return ret; 456 } 457 ctrlpriv->caam_mem = clk; 458 459 clk = caam_drv_identify_clk(&pdev->dev, "aclk"); 460 if (IS_ERR(clk)) { 461 ret = PTR_ERR(clk); 462 dev_err(&pdev->dev, 463 "can't identify CAAM aclk clk: %d\n", ret); 464 return ret; 465 } 466 ctrlpriv->caam_aclk = clk; 467 468 if (!of_machine_is_compatible("fsl,imx6ul")) { 469 clk = caam_drv_identify_clk(&pdev->dev, "emi_slow"); 470 if (IS_ERR(clk)) { 471 ret = PTR_ERR(clk); 472 dev_err(&pdev->dev, 473 "can't identify CAAM emi_slow clk: %d\n", ret); 474 return ret; 475 } 476 ctrlpriv->caam_emi_slow = clk; 477 } 478 479 ret = clk_prepare_enable(ctrlpriv->caam_ipg); 480 if (ret < 0) { 481 dev_err(&pdev->dev, "can't enable CAAM ipg clock: %d\n", ret); 482 return ret; 483 } 484 485 ret = clk_prepare_enable(ctrlpriv->caam_mem); 486 if (ret < 0) { 487 dev_err(&pdev->dev, "can't enable CAAM secure mem clock: %d\n", 488 ret); 489 goto disable_caam_ipg; 490 } 491 492 ret = clk_prepare_enable(ctrlpriv->caam_aclk); 493 if (ret < 0) { 494 dev_err(&pdev->dev, "can't enable CAAM aclk clock: %d\n", ret); 495 goto disable_caam_mem; 496 } 497 498 if (ctrlpriv->caam_emi_slow) { 499 ret = clk_prepare_enable(ctrlpriv->caam_emi_slow); 500 if (ret < 0) { 501 dev_err(&pdev->dev, "can't enable CAAM emi slow clock: %d\n", 502 ret); 503 goto disable_caam_aclk; 504 } 505 } 506 507 /* Get configuration properties from device tree */ 508 /* First, get register page */ 509 ctrl = of_iomap(nprop, 0); 510 if (ctrl == NULL) { 511 dev_err(dev, "caam: of_iomap() failed\n"); 512 ret = -ENOMEM; 513 goto disable_caam_emi_slow; 514 } 515 516 caam_little_end = !(bool)(rd_reg32(&ctrl->perfmon.status) & 517 (CSTA_PLEND | CSTA_ALT_PLEND)); 518 519 /* Finding the page size for using the CTPR_MS register */ 520 comp_params = rd_reg32(&ctrl->perfmon.comp_parms_ms); 521 pg_size = (comp_params & CTPR_MS_PG_SZ_MASK) >> CTPR_MS_PG_SZ_SHIFT; 522 523 /* Allocating the BLOCK_OFFSET based on the supported page size on 524 * the platform 525 */ 526 if (pg_size == 0) 527 BLOCK_OFFSET = PG_SIZE_4K; 528 else 529 BLOCK_OFFSET = PG_SIZE_64K; 530 531 ctrlpriv->ctrl = (struct caam_ctrl __iomem __force *)ctrl; 532 ctrlpriv->assure = (struct caam_assurance __iomem __force *) 533 ((__force uint8_t *)ctrl + 534 BLOCK_OFFSET * ASSURE_BLOCK_NUMBER 535 ); 536 ctrlpriv->deco = (struct caam_deco __iomem __force *) 537 ((__force uint8_t *)ctrl + 538 BLOCK_OFFSET * DECO_BLOCK_NUMBER 539 ); 540 541 /* Get the IRQ of the controller (for security violations only) */ 542 ctrlpriv->secvio_irq = irq_of_parse_and_map(nprop, 0); 543 544 /* 545 * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel, 546 * long pointers in master configuration register 547 */ 548 clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK | MCFGR_LONG_PTR, 549 MCFGR_AWCACHE_CACH | MCFGR_AWCACHE_BUFF | 550 MCFGR_WDENABLE | MCFGR_LARGE_BURST | 551 (sizeof(dma_addr_t) == sizeof(u64) ? MCFGR_LONG_PTR : 0)); 552 553 /* 554 * Read the Compile Time paramters and SCFGR to determine 555 * if Virtualization is enabled for this platform 556 */ 557 scfgr = rd_reg32(&ctrl->scfgr); 558 559 ctrlpriv->virt_en = 0; 560 if (comp_params & CTPR_MS_VIRT_EN_INCL) { 561 /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or 562 * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SCFGR_VIRT_EN = 1 563 */ 564 if ((comp_params & CTPR_MS_VIRT_EN_POR) || 565 (!(comp_params & CTPR_MS_VIRT_EN_POR) && 566 (scfgr & SCFGR_VIRT_EN))) 567 ctrlpriv->virt_en = 1; 568 } else { 569 /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */ 570 if (comp_params & CTPR_MS_VIRT_EN_POR) 571 ctrlpriv->virt_en = 1; 572 } 573 574 if (ctrlpriv->virt_en == 1) 575 clrsetbits_32(&ctrl->jrstart, 0, JRSTART_JR0_START | 576 JRSTART_JR1_START | JRSTART_JR2_START | 577 JRSTART_JR3_START); 578 579 if (sizeof(dma_addr_t) == sizeof(u64)) { 580 if (of_device_is_compatible(nprop, "fsl,sec-v5.0")) 581 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40)); 582 else 583 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36)); 584 } else { 585 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); 586 } 587 if (ret) { 588 dev_err(dev, "dma_set_mask_and_coherent failed (%d)\n", ret); 589 goto iounmap_ctrl; 590 } 591 592 /* 593 * Detect and enable JobRs 594 * First, find out how many ring spec'ed, allocate references 595 * for all, then go probe each one. 596 */ 597 rspec = 0; 598 for_each_available_child_of_node(nprop, np) 599 if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") || 600 of_device_is_compatible(np, "fsl,sec4.0-job-ring")) 601 rspec++; 602 603 ctrlpriv->jrpdev = devm_kcalloc(&pdev->dev, rspec, 604 sizeof(*ctrlpriv->jrpdev), GFP_KERNEL); 605 if (ctrlpriv->jrpdev == NULL) { 606 ret = -ENOMEM; 607 goto iounmap_ctrl; 608 } 609 610 #ifdef CONFIG_DEBUG_FS 611 /* 612 * FIXME: needs better naming distinction, as some amalgamation of 613 * "caam" and nprop->full_name. The OF name isn't distinctive, 614 * but does separate instances 615 */ 616 perfmon = (struct caam_perfmon __force *)&ctrl->perfmon; 617 618 ctrlpriv->dfs_root = debugfs_create_dir(dev_name(dev), NULL); 619 ctrlpriv->ctl = debugfs_create_dir("ctl", ctrlpriv->dfs_root); 620 #endif 621 ring = 0; 622 ridx = 0; 623 ctrlpriv->total_jobrs = 0; 624 for_each_available_child_of_node(nprop, np) 625 if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") || 626 of_device_is_compatible(np, "fsl,sec4.0-job-ring")) { 627 ctrlpriv->jrpdev[ring] = 628 of_platform_device_create(np, NULL, dev); 629 if (!ctrlpriv->jrpdev[ring]) { 630 pr_warn("JR physical index %d: Platform device creation error\n", 631 ridx); 632 ridx++; 633 continue; 634 } 635 ctrlpriv->jr[ring] = (struct caam_job_ring __iomem __force *) 636 ((__force uint8_t *)ctrl + 637 (ridx + JR_BLOCK_NUMBER) * 638 BLOCK_OFFSET 639 ); 640 ctrlpriv->total_jobrs++; 641 ring++; 642 ridx++; 643 } 644 645 /* Check to see if QI present. If so, enable */ 646 ctrlpriv->qi_present = 647 !!(rd_reg32(&ctrl->perfmon.comp_parms_ms) & 648 CTPR_MS_QI_MASK); 649 if (ctrlpriv->qi_present) { 650 ctrlpriv->qi = (struct caam_queue_if __iomem __force *) 651 ((__force uint8_t *)ctrl + 652 BLOCK_OFFSET * QI_BLOCK_NUMBER 653 ); 654 /* This is all that's required to physically enable QI */ 655 wr_reg32(&ctrlpriv->qi->qi_control_lo, QICTL_DQEN); 656 657 /* If QMAN driver is present, init CAAM-QI backend */ 658 #ifdef CONFIG_CAAM_QI 659 ret = caam_qi_init(pdev); 660 if (ret) 661 dev_err(dev, "caam qi i/f init failed: %d\n", ret); 662 #endif 663 } 664 665 /* If no QI and no rings specified, quit and go home */ 666 if ((!ctrlpriv->qi_present) && (!ctrlpriv->total_jobrs)) { 667 dev_err(dev, "no queues configured, terminating\n"); 668 ret = -ENOMEM; 669 goto caam_remove; 670 } 671 672 cha_vid_ls = rd_reg32(&ctrl->perfmon.cha_id_ls); 673 674 /* 675 * If SEC has RNG version >= 4 and RNG state handle has not been 676 * already instantiated, do RNG instantiation 677 */ 678 if ((cha_vid_ls & CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT >= 4) { 679 ctrlpriv->rng4_sh_init = 680 rd_reg32(&ctrl->r4tst[0].rdsta); 681 /* 682 * If the secure keys (TDKEK, JDKEK, TDSK), were already 683 * generated, signal this to the function that is instantiating 684 * the state handles. An error would occur if RNG4 attempts 685 * to regenerate these keys before the next POR. 686 */ 687 gen_sk = ctrlpriv->rng4_sh_init & RDSTA_SKVN ? 0 : 1; 688 ctrlpriv->rng4_sh_init &= RDSTA_IFMASK; 689 do { 690 int inst_handles = 691 rd_reg32(&ctrl->r4tst[0].rdsta) & 692 RDSTA_IFMASK; 693 /* 694 * If either SH were instantiated by somebody else 695 * (e.g. u-boot) then it is assumed that the entropy 696 * parameters are properly set and thus the function 697 * setting these (kick_trng(...)) is skipped. 698 * Also, if a handle was instantiated, do not change 699 * the TRNG parameters. 700 */ 701 if (!(ctrlpriv->rng4_sh_init || inst_handles)) { 702 dev_info(dev, 703 "Entropy delay = %u\n", 704 ent_delay); 705 kick_trng(pdev, ent_delay); 706 ent_delay += 400; 707 } 708 /* 709 * if instantiate_rng(...) fails, the loop will rerun 710 * and the kick_trng(...) function will modfiy the 711 * upper and lower limits of the entropy sampling 712 * interval, leading to a sucessful initialization of 713 * the RNG. 714 */ 715 ret = instantiate_rng(dev, inst_handles, 716 gen_sk); 717 if (ret == -EAGAIN) 718 /* 719 * if here, the loop will rerun, 720 * so don't hog the CPU 721 */ 722 cpu_relax(); 723 } while ((ret == -EAGAIN) && (ent_delay < RTSDCTL_ENT_DLY_MAX)); 724 if (ret) { 725 dev_err(dev, "failed to instantiate RNG"); 726 goto caam_remove; 727 } 728 /* 729 * Set handles init'ed by this module as the complement of the 730 * already initialized ones 731 */ 732 ctrlpriv->rng4_sh_init = ~ctrlpriv->rng4_sh_init & RDSTA_IFMASK; 733 734 /* Enable RDB bit so that RNG works faster */ 735 clrsetbits_32(&ctrl->scfgr, 0, SCFGR_RDBENABLE); 736 } 737 738 /* NOTE: RTIC detection ought to go here, around Si time */ 739 740 caam_id = (u64)rd_reg32(&ctrl->perfmon.caam_id_ms) << 32 | 741 (u64)rd_reg32(&ctrl->perfmon.caam_id_ls); 742 743 /* Report "alive" for developer to see */ 744 dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id, 745 caam_get_era()); 746 dev_info(dev, "job rings = %d, qi = %d\n", 747 ctrlpriv->total_jobrs, ctrlpriv->qi_present); 748 749 #ifdef CONFIG_DEBUG_FS 750 751 ctrlpriv->ctl_rq_dequeued = 752 debugfs_create_file("rq_dequeued", 753 S_IRUSR | S_IRGRP | S_IROTH, 754 ctrlpriv->ctl, &perfmon->req_dequeued, 755 &caam_fops_u64_ro); 756 ctrlpriv->ctl_ob_enc_req = 757 debugfs_create_file("ob_rq_encrypted", 758 S_IRUSR | S_IRGRP | S_IROTH, 759 ctrlpriv->ctl, &perfmon->ob_enc_req, 760 &caam_fops_u64_ro); 761 ctrlpriv->ctl_ib_dec_req = 762 debugfs_create_file("ib_rq_decrypted", 763 S_IRUSR | S_IRGRP | S_IROTH, 764 ctrlpriv->ctl, &perfmon->ib_dec_req, 765 &caam_fops_u64_ro); 766 ctrlpriv->ctl_ob_enc_bytes = 767 debugfs_create_file("ob_bytes_encrypted", 768 S_IRUSR | S_IRGRP | S_IROTH, 769 ctrlpriv->ctl, &perfmon->ob_enc_bytes, 770 &caam_fops_u64_ro); 771 ctrlpriv->ctl_ob_prot_bytes = 772 debugfs_create_file("ob_bytes_protected", 773 S_IRUSR | S_IRGRP | S_IROTH, 774 ctrlpriv->ctl, &perfmon->ob_prot_bytes, 775 &caam_fops_u64_ro); 776 ctrlpriv->ctl_ib_dec_bytes = 777 debugfs_create_file("ib_bytes_decrypted", 778 S_IRUSR | S_IRGRP | S_IROTH, 779 ctrlpriv->ctl, &perfmon->ib_dec_bytes, 780 &caam_fops_u64_ro); 781 ctrlpriv->ctl_ib_valid_bytes = 782 debugfs_create_file("ib_bytes_validated", 783 S_IRUSR | S_IRGRP | S_IROTH, 784 ctrlpriv->ctl, &perfmon->ib_valid_bytes, 785 &caam_fops_u64_ro); 786 787 /* Controller level - global status values */ 788 ctrlpriv->ctl_faultaddr = 789 debugfs_create_file("fault_addr", 790 S_IRUSR | S_IRGRP | S_IROTH, 791 ctrlpriv->ctl, &perfmon->faultaddr, 792 &caam_fops_u32_ro); 793 ctrlpriv->ctl_faultdetail = 794 debugfs_create_file("fault_detail", 795 S_IRUSR | S_IRGRP | S_IROTH, 796 ctrlpriv->ctl, &perfmon->faultdetail, 797 &caam_fops_u32_ro); 798 ctrlpriv->ctl_faultstatus = 799 debugfs_create_file("fault_status", 800 S_IRUSR | S_IRGRP | S_IROTH, 801 ctrlpriv->ctl, &perfmon->status, 802 &caam_fops_u32_ro); 803 804 /* Internal covering keys (useful in non-secure mode only) */ 805 ctrlpriv->ctl_kek_wrap.data = (__force void *)&ctrlpriv->ctrl->kek[0]; 806 ctrlpriv->ctl_kek_wrap.size = KEK_KEY_SIZE * sizeof(u32); 807 ctrlpriv->ctl_kek = debugfs_create_blob("kek", 808 S_IRUSR | 809 S_IRGRP | S_IROTH, 810 ctrlpriv->ctl, 811 &ctrlpriv->ctl_kek_wrap); 812 813 ctrlpriv->ctl_tkek_wrap.data = (__force void *)&ctrlpriv->ctrl->tkek[0]; 814 ctrlpriv->ctl_tkek_wrap.size = KEK_KEY_SIZE * sizeof(u32); 815 ctrlpriv->ctl_tkek = debugfs_create_blob("tkek", 816 S_IRUSR | 817 S_IRGRP | S_IROTH, 818 ctrlpriv->ctl, 819 &ctrlpriv->ctl_tkek_wrap); 820 821 ctrlpriv->ctl_tdsk_wrap.data = (__force void *)&ctrlpriv->ctrl->tdsk[0]; 822 ctrlpriv->ctl_tdsk_wrap.size = KEK_KEY_SIZE * sizeof(u32); 823 ctrlpriv->ctl_tdsk = debugfs_create_blob("tdsk", 824 S_IRUSR | 825 S_IRGRP | S_IROTH, 826 ctrlpriv->ctl, 827 &ctrlpriv->ctl_tdsk_wrap); 828 #endif 829 return 0; 830 831 caam_remove: 832 #ifdef CONFIG_DEBUG_FS 833 debugfs_remove_recursive(ctrlpriv->dfs_root); 834 #endif 835 caam_remove(pdev); 836 return ret; 837 838 iounmap_ctrl: 839 iounmap(ctrl); 840 disable_caam_emi_slow: 841 if (ctrlpriv->caam_emi_slow) 842 clk_disable_unprepare(ctrlpriv->caam_emi_slow); 843 disable_caam_aclk: 844 clk_disable_unprepare(ctrlpriv->caam_aclk); 845 disable_caam_mem: 846 clk_disable_unprepare(ctrlpriv->caam_mem); 847 disable_caam_ipg: 848 clk_disable_unprepare(ctrlpriv->caam_ipg); 849 return ret; 850 } 851 852 static struct of_device_id caam_match[] = { 853 { 854 .compatible = "fsl,sec-v4.0", 855 }, 856 { 857 .compatible = "fsl,sec4.0", 858 }, 859 {}, 860 }; 861 MODULE_DEVICE_TABLE(of, caam_match); 862 863 static struct platform_driver caam_driver = { 864 .driver = { 865 .name = "caam", 866 .of_match_table = caam_match, 867 }, 868 .probe = caam_probe, 869 .remove = caam_remove, 870 }; 871 872 module_platform_driver(caam_driver); 873 874 MODULE_LICENSE("GPL"); 875 MODULE_DESCRIPTION("FSL CAAM request backend"); 876 MODULE_AUTHOR("Freescale Semiconductor - NMG/STC"); 877