1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ 2 /* 3 * Copyright 2015-2016 Freescale Semiconductor Inc. 4 * Copyright 2017-2018 NXP 5 */ 6 7 #ifndef _CAAMALG_QI2_H_ 8 #define _CAAMALG_QI2_H_ 9 10 #include <soc/fsl/dpaa2-io.h> 11 #include <soc/fsl/dpaa2-fd.h> 12 #include <linux/threads.h> 13 #include <linux/netdevice.h> 14 #include "dpseci.h" 15 #include "desc_constr.h" 16 17 #define DPAA2_CAAM_STORE_SIZE 16 18 /* NAPI weight *must* be a multiple of the store size. */ 19 #define DPAA2_CAAM_NAPI_WEIGHT 512 20 21 /* The congestion entrance threshold was chosen so that on LS2088 22 * we support the maximum throughput for the available memory 23 */ 24 #define DPAA2_SEC_CONG_ENTRY_THRESH (128 * 1024 * 1024) 25 #define DPAA2_SEC_CONG_EXIT_THRESH (DPAA2_SEC_CONG_ENTRY_THRESH * 9 / 10) 26 27 /** 28 * dpaa2_caam_priv - driver private data 29 * @dpseci_id: DPSECI object unique ID 30 * @major_ver: DPSECI major version 31 * @minor_ver: DPSECI minor version 32 * @dpseci_attr: DPSECI attributes 33 * @sec_attr: SEC engine attributes 34 * @rx_queue_attr: array of Rx queue attributes 35 * @tx_queue_attr: array of Tx queue attributes 36 * @cscn_mem: pointer to memory region containing the congestion SCN 37 * it's size is larger than to accommodate alignment 38 * @cscn_mem_aligned: pointer to congestion SCN; it is computed as 39 * PTR_ALIGN(cscn_mem, DPAA2_CSCN_ALIGN) 40 * @cscn_dma: dma address used by the QMAN to write CSCN messages 41 * @dev: device associated with the DPSECI object 42 * @mc_io: pointer to MC portal's I/O object 43 * @domain: IOMMU domain 44 * @ppriv: per CPU pointers to privata data 45 */ 46 struct dpaa2_caam_priv { 47 int dpsec_id; 48 49 u16 major_ver; 50 u16 minor_ver; 51 52 struct dpseci_attr dpseci_attr; 53 struct dpseci_sec_attr sec_attr; 54 struct dpseci_rx_queue_attr rx_queue_attr[DPSECI_MAX_QUEUE_NUM]; 55 struct dpseci_tx_queue_attr tx_queue_attr[DPSECI_MAX_QUEUE_NUM]; 56 int num_pairs; 57 58 /* congestion */ 59 void *cscn_mem; 60 void *cscn_mem_aligned; 61 dma_addr_t cscn_dma; 62 63 struct device *dev; 64 struct fsl_mc_io *mc_io; 65 struct iommu_domain *domain; 66 67 struct dpaa2_caam_priv_per_cpu __percpu *ppriv; 68 struct dentry *dfs_root; 69 }; 70 71 /** 72 * dpaa2_caam_priv_per_cpu - per CPU private data 73 * @napi: napi structure 74 * @net_dev: netdev used by napi 75 * @req_fqid: (virtual) request (Tx / enqueue) FQID 76 * @rsp_fqid: (virtual) response (Rx / dequeue) FQID 77 * @prio: internal queue number - index for dpaa2_caam_priv.*_queue_attr 78 * @nctx: notification context of response FQ 79 * @store: where dequeued frames are stored 80 * @priv: backpointer to dpaa2_caam_priv 81 * @dpio: portal used for data path operations 82 */ 83 struct dpaa2_caam_priv_per_cpu { 84 struct napi_struct napi; 85 struct net_device net_dev; 86 int req_fqid; 87 int rsp_fqid; 88 int prio; 89 struct dpaa2_io_notification_ctx nctx; 90 struct dpaa2_io_store *store; 91 struct dpaa2_caam_priv *priv; 92 struct dpaa2_io *dpio; 93 }; 94 95 /* 96 * The CAAM QI hardware constructs a job descriptor which points 97 * to shared descriptor (as pointed by context_a of FQ to CAAM). 98 * When the job descriptor is executed by deco, the whole job 99 * descriptor together with shared descriptor gets loaded in 100 * deco buffer which is 64 words long (each 32-bit). 101 * 102 * The job descriptor constructed by QI hardware has layout: 103 * 104 * HEADER (1 word) 105 * Shdesc ptr (1 or 2 words) 106 * SEQ_OUT_PTR (1 word) 107 * Out ptr (1 or 2 words) 108 * Out length (1 word) 109 * SEQ_IN_PTR (1 word) 110 * In ptr (1 or 2 words) 111 * In length (1 word) 112 * 113 * The shdesc ptr is used to fetch shared descriptor contents 114 * into deco buffer. 115 * 116 * Apart from shdesc contents, the total number of words that 117 * get loaded in deco buffer are '8' or '11'. The remaining words 118 * in deco buffer can be used for storing shared descriptor. 119 */ 120 #define MAX_SDLEN ((CAAM_DESC_BYTES_MAX - DESC_JOB_IO_LEN) / CAAM_CMD_SZ) 121 122 /* Length of a single buffer in the QI driver memory cache */ 123 #define CAAM_QI_MEMCACHE_SIZE 512 124 125 /* 126 * aead_edesc - s/w-extended aead descriptor 127 * @src_nents: number of segments in input scatterlist 128 * @dst_nents: number of segments in output scatterlist 129 * @iv_dma: dma address of iv for checking continuity and link table 130 * @qm_sg_bytes: length of dma mapped h/w link table 131 * @qm_sg_dma: bus physical mapped address of h/w link table 132 * @assoclen: associated data length, in CAAM endianness 133 * @assoclen_dma: bus physical mapped address of req->assoclen 134 * @sgt: the h/w link table, followed by IV 135 */ 136 struct aead_edesc { 137 int src_nents; 138 int dst_nents; 139 dma_addr_t iv_dma; 140 int qm_sg_bytes; 141 dma_addr_t qm_sg_dma; 142 unsigned int assoclen; 143 dma_addr_t assoclen_dma; 144 struct dpaa2_sg_entry sgt[0]; 145 }; 146 147 /* 148 * skcipher_edesc - s/w-extended skcipher descriptor 149 * @src_nents: number of segments in input scatterlist 150 * @dst_nents: number of segments in output scatterlist 151 * @iv_dma: dma address of iv for checking continuity and link table 152 * @qm_sg_bytes: length of dma mapped qm_sg space 153 * @qm_sg_dma: I/O virtual address of h/w link table 154 * @sgt: the h/w link table, followed by IV 155 */ 156 struct skcipher_edesc { 157 int src_nents; 158 int dst_nents; 159 dma_addr_t iv_dma; 160 int qm_sg_bytes; 161 dma_addr_t qm_sg_dma; 162 struct dpaa2_sg_entry sgt[0]; 163 }; 164 165 /* 166 * ahash_edesc - s/w-extended ahash descriptor 167 * @qm_sg_dma: I/O virtual address of h/w link table 168 * @src_nents: number of segments in input scatterlist 169 * @qm_sg_bytes: length of dma mapped qm_sg space 170 * @sgt: pointer to h/w link table 171 */ 172 struct ahash_edesc { 173 dma_addr_t qm_sg_dma; 174 int src_nents; 175 int qm_sg_bytes; 176 struct dpaa2_sg_entry sgt[0]; 177 }; 178 179 /** 180 * caam_flc - Flow Context (FLC) 181 * @flc: Flow Context options 182 * @sh_desc: Shared Descriptor 183 */ 184 struct caam_flc { 185 u32 flc[16]; 186 u32 sh_desc[MAX_SDLEN]; 187 } ____cacheline_aligned; 188 189 enum optype { 190 ENCRYPT = 0, 191 DECRYPT, 192 NUM_OP 193 }; 194 195 /** 196 * caam_request - the request structure the driver application should fill while 197 * submitting a job to driver. 198 * @fd_flt: Frame list table defining input and output 199 * fd_flt[0] - FLE pointing to output buffer 200 * fd_flt[1] - FLE pointing to input buffer 201 * @fd_flt_dma: DMA address for the frame list table 202 * @flc: Flow Context 203 * @flc_dma: I/O virtual address of Flow Context 204 * @cbk: Callback function to invoke when job is completed 205 * @ctx: arbit context attached with request by the application 206 * @edesc: extended descriptor; points to one of {skcipher,aead}_edesc 207 */ 208 struct caam_request { 209 struct dpaa2_fl_entry fd_flt[2]; 210 dma_addr_t fd_flt_dma; 211 struct caam_flc *flc; 212 dma_addr_t flc_dma; 213 void (*cbk)(void *ctx, u32 err); 214 void *ctx; 215 void *edesc; 216 }; 217 218 /** 219 * dpaa2_caam_enqueue() - enqueue a crypto request 220 * @dev: device associated with the DPSECI object 221 * @req: pointer to caam_request 222 */ 223 int dpaa2_caam_enqueue(struct device *dev, struct caam_request *req); 224 225 #endif /* _CAAMALG_QI2_H_ */ 226