1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * AMCC SoC PPC4xx Crypto Driver 4 * 5 * Copyright (c) 2008 Applied Micro Circuits Corporation. 6 * All rights reserved. James Hsiao <jhsiao@amcc.com> 7 * 8 * This file implements AMCC crypto offload Linux device driver for use with 9 * Linux CryptoAPI. 10 */ 11 12 #include <linux/kernel.h> 13 #include <linux/interrupt.h> 14 #include <linux/spinlock_types.h> 15 #include <linux/random.h> 16 #include <linux/scatterlist.h> 17 #include <linux/crypto.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/platform_device.h> 20 #include <linux/init.h> 21 #include <linux/module.h> 22 #include <linux/of_address.h> 23 #include <linux/of_irq.h> 24 #include <linux/of_platform.h> 25 #include <linux/slab.h> 26 #include <asm/dcr.h> 27 #include <asm/dcr-regs.h> 28 #include <asm/cacheflush.h> 29 #include <crypto/aead.h> 30 #include <crypto/aes.h> 31 #include <crypto/ctr.h> 32 #include <crypto/gcm.h> 33 #include <crypto/sha1.h> 34 #include <crypto/scatterwalk.h> 35 #include <crypto/skcipher.h> 36 #include <crypto/internal/aead.h> 37 #include <crypto/internal/skcipher.h> 38 #include "crypto4xx_reg_def.h" 39 #include "crypto4xx_core.h" 40 #include "crypto4xx_sa.h" 41 #include "crypto4xx_trng.h" 42 43 #define PPC4XX_SEC_VERSION_STR "0.5" 44 45 /* 46 * PPC4xx Crypto Engine Initialization Routine 47 */ 48 static void crypto4xx_hw_init(struct crypto4xx_device *dev) 49 { 50 union ce_ring_size ring_size; 51 union ce_ring_control ring_ctrl; 52 union ce_part_ring_size part_ring_size; 53 union ce_io_threshold io_threshold; 54 u32 rand_num; 55 union ce_pe_dma_cfg pe_dma_cfg; 56 u32 device_ctrl; 57 58 writel(PPC4XX_BYTE_ORDER, dev->ce_base + CRYPTO4XX_BYTE_ORDER_CFG); 59 /* setup pe dma, include reset sg, pdr and pe, then release reset */ 60 pe_dma_cfg.w = 0; 61 pe_dma_cfg.bf.bo_sgpd_en = 1; 62 pe_dma_cfg.bf.bo_data_en = 0; 63 pe_dma_cfg.bf.bo_sa_en = 1; 64 pe_dma_cfg.bf.bo_pd_en = 1; 65 pe_dma_cfg.bf.dynamic_sa_en = 1; 66 pe_dma_cfg.bf.reset_sg = 1; 67 pe_dma_cfg.bf.reset_pdr = 1; 68 pe_dma_cfg.bf.reset_pe = 1; 69 writel(pe_dma_cfg.w, dev->ce_base + CRYPTO4XX_PE_DMA_CFG); 70 /* un reset pe,sg and pdr */ 71 pe_dma_cfg.bf.pe_mode = 0; 72 pe_dma_cfg.bf.reset_sg = 0; 73 pe_dma_cfg.bf.reset_pdr = 0; 74 pe_dma_cfg.bf.reset_pe = 0; 75 pe_dma_cfg.bf.bo_td_en = 0; 76 writel(pe_dma_cfg.w, dev->ce_base + CRYPTO4XX_PE_DMA_CFG); 77 writel(dev->pdr_pa, dev->ce_base + CRYPTO4XX_PDR_BASE); 78 writel(dev->pdr_pa, dev->ce_base + CRYPTO4XX_RDR_BASE); 79 writel(PPC4XX_PRNG_CTRL_AUTO_EN, dev->ce_base + CRYPTO4XX_PRNG_CTRL); 80 get_random_bytes(&rand_num, sizeof(rand_num)); 81 writel(rand_num, dev->ce_base + CRYPTO4XX_PRNG_SEED_L); 82 get_random_bytes(&rand_num, sizeof(rand_num)); 83 writel(rand_num, dev->ce_base + CRYPTO4XX_PRNG_SEED_H); 84 ring_size.w = 0; 85 ring_size.bf.ring_offset = PPC4XX_PD_SIZE; 86 ring_size.bf.ring_size = PPC4XX_NUM_PD; 87 writel(ring_size.w, dev->ce_base + CRYPTO4XX_RING_SIZE); 88 ring_ctrl.w = 0; 89 writel(ring_ctrl.w, dev->ce_base + CRYPTO4XX_RING_CTRL); 90 device_ctrl = readl(dev->ce_base + CRYPTO4XX_DEVICE_CTRL); 91 device_ctrl |= PPC4XX_DC_3DES_EN; 92 writel(device_ctrl, dev->ce_base + CRYPTO4XX_DEVICE_CTRL); 93 writel(dev->gdr_pa, dev->ce_base + CRYPTO4XX_GATH_RING_BASE); 94 writel(dev->sdr_pa, dev->ce_base + CRYPTO4XX_SCAT_RING_BASE); 95 part_ring_size.w = 0; 96 part_ring_size.bf.sdr_size = PPC4XX_SDR_SIZE; 97 part_ring_size.bf.gdr_size = PPC4XX_GDR_SIZE; 98 writel(part_ring_size.w, dev->ce_base + CRYPTO4XX_PART_RING_SIZE); 99 writel(PPC4XX_SD_BUFFER_SIZE, dev->ce_base + CRYPTO4XX_PART_RING_CFG); 100 io_threshold.w = 0; 101 io_threshold.bf.output_threshold = PPC4XX_OUTPUT_THRESHOLD; 102 io_threshold.bf.input_threshold = PPC4XX_INPUT_THRESHOLD; 103 writel(io_threshold.w, dev->ce_base + CRYPTO4XX_IO_THRESHOLD); 104 writel(0, dev->ce_base + CRYPTO4XX_PDR_BASE_UADDR); 105 writel(0, dev->ce_base + CRYPTO4XX_RDR_BASE_UADDR); 106 writel(0, dev->ce_base + CRYPTO4XX_PKT_SRC_UADDR); 107 writel(0, dev->ce_base + CRYPTO4XX_PKT_DEST_UADDR); 108 writel(0, dev->ce_base + CRYPTO4XX_SA_UADDR); 109 writel(0, dev->ce_base + CRYPTO4XX_GATH_RING_BASE_UADDR); 110 writel(0, dev->ce_base + CRYPTO4XX_SCAT_RING_BASE_UADDR); 111 /* un reset pe,sg and pdr */ 112 pe_dma_cfg.bf.pe_mode = 1; 113 pe_dma_cfg.bf.reset_sg = 0; 114 pe_dma_cfg.bf.reset_pdr = 0; 115 pe_dma_cfg.bf.reset_pe = 0; 116 pe_dma_cfg.bf.bo_td_en = 0; 117 writel(pe_dma_cfg.w, dev->ce_base + CRYPTO4XX_PE_DMA_CFG); 118 /*clear all pending interrupt*/ 119 writel(PPC4XX_INTERRUPT_CLR, dev->ce_base + CRYPTO4XX_INT_CLR); 120 writel(PPC4XX_INT_DESCR_CNT, dev->ce_base + CRYPTO4XX_INT_DESCR_CNT); 121 writel(PPC4XX_INT_DESCR_CNT, dev->ce_base + CRYPTO4XX_INT_DESCR_CNT); 122 writel(PPC4XX_INT_CFG, dev->ce_base + CRYPTO4XX_INT_CFG); 123 if (dev->is_revb) { 124 writel(PPC4XX_INT_TIMEOUT_CNT_REVB << 10, 125 dev->ce_base + CRYPTO4XX_INT_TIMEOUT_CNT); 126 writel(PPC4XX_PD_DONE_INT | PPC4XX_TMO_ERR_INT, 127 dev->ce_base + CRYPTO4XX_INT_EN); 128 } else { 129 writel(PPC4XX_PD_DONE_INT, dev->ce_base + CRYPTO4XX_INT_EN); 130 } 131 } 132 133 int crypto4xx_alloc_sa(struct crypto4xx_ctx *ctx, u32 size) 134 { 135 ctx->sa_in = kcalloc(size, 4, GFP_ATOMIC); 136 if (ctx->sa_in == NULL) 137 return -ENOMEM; 138 139 ctx->sa_out = kcalloc(size, 4, GFP_ATOMIC); 140 if (ctx->sa_out == NULL) { 141 kfree(ctx->sa_in); 142 ctx->sa_in = NULL; 143 return -ENOMEM; 144 } 145 146 ctx->sa_len = size; 147 148 return 0; 149 } 150 151 void crypto4xx_free_sa(struct crypto4xx_ctx *ctx) 152 { 153 kfree(ctx->sa_in); 154 ctx->sa_in = NULL; 155 kfree(ctx->sa_out); 156 ctx->sa_out = NULL; 157 ctx->sa_len = 0; 158 } 159 160 /* 161 * alloc memory for the gather ring 162 * no need to alloc buf for the ring 163 * gdr_tail, gdr_head and gdr_count are initialized by this function 164 */ 165 static u32 crypto4xx_build_pdr(struct crypto4xx_device *dev) 166 { 167 int i; 168 dev->pdr = dma_alloc_coherent(dev->core_dev->device, 169 sizeof(struct ce_pd) * PPC4XX_NUM_PD, 170 &dev->pdr_pa, GFP_KERNEL); 171 if (!dev->pdr) 172 return -ENOMEM; 173 174 dev->pdr_uinfo = kzalloc_objs(struct pd_uinfo, PPC4XX_NUM_PD); 175 if (!dev->pdr_uinfo) { 176 dma_free_coherent(dev->core_dev->device, 177 sizeof(struct ce_pd) * PPC4XX_NUM_PD, 178 dev->pdr, 179 dev->pdr_pa); 180 return -ENOMEM; 181 } 182 dev->shadow_sa_pool = dma_alloc_coherent(dev->core_dev->device, 183 sizeof(union shadow_sa_buf) * PPC4XX_NUM_PD, 184 &dev->shadow_sa_pool_pa, 185 GFP_KERNEL); 186 if (!dev->shadow_sa_pool) 187 return -ENOMEM; 188 189 dev->shadow_sr_pool = dma_alloc_coherent(dev->core_dev->device, 190 sizeof(struct sa_state_record) * PPC4XX_NUM_PD, 191 &dev->shadow_sr_pool_pa, GFP_KERNEL); 192 if (!dev->shadow_sr_pool) 193 return -ENOMEM; 194 for (i = 0; i < PPC4XX_NUM_PD; i++) { 195 struct ce_pd *pd = &dev->pdr[i]; 196 struct pd_uinfo *pd_uinfo = &dev->pdr_uinfo[i]; 197 198 pd->sa = dev->shadow_sa_pool_pa + 199 sizeof(union shadow_sa_buf) * i; 200 201 /* alloc 256 bytes which is enough for any kind of dynamic sa */ 202 pd_uinfo->sa_va = &dev->shadow_sa_pool[i].sa; 203 204 /* alloc state record */ 205 pd_uinfo->sr_va = &dev->shadow_sr_pool[i]; 206 pd_uinfo->sr_pa = dev->shadow_sr_pool_pa + 207 sizeof(struct sa_state_record) * i; 208 } 209 210 return 0; 211 } 212 213 static void crypto4xx_destroy_pdr(struct crypto4xx_device *dev) 214 { 215 if (dev->pdr) 216 dma_free_coherent(dev->core_dev->device, 217 sizeof(struct ce_pd) * PPC4XX_NUM_PD, 218 dev->pdr, dev->pdr_pa); 219 220 if (dev->shadow_sa_pool) 221 dma_free_coherent(dev->core_dev->device, 222 sizeof(union shadow_sa_buf) * PPC4XX_NUM_PD, 223 dev->shadow_sa_pool, dev->shadow_sa_pool_pa); 224 225 if (dev->shadow_sr_pool) 226 dma_free_coherent(dev->core_dev->device, 227 sizeof(struct sa_state_record) * PPC4XX_NUM_PD, 228 dev->shadow_sr_pool, dev->shadow_sr_pool_pa); 229 230 kfree(dev->pdr_uinfo); 231 } 232 233 static u32 crypto4xx_get_pd_from_pdr_nolock(struct crypto4xx_device *dev) 234 { 235 u32 retval; 236 u32 tmp; 237 238 retval = dev->pdr_head; 239 tmp = (dev->pdr_head + 1) % PPC4XX_NUM_PD; 240 241 if (tmp == dev->pdr_tail) 242 return ERING_WAS_FULL; 243 244 dev->pdr_head = tmp; 245 246 return retval; 247 } 248 249 static u32 crypto4xx_put_pd_to_pdr(struct crypto4xx_device *dev, u32 idx) 250 { 251 struct pd_uinfo *pd_uinfo = &dev->pdr_uinfo[idx]; 252 u32 tail; 253 unsigned long flags; 254 255 spin_lock_irqsave(&dev->core_dev->lock, flags); 256 pd_uinfo->state = PD_ENTRY_FREE; 257 258 if (dev->pdr_tail != PPC4XX_LAST_PD) 259 dev->pdr_tail++; 260 else 261 dev->pdr_tail = 0; 262 tail = dev->pdr_tail; 263 spin_unlock_irqrestore(&dev->core_dev->lock, flags); 264 265 return tail; 266 } 267 268 /* 269 * alloc memory for the gather ring 270 * no need to alloc buf for the ring 271 * gdr_tail, gdr_head and gdr_count are initialized by this function 272 */ 273 static u32 crypto4xx_build_gdr(struct crypto4xx_device *dev) 274 { 275 dev->gdr = dma_alloc_coherent(dev->core_dev->device, 276 sizeof(struct ce_gd) * PPC4XX_NUM_GD, 277 &dev->gdr_pa, GFP_KERNEL); 278 if (!dev->gdr) 279 return -ENOMEM; 280 281 return 0; 282 } 283 284 static inline void crypto4xx_destroy_gdr(struct crypto4xx_device *dev) 285 { 286 if (dev->gdr) 287 dma_free_coherent(dev->core_dev->device, 288 sizeof(struct ce_gd) * PPC4XX_NUM_GD, 289 dev->gdr, dev->gdr_pa); 290 } 291 292 /* 293 * when this function is called. 294 * preemption or interrupt must be disabled 295 */ 296 static u32 crypto4xx_get_n_gd(struct crypto4xx_device *dev, int n) 297 { 298 u32 retval; 299 u32 tmp; 300 301 if (n >= PPC4XX_NUM_GD) 302 return ERING_WAS_FULL; 303 304 retval = dev->gdr_head; 305 tmp = (dev->gdr_head + n) % PPC4XX_NUM_GD; 306 if (dev->gdr_head > dev->gdr_tail) { 307 if (tmp < dev->gdr_head && tmp >= dev->gdr_tail) 308 return ERING_WAS_FULL; 309 } else if (dev->gdr_head < dev->gdr_tail) { 310 if (tmp < dev->gdr_head || tmp >= dev->gdr_tail) 311 return ERING_WAS_FULL; 312 } 313 dev->gdr_head = tmp; 314 315 return retval; 316 } 317 318 static u32 crypto4xx_put_gd_to_gdr(struct crypto4xx_device *dev) 319 { 320 unsigned long flags; 321 322 spin_lock_irqsave(&dev->core_dev->lock, flags); 323 if (dev->gdr_tail == dev->gdr_head) { 324 spin_unlock_irqrestore(&dev->core_dev->lock, flags); 325 return 0; 326 } 327 328 if (dev->gdr_tail != PPC4XX_LAST_GD) 329 dev->gdr_tail++; 330 else 331 dev->gdr_tail = 0; 332 333 spin_unlock_irqrestore(&dev->core_dev->lock, flags); 334 335 return 0; 336 } 337 338 static inline struct ce_gd *crypto4xx_get_gdp(struct crypto4xx_device *dev, 339 dma_addr_t *gd_dma, u32 idx) 340 { 341 *gd_dma = dev->gdr_pa + sizeof(struct ce_gd) * idx; 342 343 return &dev->gdr[idx]; 344 } 345 346 /* 347 * alloc memory for the scatter ring 348 * need to alloc buf for the ring 349 * sdr_tail, sdr_head and sdr_count are initialized by this function 350 */ 351 static u32 crypto4xx_build_sdr(struct crypto4xx_device *dev) 352 { 353 int i; 354 355 dev->scatter_buffer_va = 356 dma_alloc_coherent(dev->core_dev->device, 357 PPC4XX_SD_BUFFER_SIZE * PPC4XX_NUM_SD, 358 &dev->scatter_buffer_pa, GFP_KERNEL); 359 if (!dev->scatter_buffer_va) 360 return -ENOMEM; 361 362 /* alloc memory for scatter descriptor ring */ 363 dev->sdr = dma_alloc_coherent(dev->core_dev->device, 364 sizeof(struct ce_sd) * PPC4XX_NUM_SD, 365 &dev->sdr_pa, GFP_KERNEL); 366 if (!dev->sdr) 367 return -ENOMEM; 368 369 for (i = 0; i < PPC4XX_NUM_SD; i++) { 370 dev->sdr[i].ptr = dev->scatter_buffer_pa + 371 PPC4XX_SD_BUFFER_SIZE * i; 372 } 373 374 return 0; 375 } 376 377 static void crypto4xx_destroy_sdr(struct crypto4xx_device *dev) 378 { 379 if (dev->sdr) 380 dma_free_coherent(dev->core_dev->device, 381 sizeof(struct ce_sd) * PPC4XX_NUM_SD, 382 dev->sdr, dev->sdr_pa); 383 384 if (dev->scatter_buffer_va) 385 dma_free_coherent(dev->core_dev->device, 386 PPC4XX_SD_BUFFER_SIZE * PPC4XX_NUM_SD, 387 dev->scatter_buffer_va, 388 dev->scatter_buffer_pa); 389 } 390 391 /* 392 * when this function is called. 393 * preemption or interrupt must be disabled 394 */ 395 static u32 crypto4xx_get_n_sd(struct crypto4xx_device *dev, int n) 396 { 397 u32 retval; 398 u32 tmp; 399 400 if (n >= PPC4XX_NUM_SD) 401 return ERING_WAS_FULL; 402 403 retval = dev->sdr_head; 404 tmp = (dev->sdr_head + n) % PPC4XX_NUM_SD; 405 if (dev->sdr_head > dev->gdr_tail) { 406 if (tmp < dev->sdr_head && tmp >= dev->sdr_tail) 407 return ERING_WAS_FULL; 408 } else if (dev->sdr_head < dev->sdr_tail) { 409 if (tmp < dev->sdr_head || tmp >= dev->sdr_tail) 410 return ERING_WAS_FULL; 411 } /* the head = tail, or empty case is already take cared */ 412 dev->sdr_head = tmp; 413 414 return retval; 415 } 416 417 static u32 crypto4xx_put_sd_to_sdr(struct crypto4xx_device *dev) 418 { 419 unsigned long flags; 420 421 spin_lock_irqsave(&dev->core_dev->lock, flags); 422 if (dev->sdr_tail == dev->sdr_head) { 423 spin_unlock_irqrestore(&dev->core_dev->lock, flags); 424 return 0; 425 } 426 if (dev->sdr_tail != PPC4XX_LAST_SD) 427 dev->sdr_tail++; 428 else 429 dev->sdr_tail = 0; 430 spin_unlock_irqrestore(&dev->core_dev->lock, flags); 431 432 return 0; 433 } 434 435 static inline struct ce_sd *crypto4xx_get_sdp(struct crypto4xx_device *dev, 436 dma_addr_t *sd_dma, u32 idx) 437 { 438 *sd_dma = dev->sdr_pa + sizeof(struct ce_sd) * idx; 439 440 return &dev->sdr[idx]; 441 } 442 443 static void crypto4xx_copy_pkt_to_dst(struct crypto4xx_device *dev, 444 struct ce_pd *pd, 445 struct pd_uinfo *pd_uinfo, 446 u32 nbytes, 447 struct scatterlist *dst) 448 { 449 unsigned int first_sd = pd_uinfo->first_sd; 450 unsigned int last_sd; 451 unsigned int overflow = 0; 452 unsigned int to_copy; 453 unsigned int dst_start = 0; 454 455 /* 456 * Because the scatter buffers are all neatly organized in one 457 * big continuous ringbuffer; scatterwalk_map_and_copy() can 458 * be instructed to copy a range of buffers in one go. 459 */ 460 461 last_sd = (first_sd + pd_uinfo->num_sd); 462 if (last_sd > PPC4XX_LAST_SD) { 463 last_sd = PPC4XX_LAST_SD; 464 overflow = last_sd % PPC4XX_NUM_SD; 465 } 466 467 while (nbytes) { 468 void *buf = dev->scatter_buffer_va + 469 first_sd * PPC4XX_SD_BUFFER_SIZE; 470 471 to_copy = min(nbytes, PPC4XX_SD_BUFFER_SIZE * 472 (1 + last_sd - first_sd)); 473 scatterwalk_map_and_copy(buf, dst, dst_start, to_copy, 1); 474 nbytes -= to_copy; 475 476 if (overflow) { 477 first_sd = 0; 478 last_sd = overflow; 479 dst_start += to_copy; 480 overflow = 0; 481 } 482 } 483 } 484 485 static void crypto4xx_ret_sg_desc(struct crypto4xx_device *dev, 486 struct pd_uinfo *pd_uinfo) 487 { 488 int i; 489 if (pd_uinfo->num_gd) { 490 for (i = 0; i < pd_uinfo->num_gd; i++) 491 crypto4xx_put_gd_to_gdr(dev); 492 pd_uinfo->first_gd = 0xffffffff; 493 pd_uinfo->num_gd = 0; 494 } 495 if (pd_uinfo->num_sd) { 496 for (i = 0; i < pd_uinfo->num_sd; i++) 497 crypto4xx_put_sd_to_sdr(dev); 498 499 pd_uinfo->first_sd = 0xffffffff; 500 pd_uinfo->num_sd = 0; 501 } 502 } 503 504 static void crypto4xx_cipher_done(struct crypto4xx_device *dev, 505 struct pd_uinfo *pd_uinfo, 506 struct ce_pd *pd) 507 { 508 struct skcipher_request *req; 509 struct scatterlist *dst; 510 511 req = skcipher_request_cast(pd_uinfo->async_req); 512 513 if (pd_uinfo->sa_va->sa_command_0.bf.scatter) { 514 crypto4xx_copy_pkt_to_dst(dev, pd, pd_uinfo, 515 req->cryptlen, req->dst); 516 } else { 517 dst = pd_uinfo->dest_va; 518 dma_unmap_page(dev->core_dev->device, pd->dest, dst->length, 519 DMA_FROM_DEVICE); 520 } 521 522 if (pd_uinfo->sa_va->sa_command_0.bf.save_iv == SA_SAVE_IV) { 523 struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req); 524 525 crypto4xx_memcpy_from_le32((u32 *)req->iv, 526 pd_uinfo->sr_va->save_iv, 527 crypto_skcipher_ivsize(skcipher)); 528 } 529 530 crypto4xx_ret_sg_desc(dev, pd_uinfo); 531 532 if (pd_uinfo->state & PD_ENTRY_BUSY) 533 skcipher_request_complete(req, -EINPROGRESS); 534 skcipher_request_complete(req, 0); 535 } 536 537 static void crypto4xx_aead_done(struct crypto4xx_device *dev, 538 struct pd_uinfo *pd_uinfo, 539 struct ce_pd *pd) 540 { 541 struct aead_request *aead_req = container_of(pd_uinfo->async_req, 542 struct aead_request, base); 543 struct scatterlist *dst = pd_uinfo->dest_va; 544 size_t cp_len = crypto_aead_authsize( 545 crypto_aead_reqtfm(aead_req)); 546 u32 icv[AES_BLOCK_SIZE]; 547 int err = 0; 548 549 if (pd_uinfo->sa_va->sa_command_0.bf.scatter) { 550 crypto4xx_copy_pkt_to_dst(dev, pd, pd_uinfo, 551 pd->pd_ctl_len.bf.pkt_len, 552 dst); 553 } else { 554 dma_unmap_page(dev->core_dev->device, pd->dest, dst->length, 555 DMA_FROM_DEVICE); 556 } 557 558 if (pd_uinfo->sa_va->sa_command_0.bf.dir == DIR_OUTBOUND) { 559 /* append icv at the end */ 560 crypto4xx_memcpy_from_le32(icv, pd_uinfo->sr_va->save_digest, 561 sizeof(icv)); 562 563 scatterwalk_map_and_copy(icv, dst, aead_req->cryptlen, 564 cp_len, 1); 565 } else { 566 /* check icv at the end */ 567 scatterwalk_map_and_copy(icv, aead_req->src, 568 aead_req->assoclen + aead_req->cryptlen - 569 cp_len, cp_len, 0); 570 571 crypto4xx_memcpy_from_le32(icv, icv, sizeof(icv)); 572 573 if (crypto_memneq(icv, pd_uinfo->sr_va->save_digest, cp_len)) 574 err = -EBADMSG; 575 } 576 577 crypto4xx_ret_sg_desc(dev, pd_uinfo); 578 579 if (pd->pd_ctl.bf.status & 0xff) { 580 if (!__ratelimit(&dev->aead_ratelimit)) { 581 if (pd->pd_ctl.bf.status & 2) 582 pr_err("pad fail error\n"); 583 if (pd->pd_ctl.bf.status & 4) 584 pr_err("seqnum fail\n"); 585 if (pd->pd_ctl.bf.status & 8) 586 pr_err("error _notify\n"); 587 pr_err("aead return err status = 0x%02x\n", 588 pd->pd_ctl.bf.status & 0xff); 589 pr_err("pd pad_ctl = 0x%08x\n", 590 pd->pd_ctl.bf.pd_pad_ctl); 591 } 592 err = -EINVAL; 593 } 594 595 if (pd_uinfo->state & PD_ENTRY_BUSY) 596 aead_request_complete(aead_req, -EINPROGRESS); 597 598 aead_request_complete(aead_req, err); 599 } 600 601 static void crypto4xx_pd_done(struct crypto4xx_device *dev, u32 idx) 602 { 603 struct ce_pd *pd = &dev->pdr[idx]; 604 struct pd_uinfo *pd_uinfo = &dev->pdr_uinfo[idx]; 605 606 switch (crypto_tfm_alg_type(pd_uinfo->async_req->tfm)) { 607 case CRYPTO_ALG_TYPE_SKCIPHER: 608 crypto4xx_cipher_done(dev, pd_uinfo, pd); 609 break; 610 case CRYPTO_ALG_TYPE_AEAD: 611 crypto4xx_aead_done(dev, pd_uinfo, pd); 612 break; 613 } 614 } 615 616 static void crypto4xx_stop_all(struct crypto4xx_core_device *core_dev) 617 { 618 crypto4xx_destroy_pdr(core_dev->dev); 619 crypto4xx_destroy_gdr(core_dev->dev); 620 crypto4xx_destroy_sdr(core_dev->dev); 621 } 622 623 static u32 get_next_gd(u32 current) 624 { 625 if (current != PPC4XX_LAST_GD) 626 return current + 1; 627 else 628 return 0; 629 } 630 631 static u32 get_next_sd(u32 current) 632 { 633 if (current != PPC4XX_LAST_SD) 634 return current + 1; 635 else 636 return 0; 637 } 638 639 int crypto4xx_build_pd(struct crypto_async_request *req, 640 struct crypto4xx_ctx *ctx, 641 struct scatterlist *src, 642 struct scatterlist *dst, 643 const unsigned int datalen, 644 const void *iv, const u32 iv_len, 645 const struct dynamic_sa_ctl *req_sa, 646 const unsigned int sa_len, 647 const unsigned int assoclen, 648 struct scatterlist *_dst) 649 { 650 struct crypto4xx_device *dev = ctx->dev; 651 struct dynamic_sa_ctl *sa; 652 struct ce_gd *gd; 653 struct ce_pd *pd; 654 u32 num_gd, num_sd; 655 u32 fst_gd = 0xffffffff; 656 u32 fst_sd = 0xffffffff; 657 u32 pd_entry; 658 unsigned long flags; 659 struct pd_uinfo *pd_uinfo; 660 unsigned int nbytes = datalen; 661 size_t offset_to_sr_ptr; 662 u32 gd_idx = 0; 663 int tmp; 664 bool is_busy, force_sd; 665 666 /* 667 * There's a very subtile/disguised "bug" in the hardware that 668 * gets indirectly mentioned in 18.1.3.5 Encryption/Decryption 669 * of the hardware spec: 670 * *drum roll* the AES/(T)DES OFB and CFB modes are listed as 671 * operation modes for >>> "Block ciphers" <<<. 672 * 673 * To workaround this issue and stop the hardware from causing 674 * "overran dst buffer" on crypttexts that are not a multiple 675 * of 16 (AES_BLOCK_SIZE), we force the driver to use the 676 * scatter buffers. 677 */ 678 force_sd = (req_sa->sa_command_1.bf.crypto_mode9_8 == CRYPTO_MODE_CFB 679 || req_sa->sa_command_1.bf.crypto_mode9_8 == CRYPTO_MODE_OFB) 680 && (datalen % AES_BLOCK_SIZE); 681 682 /* figure how many gd are needed */ 683 tmp = sg_nents_for_len(src, assoclen + datalen); 684 if (tmp < 0) { 685 dev_err(dev->core_dev->device, "Invalid number of src SG.\n"); 686 return tmp; 687 } 688 if (tmp == 1) 689 tmp = 0; 690 num_gd = tmp; 691 692 if (assoclen) { 693 nbytes += assoclen; 694 dst = scatterwalk_ffwd(_dst, dst, assoclen); 695 } 696 697 /* figure how many sd are needed */ 698 if (sg_is_last(dst) && force_sd == false) { 699 num_sd = 0; 700 } else { 701 if (datalen > PPC4XX_SD_BUFFER_SIZE) { 702 num_sd = datalen / PPC4XX_SD_BUFFER_SIZE; 703 if (datalen % PPC4XX_SD_BUFFER_SIZE) 704 num_sd++; 705 } else { 706 num_sd = 1; 707 } 708 } 709 710 /* 711 * The follow section of code needs to be protected 712 * The gather ring and scatter ring needs to be consecutive 713 * In case of run out of any kind of descriptor, the descriptor 714 * already got must be return the original place. 715 */ 716 spin_lock_irqsave(&dev->core_dev->lock, flags); 717 /* 718 * Let the caller know to slow down, once more than 13/16ths = 81% 719 * of the available data contexts are being used simultaneously. 720 * 721 * With PPC4XX_NUM_PD = 256, this will leave a "backlog queue" for 722 * 31 more contexts. Before new requests have to be rejected. 723 */ 724 if (req->flags & CRYPTO_TFM_REQ_MAY_BACKLOG) { 725 is_busy = ((dev->pdr_head - dev->pdr_tail) % PPC4XX_NUM_PD) >= 726 ((PPC4XX_NUM_PD * 13) / 16); 727 } else { 728 /* 729 * To fix contention issues between ipsec (no blacklog) and 730 * dm-crypto (backlog) reserve 32 entries for "no backlog" 731 * data contexts. 732 */ 733 is_busy = ((dev->pdr_head - dev->pdr_tail) % PPC4XX_NUM_PD) >= 734 ((PPC4XX_NUM_PD * 15) / 16); 735 736 if (is_busy) { 737 spin_unlock_irqrestore(&dev->core_dev->lock, flags); 738 return -EBUSY; 739 } 740 } 741 742 if (num_gd) { 743 fst_gd = crypto4xx_get_n_gd(dev, num_gd); 744 if (fst_gd == ERING_WAS_FULL) { 745 spin_unlock_irqrestore(&dev->core_dev->lock, flags); 746 return -EAGAIN; 747 } 748 } 749 if (num_sd) { 750 fst_sd = crypto4xx_get_n_sd(dev, num_sd); 751 if (fst_sd == ERING_WAS_FULL) { 752 if (num_gd) 753 dev->gdr_head = fst_gd; 754 spin_unlock_irqrestore(&dev->core_dev->lock, flags); 755 return -EAGAIN; 756 } 757 } 758 pd_entry = crypto4xx_get_pd_from_pdr_nolock(dev); 759 if (pd_entry == ERING_WAS_FULL) { 760 if (num_gd) 761 dev->gdr_head = fst_gd; 762 if (num_sd) 763 dev->sdr_head = fst_sd; 764 spin_unlock_irqrestore(&dev->core_dev->lock, flags); 765 return -EAGAIN; 766 } 767 spin_unlock_irqrestore(&dev->core_dev->lock, flags); 768 769 pd = &dev->pdr[pd_entry]; 770 pd->sa_len = sa_len; 771 772 pd_uinfo = &dev->pdr_uinfo[pd_entry]; 773 pd_uinfo->num_gd = num_gd; 774 pd_uinfo->num_sd = num_sd; 775 pd_uinfo->dest_va = dst; 776 pd_uinfo->async_req = req; 777 778 if (iv_len) 779 memcpy(pd_uinfo->sr_va->save_iv, iv, iv_len); 780 781 sa = pd_uinfo->sa_va; 782 memcpy(sa, req_sa, sa_len * 4); 783 784 sa->sa_command_1.bf.hash_crypto_offset = (assoclen >> 2); 785 offset_to_sr_ptr = get_dynamic_sa_offset_state_ptr_field(sa); 786 *(u32 *)((unsigned long)sa + offset_to_sr_ptr) = pd_uinfo->sr_pa; 787 788 if (num_gd) { 789 dma_addr_t gd_dma; 790 struct scatterlist *sg; 791 792 /* get first gd we are going to use */ 793 gd_idx = fst_gd; 794 pd_uinfo->first_gd = fst_gd; 795 gd = crypto4xx_get_gdp(dev, &gd_dma, gd_idx); 796 pd->src = gd_dma; 797 /* enable gather */ 798 sa->sa_command_0.bf.gather = 1; 799 /* walk the sg, and setup gather array */ 800 801 sg = src; 802 while (nbytes) { 803 size_t len; 804 805 len = min(sg->length, nbytes); 806 gd->ptr = dma_map_page(dev->core_dev->device, 807 sg_page(sg), sg->offset, len, DMA_TO_DEVICE); 808 gd->ctl_len.len = len; 809 gd->ctl_len.done = 0; 810 gd->ctl_len.ready = 1; 811 if (len >= nbytes) 812 break; 813 814 nbytes -= sg->length; 815 gd_idx = get_next_gd(gd_idx); 816 gd = crypto4xx_get_gdp(dev, &gd_dma, gd_idx); 817 sg = sg_next(sg); 818 } 819 } else { 820 pd->src = (u32)dma_map_page(dev->core_dev->device, sg_page(src), 821 src->offset, min(nbytes, src->length), 822 DMA_TO_DEVICE); 823 /* 824 * Disable gather in sa command 825 */ 826 sa->sa_command_0.bf.gather = 0; 827 /* 828 * Indicate gather array is not used 829 */ 830 pd_uinfo->first_gd = 0xffffffff; 831 } 832 if (!num_sd) { 833 /* 834 * we know application give us dst a whole piece of memory 835 * no need to use scatter ring. 836 */ 837 pd_uinfo->first_sd = 0xffffffff; 838 sa->sa_command_0.bf.scatter = 0; 839 pd->dest = (u32)dma_map_page(dev->core_dev->device, 840 sg_page(dst), dst->offset, 841 min(datalen, dst->length), 842 DMA_TO_DEVICE); 843 } else { 844 dma_addr_t sd_dma; 845 struct ce_sd *sd = NULL; 846 847 u32 sd_idx = fst_sd; 848 nbytes = datalen; 849 sa->sa_command_0.bf.scatter = 1; 850 pd_uinfo->first_sd = fst_sd; 851 sd = crypto4xx_get_sdp(dev, &sd_dma, sd_idx); 852 pd->dest = sd_dma; 853 /* setup scatter descriptor */ 854 sd->ctl.done = 0; 855 sd->ctl.rdy = 1; 856 /* sd->ptr should be setup by sd_init routine*/ 857 if (nbytes >= PPC4XX_SD_BUFFER_SIZE) 858 nbytes -= PPC4XX_SD_BUFFER_SIZE; 859 else 860 nbytes = 0; 861 while (nbytes) { 862 sd_idx = get_next_sd(sd_idx); 863 sd = crypto4xx_get_sdp(dev, &sd_dma, sd_idx); 864 /* setup scatter descriptor */ 865 sd->ctl.done = 0; 866 sd->ctl.rdy = 1; 867 if (nbytes >= PPC4XX_SD_BUFFER_SIZE) { 868 nbytes -= PPC4XX_SD_BUFFER_SIZE; 869 } else { 870 /* 871 * SD entry can hold PPC4XX_SD_BUFFER_SIZE, 872 * which is more than nbytes, so done. 873 */ 874 nbytes = 0; 875 } 876 } 877 } 878 879 pd->pd_ctl.w = PD_CTL_HOST_READY | 880 ((crypto_tfm_alg_type(req->tfm) == CRYPTO_ALG_TYPE_AEAD) ? 881 PD_CTL_HASH_FINAL : 0); 882 pd->pd_ctl_len.w = 0x00400000 | (assoclen + datalen); 883 pd_uinfo->state = PD_ENTRY_INUSE | (is_busy ? PD_ENTRY_BUSY : 0); 884 885 wmb(); 886 /* write any value to push engine to read a pd */ 887 writel(0, dev->ce_base + CRYPTO4XX_INT_DESCR_RD); 888 writel(1, dev->ce_base + CRYPTO4XX_INT_DESCR_RD); 889 return is_busy ? -EBUSY : -EINPROGRESS; 890 } 891 892 /* 893 * Algorithm Registration Functions 894 */ 895 static void crypto4xx_ctx_init(struct crypto4xx_alg *amcc_alg, 896 struct crypto4xx_ctx *ctx) 897 { 898 ctx->dev = amcc_alg->dev; 899 ctx->sa_in = NULL; 900 ctx->sa_out = NULL; 901 ctx->sa_len = 0; 902 } 903 904 static int crypto4xx_sk_init(struct crypto_skcipher *sk) 905 { 906 struct skcipher_alg *alg = crypto_skcipher_alg(sk); 907 struct crypto4xx_alg *amcc_alg; 908 struct crypto4xx_ctx *ctx = crypto_skcipher_ctx(sk); 909 910 if (alg->base.cra_flags & CRYPTO_ALG_NEED_FALLBACK) { 911 ctx->sw_cipher.cipher = 912 crypto_alloc_sync_skcipher(alg->base.cra_name, 0, 913 CRYPTO_ALG_NEED_FALLBACK); 914 if (IS_ERR(ctx->sw_cipher.cipher)) 915 return PTR_ERR(ctx->sw_cipher.cipher); 916 } 917 918 amcc_alg = container_of(alg, struct crypto4xx_alg, alg.u.cipher); 919 crypto4xx_ctx_init(amcc_alg, ctx); 920 return 0; 921 } 922 923 static void crypto4xx_common_exit(struct crypto4xx_ctx *ctx) 924 { 925 crypto4xx_free_sa(ctx); 926 } 927 928 static void crypto4xx_sk_exit(struct crypto_skcipher *sk) 929 { 930 struct crypto4xx_ctx *ctx = crypto_skcipher_ctx(sk); 931 932 crypto4xx_common_exit(ctx); 933 if (ctx->sw_cipher.cipher) 934 crypto_free_sync_skcipher(ctx->sw_cipher.cipher); 935 } 936 937 static int crypto4xx_aead_init(struct crypto_aead *tfm) 938 { 939 struct aead_alg *alg = crypto_aead_alg(tfm); 940 struct crypto4xx_ctx *ctx = crypto_aead_ctx(tfm); 941 struct crypto4xx_alg *amcc_alg; 942 943 ctx->sw_cipher.aead = crypto_alloc_aead(alg->base.cra_name, 0, 944 CRYPTO_ALG_NEED_FALLBACK | 945 CRYPTO_ALG_ASYNC); 946 if (IS_ERR(ctx->sw_cipher.aead)) 947 return PTR_ERR(ctx->sw_cipher.aead); 948 949 amcc_alg = container_of(alg, struct crypto4xx_alg, alg.u.aead); 950 crypto4xx_ctx_init(amcc_alg, ctx); 951 crypto_aead_set_reqsize(tfm, max(sizeof(struct aead_request) + 32 + 952 crypto_aead_reqsize(ctx->sw_cipher.aead), 953 sizeof(struct crypto4xx_aead_reqctx))); 954 return 0; 955 } 956 957 static void crypto4xx_aead_exit(struct crypto_aead *tfm) 958 { 959 struct crypto4xx_ctx *ctx = crypto_aead_ctx(tfm); 960 961 crypto4xx_common_exit(ctx); 962 crypto_free_aead(ctx->sw_cipher.aead); 963 } 964 965 static int crypto4xx_register_alg(struct crypto4xx_device *sec_dev, 966 struct crypto4xx_alg_common *crypto_alg, 967 int array_size) 968 { 969 struct crypto4xx_alg *alg; 970 int i; 971 int rc = 0; 972 973 for (i = 0; i < array_size; i++) { 974 alg = kzalloc_obj(struct crypto4xx_alg); 975 if (!alg) 976 return -ENOMEM; 977 978 alg->alg = crypto_alg[i]; 979 alg->dev = sec_dev; 980 981 switch (alg->alg.type) { 982 case CRYPTO_ALG_TYPE_AEAD: 983 rc = crypto_register_aead(&alg->alg.u.aead); 984 break; 985 986 default: 987 rc = crypto_register_skcipher(&alg->alg.u.cipher); 988 break; 989 } 990 991 if (rc) 992 kfree(alg); 993 else 994 list_add_tail(&alg->entry, &sec_dev->alg_list); 995 } 996 997 return 0; 998 } 999 1000 static void crypto4xx_unregister_alg(struct crypto4xx_device *sec_dev) 1001 { 1002 struct crypto4xx_alg *alg, *tmp; 1003 1004 list_for_each_entry_safe(alg, tmp, &sec_dev->alg_list, entry) { 1005 list_del(&alg->entry); 1006 switch (alg->alg.type) { 1007 case CRYPTO_ALG_TYPE_AEAD: 1008 crypto_unregister_aead(&alg->alg.u.aead); 1009 break; 1010 1011 default: 1012 crypto_unregister_skcipher(&alg->alg.u.cipher); 1013 } 1014 kfree(alg); 1015 } 1016 } 1017 1018 static void crypto4xx_bh_tasklet_cb(unsigned long data) 1019 { 1020 struct device *dev = (struct device *)data; 1021 struct crypto4xx_core_device *core_dev = dev_get_drvdata(dev); 1022 struct pd_uinfo *pd_uinfo; 1023 struct ce_pd *pd; 1024 u32 tail = core_dev->dev->pdr_tail; 1025 u32 head = core_dev->dev->pdr_head; 1026 1027 do { 1028 pd_uinfo = &core_dev->dev->pdr_uinfo[tail]; 1029 pd = &core_dev->dev->pdr[tail]; 1030 if ((pd_uinfo->state & PD_ENTRY_INUSE) && 1031 ((READ_ONCE(pd->pd_ctl.w) & 1032 (PD_CTL_PE_DONE | PD_CTL_HOST_READY)) == 1033 PD_CTL_PE_DONE)) { 1034 crypto4xx_pd_done(core_dev->dev, tail); 1035 tail = crypto4xx_put_pd_to_pdr(core_dev->dev, tail); 1036 } else { 1037 /* if tail not done, break */ 1038 break; 1039 } 1040 } while (head != tail); 1041 } 1042 1043 /* 1044 * Top Half of isr. 1045 */ 1046 static inline irqreturn_t crypto4xx_interrupt_handler(int irq, void *data, 1047 u32 clr_val) 1048 { 1049 struct device *dev = data; 1050 struct crypto4xx_core_device *core_dev = dev_get_drvdata(dev); 1051 1052 writel(clr_val, core_dev->dev->ce_base + CRYPTO4XX_INT_CLR); 1053 tasklet_schedule(&core_dev->tasklet); 1054 1055 return IRQ_HANDLED; 1056 } 1057 1058 static irqreturn_t crypto4xx_ce_interrupt_handler(int irq, void *data) 1059 { 1060 return crypto4xx_interrupt_handler(irq, data, PPC4XX_INTERRUPT_CLR); 1061 } 1062 1063 static irqreturn_t crypto4xx_ce_interrupt_handler_revb(int irq, void *data) 1064 { 1065 return crypto4xx_interrupt_handler(irq, data, PPC4XX_INTERRUPT_CLR | 1066 PPC4XX_TMO_ERR_INT); 1067 } 1068 1069 /* 1070 * Supported Crypto Algorithms 1071 */ 1072 static struct crypto4xx_alg_common crypto4xx_alg[] = { 1073 /* Crypto AES modes */ 1074 { .type = CRYPTO_ALG_TYPE_SKCIPHER, .u.cipher = { 1075 .base = { 1076 .cra_name = "cbc(aes)", 1077 .cra_driver_name = "cbc-aes-ppc4xx", 1078 .cra_priority = CRYPTO4XX_CRYPTO_PRIORITY, 1079 .cra_flags = CRYPTO_ALG_ASYNC | 1080 CRYPTO_ALG_KERN_DRIVER_ONLY, 1081 .cra_blocksize = AES_BLOCK_SIZE, 1082 .cra_ctxsize = sizeof(struct crypto4xx_ctx), 1083 .cra_module = THIS_MODULE, 1084 }, 1085 .min_keysize = AES_MIN_KEY_SIZE, 1086 .max_keysize = AES_MAX_KEY_SIZE, 1087 .ivsize = AES_IV_SIZE, 1088 .setkey = crypto4xx_setkey_aes_cbc, 1089 .encrypt = crypto4xx_encrypt_iv_block, 1090 .decrypt = crypto4xx_decrypt_iv_block, 1091 .init = crypto4xx_sk_init, 1092 .exit = crypto4xx_sk_exit, 1093 } }, 1094 { .type = CRYPTO_ALG_TYPE_SKCIPHER, .u.cipher = { 1095 .base = { 1096 .cra_name = "ctr(aes)", 1097 .cra_driver_name = "ctr-aes-ppc4xx", 1098 .cra_priority = CRYPTO4XX_CRYPTO_PRIORITY, 1099 .cra_flags = CRYPTO_ALG_NEED_FALLBACK | 1100 CRYPTO_ALG_ASYNC | 1101 CRYPTO_ALG_KERN_DRIVER_ONLY, 1102 .cra_blocksize = 1, 1103 .cra_ctxsize = sizeof(struct crypto4xx_ctx), 1104 .cra_module = THIS_MODULE, 1105 }, 1106 .min_keysize = AES_MIN_KEY_SIZE, 1107 .max_keysize = AES_MAX_KEY_SIZE, 1108 .ivsize = AES_IV_SIZE, 1109 .setkey = crypto4xx_setkey_aes_ctr, 1110 .encrypt = crypto4xx_encrypt_ctr, 1111 .decrypt = crypto4xx_decrypt_ctr, 1112 .init = crypto4xx_sk_init, 1113 .exit = crypto4xx_sk_exit, 1114 } }, 1115 { .type = CRYPTO_ALG_TYPE_SKCIPHER, .u.cipher = { 1116 .base = { 1117 .cra_name = "rfc3686(ctr(aes))", 1118 .cra_driver_name = "rfc3686-ctr-aes-ppc4xx", 1119 .cra_priority = CRYPTO4XX_CRYPTO_PRIORITY, 1120 .cra_flags = CRYPTO_ALG_ASYNC | 1121 CRYPTO_ALG_KERN_DRIVER_ONLY, 1122 .cra_blocksize = 1, 1123 .cra_ctxsize = sizeof(struct crypto4xx_ctx), 1124 .cra_module = THIS_MODULE, 1125 }, 1126 .min_keysize = AES_MIN_KEY_SIZE + CTR_RFC3686_NONCE_SIZE, 1127 .max_keysize = AES_MAX_KEY_SIZE + CTR_RFC3686_NONCE_SIZE, 1128 .ivsize = CTR_RFC3686_IV_SIZE, 1129 .setkey = crypto4xx_setkey_rfc3686, 1130 .encrypt = crypto4xx_rfc3686_encrypt, 1131 .decrypt = crypto4xx_rfc3686_decrypt, 1132 .init = crypto4xx_sk_init, 1133 .exit = crypto4xx_sk_exit, 1134 } }, 1135 { .type = CRYPTO_ALG_TYPE_SKCIPHER, .u.cipher = { 1136 .base = { 1137 .cra_name = "ecb(aes)", 1138 .cra_driver_name = "ecb-aes-ppc4xx", 1139 .cra_priority = CRYPTO4XX_CRYPTO_PRIORITY, 1140 .cra_flags = CRYPTO_ALG_ASYNC | 1141 CRYPTO_ALG_KERN_DRIVER_ONLY, 1142 .cra_blocksize = AES_BLOCK_SIZE, 1143 .cra_ctxsize = sizeof(struct crypto4xx_ctx), 1144 .cra_module = THIS_MODULE, 1145 }, 1146 .min_keysize = AES_MIN_KEY_SIZE, 1147 .max_keysize = AES_MAX_KEY_SIZE, 1148 .setkey = crypto4xx_setkey_aes_ecb, 1149 .encrypt = crypto4xx_encrypt_noiv_block, 1150 .decrypt = crypto4xx_decrypt_noiv_block, 1151 .init = crypto4xx_sk_init, 1152 .exit = crypto4xx_sk_exit, 1153 } }, 1154 1155 /* AEAD */ 1156 { .type = CRYPTO_ALG_TYPE_AEAD, .u.aead = { 1157 .setkey = crypto4xx_setkey_aes_ccm, 1158 .setauthsize = crypto4xx_setauthsize_aead, 1159 .encrypt = crypto4xx_encrypt_aes_ccm, 1160 .decrypt = crypto4xx_decrypt_aes_ccm, 1161 .init = crypto4xx_aead_init, 1162 .exit = crypto4xx_aead_exit, 1163 .ivsize = AES_BLOCK_SIZE, 1164 .maxauthsize = 16, 1165 .base = { 1166 .cra_name = "ccm(aes)", 1167 .cra_driver_name = "ccm-aes-ppc4xx", 1168 .cra_priority = CRYPTO4XX_CRYPTO_PRIORITY, 1169 .cra_flags = CRYPTO_ALG_ASYNC | 1170 CRYPTO_ALG_NEED_FALLBACK | 1171 CRYPTO_ALG_KERN_DRIVER_ONLY, 1172 .cra_blocksize = 1, 1173 .cra_ctxsize = sizeof(struct crypto4xx_ctx), 1174 .cra_module = THIS_MODULE, 1175 }, 1176 } }, 1177 { .type = CRYPTO_ALG_TYPE_AEAD, .u.aead = { 1178 .setkey = crypto4xx_setkey_aes_gcm, 1179 .setauthsize = crypto4xx_setauthsize_aead, 1180 .encrypt = crypto4xx_encrypt_aes_gcm, 1181 .decrypt = crypto4xx_decrypt_aes_gcm, 1182 .init = crypto4xx_aead_init, 1183 .exit = crypto4xx_aead_exit, 1184 .ivsize = GCM_AES_IV_SIZE, 1185 .maxauthsize = 16, 1186 .base = { 1187 .cra_name = "gcm(aes)", 1188 .cra_driver_name = "gcm-aes-ppc4xx", 1189 .cra_priority = CRYPTO4XX_CRYPTO_PRIORITY, 1190 .cra_flags = CRYPTO_ALG_ASYNC | 1191 CRYPTO_ALG_NEED_FALLBACK | 1192 CRYPTO_ALG_KERN_DRIVER_ONLY, 1193 .cra_blocksize = 1, 1194 .cra_ctxsize = sizeof(struct crypto4xx_ctx), 1195 .cra_module = THIS_MODULE, 1196 }, 1197 } }, 1198 }; 1199 1200 /* 1201 * Module Initialization Routine 1202 */ 1203 static int crypto4xx_probe(struct platform_device *ofdev) 1204 { 1205 int rc; 1206 struct device *dev = &ofdev->dev; 1207 struct crypto4xx_core_device *core_dev; 1208 struct device_node *np; 1209 u32 pvr; 1210 bool is_revb = true; 1211 1212 np = of_find_compatible_node(NULL, NULL, "amcc,ppc460ex-crypto"); 1213 if (np) { 1214 mtdcri(SDR0, PPC460EX_SDR0_SRST, 1215 mfdcri(SDR0, PPC460EX_SDR0_SRST) | PPC460EX_CE_RESET); 1216 mtdcri(SDR0, PPC460EX_SDR0_SRST, 1217 mfdcri(SDR0, PPC460EX_SDR0_SRST) & ~PPC460EX_CE_RESET); 1218 } else { 1219 np = of_find_compatible_node(NULL, NULL, "amcc,ppc405ex-crypto"); 1220 if (np) { 1221 mtdcri(SDR0, PPC405EX_SDR0_SRST, 1222 mfdcri(SDR0, PPC405EX_SDR0_SRST) | PPC405EX_CE_RESET); 1223 mtdcri(SDR0, PPC405EX_SDR0_SRST, 1224 mfdcri(SDR0, PPC405EX_SDR0_SRST) & ~PPC405EX_CE_RESET); 1225 is_revb = false; 1226 } else { 1227 np = of_find_compatible_node(NULL, NULL, "amcc,ppc460sx-crypto"); 1228 if (np) { 1229 mtdcri(SDR0, PPC460SX_SDR0_SRST, 1230 mfdcri(SDR0, PPC460SX_SDR0_SRST) | PPC460SX_CE_RESET); 1231 mtdcri(SDR0, PPC460SX_SDR0_SRST, 1232 mfdcri(SDR0, PPC460SX_SDR0_SRST) & ~PPC460SX_CE_RESET); 1233 } else { 1234 printk(KERN_ERR "Crypto Function Not supported!\n"); 1235 return -EINVAL; 1236 } 1237 } 1238 } 1239 1240 of_node_put(np); 1241 1242 core_dev = devm_kzalloc( 1243 &ofdev->dev, sizeof(struct crypto4xx_core_device), GFP_KERNEL); 1244 if (!core_dev) 1245 return -ENOMEM; 1246 1247 dev_set_drvdata(dev, core_dev); 1248 core_dev->ofdev = ofdev; 1249 core_dev->dev = devm_kzalloc( 1250 &ofdev->dev, sizeof(struct crypto4xx_device), GFP_KERNEL); 1251 if (!core_dev->dev) 1252 return -ENOMEM; 1253 1254 /* 1255 * Older version of 460EX/GT have a hardware bug. 1256 * Hence they do not support H/W based security intr coalescing 1257 */ 1258 pvr = mfspr(SPRN_PVR); 1259 if (is_revb && ((pvr >> 4) == 0x130218A)) { 1260 u32 min = PVR_MIN(pvr); 1261 1262 if (min < 4) { 1263 dev_info(dev, "RevA detected - disable interrupt coalescing\n"); 1264 is_revb = false; 1265 } 1266 } 1267 1268 core_dev->dev->core_dev = core_dev; 1269 core_dev->dev->is_revb = is_revb; 1270 core_dev->device = dev; 1271 spin_lock_init(&core_dev->lock); 1272 INIT_LIST_HEAD(&core_dev->dev->alg_list); 1273 ratelimit_default_init(&core_dev->dev->aead_ratelimit); 1274 rc = crypto4xx_build_sdr(core_dev->dev); 1275 if (rc) 1276 goto err_build_sdr; 1277 rc = crypto4xx_build_pdr(core_dev->dev); 1278 if (rc) 1279 goto err_build_sdr; 1280 1281 rc = crypto4xx_build_gdr(core_dev->dev); 1282 if (rc) 1283 goto err_build_sdr; 1284 1285 /* Init tasklet for bottom half processing */ 1286 tasklet_init(&core_dev->tasklet, crypto4xx_bh_tasklet_cb, 1287 (unsigned long) dev); 1288 1289 core_dev->dev->ce_base = devm_platform_ioremap_resource(ofdev, 0); 1290 if (IS_ERR(core_dev->dev->ce_base)) { 1291 dev_err(&ofdev->dev, "failed to ioremap resource"); 1292 rc = PTR_ERR(core_dev->dev->ce_base); 1293 goto err_build_sdr; 1294 } 1295 1296 /* Register for Crypto isr, Crypto Engine IRQ */ 1297 core_dev->irq = platform_get_irq(ofdev, 0); 1298 if (core_dev->irq < 0) { 1299 rc = core_dev->irq; 1300 goto err_iomap; 1301 } 1302 rc = devm_request_irq(&ofdev->dev, core_dev->irq, 1303 is_revb ? crypto4xx_ce_interrupt_handler_revb : 1304 crypto4xx_ce_interrupt_handler, 1305 0, KBUILD_MODNAME, dev); 1306 if (rc) 1307 goto err_iomap; 1308 1309 /* need to setup pdr, rdr, gdr and sdr before this */ 1310 crypto4xx_hw_init(core_dev->dev); 1311 1312 /* Register security algorithms with Linux CryptoAPI */ 1313 rc = crypto4xx_register_alg(core_dev->dev, crypto4xx_alg, 1314 ARRAY_SIZE(crypto4xx_alg)); 1315 if (rc) 1316 goto err_iomap; 1317 1318 ppc4xx_trng_probe(core_dev); 1319 return 0; 1320 1321 err_iomap: 1322 tasklet_kill(&core_dev->tasklet); 1323 err_build_sdr: 1324 crypto4xx_destroy_sdr(core_dev->dev); 1325 crypto4xx_destroy_gdr(core_dev->dev); 1326 crypto4xx_destroy_pdr(core_dev->dev); 1327 return rc; 1328 } 1329 1330 static void crypto4xx_remove(struct platform_device *ofdev) 1331 { 1332 struct device *dev = &ofdev->dev; 1333 struct crypto4xx_core_device *core_dev = dev_get_drvdata(dev); 1334 1335 ppc4xx_trng_remove(core_dev); 1336 1337 tasklet_kill(&core_dev->tasklet); 1338 /* Un-register with Linux CryptoAPI */ 1339 crypto4xx_unregister_alg(core_dev->dev); 1340 /* Free all allocated memory */ 1341 crypto4xx_stop_all(core_dev); 1342 } 1343 1344 static const struct of_device_id crypto4xx_match[] = { 1345 { .compatible = "amcc,ppc4xx-crypto",}, 1346 { }, 1347 }; 1348 MODULE_DEVICE_TABLE(of, crypto4xx_match); 1349 1350 static struct platform_driver crypto4xx_driver = { 1351 .driver = { 1352 .name = KBUILD_MODNAME, 1353 .of_match_table = crypto4xx_match, 1354 }, 1355 .probe = crypto4xx_probe, 1356 .remove = crypto4xx_remove, 1357 }; 1358 1359 module_platform_driver(crypto4xx_driver); 1360 1361 MODULE_LICENSE("GPL"); 1362 MODULE_AUTHOR("James Hsiao <jhsiao@amcc.com>"); 1363 MODULE_DESCRIPTION("Driver for AMCC PPC4xx crypto accelerator"); 1364