1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * TI CPUFreq/OPP hw-supported driver 4 * 5 * Copyright (C) 2016-2017 Texas Instruments, Inc. 6 * Dave Gerlach <d-gerlach@ti.com> 7 */ 8 9 #include <linux/cpu.h> 10 #include <linux/io.h> 11 #include <linux/mfd/syscon.h> 12 #include <linux/module.h> 13 #include <linux/init.h> 14 #include <linux/of.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_opp.h> 17 #include <linux/regmap.h> 18 #include <linux/slab.h> 19 #include <linux/sys_soc.h> 20 21 #define REVISION_MASK 0xF 22 #define REVISION_SHIFT 28 23 24 #define AM33XX_800M_ARM_MPU_MAX_FREQ 0x1E2F 25 #define AM43XX_600M_ARM_MPU_MAX_FREQ 0xFFA 26 27 #define DRA7_EFUSE_HAS_OD_MPU_OPP 11 28 #define DRA7_EFUSE_HAS_HIGH_MPU_OPP 15 29 #define DRA76_EFUSE_HAS_PLUS_MPU_OPP 18 30 #define DRA7_EFUSE_HAS_ALL_MPU_OPP 23 31 #define DRA76_EFUSE_HAS_ALL_MPU_OPP 24 32 33 #define DRA7_EFUSE_NOM_MPU_OPP BIT(0) 34 #define DRA7_EFUSE_OD_MPU_OPP BIT(1) 35 #define DRA7_EFUSE_HIGH_MPU_OPP BIT(2) 36 #define DRA76_EFUSE_PLUS_MPU_OPP BIT(3) 37 38 #define OMAP3_CONTROL_DEVICE_STATUS 0x4800244C 39 #define OMAP3_CONTROL_IDCODE 0x4830A204 40 #define OMAP34xx_ProdID_SKUID 0x4830A20C 41 #define OMAP3_SYSCON_BASE (0x48000000 + 0x2000 + 0x270) 42 43 #define AM625_EFUSE_K_MPU_OPP 11 44 #define AM625_EFUSE_S_MPU_OPP 19 45 #define AM625_EFUSE_T_MPU_OPP 20 46 47 #define AM625_SUPPORT_K_MPU_OPP BIT(0) 48 #define AM625_SUPPORT_S_MPU_OPP BIT(1) 49 #define AM625_SUPPORT_T_MPU_OPP BIT(2) 50 51 enum { 52 AM62A7_EFUSE_M_MPU_OPP = 13, 53 AM62A7_EFUSE_N_MPU_OPP, 54 AM62A7_EFUSE_O_MPU_OPP, 55 AM62A7_EFUSE_P_MPU_OPP, 56 AM62A7_EFUSE_Q_MPU_OPP, 57 AM62A7_EFUSE_R_MPU_OPP, 58 AM62A7_EFUSE_S_MPU_OPP, 59 /* 60 * The V, U, and T speed grade numbering is out of order 61 * to align with the AM625 more uniformly. I promise I know 62 * my ABCs ;) 63 */ 64 AM62A7_EFUSE_V_MPU_OPP, 65 AM62A7_EFUSE_U_MPU_OPP, 66 AM62A7_EFUSE_T_MPU_OPP, 67 }; 68 69 #define AM62A7_SUPPORT_N_MPU_OPP BIT(0) 70 #define AM62A7_SUPPORT_R_MPU_OPP BIT(1) 71 #define AM62A7_SUPPORT_V_MPU_OPP BIT(2) 72 73 #define AM62L3_EFUSE_E_MPU_OPP 5 74 #define AM62L3_EFUSE_O_MPU_OPP 15 75 76 #define AM62L3_SUPPORT_E_MPU_OPP BIT(0) 77 #define AM62L3_SUPPORT_O_MPU_OPP BIT(1) 78 79 #define AM62P5_EFUSE_O_MPU_OPP 15 80 #define AM62P5_EFUSE_S_MPU_OPP 19 81 #define AM62P5_EFUSE_T_MPU_OPP 20 82 #define AM62P5_EFUSE_U_MPU_OPP 21 83 #define AM62P5_EFUSE_V_MPU_OPP 22 84 85 #define AM62P5_SUPPORT_O_MPU_OPP BIT(0) 86 #define AM62P5_SUPPORT_U_MPU_OPP BIT(2) 87 88 #define VERSION_COUNT 2 89 90 struct ti_cpufreq_data; 91 92 struct ti_cpufreq_soc_data { 93 const char * const *reg_names; 94 unsigned long (*efuse_xlate)(struct ti_cpufreq_data *opp_data, 95 unsigned long efuse); 96 unsigned long efuse_fallback; 97 unsigned long efuse_offset; 98 unsigned long efuse_mask; 99 unsigned long efuse_shift; 100 unsigned long rev_offset; 101 bool multi_regulator; 102 bool needs_k3_socinfo; 103 /* Backward compatibility hack: Might have missing syscon */ 104 #define TI_QUIRK_SYSCON_MAY_BE_MISSING 0x1 105 /* Backward compatibility hack: new syscon size is 1 register wide */ 106 #define TI_QUIRK_SYSCON_IS_SINGLE_REG 0x2 107 u8 quirks; 108 }; 109 110 struct ti_cpufreq_data { 111 struct device *cpu_dev; 112 struct device_node *opp_node; 113 struct regmap *syscon; 114 const struct ti_cpufreq_soc_data *soc_data; 115 }; 116 117 static unsigned long amx3_efuse_xlate(struct ti_cpufreq_data *opp_data, 118 unsigned long efuse) 119 { 120 if (!efuse) 121 efuse = opp_data->soc_data->efuse_fallback; 122 /* AM335x and AM437x use "OPP disable" bits, so invert */ 123 return ~efuse; 124 } 125 126 static unsigned long dra7_efuse_xlate(struct ti_cpufreq_data *opp_data, 127 unsigned long efuse) 128 { 129 unsigned long calculated_efuse = DRA7_EFUSE_NOM_MPU_OPP; 130 131 /* 132 * The efuse on dra7 and am57 parts contains a specific 133 * value indicating the highest available OPP. 134 */ 135 136 switch (efuse) { 137 case DRA76_EFUSE_HAS_PLUS_MPU_OPP: 138 case DRA76_EFUSE_HAS_ALL_MPU_OPP: 139 calculated_efuse |= DRA76_EFUSE_PLUS_MPU_OPP; 140 fallthrough; 141 case DRA7_EFUSE_HAS_ALL_MPU_OPP: 142 case DRA7_EFUSE_HAS_HIGH_MPU_OPP: 143 calculated_efuse |= DRA7_EFUSE_HIGH_MPU_OPP; 144 fallthrough; 145 case DRA7_EFUSE_HAS_OD_MPU_OPP: 146 calculated_efuse |= DRA7_EFUSE_OD_MPU_OPP; 147 } 148 149 return calculated_efuse; 150 } 151 152 static unsigned long omap3_efuse_xlate(struct ti_cpufreq_data *opp_data, 153 unsigned long efuse) 154 { 155 /* OPP enable bit ("Speed Binned") */ 156 return BIT(efuse); 157 } 158 159 static unsigned long am62p5_efuse_xlate(struct ti_cpufreq_data *opp_data, 160 unsigned long efuse) 161 { 162 unsigned long calculated_efuse = AM62P5_SUPPORT_O_MPU_OPP; 163 164 switch (efuse) { 165 case AM62P5_EFUSE_V_MPU_OPP: 166 case AM62P5_EFUSE_U_MPU_OPP: 167 case AM62P5_EFUSE_T_MPU_OPP: 168 case AM62P5_EFUSE_S_MPU_OPP: 169 calculated_efuse |= AM62P5_SUPPORT_U_MPU_OPP; 170 fallthrough; 171 case AM62P5_EFUSE_O_MPU_OPP: 172 calculated_efuse |= AM62P5_SUPPORT_O_MPU_OPP; 173 } 174 175 return calculated_efuse; 176 } 177 178 static unsigned long am62a7_efuse_xlate(struct ti_cpufreq_data *opp_data, 179 unsigned long efuse) 180 { 181 unsigned long calculated_efuse = AM62A7_SUPPORT_N_MPU_OPP; 182 183 switch (efuse) { 184 case AM62A7_EFUSE_V_MPU_OPP: 185 case AM62A7_EFUSE_U_MPU_OPP: 186 case AM62A7_EFUSE_T_MPU_OPP: 187 case AM62A7_EFUSE_S_MPU_OPP: 188 calculated_efuse |= AM62A7_SUPPORT_V_MPU_OPP; 189 fallthrough; 190 case AM62A7_EFUSE_R_MPU_OPP: 191 case AM62A7_EFUSE_Q_MPU_OPP: 192 case AM62A7_EFUSE_P_MPU_OPP: 193 case AM62A7_EFUSE_O_MPU_OPP: 194 calculated_efuse |= AM62A7_SUPPORT_R_MPU_OPP; 195 fallthrough; 196 case AM62A7_EFUSE_N_MPU_OPP: 197 case AM62A7_EFUSE_M_MPU_OPP: 198 calculated_efuse |= AM62A7_SUPPORT_N_MPU_OPP; 199 } 200 201 return calculated_efuse; 202 } 203 204 static unsigned long am625_efuse_xlate(struct ti_cpufreq_data *opp_data, 205 unsigned long efuse) 206 { 207 unsigned long calculated_efuse = AM625_SUPPORT_K_MPU_OPP; 208 209 switch (efuse) { 210 case AM625_EFUSE_T_MPU_OPP: 211 calculated_efuse |= AM625_SUPPORT_T_MPU_OPP; 212 fallthrough; 213 case AM625_EFUSE_S_MPU_OPP: 214 calculated_efuse |= AM625_SUPPORT_S_MPU_OPP; 215 fallthrough; 216 case AM625_EFUSE_K_MPU_OPP: 217 calculated_efuse |= AM625_SUPPORT_K_MPU_OPP; 218 } 219 220 return calculated_efuse; 221 } 222 223 static unsigned long am62l3_efuse_xlate(struct ti_cpufreq_data *opp_data, 224 unsigned long efuse) 225 { 226 unsigned long calculated_efuse = AM62L3_SUPPORT_E_MPU_OPP; 227 228 switch (efuse) { 229 case AM62L3_EFUSE_O_MPU_OPP: 230 calculated_efuse |= AM62L3_SUPPORT_O_MPU_OPP; 231 fallthrough; 232 case AM62L3_EFUSE_E_MPU_OPP: 233 calculated_efuse |= AM62L3_SUPPORT_E_MPU_OPP; 234 } 235 236 return calculated_efuse; 237 } 238 239 static struct ti_cpufreq_soc_data am3x_soc_data = { 240 .efuse_xlate = amx3_efuse_xlate, 241 .efuse_fallback = AM33XX_800M_ARM_MPU_MAX_FREQ, 242 .efuse_offset = 0x07fc, 243 .efuse_mask = 0x1fff, 244 .rev_offset = 0x600, 245 .multi_regulator = false, 246 }; 247 248 static struct ti_cpufreq_soc_data am4x_soc_data = { 249 .efuse_xlate = amx3_efuse_xlate, 250 .efuse_fallback = AM43XX_600M_ARM_MPU_MAX_FREQ, 251 .efuse_offset = 0x0610, 252 .efuse_mask = 0x3f, 253 .rev_offset = 0x600, 254 .multi_regulator = false, 255 }; 256 257 static struct ti_cpufreq_soc_data dra7_soc_data = { 258 .efuse_xlate = dra7_efuse_xlate, 259 .efuse_offset = 0x020c, 260 .efuse_mask = 0xf80000, 261 .efuse_shift = 19, 262 .rev_offset = 0x204, 263 .multi_regulator = true, 264 }; 265 266 /* 267 * OMAP35x TRM (SPRUF98K): 268 * CONTROL_IDCODE (0x4830 A204) describes Silicon revisions. 269 * Control OMAP Status Register 15:0 (Address 0x4800 244C) 270 * to separate between omap3503, omap3515, omap3525, omap3530 271 * and feature presence. 272 * There are encodings for versions limited to 400/266MHz 273 * but we ignore. 274 * Not clear if this also holds for omap34xx. 275 * some eFuse values e.g. CONTROL_FUSE_OPP1_VDD1 276 * are stored in the SYSCON register range 277 * Register 0x4830A20C [ProdID.SKUID] [0:3] 278 * 0x0 for normal 600/430MHz device. 279 * 0x8 for 720/520MHz device. 280 * Not clear what omap34xx value is. 281 */ 282 283 static struct ti_cpufreq_soc_data omap34xx_soc_data = { 284 .efuse_xlate = omap3_efuse_xlate, 285 .efuse_offset = OMAP34xx_ProdID_SKUID - OMAP3_SYSCON_BASE, 286 .efuse_shift = 3, 287 .efuse_mask = BIT(3), 288 .rev_offset = OMAP3_CONTROL_IDCODE - OMAP3_SYSCON_BASE, 289 .multi_regulator = false, 290 .quirks = TI_QUIRK_SYSCON_MAY_BE_MISSING, 291 }; 292 293 /* 294 * AM/DM37x TRM (SPRUGN4M) 295 * CONTROL_IDCODE (0x4830 A204) describes Silicon revisions. 296 * Control Device Status Register 15:0 (Address 0x4800 244C) 297 * to separate between am3703, am3715, dm3725, dm3730 298 * and feature presence. 299 * Speed Binned = Bit 9 300 * 0 800/600 MHz 301 * 1 1000/800 MHz 302 * some eFuse values e.g. CONTROL_FUSE_OPP 1G_VDD1 303 * are stored in the SYSCON register range. 304 * There is no 0x4830A20C [ProdID.SKUID] register (exists but 305 * seems to always read as 0). 306 */ 307 308 static const char * const omap3_reg_names[] = {"cpu0", "vbb", NULL}; 309 310 static struct ti_cpufreq_soc_data omap36xx_soc_data = { 311 .reg_names = omap3_reg_names, 312 .efuse_xlate = omap3_efuse_xlate, 313 .efuse_offset = OMAP3_CONTROL_DEVICE_STATUS - OMAP3_SYSCON_BASE, 314 .efuse_shift = 9, 315 .efuse_mask = BIT(9), 316 .rev_offset = OMAP3_CONTROL_IDCODE - OMAP3_SYSCON_BASE, 317 .multi_regulator = true, 318 .quirks = TI_QUIRK_SYSCON_MAY_BE_MISSING, 319 }; 320 321 /* 322 * AM3517 is quite similar to AM/DM37x except that it has no 323 * high speed grade eFuse and no abb ldo 324 */ 325 326 static struct ti_cpufreq_soc_data am3517_soc_data = { 327 .efuse_xlate = omap3_efuse_xlate, 328 .efuse_offset = OMAP3_CONTROL_DEVICE_STATUS - OMAP3_SYSCON_BASE, 329 .efuse_shift = 0, 330 .efuse_mask = 0, 331 .rev_offset = OMAP3_CONTROL_IDCODE - OMAP3_SYSCON_BASE, 332 .multi_regulator = false, 333 .quirks = TI_QUIRK_SYSCON_MAY_BE_MISSING, 334 }; 335 336 static const struct soc_device_attribute k3_cpufreq_soc[] = { 337 { .family = "AM62X", }, 338 { .family = "AM62AX", }, 339 { .family = "AM62DX", }, 340 { .family = "AM62LX", }, 341 { .family = "AM62PX", }, 342 { /* sentinel */ } 343 }; 344 345 static struct ti_cpufreq_soc_data am625_soc_data = { 346 .efuse_xlate = am625_efuse_xlate, 347 .efuse_offset = 0x0018, 348 .efuse_mask = 0x07c0, 349 .efuse_shift = 0x6, 350 .multi_regulator = false, 351 .needs_k3_socinfo = true, 352 .quirks = TI_QUIRK_SYSCON_IS_SINGLE_REG, 353 }; 354 355 static struct ti_cpufreq_soc_data am62a7_soc_data = { 356 .efuse_xlate = am62a7_efuse_xlate, 357 .efuse_offset = 0x0, 358 .efuse_mask = 0x07c0, 359 .efuse_shift = 0x6, 360 .multi_regulator = false, 361 .needs_k3_socinfo = true, 362 }; 363 364 static struct ti_cpufreq_soc_data am62l3_soc_data = { 365 .efuse_xlate = am62l3_efuse_xlate, 366 .efuse_offset = 0x0, 367 .efuse_mask = 0x07c0, 368 .efuse_shift = 0x6, 369 .multi_regulator = false, 370 .needs_k3_socinfo = true, 371 }; 372 373 static struct ti_cpufreq_soc_data am62p5_soc_data = { 374 .efuse_xlate = am62p5_efuse_xlate, 375 .efuse_offset = 0x0, 376 .efuse_mask = 0x07c0, 377 .efuse_shift = 0x6, 378 .multi_regulator = false, 379 .needs_k3_socinfo = true, 380 }; 381 382 /** 383 * ti_cpufreq_get_efuse() - Parse and return efuse value present on SoC 384 * @opp_data: pointer to ti_cpufreq_data context 385 * @efuse_value: Set to the value parsed from efuse 386 * 387 * Returns error code if efuse not read properly. 388 */ 389 static int ti_cpufreq_get_efuse(struct ti_cpufreq_data *opp_data, 390 u32 *efuse_value) 391 { 392 struct device *dev = opp_data->cpu_dev; 393 u32 efuse; 394 int ret; 395 396 ret = regmap_read(opp_data->syscon, opp_data->soc_data->efuse_offset, 397 &efuse); 398 399 if (opp_data->soc_data->quirks & TI_QUIRK_SYSCON_IS_SINGLE_REG && ret == -EIO) 400 ret = regmap_read(opp_data->syscon, 0x0, &efuse); 401 402 if (opp_data->soc_data->quirks & TI_QUIRK_SYSCON_MAY_BE_MISSING && ret == -EIO) { 403 /* not a syscon register! */ 404 void __iomem *regs = ioremap(OMAP3_SYSCON_BASE + 405 opp_data->soc_data->efuse_offset, 4); 406 407 if (!regs) 408 return -ENOMEM; 409 efuse = readl(regs); 410 iounmap(regs); 411 } 412 else if (ret) { 413 dev_err(dev, 414 "Failed to read the efuse value from syscon: %d\n", 415 ret); 416 return ret; 417 } 418 419 efuse = (efuse & opp_data->soc_data->efuse_mask); 420 efuse >>= opp_data->soc_data->efuse_shift; 421 422 *efuse_value = opp_data->soc_data->efuse_xlate(opp_data, efuse); 423 424 return 0; 425 } 426 427 /** 428 * ti_cpufreq_get_rev() - Parse and return rev value present on SoC 429 * @opp_data: pointer to ti_cpufreq_data context 430 * @revision_value: Set to the value parsed from revision register 431 * 432 * Returns error code if revision not read properly. 433 */ 434 static int ti_cpufreq_get_rev(struct ti_cpufreq_data *opp_data, 435 u32 *revision_value) 436 { 437 struct device *dev = opp_data->cpu_dev; 438 u32 revision; 439 int ret; 440 if (soc_device_match(k3_cpufreq_soc)) { 441 /* 442 * Since the SR is 1.0, hard code the revision_value as 443 * 0x1 here. This way we avoid re using the same register 444 * that is giving us required information inside socinfo 445 * anyway. 446 */ 447 *revision_value = 0x1; 448 goto done; 449 } 450 451 /* Defer if k3-socinfo hasn't registered the SoC device yet */ 452 if (opp_data->soc_data->needs_k3_socinfo) 453 return dev_err_probe(opp_data->cpu_dev, -EPROBE_DEFER, 454 "SoC device not registered by k3-socinfo\n"); 455 456 ret = regmap_read(opp_data->syscon, opp_data->soc_data->rev_offset, 457 &revision); 458 if (opp_data->soc_data->quirks & TI_QUIRK_SYSCON_MAY_BE_MISSING && ret == -EIO) { 459 /* not a syscon register! */ 460 void __iomem *regs = ioremap(OMAP3_SYSCON_BASE + 461 opp_data->soc_data->rev_offset, 4); 462 463 if (!regs) 464 return -ENOMEM; 465 revision = readl(regs); 466 iounmap(regs); 467 } 468 else if (ret) { 469 dev_err(dev, 470 "Failed to read the revision number from syscon: %d\n", 471 ret); 472 return ret; 473 } 474 475 *revision_value = BIT((revision >> REVISION_SHIFT) & REVISION_MASK); 476 477 done: 478 return 0; 479 } 480 481 static int ti_cpufreq_setup_syscon_register(struct ti_cpufreq_data *opp_data) 482 { 483 struct device *dev = opp_data->cpu_dev; 484 struct device_node *np = opp_data->opp_node; 485 486 opp_data->syscon = syscon_regmap_lookup_by_phandle(np, 487 "syscon"); 488 if (IS_ERR(opp_data->syscon)) { 489 dev_err(dev, 490 "\"syscon\" is missing, cannot use OPPv2 table.\n"); 491 return PTR_ERR(opp_data->syscon); 492 } 493 494 return 0; 495 } 496 497 static const struct of_device_id ti_cpufreq_of_match[] __maybe_unused = { 498 { .compatible = "ti,am33xx", .data = &am3x_soc_data, }, 499 { .compatible = "ti,am3517", .data = &am3517_soc_data, }, 500 { .compatible = "ti,am43", .data = &am4x_soc_data, }, 501 { .compatible = "ti,dra7", .data = &dra7_soc_data }, 502 { .compatible = "ti,omap34xx", .data = &omap34xx_soc_data, }, 503 { .compatible = "ti,omap36xx", .data = &omap36xx_soc_data, }, 504 { .compatible = "ti,am625", .data = &am625_soc_data, }, 505 { .compatible = "ti,am62a7", .data = &am62a7_soc_data, }, 506 { .compatible = "ti,am62d2", .data = &am62a7_soc_data, }, 507 { .compatible = "ti,am62l3", .data = &am62l3_soc_data, }, 508 { .compatible = "ti,am62p5", .data = &am62p5_soc_data, }, 509 /* legacy */ 510 { .compatible = "ti,omap3430", .data = &omap34xx_soc_data, }, 511 { .compatible = "ti,omap3630", .data = &omap36xx_soc_data, }, 512 {}, 513 }; 514 515 static int ti_cpufreq_probe(struct platform_device *pdev) 516 { 517 u32 version[VERSION_COUNT]; 518 const struct of_device_id *match; 519 struct ti_cpufreq_data *opp_data; 520 const char * const default_reg_names[] = {"vdd", "vbb", NULL}; 521 int ret; 522 struct dev_pm_opp_config config = { 523 .supported_hw = version, 524 .supported_hw_count = ARRAY_SIZE(version), 525 }; 526 527 match = dev_get_platdata(&pdev->dev); 528 if (!match) 529 return -ENODEV; 530 531 opp_data = devm_kzalloc(&pdev->dev, sizeof(*opp_data), GFP_KERNEL); 532 if (!opp_data) 533 return -ENOMEM; 534 535 opp_data->soc_data = match->data; 536 537 opp_data->cpu_dev = get_cpu_device(0); 538 if (!opp_data->cpu_dev) { 539 pr_err("%s: Failed to get device for CPU0\n", __func__); 540 return -ENODEV; 541 } 542 543 opp_data->opp_node = dev_pm_opp_of_get_opp_desc_node(opp_data->cpu_dev); 544 if (!opp_data->opp_node) { 545 dev_info(opp_data->cpu_dev, 546 "OPP-v2 not supported, cpufreq-dt will attempt to use legacy tables.\n"); 547 goto register_cpufreq_dt; 548 } 549 550 ret = ti_cpufreq_setup_syscon_register(opp_data); 551 if (ret) 552 goto fail_put_node; 553 554 /* 555 * OPPs determine whether or not they are supported based on 556 * two metrics: 557 * 0 - SoC Revision 558 * 1 - eFuse value 559 */ 560 ret = ti_cpufreq_get_rev(opp_data, &version[0]); 561 if (ret) 562 goto fail_put_node; 563 564 ret = ti_cpufreq_get_efuse(opp_data, &version[1]); 565 if (ret) 566 goto fail_put_node; 567 568 if (opp_data->soc_data->multi_regulator) { 569 if (opp_data->soc_data->reg_names) 570 config.regulator_names = opp_data->soc_data->reg_names; 571 else 572 config.regulator_names = default_reg_names; 573 } 574 575 ret = dev_pm_opp_set_config(opp_data->cpu_dev, &config); 576 if (ret < 0) { 577 dev_err_probe(opp_data->cpu_dev, ret, "Failed to set OPP config\n"); 578 goto fail_put_node; 579 } 580 581 of_node_put(opp_data->opp_node); 582 583 register_cpufreq_dt: 584 platform_device_register_simple("cpufreq-dt", -1, NULL, 0); 585 586 return 0; 587 588 fail_put_node: 589 of_node_put(opp_data->opp_node); 590 591 return ret; 592 } 593 594 static int __init ti_cpufreq_init(void) 595 { 596 const struct of_device_id *match; 597 598 /* Check to ensure we are on a compatible platform */ 599 match = of_machine_get_match(ti_cpufreq_of_match); 600 if (match) 601 platform_device_register_data(NULL, "ti-cpufreq", -1, match, 602 sizeof(*match)); 603 604 return 0; 605 } 606 module_init(ti_cpufreq_init); 607 608 static struct platform_driver ti_cpufreq_driver = { 609 .probe = ti_cpufreq_probe, 610 .driver = { 611 .name = "ti-cpufreq", 612 }, 613 }; 614 builtin_platform_driver(ti_cpufreq_driver); 615 616 MODULE_DESCRIPTION("TI CPUFreq/OPP hw-supported driver"); 617 MODULE_AUTHOR("Dave Gerlach <d-gerlach@ti.com>"); 618 MODULE_LICENSE("GPL v2"); 619