1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved 4 */ 5 6 #include <linux/cpufreq.h> 7 #include <linux/dma-mapping.h> 8 #include <linux/module.h> 9 #include <linux/of.h> 10 #include <linux/platform_device.h> 11 12 #include <soc/tegra/bpmp.h> 13 #include <soc/tegra/bpmp-abi.h> 14 15 #define TEGRA186_NUM_CLUSTERS 2 16 #define EDVD_OFFSET_A57(core) ((SZ_64K * 6) + (0x20 + (core) * 0x4)) 17 #define EDVD_OFFSET_DENVER(core) ((SZ_64K * 7) + (0x20 + (core) * 0x4)) 18 #define EDVD_CORE_VOLT_FREQ_F_SHIFT 0 19 #define EDVD_CORE_VOLT_FREQ_F_MASK 0xffff 20 #define EDVD_CORE_VOLT_FREQ_V_SHIFT 16 21 22 struct tegra186_cpufreq_cpu { 23 unsigned int bpmp_cluster_id; 24 unsigned int edvd_offset; 25 }; 26 27 static const struct tegra186_cpufreq_cpu tegra186_cpus[] = { 28 /* CPU0 - A57 Cluster */ 29 { 30 .bpmp_cluster_id = 1, 31 .edvd_offset = EDVD_OFFSET_A57(0) 32 }, 33 /* CPU1 - Denver Cluster */ 34 { 35 .bpmp_cluster_id = 0, 36 .edvd_offset = EDVD_OFFSET_DENVER(0) 37 }, 38 /* CPU2 - Denver Cluster */ 39 { 40 .bpmp_cluster_id = 0, 41 .edvd_offset = EDVD_OFFSET_DENVER(1) 42 }, 43 /* CPU3 - A57 Cluster */ 44 { 45 .bpmp_cluster_id = 1, 46 .edvd_offset = EDVD_OFFSET_A57(1) 47 }, 48 /* CPU4 - A57 Cluster */ 49 { 50 .bpmp_cluster_id = 1, 51 .edvd_offset = EDVD_OFFSET_A57(2) 52 }, 53 /* CPU5 - A57 Cluster */ 54 { 55 .bpmp_cluster_id = 1, 56 .edvd_offset = EDVD_OFFSET_A57(3) 57 }, 58 }; 59 60 struct tegra186_cpufreq_cluster { 61 struct cpufreq_frequency_table *table; 62 u32 ref_clk_khz; 63 u32 div; 64 }; 65 66 struct tegra186_cpufreq_data { 67 void __iomem *regs; 68 const struct tegra186_cpufreq_cpu *cpus; 69 struct tegra186_cpufreq_cluster clusters[]; 70 }; 71 72 static int tegra186_cpufreq_init(struct cpufreq_policy *policy) 73 { 74 struct tegra186_cpufreq_data *data = cpufreq_get_driver_data(); 75 unsigned int cluster = data->cpus[policy->cpu].bpmp_cluster_id; 76 u32 cpu; 77 78 policy->freq_table = data->clusters[cluster].table; 79 policy->cpuinfo.transition_latency = 300 * 1000; 80 policy->driver_data = NULL; 81 82 /* set same policy for all cpus in a cluster */ 83 for (cpu = 0; cpu < ARRAY_SIZE(tegra186_cpus); cpu++) { 84 if (data->cpus[cpu].bpmp_cluster_id == cluster) 85 cpumask_set_cpu(cpu, policy->cpus); 86 } 87 88 return 0; 89 } 90 91 static int tegra186_cpufreq_set_target(struct cpufreq_policy *policy, 92 unsigned int index) 93 { 94 struct tegra186_cpufreq_data *data = cpufreq_get_driver_data(); 95 struct cpufreq_frequency_table *tbl = policy->freq_table + index; 96 unsigned int edvd_offset; 97 u32 edvd_val = tbl->driver_data; 98 u32 cpu; 99 100 for_each_cpu(cpu, policy->cpus) { 101 edvd_offset = data->cpus[cpu].edvd_offset; 102 writel(edvd_val, data->regs + edvd_offset); 103 } 104 105 return 0; 106 } 107 108 static unsigned int tegra186_cpufreq_get(unsigned int cpu) 109 { 110 struct cpufreq_policy *policy __free(put_cpufreq_policy) = cpufreq_cpu_get(cpu); 111 struct tegra186_cpufreq_data *data = cpufreq_get_driver_data(); 112 struct tegra186_cpufreq_cluster *cluster; 113 unsigned int edvd_offset, cluster_id; 114 u32 ndiv; 115 116 if (!policy) 117 return 0; 118 119 edvd_offset = data->cpus[policy->cpu].edvd_offset; 120 ndiv = readl(data->regs + edvd_offset) & EDVD_CORE_VOLT_FREQ_F_MASK; 121 cluster_id = data->cpus[policy->cpu].bpmp_cluster_id; 122 cluster = &data->clusters[cluster_id]; 123 124 return (cluster->ref_clk_khz * ndiv) / cluster->div; 125 } 126 127 static struct cpufreq_driver tegra186_cpufreq_driver = { 128 .name = "tegra186", 129 .flags = CPUFREQ_HAVE_GOVERNOR_PER_POLICY | 130 CPUFREQ_NEED_INITIAL_FREQ_CHECK, 131 .get = tegra186_cpufreq_get, 132 .verify = cpufreq_generic_frequency_table_verify, 133 .target_index = tegra186_cpufreq_set_target, 134 .init = tegra186_cpufreq_init, 135 }; 136 137 static struct cpufreq_frequency_table *init_vhint_table( 138 struct platform_device *pdev, struct tegra_bpmp *bpmp, 139 struct tegra186_cpufreq_cluster *cluster, unsigned int cluster_id, 140 int *num_rates) 141 { 142 struct cpufreq_frequency_table *table; 143 struct mrq_cpu_vhint_request req; 144 struct tegra_bpmp_message msg; 145 struct cpu_vhint_data *data; 146 int err, i, j; 147 dma_addr_t phys; 148 void *virt; 149 150 virt = dma_alloc_coherent(bpmp->dev, sizeof(*data), &phys, 151 GFP_KERNEL); 152 if (!virt) 153 return ERR_PTR(-ENOMEM); 154 155 data = (struct cpu_vhint_data *)virt; 156 157 memset(&req, 0, sizeof(req)); 158 req.addr = phys; 159 req.cluster_id = cluster_id; 160 161 memset(&msg, 0, sizeof(msg)); 162 msg.mrq = MRQ_CPU_VHINT; 163 msg.tx.data = &req; 164 msg.tx.size = sizeof(req); 165 166 err = tegra_bpmp_transfer(bpmp, &msg); 167 if (err) { 168 table = ERR_PTR(err); 169 goto free; 170 } 171 if (msg.rx.ret) { 172 table = ERR_PTR(-EINVAL); 173 goto free; 174 } 175 176 *num_rates = 0; 177 for (i = data->vfloor; i <= data->vceil; i++) { 178 u16 ndiv = data->ndiv[i]; 179 180 if (ndiv < data->ndiv_min || ndiv > data->ndiv_max) 181 continue; 182 183 /* Only store lowest voltage index for each rate */ 184 if (i > 0 && ndiv == data->ndiv[i - 1]) 185 continue; 186 187 (*num_rates)++; 188 } 189 190 table = devm_kcalloc(&pdev->dev, *num_rates + 1, sizeof(*table), 191 GFP_KERNEL); 192 if (!table) { 193 table = ERR_PTR(-ENOMEM); 194 goto free; 195 } 196 197 cluster->ref_clk_khz = data->ref_clk_hz / 1000; 198 cluster->div = data->pdiv * data->mdiv; 199 200 for (i = data->vfloor, j = 0; i <= data->vceil; i++) { 201 struct cpufreq_frequency_table *point; 202 u16 ndiv = data->ndiv[i]; 203 u32 edvd_val = 0; 204 205 if (ndiv < data->ndiv_min || ndiv > data->ndiv_max) 206 continue; 207 208 /* Only store lowest voltage index for each rate */ 209 if (i > 0 && ndiv == data->ndiv[i - 1]) 210 continue; 211 212 edvd_val |= i << EDVD_CORE_VOLT_FREQ_V_SHIFT; 213 edvd_val |= ndiv << EDVD_CORE_VOLT_FREQ_F_SHIFT; 214 215 point = &table[j++]; 216 point->driver_data = edvd_val; 217 point->frequency = (cluster->ref_clk_khz * ndiv) / cluster->div; 218 } 219 220 table[j].frequency = CPUFREQ_TABLE_END; 221 222 free: 223 dma_free_coherent(bpmp->dev, sizeof(*data), virt, phys); 224 225 return table; 226 } 227 228 static int tegra186_cpufreq_probe(struct platform_device *pdev) 229 { 230 struct tegra186_cpufreq_data *data; 231 struct tegra_bpmp *bpmp; 232 unsigned int i = 0, err, edvd_offset; 233 int num_rates = 0; 234 u32 edvd_val, cpu; 235 236 data = devm_kzalloc(&pdev->dev, 237 struct_size(data, clusters, TEGRA186_NUM_CLUSTERS), 238 GFP_KERNEL); 239 if (!data) 240 return -ENOMEM; 241 242 data->cpus = tegra186_cpus; 243 244 bpmp = tegra_bpmp_get(&pdev->dev); 245 if (IS_ERR(bpmp)) 246 return PTR_ERR(bpmp); 247 248 data->regs = devm_platform_ioremap_resource(pdev, 0); 249 if (IS_ERR(data->regs)) { 250 err = PTR_ERR(data->regs); 251 goto put_bpmp; 252 } 253 254 for (i = 0; i < TEGRA186_NUM_CLUSTERS; i++) { 255 struct tegra186_cpufreq_cluster *cluster = &data->clusters[i]; 256 257 cluster->table = init_vhint_table(pdev, bpmp, cluster, i, &num_rates); 258 if (IS_ERR(cluster->table)) { 259 err = PTR_ERR(cluster->table); 260 goto put_bpmp; 261 } else if (!num_rates) { 262 err = -EINVAL; 263 goto put_bpmp; 264 } 265 266 for (cpu = 0; cpu < ARRAY_SIZE(tegra186_cpus); cpu++) { 267 if (data->cpus[cpu].bpmp_cluster_id == i) { 268 edvd_val = cluster->table[num_rates - 1].driver_data; 269 edvd_offset = data->cpus[cpu].edvd_offset; 270 writel(edvd_val, data->regs + edvd_offset); 271 } 272 } 273 } 274 275 tegra186_cpufreq_driver.driver_data = data; 276 277 err = cpufreq_register_driver(&tegra186_cpufreq_driver); 278 279 put_bpmp: 280 tegra_bpmp_put(bpmp); 281 282 return err; 283 } 284 285 static void tegra186_cpufreq_remove(struct platform_device *pdev) 286 { 287 cpufreq_unregister_driver(&tegra186_cpufreq_driver); 288 } 289 290 static const struct of_device_id tegra186_cpufreq_of_match[] = { 291 { .compatible = "nvidia,tegra186-ccplex-cluster", }, 292 { } 293 }; 294 MODULE_DEVICE_TABLE(of, tegra186_cpufreq_of_match); 295 296 static struct platform_driver tegra186_cpufreq_platform_driver = { 297 .driver = { 298 .name = "tegra186-cpufreq", 299 .of_match_table = tegra186_cpufreq_of_match, 300 }, 301 .probe = tegra186_cpufreq_probe, 302 .remove = tegra186_cpufreq_remove, 303 }; 304 module_platform_driver(tegra186_cpufreq_platform_driver); 305 306 MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>"); 307 MODULE_DESCRIPTION("NVIDIA Tegra186 cpufreq driver"); 308 MODULE_LICENSE("GPL v2"); 309