1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved 4 */ 5 6 #include <linux/cpufreq.h> 7 #include <linux/dma-mapping.h> 8 #include <linux/module.h> 9 #include <linux/of.h> 10 #include <linux/platform_device.h> 11 12 #include <soc/tegra/bpmp.h> 13 #include <soc/tegra/bpmp-abi.h> 14 15 #define TEGRA186_NUM_CLUSTERS 2 16 #define EDVD_OFFSET_A57(core) ((SZ_64K * 6) + (0x20 + (core) * 0x4)) 17 #define EDVD_OFFSET_DENVER(core) ((SZ_64K * 7) + (0x20 + (core) * 0x4)) 18 #define EDVD_CORE_VOLT_FREQ_F_SHIFT 0 19 #define EDVD_CORE_VOLT_FREQ_F_MASK 0xffff 20 #define EDVD_CORE_VOLT_FREQ_V_SHIFT 16 21 22 struct tegra186_cpufreq_cpu { 23 unsigned int bpmp_cluster_id; 24 unsigned int edvd_offset; 25 }; 26 27 static const struct tegra186_cpufreq_cpu tegra186_cpus[] = { 28 /* CPU0 - A57 Cluster */ 29 { 30 .bpmp_cluster_id = 1, 31 .edvd_offset = EDVD_OFFSET_A57(0) 32 }, 33 /* CPU1 - Denver Cluster */ 34 { 35 .bpmp_cluster_id = 0, 36 .edvd_offset = EDVD_OFFSET_DENVER(0) 37 }, 38 /* CPU2 - Denver Cluster */ 39 { 40 .bpmp_cluster_id = 0, 41 .edvd_offset = EDVD_OFFSET_DENVER(1) 42 }, 43 /* CPU3 - A57 Cluster */ 44 { 45 .bpmp_cluster_id = 1, 46 .edvd_offset = EDVD_OFFSET_A57(1) 47 }, 48 /* CPU4 - A57 Cluster */ 49 { 50 .bpmp_cluster_id = 1, 51 .edvd_offset = EDVD_OFFSET_A57(2) 52 }, 53 /* CPU5 - A57 Cluster */ 54 { 55 .bpmp_cluster_id = 1, 56 .edvd_offset = EDVD_OFFSET_A57(3) 57 }, 58 }; 59 60 struct tegra186_cpufreq_cluster { 61 struct cpufreq_frequency_table *table; 62 u32 ref_clk_khz; 63 u32 div; 64 }; 65 66 struct tegra186_cpufreq_data { 67 void __iomem *regs; 68 const struct tegra186_cpufreq_cpu *cpus; 69 struct tegra186_cpufreq_cluster clusters[]; 70 }; 71 72 static int tegra186_cpufreq_init(struct cpufreq_policy *policy) 73 { 74 struct tegra186_cpufreq_data *data = cpufreq_get_driver_data(); 75 unsigned int cluster = data->cpus[policy->cpu].bpmp_cluster_id; 76 u32 cpu; 77 78 policy->freq_table = data->clusters[cluster].table; 79 policy->cpuinfo.transition_latency = 300 * 1000; 80 policy->driver_data = NULL; 81 82 /* set same policy for all cpus in a cluster */ 83 for (cpu = 0; cpu < ARRAY_SIZE(tegra186_cpus); cpu++) { 84 if (data->cpus[cpu].bpmp_cluster_id == cluster) 85 cpumask_set_cpu(cpu, policy->cpus); 86 } 87 88 return 0; 89 } 90 91 static int tegra186_cpufreq_set_target(struct cpufreq_policy *policy, 92 unsigned int index) 93 { 94 struct tegra186_cpufreq_data *data = cpufreq_get_driver_data(); 95 struct cpufreq_frequency_table *tbl = policy->freq_table + index; 96 unsigned int edvd_offset = data->cpus[policy->cpu].edvd_offset; 97 u32 edvd_val = tbl->driver_data; 98 99 writel(edvd_val, data->regs + edvd_offset); 100 101 return 0; 102 } 103 104 static unsigned int tegra186_cpufreq_get(unsigned int cpu) 105 { 106 struct cpufreq_policy *policy __free(put_cpufreq_policy) = cpufreq_cpu_get(cpu); 107 struct tegra186_cpufreq_data *data = cpufreq_get_driver_data(); 108 struct tegra186_cpufreq_cluster *cluster; 109 unsigned int edvd_offset, cluster_id; 110 u32 ndiv; 111 112 if (!policy) 113 return 0; 114 115 edvd_offset = data->cpus[policy->cpu].edvd_offset; 116 ndiv = readl(data->regs + edvd_offset) & EDVD_CORE_VOLT_FREQ_F_MASK; 117 cluster_id = data->cpus[policy->cpu].bpmp_cluster_id; 118 cluster = &data->clusters[cluster_id]; 119 120 return (cluster->ref_clk_khz * ndiv) / cluster->div; 121 } 122 123 static struct cpufreq_driver tegra186_cpufreq_driver = { 124 .name = "tegra186", 125 .flags = CPUFREQ_HAVE_GOVERNOR_PER_POLICY | 126 CPUFREQ_NEED_INITIAL_FREQ_CHECK, 127 .get = tegra186_cpufreq_get, 128 .verify = cpufreq_generic_frequency_table_verify, 129 .target_index = tegra186_cpufreq_set_target, 130 .init = tegra186_cpufreq_init, 131 }; 132 133 static struct cpufreq_frequency_table *init_vhint_table( 134 struct platform_device *pdev, struct tegra_bpmp *bpmp, 135 struct tegra186_cpufreq_cluster *cluster, unsigned int cluster_id) 136 { 137 struct cpufreq_frequency_table *table; 138 struct mrq_cpu_vhint_request req; 139 struct tegra_bpmp_message msg; 140 struct cpu_vhint_data *data; 141 int err, i, j, num_rates = 0; 142 dma_addr_t phys; 143 void *virt; 144 145 virt = dma_alloc_coherent(bpmp->dev, sizeof(*data), &phys, 146 GFP_KERNEL); 147 if (!virt) 148 return ERR_PTR(-ENOMEM); 149 150 data = (struct cpu_vhint_data *)virt; 151 152 memset(&req, 0, sizeof(req)); 153 req.addr = phys; 154 req.cluster_id = cluster_id; 155 156 memset(&msg, 0, sizeof(msg)); 157 msg.mrq = MRQ_CPU_VHINT; 158 msg.tx.data = &req; 159 msg.tx.size = sizeof(req); 160 161 err = tegra_bpmp_transfer(bpmp, &msg); 162 if (err) { 163 table = ERR_PTR(err); 164 goto free; 165 } 166 if (msg.rx.ret) { 167 table = ERR_PTR(-EINVAL); 168 goto free; 169 } 170 171 for (i = data->vfloor; i <= data->vceil; i++) { 172 u16 ndiv = data->ndiv[i]; 173 174 if (ndiv < data->ndiv_min || ndiv > data->ndiv_max) 175 continue; 176 177 /* Only store lowest voltage index for each rate */ 178 if (i > 0 && ndiv == data->ndiv[i - 1]) 179 continue; 180 181 num_rates++; 182 } 183 184 table = devm_kcalloc(&pdev->dev, num_rates + 1, sizeof(*table), 185 GFP_KERNEL); 186 if (!table) { 187 table = ERR_PTR(-ENOMEM); 188 goto free; 189 } 190 191 cluster->ref_clk_khz = data->ref_clk_hz / 1000; 192 cluster->div = data->pdiv * data->mdiv; 193 194 for (i = data->vfloor, j = 0; i <= data->vceil; i++) { 195 struct cpufreq_frequency_table *point; 196 u16 ndiv = data->ndiv[i]; 197 u32 edvd_val = 0; 198 199 if (ndiv < data->ndiv_min || ndiv > data->ndiv_max) 200 continue; 201 202 /* Only store lowest voltage index for each rate */ 203 if (i > 0 && ndiv == data->ndiv[i - 1]) 204 continue; 205 206 edvd_val |= i << EDVD_CORE_VOLT_FREQ_V_SHIFT; 207 edvd_val |= ndiv << EDVD_CORE_VOLT_FREQ_F_SHIFT; 208 209 point = &table[j++]; 210 point->driver_data = edvd_val; 211 point->frequency = (cluster->ref_clk_khz * ndiv) / cluster->div; 212 } 213 214 table[j].frequency = CPUFREQ_TABLE_END; 215 216 free: 217 dma_free_coherent(bpmp->dev, sizeof(*data), virt, phys); 218 219 return table; 220 } 221 222 static int tegra186_cpufreq_probe(struct platform_device *pdev) 223 { 224 struct tegra186_cpufreq_data *data; 225 struct tegra_bpmp *bpmp; 226 unsigned int i = 0, err; 227 228 data = devm_kzalloc(&pdev->dev, 229 struct_size(data, clusters, TEGRA186_NUM_CLUSTERS), 230 GFP_KERNEL); 231 if (!data) 232 return -ENOMEM; 233 234 data->cpus = tegra186_cpus; 235 236 bpmp = tegra_bpmp_get(&pdev->dev); 237 if (IS_ERR(bpmp)) 238 return PTR_ERR(bpmp); 239 240 data->regs = devm_platform_ioremap_resource(pdev, 0); 241 if (IS_ERR(data->regs)) { 242 err = PTR_ERR(data->regs); 243 goto put_bpmp; 244 } 245 246 for (i = 0; i < TEGRA186_NUM_CLUSTERS; i++) { 247 struct tegra186_cpufreq_cluster *cluster = &data->clusters[i]; 248 249 cluster->table = init_vhint_table(pdev, bpmp, cluster, i); 250 if (IS_ERR(cluster->table)) { 251 err = PTR_ERR(cluster->table); 252 goto put_bpmp; 253 } 254 } 255 256 tegra186_cpufreq_driver.driver_data = data; 257 258 err = cpufreq_register_driver(&tegra186_cpufreq_driver); 259 260 put_bpmp: 261 tegra_bpmp_put(bpmp); 262 263 return err; 264 } 265 266 static void tegra186_cpufreq_remove(struct platform_device *pdev) 267 { 268 cpufreq_unregister_driver(&tegra186_cpufreq_driver); 269 } 270 271 static const struct of_device_id tegra186_cpufreq_of_match[] = { 272 { .compatible = "nvidia,tegra186-ccplex-cluster", }, 273 { } 274 }; 275 MODULE_DEVICE_TABLE(of, tegra186_cpufreq_of_match); 276 277 static struct platform_driver tegra186_cpufreq_platform_driver = { 278 .driver = { 279 .name = "tegra186-cpufreq", 280 .of_match_table = tegra186_cpufreq_of_match, 281 }, 282 .probe = tegra186_cpufreq_probe, 283 .remove = tegra186_cpufreq_remove, 284 }; 285 module_platform_driver(tegra186_cpufreq_platform_driver); 286 287 MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>"); 288 MODULE_DESCRIPTION("NVIDIA Tegra186 cpufreq driver"); 289 MODULE_LICENSE("GPL v2"); 290