1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de> 4 * 5 * Library for common functions for Intel SpeedStep v.1 and v.2 support 6 * 7 * BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous* 8 */ 9 10 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 11 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/moduleparam.h> 15 #include <linux/init.h> 16 #include <linux/cpufreq.h> 17 18 #include <asm/cpuid/api.h> 19 #include <asm/msr.h> 20 #include <asm/tsc.h> 21 #include "speedstep-lib.h" 22 23 #define PFX "speedstep-lib: " 24 25 #ifdef CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK 26 static int relaxed_check; 27 #else 28 #define relaxed_check 0 29 #endif 30 31 /********************************************************************* 32 * GET PROCESSOR CORE SPEED IN KHZ * 33 *********************************************************************/ 34 35 static unsigned int pentium3_get_frequency(enum speedstep_processor processor) 36 { 37 /* See table 14 of p3_ds.pdf and table 22 of 29834003.pdf */ 38 static const struct { 39 unsigned int ratio; /* Frequency Multiplier (x10) */ 40 u8 bitmap; /* power on configuration bits 41 [27, 25:22] (in MSR 0x2a) */ 42 } msr_decode_mult[] = { 43 { 30, 0x01 }, 44 { 35, 0x05 }, 45 { 40, 0x02 }, 46 { 45, 0x06 }, 47 { 50, 0x00 }, 48 { 55, 0x04 }, 49 { 60, 0x0b }, 50 { 65, 0x0f }, 51 { 70, 0x09 }, 52 { 75, 0x0d }, 53 { 80, 0x0a }, 54 { 85, 0x26 }, 55 { 90, 0x20 }, 56 { 100, 0x2b }, 57 { 0, 0xff } /* error or unknown value */ 58 }; 59 60 /* PIII(-M) FSB settings: see table b1-b of 24547206.pdf */ 61 static const struct { 62 unsigned int value; /* Front Side Bus speed in MHz */ 63 u8 bitmap; /* power on configuration bits [18: 19] 64 (in MSR 0x2a) */ 65 } msr_decode_fsb[] = { 66 { 66, 0x0 }, 67 { 100, 0x2 }, 68 { 133, 0x1 }, 69 { 0, 0xff} 70 }; 71 72 struct msr msr; 73 u32 msr_lo, msr_tmp; 74 int i = 0, j = 0; 75 76 /* read MSR 0x2a - we only need the low 32 bits */ 77 rdmsrq(MSR_IA32_EBL_CR_POWERON, msr.q); 78 pr_debug("P3 - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr.l, msr.h); 79 msr_tmp = msr_lo = msr.l; 80 81 /* decode the FSB */ 82 msr_tmp &= 0x00c0000; 83 msr_tmp >>= 18; 84 while (msr_tmp != msr_decode_fsb[i].bitmap) { 85 if (msr_decode_fsb[i].bitmap == 0xff) 86 return 0; 87 i++; 88 } 89 90 /* decode the multiplier */ 91 if (processor == SPEEDSTEP_CPU_PIII_C_EARLY) { 92 pr_debug("workaround for early PIIIs\n"); 93 msr_lo &= 0x03c00000; 94 } else 95 msr_lo &= 0x0bc00000; 96 msr_lo >>= 22; 97 while (msr_lo != msr_decode_mult[j].bitmap) { 98 if (msr_decode_mult[j].bitmap == 0xff) 99 return 0; 100 j++; 101 } 102 103 pr_debug("speed is %u\n", 104 (msr_decode_mult[j].ratio * msr_decode_fsb[i].value * 100)); 105 106 return msr_decode_mult[j].ratio * msr_decode_fsb[i].value * 100; 107 } 108 109 110 static unsigned int pentiumM_get_frequency(void) 111 { 112 struct msr msr; 113 u32 msr_tmp; 114 115 rdmsrq(MSR_IA32_EBL_CR_POWERON, msr.q); 116 pr_debug("PM - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr.l, msr.h); 117 118 /* see table B-2 of 24547212.pdf */ 119 if (msr.l & 0x00040000) { 120 printk(KERN_DEBUG PFX "PM - invalid FSB: 0x%x 0x%x\n", 121 msr.l, msr.h); 122 return 0; 123 } 124 125 msr_tmp = (msr.l >> 22) & 0x1f; 126 pr_debug("bits 22-26 are 0x%x, speed is %u\n", 127 msr_tmp, (msr_tmp * 100 * 1000)); 128 129 return msr_tmp * 100 * 1000; 130 } 131 132 static unsigned int pentium_core_get_frequency(void) 133 { 134 struct msr msr; 135 u32 fsb = 0; 136 u32 msr_tmp; 137 int ret; 138 139 rdmsrq(MSR_FSB_FREQ, msr.q); 140 /* see table B-2 of 25366920.pdf */ 141 switch (msr.l & 0x07) { 142 case 5: 143 fsb = 100000; 144 break; 145 case 1: 146 fsb = 133333; 147 break; 148 case 3: 149 fsb = 166667; 150 break; 151 case 2: 152 fsb = 200000; 153 break; 154 case 0: 155 fsb = 266667; 156 break; 157 case 4: 158 fsb = 333333; 159 break; 160 default: 161 pr_err("PCORE - MSR_FSB_FREQ undefined value\n"); 162 } 163 164 rdmsrq(MSR_IA32_EBL_CR_POWERON, msr.q); 165 pr_debug("PCORE - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", 166 msr.l, msr.h); 167 168 msr_tmp = (msr.l >> 22) & 0x1f; 169 pr_debug("bits 22-26 are 0x%x, speed is %u\n", 170 msr_tmp, (msr_tmp * fsb)); 171 172 ret = (msr_tmp * fsb); 173 return ret; 174 } 175 176 177 static unsigned int pentium4_get_frequency(void) 178 { 179 struct cpuinfo_x86 *c = &boot_cpu_data; 180 struct msr msr; 181 u32 mult; 182 unsigned int fsb = 0; 183 unsigned int ret; 184 u8 fsb_code; 185 186 /* Pentium 4 Model 0 and 1 do not have the Core Clock Frequency 187 * to System Bus Frequency Ratio Field in the Processor Frequency 188 * Configuration Register of the MSR. Therefore the current 189 * frequency cannot be calculated and has to be measured. 190 */ 191 if (c->x86_model < 2) 192 return cpu_khz; 193 194 rdmsrq(0x2c, msr.q); 195 196 pr_debug("P4 - MSR_EBC_FREQUENCY_ID: 0x%x 0x%x\n", msr.l, msr.h); 197 198 /* decode the FSB: see IA-32 Intel (C) Architecture Software 199 * Developer's Manual, Volume 3: System Prgramming Guide, 200 * revision #12 in Table B-1: MSRs in the Pentium 4 and 201 * Intel Xeon Processors, on page B-4 and B-5. 202 */ 203 fsb_code = (msr.l >> 16) & 0x7; 204 switch (fsb_code) { 205 case 0: 206 fsb = 100 * 1000; 207 break; 208 case 1: 209 fsb = 13333 * 10; 210 break; 211 case 2: 212 fsb = 200 * 1000; 213 break; 214 } 215 216 if (!fsb) 217 printk(KERN_DEBUG PFX "couldn't detect FSB speed. " 218 "Please send an e-mail to <linux@brodo.de>\n"); 219 220 /* Multiplier. */ 221 mult = msr.l >> 24; 222 223 pr_debug("P4 - FSB %u kHz; Multiplier %u; Speed %u kHz\n", 224 fsb, mult, (fsb * mult)); 225 226 ret = (fsb * mult); 227 return ret; 228 } 229 230 231 /* Warning: may get called from smp_call_function_single. */ 232 unsigned int speedstep_get_frequency(enum speedstep_processor processor) 233 { 234 switch (processor) { 235 case SPEEDSTEP_CPU_PCORE: 236 return pentium_core_get_frequency(); 237 case SPEEDSTEP_CPU_PM: 238 return pentiumM_get_frequency(); 239 case SPEEDSTEP_CPU_P4D: 240 case SPEEDSTEP_CPU_P4M: 241 return pentium4_get_frequency(); 242 case SPEEDSTEP_CPU_PIII_T: 243 case SPEEDSTEP_CPU_PIII_C: 244 case SPEEDSTEP_CPU_PIII_C_EARLY: 245 return pentium3_get_frequency(processor); 246 default: 247 return 0; 248 } 249 return 0; 250 } 251 EXPORT_SYMBOL_GPL(speedstep_get_frequency); 252 253 254 /********************************************************************* 255 * DETECT SPEEDSTEP-CAPABLE PROCESSOR * 256 *********************************************************************/ 257 258 /* Keep in sync with the x86_cpu_id tables in the different modules */ 259 enum speedstep_processor speedstep_detect_processor(void) 260 { 261 struct cpuinfo_x86 *c = &cpu_data(0); 262 struct msr msr; 263 u32 ebx; 264 265 pr_debug("x86: %x, model: %x\n", c->x86, c->x86_model); 266 267 if ((c->x86_vendor != X86_VENDOR_INTEL) || 268 ((c->x86 != 6) && (c->x86 != 0xF))) 269 return 0; 270 271 if (c->x86 == 0xF) { 272 /* Intel Mobile Pentium 4-M 273 * or Intel Mobile Pentium 4 with 533 MHz FSB */ 274 if (c->x86_model != 2) 275 return 0; 276 277 ebx = cpuid_ebx(0x00000001); 278 ebx &= 0x000000FF; 279 280 pr_debug("ebx value is %x, x86_stepping is %x\n", ebx, c->x86_stepping); 281 282 switch (c->x86_stepping) { 283 case 4: 284 /* 285 * B-stepping [M-P4-M] 286 * sample has ebx = 0x0f, production has 0x0e. 287 */ 288 if ((ebx == 0x0e) || (ebx == 0x0f)) 289 return SPEEDSTEP_CPU_P4M; 290 break; 291 case 7: 292 /* 293 * C-stepping [M-P4-M] 294 * needs to have ebx=0x0e, else it's a celeron: 295 * cf. 25130917.pdf / page 7, footnote 5 even 296 * though 25072120.pdf / page 7 doesn't say 297 * samples are only of B-stepping... 298 */ 299 if (ebx == 0x0e) 300 return SPEEDSTEP_CPU_P4M; 301 break; 302 case 9: 303 /* 304 * D-stepping [M-P4-M or M-P4/533] 305 * 306 * this is totally strange: CPUID 0x0F29 is 307 * used by M-P4-M, M-P4/533 and(!) Celeron CPUs. 308 * The latter need to be sorted out as they don't 309 * support speedstep. 310 * Celerons with CPUID 0x0F29 may have either 311 * ebx=0x8 or 0xf -- 25130917.pdf doesn't say anything 312 * specific. 313 * M-P4-Ms may have either ebx=0xe or 0xf [see above] 314 * M-P4/533 have either ebx=0xe or 0xf. [25317607.pdf] 315 * also, M-P4M HTs have ebx=0x8, too 316 * For now, they are distinguished by the model_id 317 * string 318 */ 319 if ((ebx == 0x0e) || 320 (strstr(c->x86_model_id, 321 "Mobile Intel(R) Pentium(R) 4") != NULL)) 322 return SPEEDSTEP_CPU_P4M; 323 break; 324 default: 325 break; 326 } 327 return 0; 328 } 329 330 switch (c->x86_model) { 331 case 0x0B: /* Intel PIII [Tualatin] */ 332 /* cpuid_ebx(1) is 0x04 for desktop PIII, 333 * 0x06 for mobile PIII-M */ 334 ebx = cpuid_ebx(0x00000001); 335 pr_debug("ebx is %x\n", ebx); 336 337 ebx &= 0x000000FF; 338 339 if (ebx != 0x06) 340 return 0; 341 342 /* So far all PIII-M processors support SpeedStep. See 343 * Intel's 24540640.pdf of June 2003 344 */ 345 return SPEEDSTEP_CPU_PIII_T; 346 347 case 0x08: /* Intel PIII [Coppermine] */ 348 349 /* all mobile PIII Coppermines have FSB 100 MHz 350 * ==> sort out a few desktop PIIIs. */ 351 rdmsrq(MSR_IA32_EBL_CR_POWERON, msr.q); 352 pr_debug("Coppermine: MSR_IA32_EBL_CR_POWERON is 0x%x, 0x%x\n", 353 msr.l, msr.h); 354 msr.l &= 0x00c0000; 355 if (msr.l != 0x0080000) 356 return 0; 357 358 /* 359 * If the processor is a mobile version, 360 * platform ID has bit 50 set 361 * it has SpeedStep technology if either 362 * bit 56 or 57 is set 363 */ 364 rdmsrq(MSR_IA32_PLATFORM_ID, msr.q); 365 pr_debug("Coppermine: MSR_IA32_PLATFORM ID is 0x%x, 0x%x\n", 366 msr.l, msr.h); 367 if ((msr.h & (1<<18)) && 368 (relaxed_check ? 1 : (msr.h & (3<<24)))) { 369 if (c->x86_stepping == 0x01) { 370 pr_debug("early PIII version\n"); 371 return SPEEDSTEP_CPU_PIII_C_EARLY; 372 } else 373 return SPEEDSTEP_CPU_PIII_C; 374 } 375 fallthrough; 376 default: 377 return 0; 378 } 379 } 380 EXPORT_SYMBOL_GPL(speedstep_detect_processor); 381 382 383 /********************************************************************* 384 * DETECT SPEEDSTEP SPEEDS * 385 *********************************************************************/ 386 387 int speedstep_get_freqs(enum speedstep_processor processor, 388 unsigned int *low_speed, 389 unsigned int *high_speed, 390 unsigned int *transition_latency, 391 void (*set_state)(unsigned int state)) 392 { 393 unsigned int prev_speed; 394 unsigned long flags; 395 ktime_t tv1, tv2; 396 int ret = 0; 397 398 if ((!processor) || (!low_speed) || (!high_speed) || (!set_state)) 399 return -EINVAL; 400 401 pr_debug("trying to determine both speeds\n"); 402 403 /* get current speed */ 404 prev_speed = speedstep_get_frequency(processor); 405 if (!prev_speed) 406 return -EIO; 407 408 pr_debug("previous speed is %u\n", prev_speed); 409 410 preempt_disable(); 411 local_irq_save(flags); 412 413 /* switch to low state */ 414 set_state(SPEEDSTEP_LOW); 415 *low_speed = speedstep_get_frequency(processor); 416 if (!*low_speed) { 417 ret = -EIO; 418 goto out; 419 } 420 421 pr_debug("low speed is %u\n", *low_speed); 422 423 /* start latency measurement */ 424 if (transition_latency) 425 tv1 = ktime_get(); 426 427 /* switch to high state */ 428 set_state(SPEEDSTEP_HIGH); 429 430 /* end latency measurement */ 431 if (transition_latency) 432 tv2 = ktime_get(); 433 434 *high_speed = speedstep_get_frequency(processor); 435 if (!*high_speed) { 436 ret = -EIO; 437 goto out; 438 } 439 440 pr_debug("high speed is %u\n", *high_speed); 441 442 if (*low_speed == *high_speed) { 443 ret = -ENODEV; 444 goto out; 445 } 446 447 /* switch to previous state, if necessary */ 448 if (*high_speed != prev_speed) 449 set_state(SPEEDSTEP_LOW); 450 451 if (transition_latency) { 452 *transition_latency = ktime_to_us(ktime_sub(tv2, tv1)); 453 pr_debug("transition latency is %u uSec\n", *transition_latency); 454 455 /* convert uSec to nSec and add 20% for safety reasons */ 456 *transition_latency *= 1200; 457 458 /* check if the latency measurement is too high or too low 459 * and set it to a safe value (500uSec) in that case 460 */ 461 if (*transition_latency > 10000000 || 462 *transition_latency < 50000) { 463 pr_warn("frequency transition measured seems out of range (%u nSec), falling back to a safe one of %u nSec\n", 464 *transition_latency, 500000); 465 *transition_latency = 500000; 466 } 467 } 468 469 out: 470 local_irq_restore(flags); 471 preempt_enable(); 472 473 return ret; 474 } 475 EXPORT_SYMBOL_GPL(speedstep_get_freqs); 476 477 #ifdef CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK 478 module_param(relaxed_check, int, 0444); 479 MODULE_PARM_DESC(relaxed_check, 480 "Don't do all checks for speedstep capability."); 481 #endif 482 483 MODULE_AUTHOR("Dominik Brodowski <linux@brodo.de>"); 484 MODULE_DESCRIPTION("Library for Intel SpeedStep 1 or 2 cpufreq drivers."); 485 MODULE_LICENSE("GPL"); 486