1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright 2009 Wolfson Microelectronics plc 4 * 5 * S3C64xx CPUfreq Support 6 */ 7 8 #define pr_fmt(fmt) "cpufreq: " fmt 9 10 #include <linux/kernel.h> 11 #include <linux/types.h> 12 #include <linux/init.h> 13 #include <linux/cpufreq.h> 14 #include <linux/clk.h> 15 #include <linux/err.h> 16 #include <linux/regulator/consumer.h> 17 #include <linux/module.h> 18 19 static struct regulator *vddarm; 20 static unsigned long regulator_latency; 21 22 struct s3c64xx_dvfs { 23 unsigned int vddarm_min; 24 unsigned int vddarm_max; 25 }; 26 27 #ifdef CONFIG_REGULATOR 28 static struct s3c64xx_dvfs s3c64xx_dvfs_table[] = { 29 [0] = { 1000000, 1150000 }, 30 [1] = { 1050000, 1150000 }, 31 [2] = { 1100000, 1150000 }, 32 [3] = { 1200000, 1350000 }, 33 [4] = { 1300000, 1350000 }, 34 }; 35 #endif 36 37 static struct cpufreq_frequency_table s3c64xx_freq_table[] = { 38 { 0, 0, 66000 }, 39 { 0, 0, 100000 }, 40 { 0, 0, 133000 }, 41 { 0, 1, 200000 }, 42 { 0, 1, 222000 }, 43 { 0, 1, 266000 }, 44 { 0, 2, 333000 }, 45 { 0, 2, 400000 }, 46 { 0, 2, 532000 }, 47 { 0, 2, 533000 }, 48 { 0, 3, 667000 }, 49 { 0, 4, 800000 }, 50 { 0, 0, CPUFREQ_TABLE_END }, 51 }; 52 53 static int s3c64xx_cpufreq_set_target(struct cpufreq_policy *policy, 54 unsigned int index) 55 { 56 unsigned int new_freq = s3c64xx_freq_table[index].frequency; 57 int ret; 58 59 #ifdef CONFIG_REGULATOR 60 struct s3c64xx_dvfs *dvfs; 61 unsigned int old_freq; 62 63 old_freq = clk_get_rate(policy->clk) / 1000; 64 dvfs = &s3c64xx_dvfs_table[s3c64xx_freq_table[index].driver_data]; 65 66 if (vddarm && new_freq > old_freq) { 67 ret = regulator_set_voltage(vddarm, 68 dvfs->vddarm_min, 69 dvfs->vddarm_max); 70 if (ret != 0) { 71 pr_err("Failed to set VDDARM for %dkHz: %d\n", 72 new_freq, ret); 73 return ret; 74 } 75 } 76 #endif 77 78 ret = clk_set_rate(policy->clk, new_freq * 1000); 79 if (ret < 0) { 80 pr_err("Failed to set rate %dkHz: %d\n", 81 new_freq, ret); 82 return ret; 83 } 84 85 #ifdef CONFIG_REGULATOR 86 if (vddarm && new_freq < old_freq) { 87 ret = regulator_set_voltage(vddarm, 88 dvfs->vddarm_min, 89 dvfs->vddarm_max); 90 if (ret != 0) { 91 pr_err("Failed to set VDDARM for %dkHz: %d\n", 92 new_freq, ret); 93 if (clk_set_rate(policy->clk, old_freq * 1000) < 0) 94 pr_err("Failed to restore original clock rate\n"); 95 96 return ret; 97 } 98 } 99 #endif 100 101 pr_debug("Set actual frequency %lukHz\n", 102 clk_get_rate(policy->clk) / 1000); 103 104 return 0; 105 } 106 107 #ifdef CONFIG_REGULATOR 108 static void s3c64xx_cpufreq_config_regulator(void) 109 { 110 int count, v, i, found; 111 struct cpufreq_frequency_table *freq; 112 struct s3c64xx_dvfs *dvfs; 113 114 count = regulator_count_voltages(vddarm); 115 if (count < 0) { 116 pr_err("Unable to check supported voltages\n"); 117 } 118 119 if (!count) 120 goto out; 121 122 cpufreq_for_each_valid_entry(freq, s3c64xx_freq_table) { 123 dvfs = &s3c64xx_dvfs_table[freq->driver_data]; 124 found = 0; 125 126 for (i = 0; i < count; i++) { 127 v = regulator_list_voltage(vddarm, i); 128 if (v >= dvfs->vddarm_min && v <= dvfs->vddarm_max) 129 found = 1; 130 } 131 132 if (!found) { 133 pr_debug("%dkHz unsupported by regulator\n", 134 freq->frequency); 135 freq->frequency = CPUFREQ_ENTRY_INVALID; 136 } 137 } 138 139 out: 140 /* Guess based on having to do an I2C/SPI write; in future we 141 * will be able to query the regulator performance here. */ 142 regulator_latency = 1 * 1000 * 1000; 143 } 144 #endif 145 146 static int s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy) 147 { 148 struct cpufreq_frequency_table *freq; 149 150 if (policy->cpu != 0) 151 return -EINVAL; 152 153 policy->clk = clk_get(NULL, "armclk"); 154 if (IS_ERR(policy->clk)) { 155 pr_err("Unable to obtain ARMCLK: %ld\n", 156 PTR_ERR(policy->clk)); 157 return PTR_ERR(policy->clk); 158 } 159 160 #ifdef CONFIG_REGULATOR 161 vddarm = regulator_get(NULL, "vddarm"); 162 if (IS_ERR(vddarm)) { 163 pr_err("Failed to obtain VDDARM: %ld\n", PTR_ERR(vddarm)); 164 pr_err("Only frequency scaling available\n"); 165 vddarm = NULL; 166 } else { 167 s3c64xx_cpufreq_config_regulator(); 168 } 169 #endif 170 171 cpufreq_for_each_entry(freq, s3c64xx_freq_table) { 172 unsigned long r; 173 174 /* Check for frequencies we can generate */ 175 r = clk_round_rate(policy->clk, freq->frequency * 1000); 176 r /= 1000; 177 if (r != freq->frequency) { 178 pr_debug("%dkHz unsupported by clock\n", 179 freq->frequency); 180 freq->frequency = CPUFREQ_ENTRY_INVALID; 181 } 182 183 /* If we have no regulator then assume startup 184 * frequency is the maximum we can support. */ 185 if (!vddarm && freq->frequency > clk_get_rate(policy->clk) / 1000) 186 freq->frequency = CPUFREQ_ENTRY_INVALID; 187 } 188 189 /* Datasheet says PLL stabalisation time (if we were to use 190 * the PLLs, which we don't currently) is ~300us worst case, 191 * but add some fudge. 192 */ 193 cpufreq_generic_init(policy, s3c64xx_freq_table, 194 (500 * 1000) + regulator_latency); 195 return 0; 196 } 197 198 static struct cpufreq_driver s3c64xx_cpufreq_driver = { 199 .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK, 200 .verify = cpufreq_generic_frequency_table_verify, 201 .target_index = s3c64xx_cpufreq_set_target, 202 .get = cpufreq_generic_get, 203 .init = s3c64xx_cpufreq_driver_init, 204 .name = "s3c", 205 }; 206 207 static int __init s3c64xx_cpufreq_init(void) 208 { 209 return cpufreq_register_driver(&s3c64xx_cpufreq_driver); 210 } 211 module_init(s3c64xx_cpufreq_init); 212