1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 4 */ 5 6 /* 7 * In Certain QCOM SoCs like apq8096 and msm8996 that have KRYO processors, 8 * the CPU frequency subset and voltage value of each OPP varies 9 * based on the silicon variant in use. Qualcomm Process Voltage Scaling Tables 10 * defines the voltage and frequency value based on the msm-id in SMEM 11 * and speedbin blown in the efuse combination. 12 * The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC 13 * to provide the OPP framework with required information. 14 * This is used to determine the voltage and frequency value for each OPP of 15 * operating-points-v2 table when it is parsed by the OPP framework. 16 */ 17 18 #include <linux/cpu.h> 19 #include <linux/err.h> 20 #include <linux/init.h> 21 #include <linux/kernel.h> 22 #include <linux/module.h> 23 #include <linux/nvmem-consumer.h> 24 #include <linux/of.h> 25 #include <linux/platform_device.h> 26 #include <linux/pm.h> 27 #include <linux/pm_domain.h> 28 #include <linux/pm_opp.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/slab.h> 31 #include <linux/soc/qcom/smem.h> 32 33 #include <dt-bindings/arm/qcom,ids.h> 34 35 enum ipq806x_versions { 36 IPQ8062_VERSION = 0, 37 IPQ8064_VERSION, 38 IPQ8065_VERSION, 39 }; 40 41 #define IPQ6000_VERSION BIT(2) 42 43 enum ipq8074_versions { 44 IPQ8074_HAWKEYE_VERSION = 0, 45 IPQ8074_ACORN_VERSION, 46 }; 47 48 struct qcom_cpufreq_drv; 49 50 struct qcom_cpufreq_match_data { 51 int (*get_version)(struct device *cpu_dev, 52 struct nvmem_cell *speedbin_nvmem, 53 char **pvs_name, 54 struct qcom_cpufreq_drv *drv); 55 const char **pd_names; 56 unsigned int num_pd_names; 57 }; 58 59 struct qcom_cpufreq_drv_cpu { 60 int opp_token; 61 struct dev_pm_domain_list *pd_list; 62 }; 63 64 struct qcom_cpufreq_drv { 65 u32 versions; 66 const struct qcom_cpufreq_match_data *data; 67 struct qcom_cpufreq_drv_cpu cpus[]; 68 }; 69 70 static struct platform_device *cpufreq_dt_pdev, *cpufreq_pdev; 71 72 static int qcom_cpufreq_simple_get_version(struct device *cpu_dev, 73 struct nvmem_cell *speedbin_nvmem, 74 char **pvs_name, 75 struct qcom_cpufreq_drv *drv) 76 { 77 u8 *speedbin; 78 79 *pvs_name = NULL; 80 speedbin = nvmem_cell_read(speedbin_nvmem, NULL); 81 if (IS_ERR(speedbin)) 82 return PTR_ERR(speedbin); 83 84 dev_dbg(cpu_dev, "speedbin: %d\n", *speedbin); 85 drv->versions = 1 << *speedbin; 86 kfree(speedbin); 87 return 0; 88 } 89 90 static void get_krait_bin_format_a(struct device *cpu_dev, 91 int *speed, int *pvs, 92 u8 *buf) 93 { 94 u32 pte_efuse; 95 96 pte_efuse = *((u32 *)buf); 97 98 *speed = pte_efuse & 0xf; 99 if (*speed == 0xf) 100 *speed = (pte_efuse >> 4) & 0xf; 101 102 if (*speed == 0xf) { 103 *speed = 0; 104 dev_warn(cpu_dev, "Speed bin: Defaulting to %d\n", *speed); 105 } else { 106 dev_dbg(cpu_dev, "Speed bin: %d\n", *speed); 107 } 108 109 *pvs = (pte_efuse >> 10) & 0x7; 110 if (*pvs == 0x7) 111 *pvs = (pte_efuse >> 13) & 0x7; 112 113 if (*pvs == 0x7) { 114 *pvs = 0; 115 dev_warn(cpu_dev, "PVS bin: Defaulting to %d\n", *pvs); 116 } else { 117 dev_dbg(cpu_dev, "PVS bin: %d\n", *pvs); 118 } 119 } 120 121 static void get_krait_bin_format_b(struct device *cpu_dev, 122 int *speed, int *pvs, int *pvs_ver, 123 u8 *buf) 124 { 125 u32 pte_efuse, redundant_sel; 126 127 pte_efuse = *((u32 *)buf); 128 redundant_sel = (pte_efuse >> 24) & 0x7; 129 130 *pvs_ver = (pte_efuse >> 4) & 0x3; 131 132 switch (redundant_sel) { 133 case 1: 134 *pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7); 135 *speed = (pte_efuse >> 27) & 0xf; 136 break; 137 case 2: 138 *pvs = (pte_efuse >> 27) & 0xf; 139 *speed = pte_efuse & 0x7; 140 break; 141 default: 142 /* 4 bits of PVS are in efuse register bits 31, 8-6. */ 143 *pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7); 144 *speed = pte_efuse & 0x7; 145 } 146 147 /* Check SPEED_BIN_BLOW_STATUS */ 148 if (pte_efuse & BIT(3)) { 149 dev_dbg(cpu_dev, "Speed bin: %d\n", *speed); 150 } else { 151 dev_warn(cpu_dev, "Speed bin not set. Defaulting to 0!\n"); 152 *speed = 0; 153 } 154 155 /* Check PVS_BLOW_STATUS */ 156 pte_efuse = *(((u32 *)buf) + 1); 157 pte_efuse &= BIT(21); 158 if (pte_efuse) { 159 dev_dbg(cpu_dev, "PVS bin: %d\n", *pvs); 160 } else { 161 dev_warn(cpu_dev, "PVS bin not set. Defaulting to 0!\n"); 162 *pvs = 0; 163 } 164 165 dev_dbg(cpu_dev, "PVS version: %d\n", *pvs_ver); 166 } 167 168 static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev, 169 struct nvmem_cell *speedbin_nvmem, 170 char **pvs_name, 171 struct qcom_cpufreq_drv *drv) 172 { 173 size_t len; 174 u32 msm_id; 175 u8 *speedbin; 176 int ret; 177 *pvs_name = NULL; 178 179 ret = qcom_smem_get_soc_id(&msm_id); 180 if (ret) 181 return ret; 182 183 speedbin = nvmem_cell_read(speedbin_nvmem, &len); 184 if (IS_ERR(speedbin)) 185 return PTR_ERR(speedbin); 186 187 switch (msm_id) { 188 case QCOM_ID_MSM8996: 189 case QCOM_ID_APQ8096: 190 case QCOM_ID_IPQ5332: 191 case QCOM_ID_IPQ5322: 192 case QCOM_ID_IPQ5312: 193 case QCOM_ID_IPQ5302: 194 case QCOM_ID_IPQ5300: 195 case QCOM_ID_IPQ5321: 196 case QCOM_ID_IPQ9514: 197 case QCOM_ID_IPQ9550: 198 case QCOM_ID_IPQ9554: 199 case QCOM_ID_IPQ9570: 200 case QCOM_ID_IPQ9574: 201 drv->versions = 1 << (unsigned int)(*speedbin); 202 break; 203 case QCOM_ID_IPQ5424: 204 case QCOM_ID_IPQ5404: 205 drv->versions = (*speedbin == 0x3b) ? BIT(1) : BIT(0); 206 break; 207 case QCOM_ID_MSM8996SG: 208 case QCOM_ID_APQ8096SG: 209 drv->versions = 1 << ((unsigned int)(*speedbin) + 4); 210 break; 211 default: 212 BUG(); 213 break; 214 } 215 216 kfree(speedbin); 217 return 0; 218 } 219 220 static int qcom_cpufreq_krait_name_version(struct device *cpu_dev, 221 struct nvmem_cell *speedbin_nvmem, 222 char **pvs_name, 223 struct qcom_cpufreq_drv *drv) 224 { 225 int speed = 0, pvs = 0, pvs_ver = 0; 226 u8 *speedbin; 227 size_t len; 228 int ret = 0; 229 230 speedbin = nvmem_cell_read(speedbin_nvmem, &len); 231 232 if (IS_ERR(speedbin)) 233 return PTR_ERR(speedbin); 234 235 switch (len) { 236 case 4: 237 get_krait_bin_format_a(cpu_dev, &speed, &pvs, speedbin); 238 break; 239 case 8: 240 get_krait_bin_format_b(cpu_dev, &speed, &pvs, &pvs_ver, 241 speedbin); 242 break; 243 default: 244 dev_err(cpu_dev, "Unable to read nvmem data. Defaulting to 0!\n"); 245 ret = -ENODEV; 246 goto len_error; 247 } 248 249 snprintf(*pvs_name, sizeof("speedXX-pvsXX-vXX"), "speed%d-pvs%d-v%d", 250 speed, pvs, pvs_ver); 251 252 drv->versions = (1 << speed); 253 254 len_error: 255 kfree(speedbin); 256 return ret; 257 } 258 259 static const struct of_device_id qcom_cpufreq_ipq806x_match_list[] __maybe_unused = { 260 { .compatible = "qcom,ipq8062", .data = (const void *)QCOM_ID_IPQ8062 }, 261 { .compatible = "qcom,ipq8064", .data = (const void *)QCOM_ID_IPQ8064 }, 262 { .compatible = "qcom,ipq8065", .data = (const void *)QCOM_ID_IPQ8065 }, 263 { .compatible = "qcom,ipq8066", .data = (const void *)QCOM_ID_IPQ8066 }, 264 { .compatible = "qcom,ipq8068", .data = (const void *)QCOM_ID_IPQ8068 }, 265 { .compatible = "qcom,ipq8069", .data = (const void *)QCOM_ID_IPQ8069 }, 266 }; 267 268 static int qcom_cpufreq_ipq8064_name_version(struct device *cpu_dev, 269 struct nvmem_cell *speedbin_nvmem, 270 char **pvs_name, 271 struct qcom_cpufreq_drv *drv) 272 { 273 int msm_id = -1, ret = 0; 274 int speed = 0, pvs = 0; 275 u8 *speedbin; 276 size_t len; 277 278 speedbin = nvmem_cell_read(speedbin_nvmem, &len); 279 if (IS_ERR(speedbin)) 280 return PTR_ERR(speedbin); 281 282 if (len != 4) { 283 dev_err(cpu_dev, "Unable to read nvmem data. Defaulting to 0!\n"); 284 ret = -ENODEV; 285 goto exit; 286 } 287 288 get_krait_bin_format_a(cpu_dev, &speed, &pvs, speedbin); 289 290 ret = qcom_smem_get_soc_id(&msm_id); 291 if (ret == -ENODEV) { 292 const struct of_device_id *match; 293 struct device_node *root; 294 295 root = of_find_node_by_path("/"); 296 if (!root) { 297 ret = -ENODEV; 298 goto exit; 299 } 300 301 /* Fallback to compatible match with no SMEM initialized */ 302 match = of_match_node(qcom_cpufreq_ipq806x_match_list, root); 303 of_node_put(root); 304 if (!match) { 305 ret = -ENODEV; 306 goto exit; 307 } 308 309 /* We found a matching device, get the msm_id from the data entry */ 310 msm_id = (int)(uintptr_t)match->data; 311 ret = 0; 312 } else if (ret) { 313 goto exit; 314 } 315 316 switch (msm_id) { 317 case QCOM_ID_IPQ8062: 318 drv->versions = BIT(IPQ8062_VERSION); 319 break; 320 case QCOM_ID_IPQ8064: 321 case QCOM_ID_IPQ8066: 322 case QCOM_ID_IPQ8068: 323 drv->versions = BIT(IPQ8064_VERSION); 324 break; 325 case QCOM_ID_IPQ8065: 326 case QCOM_ID_IPQ8069: 327 drv->versions = BIT(IPQ8065_VERSION); 328 break; 329 default: 330 dev_err(cpu_dev, 331 "SoC ID %u is not part of IPQ8064 family, limiting to 1.0GHz!\n", 332 msm_id); 333 drv->versions = BIT(IPQ8062_VERSION); 334 break; 335 } 336 337 /* IPQ8064 speed is never fused. Only pvs values are fused. */ 338 snprintf(*pvs_name, sizeof("speed0-pvsXX"), "speed0-pvs%d", pvs); 339 340 exit: 341 kfree(speedbin); 342 return ret; 343 } 344 345 static int qcom_cpufreq_ipq6018_name_version(struct device *cpu_dev, 346 struct nvmem_cell *speedbin_nvmem, 347 char **pvs_name, 348 struct qcom_cpufreq_drv *drv) 349 { 350 u32 msm_id; 351 int ret; 352 u8 *speedbin; 353 *pvs_name = NULL; 354 355 ret = qcom_smem_get_soc_id(&msm_id); 356 if (ret) 357 return ret; 358 359 speedbin = nvmem_cell_read(speedbin_nvmem, NULL); 360 if (IS_ERR(speedbin)) 361 return PTR_ERR(speedbin); 362 363 switch (msm_id) { 364 case QCOM_ID_IPQ6005: 365 case QCOM_ID_IPQ6010: 366 case QCOM_ID_IPQ6018: 367 case QCOM_ID_IPQ6028: 368 /* Fuse Value Freq BIT to set 369 * --------------------------------- 370 * 2’b0 No Limit BIT(0) 371 * 2’b1 1.5 GHz BIT(1) 372 */ 373 drv->versions = 1 << (unsigned int)(*speedbin); 374 break; 375 case QCOM_ID_IPQ6000: 376 /* 377 * IPQ6018 family only has one bit to advertise the CPU 378 * speed-bin, but that is not enough for IPQ6000 which 379 * is only rated up to 1.2GHz. 380 * So for IPQ6000 manually set BIT(2) based on SMEM ID. 381 */ 382 drv->versions = IPQ6000_VERSION; 383 break; 384 default: 385 dev_err(cpu_dev, 386 "SoC ID %u is not part of IPQ6018 family, limiting to 1.2GHz!\n", 387 msm_id); 388 drv->versions = IPQ6000_VERSION; 389 break; 390 } 391 392 kfree(speedbin); 393 return 0; 394 } 395 396 static int qcom_cpufreq_ipq8074_name_version(struct device *cpu_dev, 397 struct nvmem_cell *speedbin_nvmem, 398 char **pvs_name, 399 struct qcom_cpufreq_drv *drv) 400 { 401 u32 msm_id; 402 int ret; 403 *pvs_name = NULL; 404 405 ret = qcom_smem_get_soc_id(&msm_id); 406 if (ret) 407 return ret; 408 409 switch (msm_id) { 410 case QCOM_ID_IPQ8070A: 411 case QCOM_ID_IPQ8071A: 412 case QCOM_ID_IPQ8172: 413 case QCOM_ID_IPQ8173: 414 case QCOM_ID_IPQ8174: 415 drv->versions = BIT(IPQ8074_ACORN_VERSION); 416 break; 417 case QCOM_ID_IPQ8072A: 418 case QCOM_ID_IPQ8074A: 419 case QCOM_ID_IPQ8076A: 420 case QCOM_ID_IPQ8078A: 421 drv->versions = BIT(IPQ8074_HAWKEYE_VERSION); 422 break; 423 default: 424 dev_err(cpu_dev, 425 "SoC ID %u is not part of IPQ8074 family, limiting to 1.4GHz!\n", 426 msm_id); 427 drv->versions = BIT(IPQ8074_ACORN_VERSION); 428 break; 429 } 430 431 return 0; 432 } 433 434 static const struct qcom_cpufreq_match_data match_data_kryo = { 435 .get_version = qcom_cpufreq_kryo_name_version, 436 }; 437 438 static const struct qcom_cpufreq_match_data match_data_krait = { 439 .get_version = qcom_cpufreq_krait_name_version, 440 }; 441 442 static const struct qcom_cpufreq_match_data match_data_msm8909 = { 443 .get_version = qcom_cpufreq_simple_get_version, 444 .pd_names = (const char *[]) { "perf" }, 445 .num_pd_names = 1, 446 }; 447 448 static const struct qcom_cpufreq_match_data match_data_qcs404 = { 449 .pd_names = (const char *[]) { "cpr" }, 450 .num_pd_names = 1, 451 }; 452 453 static const struct qcom_cpufreq_match_data match_data_ipq6018 = { 454 .get_version = qcom_cpufreq_ipq6018_name_version, 455 }; 456 457 static const struct qcom_cpufreq_match_data match_data_ipq8064 = { 458 .get_version = qcom_cpufreq_ipq8064_name_version, 459 }; 460 461 static const struct qcom_cpufreq_match_data match_data_ipq8074 = { 462 .get_version = qcom_cpufreq_ipq8074_name_version, 463 }; 464 465 static void qcom_cpufreq_suspend_pd_devs(struct qcom_cpufreq_drv *drv, unsigned int cpu) 466 { 467 struct dev_pm_domain_list *pd_list = drv->cpus[cpu].pd_list; 468 int i; 469 470 if (!pd_list) 471 return; 472 473 for (i = 0; i < pd_list->num_pds; i++) 474 device_set_awake_path(pd_list->pd_devs[i]); 475 } 476 477 static int qcom_cpufreq_probe(struct platform_device *pdev) 478 { 479 struct qcom_cpufreq_drv *drv; 480 struct nvmem_cell *speedbin_nvmem; 481 struct device *cpu_dev; 482 char pvs_name_buffer[] = "speedXX-pvsXX-vXX"; 483 char *pvs_name = pvs_name_buffer; 484 unsigned cpu; 485 const struct of_device_id *match; 486 int ret; 487 488 cpu_dev = get_cpu_device(0); 489 if (!cpu_dev) 490 return -ENODEV; 491 492 struct device_node *np __free(device_node) = 493 dev_pm_opp_of_get_opp_desc_node(cpu_dev); 494 if (!np) 495 return -ENOENT; 496 497 ret = of_device_is_compatible(np, "operating-points-v2-kryo-cpu") || 498 of_device_is_compatible(np, "operating-points-v2-krait-cpu"); 499 if (!ret) 500 return -ENOENT; 501 502 drv = devm_kzalloc(&pdev->dev, struct_size(drv, cpus, num_possible_cpus()), 503 GFP_KERNEL); 504 if (!drv) 505 return -ENOMEM; 506 507 match = pdev->dev.platform_data; 508 drv->data = match->data; 509 if (!drv->data) 510 return -ENODEV; 511 512 if (drv->data->get_version) { 513 speedbin_nvmem = of_nvmem_cell_get(np, NULL); 514 if (IS_ERR(speedbin_nvmem)) 515 return dev_err_probe(cpu_dev, PTR_ERR(speedbin_nvmem), 516 "Could not get nvmem cell\n"); 517 518 ret = drv->data->get_version(cpu_dev, 519 speedbin_nvmem, &pvs_name, drv); 520 if (ret) { 521 nvmem_cell_put(speedbin_nvmem); 522 return ret; 523 } 524 nvmem_cell_put(speedbin_nvmem); 525 } 526 527 for_each_present_cpu(cpu) { 528 struct dev_pm_opp_config config = { 529 .supported_hw = NULL, 530 }; 531 532 cpu_dev = get_cpu_device(cpu); 533 if (NULL == cpu_dev) { 534 ret = -ENODEV; 535 goto free_opp; 536 } 537 538 if (drv->data->get_version) { 539 config.supported_hw = &drv->versions; 540 config.supported_hw_count = 1; 541 542 if (pvs_name) 543 config.prop_name = pvs_name; 544 } 545 546 if (config.supported_hw) { 547 drv->cpus[cpu].opp_token = dev_pm_opp_set_config(cpu_dev, &config); 548 if (drv->cpus[cpu].opp_token < 0) { 549 ret = drv->cpus[cpu].opp_token; 550 dev_err(cpu_dev, "Failed to set OPP config\n"); 551 goto free_opp; 552 } 553 } 554 555 if (drv->data->pd_names) { 556 struct dev_pm_domain_attach_data attach_data = { 557 .pd_names = drv->data->pd_names, 558 .num_pd_names = drv->data->num_pd_names, 559 .pd_flags = PD_FLAG_DEV_LINK_ON | 560 PD_FLAG_REQUIRED_OPP, 561 }; 562 563 ret = dev_pm_domain_attach_list(cpu_dev, &attach_data, 564 &drv->cpus[cpu].pd_list); 565 if (ret < 0) 566 goto free_opp; 567 } 568 } 569 570 cpufreq_dt_pdev = platform_device_register_simple("cpufreq-dt", -1, 571 NULL, 0); 572 if (!IS_ERR(cpufreq_dt_pdev)) { 573 platform_set_drvdata(pdev, drv); 574 return 0; 575 } 576 577 ret = PTR_ERR(cpufreq_dt_pdev); 578 dev_err(cpu_dev, "Failed to register platform device\n"); 579 580 free_opp: 581 for_each_present_cpu(cpu) { 582 dev_pm_domain_detach_list(drv->cpus[cpu].pd_list); 583 dev_pm_opp_clear_config(drv->cpus[cpu].opp_token); 584 } 585 return ret; 586 } 587 588 static void qcom_cpufreq_remove(struct platform_device *pdev) 589 { 590 struct qcom_cpufreq_drv *drv = platform_get_drvdata(pdev); 591 unsigned int cpu; 592 593 platform_device_unregister(cpufreq_dt_pdev); 594 595 for_each_present_cpu(cpu) { 596 dev_pm_domain_detach_list(drv->cpus[cpu].pd_list); 597 dev_pm_opp_clear_config(drv->cpus[cpu].opp_token); 598 } 599 } 600 601 static int qcom_cpufreq_suspend(struct device *dev) 602 { 603 struct qcom_cpufreq_drv *drv = dev_get_drvdata(dev); 604 unsigned int cpu; 605 606 for_each_present_cpu(cpu) 607 qcom_cpufreq_suspend_pd_devs(drv, cpu); 608 609 return 0; 610 } 611 612 static DEFINE_SIMPLE_DEV_PM_OPS(qcom_cpufreq_pm_ops, qcom_cpufreq_suspend, NULL); 613 614 static struct platform_driver qcom_cpufreq_driver = { 615 .probe = qcom_cpufreq_probe, 616 .remove = qcom_cpufreq_remove, 617 .driver = { 618 .name = "qcom-cpufreq-nvmem", 619 .pm = pm_sleep_ptr(&qcom_cpufreq_pm_ops), 620 }, 621 }; 622 623 static const struct of_device_id qcom_cpufreq_match_list[] __initconst __maybe_unused = { 624 { .compatible = "qcom,apq8096", .data = &match_data_kryo }, 625 { .compatible = "qcom,msm8909", .data = &match_data_msm8909 }, 626 { .compatible = "qcom,msm8996", .data = &match_data_kryo }, 627 { .compatible = "qcom,qcs404", .data = &match_data_qcs404 }, 628 { .compatible = "qcom,ipq5332", .data = &match_data_kryo }, 629 { .compatible = "qcom,ipq5424", .data = &match_data_kryo }, 630 { .compatible = "qcom,ipq6018", .data = &match_data_ipq6018 }, 631 { .compatible = "qcom,ipq8064", .data = &match_data_ipq8064 }, 632 { .compatible = "qcom,ipq8074", .data = &match_data_ipq8074 }, 633 { .compatible = "qcom,apq8064", .data = &match_data_krait }, 634 { .compatible = "qcom,ipq9574", .data = &match_data_kryo }, 635 { .compatible = "qcom,msm8974", .data = &match_data_krait }, 636 { .compatible = "qcom,msm8960", .data = &match_data_krait }, 637 {}, 638 }; 639 MODULE_DEVICE_TABLE(of, qcom_cpufreq_match_list); 640 641 /* 642 * Since the driver depends on smem and nvmem drivers, which may 643 * return EPROBE_DEFER, all the real activity is done in the probe, 644 * which may be defered as well. The init here is only registering 645 * the driver and the platform device. 646 */ 647 static int __init qcom_cpufreq_init(void) 648 { 649 struct device_node *np __free(device_node) = of_find_node_by_path("/"); 650 const struct of_device_id *match; 651 int ret; 652 653 if (!np) 654 return -ENODEV; 655 656 match = of_match_node(qcom_cpufreq_match_list, np); 657 if (!match) 658 return -ENODEV; 659 660 ret = platform_driver_register(&qcom_cpufreq_driver); 661 if (unlikely(ret < 0)) 662 return ret; 663 664 cpufreq_pdev = platform_device_register_data(NULL, "qcom-cpufreq-nvmem", 665 -1, match, sizeof(*match)); 666 ret = PTR_ERR_OR_ZERO(cpufreq_pdev); 667 if (0 == ret) 668 return 0; 669 670 platform_driver_unregister(&qcom_cpufreq_driver); 671 return ret; 672 } 673 module_init(qcom_cpufreq_init); 674 675 static void __exit qcom_cpufreq_exit(void) 676 { 677 platform_device_unregister(cpufreq_pdev); 678 platform_driver_unregister(&qcom_cpufreq_driver); 679 } 680 module_exit(qcom_cpufreq_exit); 681 682 MODULE_DESCRIPTION("Qualcomm Technologies, Inc. CPUfreq driver"); 683 MODULE_LICENSE("GPL v2"); 684