1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 4 */ 5 6 /* 7 * In Certain QCOM SoCs like apq8096 and msm8996 that have KRYO processors, 8 * the CPU frequency subset and voltage value of each OPP varies 9 * based on the silicon variant in use. Qualcomm Process Voltage Scaling Tables 10 * defines the voltage and frequency value based on the msm-id in SMEM 11 * and speedbin blown in the efuse combination. 12 * The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC 13 * to provide the OPP framework with required information. 14 * This is used to determine the voltage and frequency value for each OPP of 15 * operating-points-v2 table when it is parsed by the OPP framework. 16 */ 17 18 #include <linux/cpu.h> 19 #include <linux/err.h> 20 #include <linux/init.h> 21 #include <linux/kernel.h> 22 #include <linux/module.h> 23 #include <linux/nvmem-consumer.h> 24 #include <linux/of.h> 25 #include <linux/platform_device.h> 26 #include <linux/pm.h> 27 #include <linux/pm_domain.h> 28 #include <linux/pm_opp.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/slab.h> 31 #include <linux/soc/qcom/smem.h> 32 33 #include <dt-bindings/arm/qcom,ids.h> 34 35 enum ipq806x_versions { 36 IPQ8062_VERSION = 0, 37 IPQ8064_VERSION, 38 IPQ8065_VERSION, 39 }; 40 41 #define IPQ6000_VERSION BIT(2) 42 43 enum ipq8074_versions { 44 IPQ8074_HAWKEYE_VERSION = 0, 45 IPQ8074_ACORN_VERSION, 46 }; 47 48 struct qcom_cpufreq_drv; 49 50 struct qcom_cpufreq_match_data { 51 int (*get_version)(struct device *cpu_dev, 52 struct nvmem_cell *speedbin_nvmem, 53 char **pvs_name, 54 struct qcom_cpufreq_drv *drv); 55 const char **pd_names; 56 unsigned int num_pd_names; 57 }; 58 59 struct qcom_cpufreq_drv_cpu { 60 int opp_token; 61 struct dev_pm_domain_list *pd_list; 62 }; 63 64 struct qcom_cpufreq_drv { 65 u32 versions; 66 const struct qcom_cpufreq_match_data *data; 67 struct qcom_cpufreq_drv_cpu cpus[]; 68 }; 69 70 static struct platform_device *cpufreq_dt_pdev, *cpufreq_pdev; 71 72 static int qcom_cpufreq_simple_get_version(struct device *cpu_dev, 73 struct nvmem_cell *speedbin_nvmem, 74 char **pvs_name, 75 struct qcom_cpufreq_drv *drv) 76 { 77 u8 *speedbin; 78 79 *pvs_name = NULL; 80 speedbin = nvmem_cell_read(speedbin_nvmem, NULL); 81 if (IS_ERR(speedbin)) 82 return PTR_ERR(speedbin); 83 84 dev_dbg(cpu_dev, "speedbin: %d\n", *speedbin); 85 drv->versions = 1 << *speedbin; 86 kfree(speedbin); 87 return 0; 88 } 89 90 static void get_krait_bin_format_a(struct device *cpu_dev, 91 int *speed, int *pvs, 92 u8 *buf) 93 { 94 u32 pte_efuse; 95 96 pte_efuse = *((u32 *)buf); 97 98 *speed = pte_efuse & 0xf; 99 if (*speed == 0xf) 100 *speed = (pte_efuse >> 4) & 0xf; 101 102 if (*speed == 0xf) { 103 *speed = 0; 104 dev_warn(cpu_dev, "Speed bin: Defaulting to %d\n", *speed); 105 } else { 106 dev_dbg(cpu_dev, "Speed bin: %d\n", *speed); 107 } 108 109 *pvs = (pte_efuse >> 10) & 0x7; 110 if (*pvs == 0x7) 111 *pvs = (pte_efuse >> 13) & 0x7; 112 113 if (*pvs == 0x7) { 114 *pvs = 0; 115 dev_warn(cpu_dev, "PVS bin: Defaulting to %d\n", *pvs); 116 } else { 117 dev_dbg(cpu_dev, "PVS bin: %d\n", *pvs); 118 } 119 } 120 121 static void get_krait_bin_format_b(struct device *cpu_dev, 122 int *speed, int *pvs, int *pvs_ver, 123 u8 *buf) 124 { 125 u32 pte_efuse, redundant_sel; 126 127 pte_efuse = *((u32 *)buf); 128 redundant_sel = (pte_efuse >> 24) & 0x7; 129 130 *pvs_ver = (pte_efuse >> 4) & 0x3; 131 132 switch (redundant_sel) { 133 case 1: 134 *pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7); 135 *speed = (pte_efuse >> 27) & 0xf; 136 break; 137 case 2: 138 *pvs = (pte_efuse >> 27) & 0xf; 139 *speed = pte_efuse & 0x7; 140 break; 141 default: 142 /* 4 bits of PVS are in efuse register bits 31, 8-6. */ 143 *pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7); 144 *speed = pte_efuse & 0x7; 145 } 146 147 /* Check SPEED_BIN_BLOW_STATUS */ 148 if (pte_efuse & BIT(3)) { 149 dev_dbg(cpu_dev, "Speed bin: %d\n", *speed); 150 } else { 151 dev_warn(cpu_dev, "Speed bin not set. Defaulting to 0!\n"); 152 *speed = 0; 153 } 154 155 /* Check PVS_BLOW_STATUS */ 156 pte_efuse = *(((u32 *)buf) + 1); 157 pte_efuse &= BIT(21); 158 if (pte_efuse) { 159 dev_dbg(cpu_dev, "PVS bin: %d\n", *pvs); 160 } else { 161 dev_warn(cpu_dev, "PVS bin not set. Defaulting to 0!\n"); 162 *pvs = 0; 163 } 164 165 dev_dbg(cpu_dev, "PVS version: %d\n", *pvs_ver); 166 } 167 168 static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev, 169 struct nvmem_cell *speedbin_nvmem, 170 char **pvs_name, 171 struct qcom_cpufreq_drv *drv) 172 { 173 size_t len; 174 u32 msm_id; 175 u8 *speedbin; 176 int ret; 177 *pvs_name = NULL; 178 179 ret = qcom_smem_get_soc_id(&msm_id); 180 if (ret) 181 return ret; 182 183 speedbin = nvmem_cell_read(speedbin_nvmem, &len); 184 if (IS_ERR(speedbin)) 185 return PTR_ERR(speedbin); 186 187 switch (msm_id) { 188 case QCOM_ID_MSM8996: 189 case QCOM_ID_APQ8096: 190 case QCOM_ID_IPQ5332: 191 case QCOM_ID_IPQ5322: 192 case QCOM_ID_IPQ5312: 193 case QCOM_ID_IPQ5302: 194 case QCOM_ID_IPQ5300: 195 case QCOM_ID_IPQ5321: 196 case QCOM_ID_IPQ9514: 197 case QCOM_ID_IPQ9550: 198 case QCOM_ID_IPQ9554: 199 case QCOM_ID_IPQ9570: 200 case QCOM_ID_IPQ9574: 201 drv->versions = 1 << (unsigned int)(*speedbin); 202 break; 203 case QCOM_ID_MSM8996SG: 204 case QCOM_ID_APQ8096SG: 205 drv->versions = 1 << ((unsigned int)(*speedbin) + 4); 206 break; 207 default: 208 BUG(); 209 break; 210 } 211 212 kfree(speedbin); 213 return 0; 214 } 215 216 static int qcom_cpufreq_krait_name_version(struct device *cpu_dev, 217 struct nvmem_cell *speedbin_nvmem, 218 char **pvs_name, 219 struct qcom_cpufreq_drv *drv) 220 { 221 int speed = 0, pvs = 0, pvs_ver = 0; 222 u8 *speedbin; 223 size_t len; 224 int ret = 0; 225 226 speedbin = nvmem_cell_read(speedbin_nvmem, &len); 227 228 if (IS_ERR(speedbin)) 229 return PTR_ERR(speedbin); 230 231 switch (len) { 232 case 4: 233 get_krait_bin_format_a(cpu_dev, &speed, &pvs, speedbin); 234 break; 235 case 8: 236 get_krait_bin_format_b(cpu_dev, &speed, &pvs, &pvs_ver, 237 speedbin); 238 break; 239 default: 240 dev_err(cpu_dev, "Unable to read nvmem data. Defaulting to 0!\n"); 241 ret = -ENODEV; 242 goto len_error; 243 } 244 245 snprintf(*pvs_name, sizeof("speedXX-pvsXX-vXX"), "speed%d-pvs%d-v%d", 246 speed, pvs, pvs_ver); 247 248 drv->versions = (1 << speed); 249 250 len_error: 251 kfree(speedbin); 252 return ret; 253 } 254 255 static int qcom_cpufreq_ipq8064_name_version(struct device *cpu_dev, 256 struct nvmem_cell *speedbin_nvmem, 257 char **pvs_name, 258 struct qcom_cpufreq_drv *drv) 259 { 260 int speed = 0, pvs = 0; 261 int msm_id, ret = 0; 262 u8 *speedbin; 263 size_t len; 264 265 speedbin = nvmem_cell_read(speedbin_nvmem, &len); 266 if (IS_ERR(speedbin)) 267 return PTR_ERR(speedbin); 268 269 if (len != 4) { 270 dev_err(cpu_dev, "Unable to read nvmem data. Defaulting to 0!\n"); 271 ret = -ENODEV; 272 goto exit; 273 } 274 275 get_krait_bin_format_a(cpu_dev, &speed, &pvs, speedbin); 276 277 ret = qcom_smem_get_soc_id(&msm_id); 278 if (ret) 279 goto exit; 280 281 switch (msm_id) { 282 case QCOM_ID_IPQ8062: 283 drv->versions = BIT(IPQ8062_VERSION); 284 break; 285 case QCOM_ID_IPQ8064: 286 case QCOM_ID_IPQ8066: 287 case QCOM_ID_IPQ8068: 288 drv->versions = BIT(IPQ8064_VERSION); 289 break; 290 case QCOM_ID_IPQ8065: 291 case QCOM_ID_IPQ8069: 292 drv->versions = BIT(IPQ8065_VERSION); 293 break; 294 default: 295 dev_err(cpu_dev, 296 "SoC ID %u is not part of IPQ8064 family, limiting to 1.0GHz!\n", 297 msm_id); 298 drv->versions = BIT(IPQ8062_VERSION); 299 break; 300 } 301 302 /* IPQ8064 speed is never fused. Only pvs values are fused. */ 303 snprintf(*pvs_name, sizeof("speed0-pvsXX"), "speed0-pvs%d", pvs); 304 305 exit: 306 kfree(speedbin); 307 return ret; 308 } 309 310 static int qcom_cpufreq_ipq6018_name_version(struct device *cpu_dev, 311 struct nvmem_cell *speedbin_nvmem, 312 char **pvs_name, 313 struct qcom_cpufreq_drv *drv) 314 { 315 u32 msm_id; 316 int ret; 317 u8 *speedbin; 318 *pvs_name = NULL; 319 320 ret = qcom_smem_get_soc_id(&msm_id); 321 if (ret) 322 return ret; 323 324 speedbin = nvmem_cell_read(speedbin_nvmem, NULL); 325 if (IS_ERR(speedbin)) 326 return PTR_ERR(speedbin); 327 328 switch (msm_id) { 329 case QCOM_ID_IPQ6005: 330 case QCOM_ID_IPQ6010: 331 case QCOM_ID_IPQ6018: 332 case QCOM_ID_IPQ6028: 333 /* Fuse Value Freq BIT to set 334 * --------------------------------- 335 * 2’b0 No Limit BIT(0) 336 * 2’b1 1.5 GHz BIT(1) 337 */ 338 drv->versions = 1 << (unsigned int)(*speedbin); 339 break; 340 case QCOM_ID_IPQ6000: 341 /* 342 * IPQ6018 family only has one bit to advertise the CPU 343 * speed-bin, but that is not enough for IPQ6000 which 344 * is only rated up to 1.2GHz. 345 * So for IPQ6000 manually set BIT(2) based on SMEM ID. 346 */ 347 drv->versions = IPQ6000_VERSION; 348 break; 349 default: 350 dev_err(cpu_dev, 351 "SoC ID %u is not part of IPQ6018 family, limiting to 1.2GHz!\n", 352 msm_id); 353 drv->versions = IPQ6000_VERSION; 354 break; 355 } 356 357 kfree(speedbin); 358 return 0; 359 } 360 361 static int qcom_cpufreq_ipq8074_name_version(struct device *cpu_dev, 362 struct nvmem_cell *speedbin_nvmem, 363 char **pvs_name, 364 struct qcom_cpufreq_drv *drv) 365 { 366 u32 msm_id; 367 int ret; 368 *pvs_name = NULL; 369 370 ret = qcom_smem_get_soc_id(&msm_id); 371 if (ret) 372 return ret; 373 374 switch (msm_id) { 375 case QCOM_ID_IPQ8070A: 376 case QCOM_ID_IPQ8071A: 377 case QCOM_ID_IPQ8172: 378 case QCOM_ID_IPQ8173: 379 case QCOM_ID_IPQ8174: 380 drv->versions = BIT(IPQ8074_ACORN_VERSION); 381 break; 382 case QCOM_ID_IPQ8072A: 383 case QCOM_ID_IPQ8074A: 384 case QCOM_ID_IPQ8076A: 385 case QCOM_ID_IPQ8078A: 386 drv->versions = BIT(IPQ8074_HAWKEYE_VERSION); 387 break; 388 default: 389 dev_err(cpu_dev, 390 "SoC ID %u is not part of IPQ8074 family, limiting to 1.4GHz!\n", 391 msm_id); 392 drv->versions = BIT(IPQ8074_ACORN_VERSION); 393 break; 394 } 395 396 return 0; 397 } 398 399 static const struct qcom_cpufreq_match_data match_data_kryo = { 400 .get_version = qcom_cpufreq_kryo_name_version, 401 }; 402 403 static const struct qcom_cpufreq_match_data match_data_krait = { 404 .get_version = qcom_cpufreq_krait_name_version, 405 }; 406 407 static const struct qcom_cpufreq_match_data match_data_msm8909 = { 408 .get_version = qcom_cpufreq_simple_get_version, 409 .pd_names = (const char *[]) { "perf" }, 410 .num_pd_names = 1, 411 }; 412 413 static const struct qcom_cpufreq_match_data match_data_qcs404 = { 414 .pd_names = (const char *[]) { "cpr" }, 415 .num_pd_names = 1, 416 }; 417 418 static const struct qcom_cpufreq_match_data match_data_ipq6018 = { 419 .get_version = qcom_cpufreq_ipq6018_name_version, 420 }; 421 422 static const struct qcom_cpufreq_match_data match_data_ipq8064 = { 423 .get_version = qcom_cpufreq_ipq8064_name_version, 424 }; 425 426 static const struct qcom_cpufreq_match_data match_data_ipq8074 = { 427 .get_version = qcom_cpufreq_ipq8074_name_version, 428 }; 429 430 static void qcom_cpufreq_suspend_pd_devs(struct qcom_cpufreq_drv *drv, unsigned int cpu) 431 { 432 struct dev_pm_domain_list *pd_list = drv->cpus[cpu].pd_list; 433 int i; 434 435 if (!pd_list) 436 return; 437 438 for (i = 0; i < pd_list->num_pds; i++) 439 device_set_awake_path(pd_list->pd_devs[i]); 440 } 441 442 static int qcom_cpufreq_probe(struct platform_device *pdev) 443 { 444 struct qcom_cpufreq_drv *drv; 445 struct nvmem_cell *speedbin_nvmem; 446 struct device *cpu_dev; 447 char pvs_name_buffer[] = "speedXX-pvsXX-vXX"; 448 char *pvs_name = pvs_name_buffer; 449 unsigned cpu; 450 const struct of_device_id *match; 451 int ret; 452 453 cpu_dev = get_cpu_device(0); 454 if (!cpu_dev) 455 return -ENODEV; 456 457 struct device_node *np __free(device_node) = 458 dev_pm_opp_of_get_opp_desc_node(cpu_dev); 459 if (!np) 460 return -ENOENT; 461 462 ret = of_device_is_compatible(np, "operating-points-v2-kryo-cpu") || 463 of_device_is_compatible(np, "operating-points-v2-krait-cpu"); 464 if (!ret) 465 return -ENOENT; 466 467 drv = devm_kzalloc(&pdev->dev, struct_size(drv, cpus, num_possible_cpus()), 468 GFP_KERNEL); 469 if (!drv) 470 return -ENOMEM; 471 472 match = pdev->dev.platform_data; 473 drv->data = match->data; 474 if (!drv->data) 475 return -ENODEV; 476 477 if (drv->data->get_version) { 478 speedbin_nvmem = of_nvmem_cell_get(np, NULL); 479 if (IS_ERR(speedbin_nvmem)) 480 return dev_err_probe(cpu_dev, PTR_ERR(speedbin_nvmem), 481 "Could not get nvmem cell\n"); 482 483 ret = drv->data->get_version(cpu_dev, 484 speedbin_nvmem, &pvs_name, drv); 485 if (ret) { 486 nvmem_cell_put(speedbin_nvmem); 487 return ret; 488 } 489 nvmem_cell_put(speedbin_nvmem); 490 } 491 492 for_each_possible_cpu(cpu) { 493 struct dev_pm_opp_config config = { 494 .supported_hw = NULL, 495 }; 496 497 cpu_dev = get_cpu_device(cpu); 498 if (NULL == cpu_dev) { 499 ret = -ENODEV; 500 goto free_opp; 501 } 502 503 if (drv->data->get_version) { 504 config.supported_hw = &drv->versions; 505 config.supported_hw_count = 1; 506 507 if (pvs_name) 508 config.prop_name = pvs_name; 509 } 510 511 if (config.supported_hw) { 512 drv->cpus[cpu].opp_token = dev_pm_opp_set_config(cpu_dev, &config); 513 if (drv->cpus[cpu].opp_token < 0) { 514 ret = drv->cpus[cpu].opp_token; 515 dev_err(cpu_dev, "Failed to set OPP config\n"); 516 goto free_opp; 517 } 518 } 519 520 if (drv->data->pd_names) { 521 struct dev_pm_domain_attach_data attach_data = { 522 .pd_names = drv->data->pd_names, 523 .num_pd_names = drv->data->num_pd_names, 524 .pd_flags = PD_FLAG_DEV_LINK_ON | 525 PD_FLAG_REQUIRED_OPP, 526 }; 527 528 ret = dev_pm_domain_attach_list(cpu_dev, &attach_data, 529 &drv->cpus[cpu].pd_list); 530 if (ret < 0) 531 goto free_opp; 532 } 533 } 534 535 cpufreq_dt_pdev = platform_device_register_simple("cpufreq-dt", -1, 536 NULL, 0); 537 if (!IS_ERR(cpufreq_dt_pdev)) { 538 platform_set_drvdata(pdev, drv); 539 return 0; 540 } 541 542 ret = PTR_ERR(cpufreq_dt_pdev); 543 dev_err(cpu_dev, "Failed to register platform device\n"); 544 545 free_opp: 546 for_each_possible_cpu(cpu) { 547 dev_pm_domain_detach_list(drv->cpus[cpu].pd_list); 548 dev_pm_opp_clear_config(drv->cpus[cpu].opp_token); 549 } 550 return ret; 551 } 552 553 static void qcom_cpufreq_remove(struct platform_device *pdev) 554 { 555 struct qcom_cpufreq_drv *drv = platform_get_drvdata(pdev); 556 unsigned int cpu; 557 558 platform_device_unregister(cpufreq_dt_pdev); 559 560 for_each_possible_cpu(cpu) { 561 dev_pm_domain_detach_list(drv->cpus[cpu].pd_list); 562 dev_pm_opp_clear_config(drv->cpus[cpu].opp_token); 563 } 564 } 565 566 static int qcom_cpufreq_suspend(struct device *dev) 567 { 568 struct qcom_cpufreq_drv *drv = dev_get_drvdata(dev); 569 unsigned int cpu; 570 571 for_each_possible_cpu(cpu) 572 qcom_cpufreq_suspend_pd_devs(drv, cpu); 573 574 return 0; 575 } 576 577 static DEFINE_SIMPLE_DEV_PM_OPS(qcom_cpufreq_pm_ops, qcom_cpufreq_suspend, NULL); 578 579 static struct platform_driver qcom_cpufreq_driver = { 580 .probe = qcom_cpufreq_probe, 581 .remove = qcom_cpufreq_remove, 582 .driver = { 583 .name = "qcom-cpufreq-nvmem", 584 .pm = pm_sleep_ptr(&qcom_cpufreq_pm_ops), 585 }, 586 }; 587 588 static const struct of_device_id qcom_cpufreq_match_list[] __initconst __maybe_unused = { 589 { .compatible = "qcom,apq8096", .data = &match_data_kryo }, 590 { .compatible = "qcom,msm8909", .data = &match_data_msm8909 }, 591 { .compatible = "qcom,msm8996", .data = &match_data_kryo }, 592 { .compatible = "qcom,qcs404", .data = &match_data_qcs404 }, 593 { .compatible = "qcom,ipq5332", .data = &match_data_kryo }, 594 { .compatible = "qcom,ipq6018", .data = &match_data_ipq6018 }, 595 { .compatible = "qcom,ipq8064", .data = &match_data_ipq8064 }, 596 { .compatible = "qcom,ipq8074", .data = &match_data_ipq8074 }, 597 { .compatible = "qcom,apq8064", .data = &match_data_krait }, 598 { .compatible = "qcom,ipq9574", .data = &match_data_kryo }, 599 { .compatible = "qcom,msm8974", .data = &match_data_krait }, 600 { .compatible = "qcom,msm8960", .data = &match_data_krait }, 601 {}, 602 }; 603 MODULE_DEVICE_TABLE(of, qcom_cpufreq_match_list); 604 605 /* 606 * Since the driver depends on smem and nvmem drivers, which may 607 * return EPROBE_DEFER, all the real activity is done in the probe, 608 * which may be defered as well. The init here is only registering 609 * the driver and the platform device. 610 */ 611 static int __init qcom_cpufreq_init(void) 612 { 613 struct device_node *np __free(device_node) = of_find_node_by_path("/"); 614 const struct of_device_id *match; 615 int ret; 616 617 if (!np) 618 return -ENODEV; 619 620 match = of_match_node(qcom_cpufreq_match_list, np); 621 if (!match) 622 return -ENODEV; 623 624 ret = platform_driver_register(&qcom_cpufreq_driver); 625 if (unlikely(ret < 0)) 626 return ret; 627 628 cpufreq_pdev = platform_device_register_data(NULL, "qcom-cpufreq-nvmem", 629 -1, match, sizeof(*match)); 630 ret = PTR_ERR_OR_ZERO(cpufreq_pdev); 631 if (0 == ret) 632 return 0; 633 634 platform_driver_unregister(&qcom_cpufreq_driver); 635 return ret; 636 } 637 module_init(qcom_cpufreq_init); 638 639 static void __exit qcom_cpufreq_exit(void) 640 { 641 platform_device_unregister(cpufreq_pdev); 642 platform_driver_unregister(&qcom_cpufreq_driver); 643 } 644 module_exit(qcom_cpufreq_exit); 645 646 MODULE_DESCRIPTION("Qualcomm Technologies, Inc. CPUfreq driver"); 647 MODULE_LICENSE("GPL v2"); 648