1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 4 */ 5 6 /* 7 * In Certain QCOM SoCs like apq8096 and msm8996 that have KRYO processors, 8 * the CPU frequency subset and voltage value of each OPP varies 9 * based on the silicon variant in use. Qualcomm Process Voltage Scaling Tables 10 * defines the voltage and frequency value based on the msm-id in SMEM 11 * and speedbin blown in the efuse combination. 12 * The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC 13 * to provide the OPP framework with required information. 14 * This is used to determine the voltage and frequency value for each OPP of 15 * operating-points-v2 table when it is parsed by the OPP framework. 16 */ 17 18 #include <linux/cpu.h> 19 #include <linux/err.h> 20 #include <linux/init.h> 21 #include <linux/kernel.h> 22 #include <linux/module.h> 23 #include <linux/nvmem-consumer.h> 24 #include <linux/of.h> 25 #include <linux/platform_device.h> 26 #include <linux/pm.h> 27 #include <linux/pm_domain.h> 28 #include <linux/pm_opp.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/slab.h> 31 #include <linux/soc/qcom/smem.h> 32 33 #include <dt-bindings/arm/qcom,ids.h> 34 35 enum ipq806x_versions { 36 IPQ8062_VERSION = 0, 37 IPQ8064_VERSION, 38 IPQ8065_VERSION, 39 }; 40 41 #define IPQ6000_VERSION BIT(2) 42 43 enum ipq8074_versions { 44 IPQ8074_HAWKEYE_VERSION = 0, 45 IPQ8074_ACORN_VERSION, 46 }; 47 48 struct qcom_cpufreq_drv; 49 50 struct qcom_cpufreq_match_data { 51 int (*get_version)(struct device *cpu_dev, 52 struct nvmem_cell *speedbin_nvmem, 53 char **pvs_name, 54 struct qcom_cpufreq_drv *drv); 55 const char **pd_names; 56 unsigned int num_pd_names; 57 }; 58 59 struct qcom_cpufreq_drv_cpu { 60 int opp_token; 61 struct dev_pm_domain_list *pd_list; 62 }; 63 64 struct qcom_cpufreq_drv { 65 u32 versions; 66 const struct qcom_cpufreq_match_data *data; 67 struct qcom_cpufreq_drv_cpu cpus[]; 68 }; 69 70 static struct platform_device *cpufreq_dt_pdev, *cpufreq_pdev; 71 72 static int qcom_cpufreq_simple_get_version(struct device *cpu_dev, 73 struct nvmem_cell *speedbin_nvmem, 74 char **pvs_name, 75 struct qcom_cpufreq_drv *drv) 76 { 77 u8 *speedbin; 78 79 *pvs_name = NULL; 80 speedbin = nvmem_cell_read(speedbin_nvmem, NULL); 81 if (IS_ERR(speedbin)) 82 return PTR_ERR(speedbin); 83 84 dev_dbg(cpu_dev, "speedbin: %d\n", *speedbin); 85 drv->versions = 1 << *speedbin; 86 kfree(speedbin); 87 return 0; 88 } 89 90 static void get_krait_bin_format_a(struct device *cpu_dev, 91 int *speed, int *pvs, 92 u8 *buf) 93 { 94 u32 pte_efuse; 95 96 pte_efuse = *((u32 *)buf); 97 98 *speed = pte_efuse & 0xf; 99 if (*speed == 0xf) 100 *speed = (pte_efuse >> 4) & 0xf; 101 102 if (*speed == 0xf) { 103 *speed = 0; 104 dev_warn(cpu_dev, "Speed bin: Defaulting to %d\n", *speed); 105 } else { 106 dev_dbg(cpu_dev, "Speed bin: %d\n", *speed); 107 } 108 109 *pvs = (pte_efuse >> 10) & 0x7; 110 if (*pvs == 0x7) 111 *pvs = (pte_efuse >> 13) & 0x7; 112 113 if (*pvs == 0x7) { 114 *pvs = 0; 115 dev_warn(cpu_dev, "PVS bin: Defaulting to %d\n", *pvs); 116 } else { 117 dev_dbg(cpu_dev, "PVS bin: %d\n", *pvs); 118 } 119 } 120 121 static void get_krait_bin_format_b(struct device *cpu_dev, 122 int *speed, int *pvs, int *pvs_ver, 123 u8 *buf) 124 { 125 u32 pte_efuse, redundant_sel; 126 127 pte_efuse = *((u32 *)buf); 128 redundant_sel = (pte_efuse >> 24) & 0x7; 129 130 *pvs_ver = (pte_efuse >> 4) & 0x3; 131 132 switch (redundant_sel) { 133 case 1: 134 *pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7); 135 *speed = (pte_efuse >> 27) & 0xf; 136 break; 137 case 2: 138 *pvs = (pte_efuse >> 27) & 0xf; 139 *speed = pte_efuse & 0x7; 140 break; 141 default: 142 /* 4 bits of PVS are in efuse register bits 31, 8-6. */ 143 *pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7); 144 *speed = pte_efuse & 0x7; 145 } 146 147 /* Check SPEED_BIN_BLOW_STATUS */ 148 if (pte_efuse & BIT(3)) { 149 dev_dbg(cpu_dev, "Speed bin: %d\n", *speed); 150 } else { 151 dev_warn(cpu_dev, "Speed bin not set. Defaulting to 0!\n"); 152 *speed = 0; 153 } 154 155 /* Check PVS_BLOW_STATUS */ 156 pte_efuse = *(((u32 *)buf) + 1); 157 pte_efuse &= BIT(21); 158 if (pte_efuse) { 159 dev_dbg(cpu_dev, "PVS bin: %d\n", *pvs); 160 } else { 161 dev_warn(cpu_dev, "PVS bin not set. Defaulting to 0!\n"); 162 *pvs = 0; 163 } 164 165 dev_dbg(cpu_dev, "PVS version: %d\n", *pvs_ver); 166 } 167 168 static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev, 169 struct nvmem_cell *speedbin_nvmem, 170 char **pvs_name, 171 struct qcom_cpufreq_drv *drv) 172 { 173 size_t len; 174 u32 msm_id; 175 u8 *speedbin; 176 int ret; 177 *pvs_name = NULL; 178 179 ret = qcom_smem_get_soc_id(&msm_id); 180 if (ret) 181 return ret; 182 183 speedbin = nvmem_cell_read(speedbin_nvmem, &len); 184 if (IS_ERR(speedbin)) 185 return PTR_ERR(speedbin); 186 187 switch (msm_id) { 188 case QCOM_ID_MSM8996: 189 case QCOM_ID_APQ8096: 190 case QCOM_ID_IPQ5332: 191 case QCOM_ID_IPQ5322: 192 case QCOM_ID_IPQ5312: 193 case QCOM_ID_IPQ5302: 194 case QCOM_ID_IPQ5300: 195 case QCOM_ID_IPQ5321: 196 case QCOM_ID_IPQ9514: 197 case QCOM_ID_IPQ9550: 198 case QCOM_ID_IPQ9554: 199 case QCOM_ID_IPQ9570: 200 case QCOM_ID_IPQ9574: 201 drv->versions = 1 << (unsigned int)(*speedbin); 202 break; 203 case QCOM_ID_IPQ5200: 204 case QCOM_ID_IPQ5210: 205 case QCOM_ID_QCF2200: 206 case QCOM_ID_QCF3200: 207 case QCOM_ID_QCF3210: 208 drv->versions = (*speedbin == 0xcd) ? BIT(1) : BIT(0); 209 break; 210 case QCOM_ID_IPQ5424: 211 case QCOM_ID_IPQ5404: 212 drv->versions = (*speedbin == 0x3b) ? BIT(1) : BIT(0); 213 break; 214 case QCOM_ID_IPQ9610: 215 case QCOM_ID_IPQ9620: 216 case QCOM_ID_IPQ9630: 217 case QCOM_ID_IPQ9640: 218 case QCOM_ID_IPQ9650: 219 case QCOM_ID_IPQ9670: 220 drv->versions = (*speedbin == 0x4b) ? BIT(3) : BIT(2); 221 break; 222 case QCOM_ID_MSM8996SG: 223 case QCOM_ID_APQ8096SG: 224 drv->versions = 1 << ((unsigned int)(*speedbin) + 4); 225 break; 226 default: 227 BUG(); 228 break; 229 } 230 231 kfree(speedbin); 232 return 0; 233 } 234 235 static int qcom_cpufreq_krait_name_version(struct device *cpu_dev, 236 struct nvmem_cell *speedbin_nvmem, 237 char **pvs_name, 238 struct qcom_cpufreq_drv *drv) 239 { 240 int speed = 0, pvs = 0, pvs_ver = 0; 241 u8 *speedbin; 242 size_t len; 243 int ret = 0; 244 245 speedbin = nvmem_cell_read(speedbin_nvmem, &len); 246 247 if (IS_ERR(speedbin)) 248 return PTR_ERR(speedbin); 249 250 switch (len) { 251 case 4: 252 get_krait_bin_format_a(cpu_dev, &speed, &pvs, speedbin); 253 break; 254 case 8: 255 get_krait_bin_format_b(cpu_dev, &speed, &pvs, &pvs_ver, 256 speedbin); 257 break; 258 default: 259 dev_err(cpu_dev, "Unable to read nvmem data. Defaulting to 0!\n"); 260 ret = -ENODEV; 261 goto len_error; 262 } 263 264 snprintf(*pvs_name, sizeof("speedXX-pvsXX-vXX"), "speed%d-pvs%d-v%d", 265 speed, pvs, pvs_ver); 266 267 drv->versions = (1 << speed); 268 269 len_error: 270 kfree(speedbin); 271 return ret; 272 } 273 274 static const struct of_device_id qcom_cpufreq_ipq806x_match_list[] __maybe_unused = { 275 { .compatible = "qcom,ipq8062", .data = (const void *)QCOM_ID_IPQ8062 }, 276 { .compatible = "qcom,ipq8064", .data = (const void *)QCOM_ID_IPQ8064 }, 277 { .compatible = "qcom,ipq8065", .data = (const void *)QCOM_ID_IPQ8065 }, 278 { .compatible = "qcom,ipq8066", .data = (const void *)QCOM_ID_IPQ8066 }, 279 { .compatible = "qcom,ipq8068", .data = (const void *)QCOM_ID_IPQ8068 }, 280 { .compatible = "qcom,ipq8069", .data = (const void *)QCOM_ID_IPQ8069 }, 281 { /* sentinel */ } 282 }; 283 284 static int qcom_cpufreq_ipq8064_name_version(struct device *cpu_dev, 285 struct nvmem_cell *speedbin_nvmem, 286 char **pvs_name, 287 struct qcom_cpufreq_drv *drv) 288 { 289 int msm_id = -1, ret = 0; 290 int speed = 0, pvs = 0; 291 u8 *speedbin; 292 size_t len; 293 294 speedbin = nvmem_cell_read(speedbin_nvmem, &len); 295 if (IS_ERR(speedbin)) 296 return PTR_ERR(speedbin); 297 298 if (len != 4) { 299 dev_err(cpu_dev, "Unable to read nvmem data. Defaulting to 0!\n"); 300 ret = -ENODEV; 301 goto exit; 302 } 303 304 get_krait_bin_format_a(cpu_dev, &speed, &pvs, speedbin); 305 306 ret = qcom_smem_get_soc_id(&msm_id); 307 if (ret == -ENODEV) { 308 const struct of_device_id *match; 309 310 /* Fallback to compatible match with no SMEM initialized */ 311 match = of_machine_get_match(qcom_cpufreq_ipq806x_match_list); 312 if (!match) { 313 ret = -ENODEV; 314 goto exit; 315 } 316 317 /* We found a matching device, get the msm_id from the data entry */ 318 msm_id = (int)(uintptr_t)match->data; 319 ret = 0; 320 } else if (ret) { 321 goto exit; 322 } 323 324 switch (msm_id) { 325 case QCOM_ID_IPQ8062: 326 drv->versions = BIT(IPQ8062_VERSION); 327 break; 328 case QCOM_ID_IPQ8064: 329 case QCOM_ID_IPQ8066: 330 case QCOM_ID_IPQ8068: 331 drv->versions = BIT(IPQ8064_VERSION); 332 break; 333 case QCOM_ID_IPQ8065: 334 case QCOM_ID_IPQ8069: 335 drv->versions = BIT(IPQ8065_VERSION); 336 break; 337 default: 338 dev_err(cpu_dev, 339 "SoC ID %u is not part of IPQ8064 family, limiting to 1.0GHz!\n", 340 msm_id); 341 drv->versions = BIT(IPQ8062_VERSION); 342 break; 343 } 344 345 /* IPQ8064 speed is never fused. Only pvs values are fused. */ 346 snprintf(*pvs_name, sizeof("speed0-pvsXX"), "speed0-pvs%d", pvs); 347 348 exit: 349 kfree(speedbin); 350 return ret; 351 } 352 353 static int qcom_cpufreq_ipq6018_name_version(struct device *cpu_dev, 354 struct nvmem_cell *speedbin_nvmem, 355 char **pvs_name, 356 struct qcom_cpufreq_drv *drv) 357 { 358 u32 msm_id; 359 int ret; 360 u8 *speedbin; 361 *pvs_name = NULL; 362 363 ret = qcom_smem_get_soc_id(&msm_id); 364 if (ret) 365 return ret; 366 367 speedbin = nvmem_cell_read(speedbin_nvmem, NULL); 368 if (IS_ERR(speedbin)) 369 return PTR_ERR(speedbin); 370 371 switch (msm_id) { 372 case QCOM_ID_IPQ6005: 373 case QCOM_ID_IPQ6010: 374 case QCOM_ID_IPQ6018: 375 case QCOM_ID_IPQ6028: 376 /* Fuse Value Freq BIT to set 377 * --------------------------------- 378 * 2’b0 No Limit BIT(0) 379 * 2’b1 1.5 GHz BIT(1) 380 */ 381 drv->versions = 1 << (unsigned int)(*speedbin); 382 break; 383 case QCOM_ID_IPQ6000: 384 /* 385 * IPQ6018 family only has one bit to advertise the CPU 386 * speed-bin, but that is not enough for IPQ6000 which 387 * is only rated up to 1.2GHz. 388 * So for IPQ6000 manually set BIT(2) based on SMEM ID. 389 */ 390 drv->versions = IPQ6000_VERSION; 391 break; 392 default: 393 dev_err(cpu_dev, 394 "SoC ID %u is not part of IPQ6018 family, limiting to 1.2GHz!\n", 395 msm_id); 396 drv->versions = IPQ6000_VERSION; 397 break; 398 } 399 400 kfree(speedbin); 401 return 0; 402 } 403 404 static int qcom_cpufreq_ipq8074_name_version(struct device *cpu_dev, 405 struct nvmem_cell *speedbin_nvmem, 406 char **pvs_name, 407 struct qcom_cpufreq_drv *drv) 408 { 409 u32 msm_id; 410 int ret; 411 *pvs_name = NULL; 412 413 ret = qcom_smem_get_soc_id(&msm_id); 414 if (ret) 415 return ret; 416 417 switch (msm_id) { 418 case QCOM_ID_IPQ8070A: 419 case QCOM_ID_IPQ8071A: 420 case QCOM_ID_IPQ8172: 421 case QCOM_ID_IPQ8173: 422 case QCOM_ID_IPQ8174: 423 drv->versions = BIT(IPQ8074_ACORN_VERSION); 424 break; 425 case QCOM_ID_IPQ8072A: 426 case QCOM_ID_IPQ8074A: 427 case QCOM_ID_IPQ8076A: 428 case QCOM_ID_IPQ8078A: 429 drv->versions = BIT(IPQ8074_HAWKEYE_VERSION); 430 break; 431 default: 432 dev_err(cpu_dev, 433 "SoC ID %u is not part of IPQ8074 family, limiting to 1.4GHz!\n", 434 msm_id); 435 drv->versions = BIT(IPQ8074_ACORN_VERSION); 436 break; 437 } 438 439 return 0; 440 } 441 442 static const struct qcom_cpufreq_match_data match_data_kryo = { 443 .get_version = qcom_cpufreq_kryo_name_version, 444 }; 445 446 static const struct qcom_cpufreq_match_data match_data_krait = { 447 .get_version = qcom_cpufreq_krait_name_version, 448 }; 449 450 static const struct qcom_cpufreq_match_data match_data_msm8909 = { 451 .get_version = qcom_cpufreq_simple_get_version, 452 .pd_names = (const char *[]) { "perf" }, 453 .num_pd_names = 1, 454 }; 455 456 static const struct qcom_cpufreq_match_data match_data_qcs404 = { 457 .pd_names = (const char *[]) { "cpr" }, 458 .num_pd_names = 1, 459 }; 460 461 static const struct qcom_cpufreq_match_data match_data_ipq6018 = { 462 .get_version = qcom_cpufreq_ipq6018_name_version, 463 }; 464 465 static const struct qcom_cpufreq_match_data match_data_ipq8064 = { 466 .get_version = qcom_cpufreq_ipq8064_name_version, 467 }; 468 469 static const struct qcom_cpufreq_match_data match_data_ipq8074 = { 470 .get_version = qcom_cpufreq_ipq8074_name_version, 471 }; 472 473 static void qcom_cpufreq_suspend_pd_devs(struct qcom_cpufreq_drv *drv, unsigned int cpu) 474 { 475 struct dev_pm_domain_list *pd_list = drv->cpus[cpu].pd_list; 476 int i; 477 478 if (!pd_list) 479 return; 480 481 for (i = 0; i < pd_list->num_pds; i++) 482 device_set_awake_path(pd_list->pd_devs[i]); 483 } 484 485 static int qcom_cpufreq_probe(struct platform_device *pdev) 486 { 487 struct qcom_cpufreq_drv *drv; 488 struct nvmem_cell *speedbin_nvmem; 489 struct device *cpu_dev; 490 char pvs_name_buffer[] = "speedXX-pvsXX-vXX"; 491 char *pvs_name = pvs_name_buffer; 492 unsigned cpu; 493 const struct of_device_id *match; 494 int ret; 495 496 cpu_dev = get_cpu_device(0); 497 if (!cpu_dev) 498 return -ENODEV; 499 500 struct device_node *np __free(device_node) = 501 dev_pm_opp_of_get_opp_desc_node(cpu_dev); 502 if (!np) 503 return -ENOENT; 504 505 ret = of_device_is_compatible(np, "operating-points-v2-kryo-cpu") || 506 of_device_is_compatible(np, "operating-points-v2-krait-cpu"); 507 if (!ret) 508 return -ENOENT; 509 510 drv = devm_kzalloc(&pdev->dev, struct_size(drv, cpus, num_possible_cpus()), 511 GFP_KERNEL); 512 if (!drv) 513 return -ENOMEM; 514 515 match = pdev->dev.platform_data; 516 drv->data = match->data; 517 if (!drv->data) 518 return -ENODEV; 519 520 if (drv->data->get_version) { 521 speedbin_nvmem = of_nvmem_cell_get(np, NULL); 522 if (IS_ERR(speedbin_nvmem)) 523 return dev_err_probe(cpu_dev, PTR_ERR(speedbin_nvmem), 524 "Could not get nvmem cell\n"); 525 526 ret = drv->data->get_version(cpu_dev, 527 speedbin_nvmem, &pvs_name, drv); 528 if (ret) { 529 nvmem_cell_put(speedbin_nvmem); 530 return ret; 531 } 532 nvmem_cell_put(speedbin_nvmem); 533 } 534 535 for_each_present_cpu(cpu) { 536 struct dev_pm_opp_config config = { 537 .supported_hw = NULL, 538 }; 539 540 cpu_dev = get_cpu_device(cpu); 541 if (NULL == cpu_dev) { 542 ret = -ENODEV; 543 goto free_opp; 544 } 545 546 if (drv->data->get_version) { 547 config.supported_hw = &drv->versions; 548 config.supported_hw_count = 1; 549 550 if (pvs_name) 551 config.prop_name = pvs_name; 552 } 553 554 if (config.supported_hw) { 555 drv->cpus[cpu].opp_token = dev_pm_opp_set_config(cpu_dev, &config); 556 if (drv->cpus[cpu].opp_token < 0) { 557 ret = drv->cpus[cpu].opp_token; 558 dev_err(cpu_dev, "Failed to set OPP config\n"); 559 goto free_opp; 560 } 561 } 562 563 if (drv->data->pd_names) { 564 struct dev_pm_domain_attach_data attach_data = { 565 .pd_names = drv->data->pd_names, 566 .num_pd_names = drv->data->num_pd_names, 567 .pd_flags = PD_FLAG_DEV_LINK_ON | 568 PD_FLAG_REQUIRED_OPP, 569 }; 570 571 ret = dev_pm_domain_attach_list(cpu_dev, &attach_data, 572 &drv->cpus[cpu].pd_list); 573 if (ret < 0) 574 goto free_opp; 575 } 576 } 577 578 cpufreq_dt_pdev = platform_device_register_simple("cpufreq-dt", -1, 579 NULL, 0); 580 if (!IS_ERR(cpufreq_dt_pdev)) { 581 platform_set_drvdata(pdev, drv); 582 return 0; 583 } 584 585 ret = PTR_ERR(cpufreq_dt_pdev); 586 dev_err(cpu_dev, "Failed to register platform device\n"); 587 588 free_opp: 589 for_each_present_cpu(cpu) { 590 dev_pm_domain_detach_list(drv->cpus[cpu].pd_list); 591 dev_pm_opp_clear_config(drv->cpus[cpu].opp_token); 592 } 593 return ret; 594 } 595 596 static void qcom_cpufreq_remove(struct platform_device *pdev) 597 { 598 struct qcom_cpufreq_drv *drv = platform_get_drvdata(pdev); 599 unsigned int cpu; 600 601 platform_device_unregister(cpufreq_dt_pdev); 602 603 for_each_present_cpu(cpu) { 604 dev_pm_domain_detach_list(drv->cpus[cpu].pd_list); 605 dev_pm_opp_clear_config(drv->cpus[cpu].opp_token); 606 } 607 } 608 609 static int qcom_cpufreq_suspend(struct device *dev) 610 { 611 struct qcom_cpufreq_drv *drv = dev_get_drvdata(dev); 612 unsigned int cpu; 613 614 for_each_present_cpu(cpu) 615 qcom_cpufreq_suspend_pd_devs(drv, cpu); 616 617 return 0; 618 } 619 620 static DEFINE_SIMPLE_DEV_PM_OPS(qcom_cpufreq_pm_ops, qcom_cpufreq_suspend, NULL); 621 622 static struct platform_driver qcom_cpufreq_driver = { 623 .probe = qcom_cpufreq_probe, 624 .remove = qcom_cpufreq_remove, 625 .driver = { 626 .name = "qcom-cpufreq-nvmem", 627 .pm = pm_sleep_ptr(&qcom_cpufreq_pm_ops), 628 }, 629 }; 630 631 static const struct of_device_id qcom_cpufreq_match_list[] __initconst __maybe_unused = { 632 { .compatible = "qcom,apq8096", .data = &match_data_kryo }, 633 { .compatible = "qcom,msm8909", .data = &match_data_msm8909 }, 634 { .compatible = "qcom,msm8996", .data = &match_data_kryo }, 635 { .compatible = "qcom,qcs404", .data = &match_data_qcs404 }, 636 { .compatible = "qcom,ipq5210", .data = &match_data_kryo }, 637 { .compatible = "qcom,ipq5332", .data = &match_data_kryo }, 638 { .compatible = "qcom,ipq5424", .data = &match_data_kryo }, 639 { .compatible = "qcom,ipq6018", .data = &match_data_ipq6018 }, 640 { .compatible = "qcom,ipq8064", .data = &match_data_ipq8064 }, 641 { .compatible = "qcom,ipq8074", .data = &match_data_ipq8074 }, 642 { .compatible = "qcom,apq8064", .data = &match_data_krait }, 643 { .compatible = "qcom,ipq9574", .data = &match_data_kryo }, 644 { .compatible = "qcom,ipq9650", .data = &match_data_kryo }, 645 { .compatible = "qcom,msm8974", .data = &match_data_krait }, 646 { .compatible = "qcom,msm8960", .data = &match_data_krait }, 647 {}, 648 }; 649 MODULE_DEVICE_TABLE(of, qcom_cpufreq_match_list); 650 651 /* 652 * Since the driver depends on smem and nvmem drivers, which may 653 * return EPROBE_DEFER, all the real activity is done in the probe, 654 * which may be defered as well. The init here is only registering 655 * the driver and the platform device. 656 */ 657 static int __init qcom_cpufreq_init(void) 658 { 659 const struct of_device_id *match; 660 int ret; 661 662 match = of_machine_get_match(qcom_cpufreq_match_list); 663 if (!match) 664 return -ENODEV; 665 666 ret = platform_driver_register(&qcom_cpufreq_driver); 667 if (unlikely(ret < 0)) 668 return ret; 669 670 cpufreq_pdev = platform_device_register_data(NULL, "qcom-cpufreq-nvmem", 671 -1, match, sizeof(*match)); 672 ret = PTR_ERR_OR_ZERO(cpufreq_pdev); 673 if (0 == ret) 674 return 0; 675 676 platform_driver_unregister(&qcom_cpufreq_driver); 677 return ret; 678 } 679 module_init(qcom_cpufreq_init); 680 681 static void __exit qcom_cpufreq_exit(void) 682 { 683 platform_device_unregister(cpufreq_pdev); 684 platform_driver_unregister(&qcom_cpufreq_driver); 685 } 686 module_exit(qcom_cpufreq_exit); 687 688 MODULE_DESCRIPTION("Qualcomm Technologies, Inc. CPUfreq driver"); 689 MODULE_LICENSE("GPL v2"); 690