1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/bitfield.h> 7 #include <linux/clk-provider.h> 8 #include <linux/cpufreq.h> 9 #include <linux/init.h> 10 #include <linux/interconnect.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm_opp.h> 18 #include <linux/slab.h> 19 #include <linux/spinlock.h> 20 #include <linux/units.h> 21 22 #define LUT_MAX_ENTRIES 40U 23 #define LUT_SRC GENMASK(31, 30) 24 #define LUT_L_VAL GENMASK(7, 0) 25 #define LUT_CORE_COUNT GENMASK(18, 16) 26 #define LUT_VOLT GENMASK(11, 0) 27 #define CLK_HW_DIV 2 28 #define LUT_TURBO_IND 1 29 30 #define GT_IRQ_STATUS BIT(2) 31 32 #define MAX_FREQ_DOMAINS 4 33 34 struct qcom_cpufreq_soc_data { 35 u32 reg_enable; 36 u32 reg_domain_state; 37 u32 reg_dcvs_ctrl; 38 u32 reg_freq_lut; 39 u32 reg_volt_lut; 40 u32 reg_intr_clr; 41 u32 reg_current_vote; 42 u32 reg_perf_state; 43 u8 lut_row_size; 44 }; 45 46 struct qcom_cpufreq_data { 47 void __iomem *base; 48 49 /* 50 * Mutex to synchronize between de-init sequence and re-starting LMh 51 * polling/interrupts 52 */ 53 struct mutex throttle_lock; 54 int throttle_irq; 55 char irq_name[15]; 56 bool cancel_throttle; 57 struct delayed_work throttle_work; 58 struct cpufreq_policy *policy; 59 struct clk_hw cpu_clk; 60 61 bool per_core_dcvs; 62 }; 63 64 static struct { 65 struct qcom_cpufreq_data *data; 66 const struct qcom_cpufreq_soc_data *soc_data; 67 } qcom_cpufreq; 68 69 static unsigned long cpu_hw_rate, xo_rate; 70 static bool icc_scaling_enabled; 71 72 static int qcom_cpufreq_set_bw(struct cpufreq_policy *policy, 73 unsigned long freq_khz) 74 { 75 unsigned long freq_hz = freq_khz * 1000; 76 struct dev_pm_opp *opp; 77 struct device *dev; 78 int ret; 79 80 dev = get_cpu_device(policy->cpu); 81 if (!dev) 82 return -ENODEV; 83 84 opp = dev_pm_opp_find_freq_exact(dev, freq_hz, true); 85 if (IS_ERR(opp)) 86 return PTR_ERR(opp); 87 88 ret = dev_pm_opp_set_opp(dev, opp); 89 dev_pm_opp_put(opp); 90 return ret; 91 } 92 93 static int qcom_cpufreq_update_opp(struct device *cpu_dev, 94 unsigned long freq_khz, 95 unsigned long volt) 96 { 97 unsigned long freq_hz = freq_khz * 1000; 98 int ret; 99 100 /* Skip voltage update if the opp table is not available */ 101 if (!icc_scaling_enabled) 102 return dev_pm_opp_add(cpu_dev, freq_hz, volt); 103 104 ret = dev_pm_opp_adjust_voltage(cpu_dev, freq_hz, volt, volt, volt); 105 if (ret) { 106 dev_err(cpu_dev, "Voltage update failed freq=%ld\n", freq_khz); 107 return ret; 108 } 109 110 return dev_pm_opp_enable(cpu_dev, freq_hz); 111 } 112 113 static int qcom_cpufreq_hw_target_index(struct cpufreq_policy *policy, 114 unsigned int index) 115 { 116 struct qcom_cpufreq_data *data = policy->driver_data; 117 const struct qcom_cpufreq_soc_data *soc_data = qcom_cpufreq.soc_data; 118 unsigned long freq = policy->freq_table[index].frequency; 119 unsigned int i; 120 121 writel_relaxed(index, data->base + soc_data->reg_perf_state); 122 123 if (data->per_core_dcvs) 124 for (i = 1; i < cpumask_weight(policy->related_cpus); i++) 125 writel_relaxed(index, data->base + soc_data->reg_perf_state + i * 4); 126 127 if (icc_scaling_enabled) 128 qcom_cpufreq_set_bw(policy, freq); 129 130 return 0; 131 } 132 133 static unsigned long qcom_lmh_get_throttle_freq(struct qcom_cpufreq_data *data) 134 { 135 unsigned int lval; 136 137 if (qcom_cpufreq.soc_data->reg_current_vote) 138 lval = readl_relaxed(data->base + qcom_cpufreq.soc_data->reg_current_vote) & 0x3ff; 139 else 140 lval = readl_relaxed(data->base + qcom_cpufreq.soc_data->reg_domain_state) & 0xff; 141 142 return lval * xo_rate; 143 } 144 145 /* Get the frequency requested by the cpufreq core for the CPU */ 146 static unsigned int qcom_cpufreq_get_freq(struct cpufreq_policy *policy) 147 { 148 struct qcom_cpufreq_data *data; 149 const struct qcom_cpufreq_soc_data *soc_data; 150 unsigned int index; 151 152 if (!policy) 153 return 0; 154 155 data = policy->driver_data; 156 soc_data = qcom_cpufreq.soc_data; 157 158 index = readl_relaxed(data->base + soc_data->reg_perf_state); 159 index = min(index, LUT_MAX_ENTRIES - 1); 160 161 return policy->freq_table[index].frequency; 162 } 163 164 static unsigned int __qcom_cpufreq_hw_get(struct cpufreq_policy *policy) 165 { 166 struct qcom_cpufreq_data *data; 167 168 if (!policy) 169 return 0; 170 171 data = policy->driver_data; 172 173 if (data->throttle_irq >= 0) 174 return qcom_lmh_get_throttle_freq(data) / HZ_PER_KHZ; 175 176 return qcom_cpufreq_get_freq(policy); 177 } 178 179 static unsigned int qcom_cpufreq_hw_get(unsigned int cpu) 180 { 181 return __qcom_cpufreq_hw_get(cpufreq_cpu_get_raw(cpu)); 182 } 183 184 static unsigned int qcom_cpufreq_hw_fast_switch(struct cpufreq_policy *policy, 185 unsigned int target_freq) 186 { 187 struct qcom_cpufreq_data *data = policy->driver_data; 188 const struct qcom_cpufreq_soc_data *soc_data = qcom_cpufreq.soc_data; 189 unsigned int index; 190 unsigned int i; 191 192 index = policy->cached_resolved_idx; 193 writel_relaxed(index, data->base + soc_data->reg_perf_state); 194 195 if (data->per_core_dcvs) 196 for (i = 1; i < cpumask_weight(policy->related_cpus); i++) 197 writel_relaxed(index, data->base + soc_data->reg_perf_state + i * 4); 198 199 return policy->freq_table[index].frequency; 200 } 201 202 static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev, 203 struct cpufreq_policy *policy) 204 { 205 u32 data, src, lval, i, core_count, prev_freq = 0, freq; 206 u32 volt; 207 struct cpufreq_frequency_table *table; 208 struct dev_pm_opp *opp; 209 unsigned long rate; 210 int ret; 211 struct qcom_cpufreq_data *drv_data = policy->driver_data; 212 const struct qcom_cpufreq_soc_data *soc_data = qcom_cpufreq.soc_data; 213 214 table = kcalloc(LUT_MAX_ENTRIES + 1, sizeof(*table), GFP_KERNEL); 215 if (!table) 216 return -ENOMEM; 217 218 ret = dev_pm_opp_of_add_table(cpu_dev); 219 if (!ret) { 220 /* Disable all opps and cross-validate against LUT later */ 221 icc_scaling_enabled = true; 222 for (rate = 0; ; rate++) { 223 opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate); 224 if (IS_ERR(opp)) 225 break; 226 227 dev_pm_opp_put(opp); 228 dev_pm_opp_disable(cpu_dev, rate); 229 } 230 } else if (ret != -ENODEV) { 231 dev_err(cpu_dev, "Invalid opp table in device tree\n"); 232 kfree(table); 233 return ret; 234 } else { 235 policy->fast_switch_possible = true; 236 icc_scaling_enabled = false; 237 } 238 239 for (i = 0; i < LUT_MAX_ENTRIES; i++) { 240 data = readl_relaxed(drv_data->base + soc_data->reg_freq_lut + 241 i * soc_data->lut_row_size); 242 src = FIELD_GET(LUT_SRC, data); 243 lval = FIELD_GET(LUT_L_VAL, data); 244 core_count = FIELD_GET(LUT_CORE_COUNT, data); 245 246 data = readl_relaxed(drv_data->base + soc_data->reg_volt_lut + 247 i * soc_data->lut_row_size); 248 volt = FIELD_GET(LUT_VOLT, data) * 1000; 249 250 if (src) 251 freq = xo_rate * lval / 1000; 252 else 253 freq = cpu_hw_rate / 1000; 254 255 if (freq != prev_freq && core_count != LUT_TURBO_IND) { 256 if (!qcom_cpufreq_update_opp(cpu_dev, freq, volt)) { 257 table[i].frequency = freq; 258 dev_dbg(cpu_dev, "index=%d freq=%d, core_count %d\n", i, 259 freq, core_count); 260 } else { 261 dev_warn(cpu_dev, "failed to update OPP for freq=%d\n", freq); 262 table[i].frequency = CPUFREQ_ENTRY_INVALID; 263 } 264 265 } else if (core_count == LUT_TURBO_IND) { 266 table[i].frequency = CPUFREQ_ENTRY_INVALID; 267 } 268 269 /* 270 * Two of the same frequencies with the same core counts means 271 * end of table 272 */ 273 if (i > 0 && prev_freq == freq) { 274 struct cpufreq_frequency_table *prev = &table[i - 1]; 275 276 /* 277 * Only treat the last frequency that might be a boost 278 * as the boost frequency 279 */ 280 if (prev->frequency == CPUFREQ_ENTRY_INVALID) { 281 if (!qcom_cpufreq_update_opp(cpu_dev, prev_freq, volt)) { 282 prev->frequency = prev_freq; 283 prev->flags = CPUFREQ_BOOST_FREQ; 284 } else { 285 dev_warn(cpu_dev, "failed to update OPP for freq=%d\n", 286 freq); 287 } 288 } 289 290 break; 291 } 292 293 prev_freq = freq; 294 } 295 296 table[i].frequency = CPUFREQ_TABLE_END; 297 policy->freq_table = table; 298 dev_pm_opp_set_sharing_cpus(cpu_dev, policy->cpus); 299 300 return 0; 301 } 302 303 static void qcom_get_related_cpus(int index, struct cpumask *m) 304 { 305 struct device_node *cpu_np; 306 struct of_phandle_args args; 307 int cpu, ret; 308 309 for_each_present_cpu(cpu) { 310 cpu_np = of_cpu_device_node_get(cpu); 311 if (!cpu_np) 312 continue; 313 314 ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain", 315 "#freq-domain-cells", 0, 316 &args); 317 of_node_put(cpu_np); 318 if (ret < 0) 319 continue; 320 321 if (index == args.args[0]) 322 cpumask_set_cpu(cpu, m); 323 } 324 } 325 326 static void qcom_lmh_dcvs_notify(struct qcom_cpufreq_data *data) 327 { 328 struct cpufreq_policy *policy = data->policy; 329 int cpu = cpumask_first(policy->related_cpus); 330 struct device *dev = get_cpu_device(cpu); 331 unsigned long freq_hz, throttled_freq; 332 struct dev_pm_opp *opp; 333 334 /* 335 * Get the h/w throttled frequency, normalize it using the 336 * registered opp table and use it to calculate thermal pressure. 337 */ 338 freq_hz = qcom_lmh_get_throttle_freq(data); 339 340 opp = dev_pm_opp_find_freq_floor(dev, &freq_hz); 341 if (IS_ERR(opp) && PTR_ERR(opp) == -ERANGE) 342 opp = dev_pm_opp_find_freq_ceil(dev, &freq_hz); 343 344 if (IS_ERR(opp)) { 345 dev_warn(dev, "Can't find the OPP for throttling: %pe!\n", opp); 346 } else { 347 dev_pm_opp_put(opp); 348 } 349 350 throttled_freq = freq_hz / HZ_PER_KHZ; 351 352 /* Update HW pressure (the boost frequencies are accepted) */ 353 arch_update_hw_pressure(policy->related_cpus, throttled_freq); 354 355 /* 356 * In the unlikely case policy is unregistered do not enable 357 * polling or h/w interrupt 358 */ 359 mutex_lock(&data->throttle_lock); 360 if (data->cancel_throttle) 361 goto out; 362 363 /* 364 * If h/w throttled frequency is higher than what cpufreq has requested 365 * for, then stop polling and switch back to interrupt mechanism. 366 */ 367 if (throttled_freq >= qcom_cpufreq_get_freq(cpufreq_cpu_get_raw(cpu))) 368 enable_irq(data->throttle_irq); 369 else 370 mod_delayed_work(system_highpri_wq, &data->throttle_work, 371 msecs_to_jiffies(10)); 372 373 out: 374 mutex_unlock(&data->throttle_lock); 375 } 376 377 static void qcom_lmh_dcvs_poll(struct work_struct *work) 378 { 379 struct qcom_cpufreq_data *data; 380 381 data = container_of(work, struct qcom_cpufreq_data, throttle_work.work); 382 qcom_lmh_dcvs_notify(data); 383 } 384 385 static irqreturn_t qcom_lmh_dcvs_handle_irq(int irq, void *data) 386 { 387 struct qcom_cpufreq_data *c_data = data; 388 389 /* Disable interrupt and enable polling */ 390 disable_irq_nosync(c_data->throttle_irq); 391 schedule_delayed_work(&c_data->throttle_work, 0); 392 393 if (qcom_cpufreq.soc_data->reg_intr_clr) 394 writel_relaxed(GT_IRQ_STATUS, 395 c_data->base + qcom_cpufreq.soc_data->reg_intr_clr); 396 397 return IRQ_HANDLED; 398 } 399 400 static const struct qcom_cpufreq_soc_data qcom_soc_data = { 401 .reg_enable = 0x0, 402 .reg_dcvs_ctrl = 0xbc, 403 .reg_freq_lut = 0x110, 404 .reg_volt_lut = 0x114, 405 .reg_current_vote = 0x704, 406 .reg_perf_state = 0x920, 407 .lut_row_size = 32, 408 }; 409 410 static const struct qcom_cpufreq_soc_data epss_soc_data = { 411 .reg_enable = 0x0, 412 .reg_domain_state = 0x20, 413 .reg_dcvs_ctrl = 0xb0, 414 .reg_freq_lut = 0x100, 415 .reg_volt_lut = 0x200, 416 .reg_intr_clr = 0x308, 417 .reg_perf_state = 0x320, 418 .lut_row_size = 4, 419 }; 420 421 static const struct of_device_id qcom_cpufreq_hw_match[] = { 422 { .compatible = "qcom,cpufreq-hw", .data = &qcom_soc_data }, 423 { .compatible = "qcom,cpufreq-epss", .data = &epss_soc_data }, 424 {} 425 }; 426 MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match); 427 428 static int qcom_cpufreq_hw_lmh_init(struct cpufreq_policy *policy, int index) 429 { 430 struct qcom_cpufreq_data *data = policy->driver_data; 431 struct platform_device *pdev = cpufreq_get_driver_data(); 432 int ret; 433 434 /* 435 * Look for LMh interrupt. If no interrupt line is specified / 436 * if there is an error, allow cpufreq to be enabled as usual. 437 */ 438 data->throttle_irq = platform_get_irq_optional(pdev, index); 439 if (data->throttle_irq == -ENXIO) 440 return 0; 441 if (data->throttle_irq < 0) 442 return data->throttle_irq; 443 444 data->cancel_throttle = false; 445 446 mutex_init(&data->throttle_lock); 447 INIT_DEFERRABLE_WORK(&data->throttle_work, qcom_lmh_dcvs_poll); 448 449 snprintf(data->irq_name, sizeof(data->irq_name), "dcvsh-irq-%u", policy->cpu); 450 ret = request_threaded_irq(data->throttle_irq, NULL, qcom_lmh_dcvs_handle_irq, 451 IRQF_ONESHOT | IRQF_NO_AUTOEN, data->irq_name, data); 452 if (ret) { 453 dev_err(&pdev->dev, "Error registering %s: %d\n", data->irq_name, ret); 454 return 0; 455 } 456 457 ret = irq_set_affinity_and_hint(data->throttle_irq, policy->cpus); 458 if (ret) 459 dev_err(&pdev->dev, "Failed to set CPU affinity of %s[%d]\n", 460 data->irq_name, data->throttle_irq); 461 462 return 0; 463 } 464 465 static int qcom_cpufreq_hw_cpu_online(struct cpufreq_policy *policy) 466 { 467 struct qcom_cpufreq_data *data = policy->driver_data; 468 struct platform_device *pdev = cpufreq_get_driver_data(); 469 int ret; 470 471 if (data->throttle_irq <= 0) 472 return 0; 473 474 mutex_lock(&data->throttle_lock); 475 data->cancel_throttle = false; 476 mutex_unlock(&data->throttle_lock); 477 478 ret = irq_set_affinity_and_hint(data->throttle_irq, policy->cpus); 479 if (ret) 480 dev_err(&pdev->dev, "Failed to set CPU affinity of %s[%d]\n", 481 data->irq_name, data->throttle_irq); 482 483 return ret; 484 } 485 486 static int qcom_cpufreq_hw_cpu_offline(struct cpufreq_policy *policy) 487 { 488 struct qcom_cpufreq_data *data = policy->driver_data; 489 490 if (data->throttle_irq <= 0) 491 return 0; 492 493 mutex_lock(&data->throttle_lock); 494 data->cancel_throttle = true; 495 mutex_unlock(&data->throttle_lock); 496 497 cancel_delayed_work_sync(&data->throttle_work); 498 irq_set_affinity_and_hint(data->throttle_irq, NULL); 499 disable_irq_nosync(data->throttle_irq); 500 501 return 0; 502 } 503 504 static void qcom_cpufreq_hw_lmh_exit(struct qcom_cpufreq_data *data) 505 { 506 if (data->throttle_irq <= 0) 507 return; 508 509 free_irq(data->throttle_irq, data); 510 } 511 512 static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) 513 { 514 struct platform_device *pdev = cpufreq_get_driver_data(); 515 struct device *dev = &pdev->dev; 516 struct of_phandle_args args; 517 struct device_node *cpu_np; 518 struct device *cpu_dev; 519 struct qcom_cpufreq_data *data; 520 int ret, index; 521 522 cpu_dev = get_cpu_device(policy->cpu); 523 if (!cpu_dev) { 524 pr_err("%s: failed to get cpu%d device\n", __func__, 525 policy->cpu); 526 return -ENODEV; 527 } 528 529 cpu_np = of_cpu_device_node_get(policy->cpu); 530 if (!cpu_np) 531 return -EINVAL; 532 533 ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain", 534 "#freq-domain-cells", 0, &args); 535 of_node_put(cpu_np); 536 if (ret) 537 return ret; 538 539 index = args.args[0]; 540 data = &qcom_cpufreq.data[index]; 541 542 /* HW should be in enabled state to proceed */ 543 if (!(readl_relaxed(data->base + qcom_cpufreq.soc_data->reg_enable) & 0x1)) { 544 dev_err(dev, "Domain-%d cpufreq hardware not enabled\n", index); 545 return -ENODEV; 546 } 547 548 if (readl_relaxed(data->base + qcom_cpufreq.soc_data->reg_dcvs_ctrl) & 0x1) 549 data->per_core_dcvs = true; 550 551 qcom_get_related_cpus(index, policy->cpus); 552 553 policy->driver_data = data; 554 policy->dvfs_possible_from_any_cpu = true; 555 data->policy = policy; 556 557 ret = qcom_cpufreq_hw_read_lut(cpu_dev, policy); 558 if (ret) { 559 dev_err(dev, "Domain-%d failed to read LUT\n", index); 560 return ret; 561 } 562 563 ret = dev_pm_opp_get_opp_count(cpu_dev); 564 if (ret <= 0) { 565 dev_err(cpu_dev, "Failed to add OPPs\n"); 566 return -ENODEV; 567 } 568 569 return qcom_cpufreq_hw_lmh_init(policy, index); 570 } 571 572 static void qcom_cpufreq_hw_cpu_exit(struct cpufreq_policy *policy) 573 { 574 struct device *cpu_dev = get_cpu_device(policy->cpu); 575 struct qcom_cpufreq_data *data = policy->driver_data; 576 577 dev_pm_opp_remove_all_dynamic(cpu_dev); 578 dev_pm_opp_of_cpumask_remove_table(policy->related_cpus); 579 qcom_cpufreq_hw_lmh_exit(data); 580 kfree(policy->freq_table); 581 kfree(data); 582 } 583 584 static void qcom_cpufreq_ready(struct cpufreq_policy *policy) 585 { 586 struct qcom_cpufreq_data *data = policy->driver_data; 587 588 if (data->throttle_irq >= 0) 589 enable_irq(data->throttle_irq); 590 } 591 592 static struct cpufreq_driver cpufreq_qcom_hw_driver = { 593 .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK | 594 CPUFREQ_HAVE_GOVERNOR_PER_POLICY | 595 CPUFREQ_IS_COOLING_DEV, 596 .verify = cpufreq_generic_frequency_table_verify, 597 .target_index = qcom_cpufreq_hw_target_index, 598 .get = qcom_cpufreq_hw_get, 599 .init = qcom_cpufreq_hw_cpu_init, 600 .exit = qcom_cpufreq_hw_cpu_exit, 601 .online = qcom_cpufreq_hw_cpu_online, 602 .offline = qcom_cpufreq_hw_cpu_offline, 603 .register_em = cpufreq_register_em_with_opp, 604 .fast_switch = qcom_cpufreq_hw_fast_switch, 605 .name = "qcom-cpufreq-hw", 606 .ready = qcom_cpufreq_ready, 607 .set_boost = cpufreq_boost_set_sw, 608 }; 609 610 static unsigned long qcom_cpufreq_hw_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 611 { 612 struct qcom_cpufreq_data *data = container_of(hw, struct qcom_cpufreq_data, cpu_clk); 613 614 return __qcom_cpufreq_hw_get(data->policy) * HZ_PER_KHZ; 615 } 616 617 /* 618 * Since we cannot determine the closest rate of the target rate, let's just 619 * return the actual rate at which the clock is running at. This is needed to 620 * make clk_set_rate() API work properly. 621 */ 622 static int qcom_cpufreq_hw_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) 623 { 624 req->rate = qcom_cpufreq_hw_recalc_rate(hw, 0); 625 626 return 0; 627 } 628 629 static const struct clk_ops qcom_cpufreq_hw_clk_ops = { 630 .recalc_rate = qcom_cpufreq_hw_recalc_rate, 631 .determine_rate = qcom_cpufreq_hw_determine_rate, 632 }; 633 634 static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev) 635 { 636 struct clk_hw_onecell_data *clk_data; 637 struct device *dev = &pdev->dev; 638 struct device *cpu_dev; 639 struct clk *clk; 640 int ret, i, num_domains; 641 642 clk = clk_get(dev, "xo"); 643 if (IS_ERR(clk)) 644 return PTR_ERR(clk); 645 646 xo_rate = clk_get_rate(clk); 647 clk_put(clk); 648 649 clk = clk_get(dev, "alternate"); 650 if (IS_ERR(clk)) 651 return PTR_ERR(clk); 652 653 cpu_hw_rate = clk_get_rate(clk) / CLK_HW_DIV; 654 clk_put(clk); 655 656 cpufreq_qcom_hw_driver.driver_data = pdev; 657 658 /* Check for optional interconnect paths on CPU0 */ 659 cpu_dev = get_cpu_device(0); 660 if (!cpu_dev) 661 return -EPROBE_DEFER; 662 663 ret = dev_pm_opp_of_find_icc_paths(cpu_dev, NULL); 664 if (ret) 665 return dev_err_probe(dev, ret, "Failed to find icc paths\n"); 666 667 for (num_domains = 0; num_domains < MAX_FREQ_DOMAINS; num_domains++) 668 if (!platform_get_resource(pdev, IORESOURCE_MEM, num_domains)) 669 break; 670 671 qcom_cpufreq.data = devm_kzalloc(dev, sizeof(struct qcom_cpufreq_data) * num_domains, 672 GFP_KERNEL); 673 if (!qcom_cpufreq.data) 674 return -ENOMEM; 675 676 qcom_cpufreq.soc_data = of_device_get_match_data(dev); 677 if (!qcom_cpufreq.soc_data) 678 return -ENODEV; 679 680 clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, num_domains), GFP_KERNEL); 681 if (!clk_data) 682 return -ENOMEM; 683 684 clk_data->num = num_domains; 685 686 for (i = 0; i < num_domains; i++) { 687 struct qcom_cpufreq_data *data = &qcom_cpufreq.data[i]; 688 struct clk_init_data clk_init = {}; 689 void __iomem *base; 690 691 base = devm_platform_ioremap_resource(pdev, i); 692 if (IS_ERR(base)) { 693 dev_err(dev, "Failed to map resource index %d\n", i); 694 return PTR_ERR(base); 695 } 696 697 data->base = base; 698 699 /* Register CPU clock for each frequency domain */ 700 clk_init.name = kasprintf(GFP_KERNEL, "qcom_cpufreq%d", i); 701 if (!clk_init.name) 702 return -ENOMEM; 703 704 clk_init.flags = CLK_GET_RATE_NOCACHE; 705 clk_init.ops = &qcom_cpufreq_hw_clk_ops; 706 data->cpu_clk.init = &clk_init; 707 708 ret = devm_clk_hw_register(dev, &data->cpu_clk); 709 if (ret < 0) { 710 dev_err(dev, "Failed to register clock %d: %d\n", i, ret); 711 kfree(clk_init.name); 712 return ret; 713 } 714 715 clk_data->hws[i] = &data->cpu_clk; 716 kfree(clk_init.name); 717 } 718 719 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data); 720 if (ret < 0) { 721 dev_err(dev, "Failed to add clock provider\n"); 722 return ret; 723 } 724 725 ret = cpufreq_register_driver(&cpufreq_qcom_hw_driver); 726 if (ret) 727 dev_err(dev, "CPUFreq HW driver failed to register\n"); 728 else 729 dev_dbg(dev, "QCOM CPUFreq HW driver initialized\n"); 730 731 return ret; 732 } 733 734 static void qcom_cpufreq_hw_driver_remove(struct platform_device *pdev) 735 { 736 cpufreq_unregister_driver(&cpufreq_qcom_hw_driver); 737 } 738 739 static struct platform_driver qcom_cpufreq_hw_driver = { 740 .probe = qcom_cpufreq_hw_driver_probe, 741 .remove = qcom_cpufreq_hw_driver_remove, 742 .driver = { 743 .name = "qcom-cpufreq-hw", 744 .of_match_table = qcom_cpufreq_hw_match, 745 }, 746 }; 747 748 static int __init qcom_cpufreq_hw_init(void) 749 { 750 return platform_driver_register(&qcom_cpufreq_hw_driver); 751 } 752 postcore_initcall(qcom_cpufreq_hw_init); 753 754 static void __exit qcom_cpufreq_hw_exit(void) 755 { 756 platform_driver_unregister(&qcom_cpufreq_hw_driver); 757 } 758 module_exit(qcom_cpufreq_hw_exit); 759 760 MODULE_DESCRIPTION("QCOM CPUFREQ HW Driver"); 761 MODULE_LICENSE("GPL v2"); 762