1 /* 2 * Copyright (C) 2002 - 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org> 3 * and Markus Demleitner <msdemlei@cl.uni-heidelberg.de> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This driver adds basic cpufreq support for SMU & 970FX based G5 Macs, 10 * that is iMac G5 and latest single CPU desktop. 11 */ 12 13 #undef DEBUG 14 15 #include <linux/module.h> 16 #include <linux/types.h> 17 #include <linux/errno.h> 18 #include <linux/kernel.h> 19 #include <linux/delay.h> 20 #include <linux/sched.h> 21 #include <linux/cpufreq.h> 22 #include <linux/init.h> 23 #include <linux/completion.h> 24 #include <linux/mutex.h> 25 #include <linux/of_device.h> 26 #include <asm/prom.h> 27 #include <asm/machdep.h> 28 #include <asm/irq.h> 29 #include <asm/sections.h> 30 #include <asm/cputable.h> 31 #include <asm/time.h> 32 #include <asm/smu.h> 33 #include <asm/pmac_pfunc.h> 34 35 #define DBG(fmt...) pr_debug(fmt) 36 37 /* see 970FX user manual */ 38 39 #define SCOM_PCR 0x0aa001 /* PCR scom addr */ 40 41 #define PCR_HILO_SELECT 0x80000000U /* 1 = PCR, 0 = PCRH */ 42 #define PCR_SPEED_FULL 0x00000000U /* 1:1 speed value */ 43 #define PCR_SPEED_HALF 0x00020000U /* 1:2 speed value */ 44 #define PCR_SPEED_QUARTER 0x00040000U /* 1:4 speed value */ 45 #define PCR_SPEED_MASK 0x000e0000U /* speed mask */ 46 #define PCR_SPEED_SHIFT 17 47 #define PCR_FREQ_REQ_VALID 0x00010000U /* freq request valid */ 48 #define PCR_VOLT_REQ_VALID 0x00008000U /* volt request valid */ 49 #define PCR_TARGET_TIME_MASK 0x00006000U /* target time */ 50 #define PCR_STATLAT_MASK 0x00001f00U /* STATLAT value */ 51 #define PCR_SNOOPLAT_MASK 0x000000f0U /* SNOOPLAT value */ 52 #define PCR_SNOOPACC_MASK 0x0000000fU /* SNOOPACC value */ 53 54 #define SCOM_PSR 0x408001 /* PSR scom addr */ 55 /* warning: PSR is a 64 bits register */ 56 #define PSR_CMD_RECEIVED 0x2000000000000000U /* command received */ 57 #define PSR_CMD_COMPLETED 0x1000000000000000U /* command completed */ 58 #define PSR_CUR_SPEED_MASK 0x0300000000000000U /* current speed */ 59 #define PSR_CUR_SPEED_SHIFT (56) 60 61 /* 62 * The G5 only supports two frequencies (Quarter speed is not supported) 63 */ 64 #define CPUFREQ_HIGH 0 65 #define CPUFREQ_LOW 1 66 67 static struct cpufreq_frequency_table g5_cpu_freqs[] = { 68 {CPUFREQ_HIGH, 0}, 69 {CPUFREQ_LOW, 0}, 70 {0, CPUFREQ_TABLE_END}, 71 }; 72 73 static struct freq_attr* g5_cpu_freqs_attr[] = { 74 &cpufreq_freq_attr_scaling_available_freqs, 75 NULL, 76 }; 77 78 /* Power mode data is an array of the 32 bits PCR values to use for 79 * the various frequencies, retrieved from the device-tree 80 */ 81 static int g5_pmode_cur; 82 83 static void (*g5_switch_volt)(int speed_mode); 84 static int (*g5_switch_freq)(int speed_mode); 85 static int (*g5_query_freq)(void); 86 87 static DEFINE_MUTEX(g5_switch_mutex); 88 89 static unsigned long transition_latency; 90 91 #ifdef CONFIG_PMAC_SMU 92 93 static const u32 *g5_pmode_data; 94 static int g5_pmode_max; 95 96 static struct smu_sdbp_fvt *g5_fvt_table; /* table of op. points */ 97 static int g5_fvt_count; /* number of op. points */ 98 static int g5_fvt_cur; /* current op. point */ 99 100 /* 101 * SMU based voltage switching for Neo2 platforms 102 */ 103 104 static void g5_smu_switch_volt(int speed_mode) 105 { 106 struct smu_simple_cmd cmd; 107 108 DECLARE_COMPLETION_ONSTACK(comp); 109 smu_queue_simple(&cmd, SMU_CMD_POWER_COMMAND, 8, smu_done_complete, 110 &comp, 'V', 'S', 'L', 'E', 'W', 111 0xff, g5_fvt_cur+1, speed_mode); 112 wait_for_completion(&comp); 113 } 114 115 /* 116 * Platform function based voltage/vdnap switching for Neo2 117 */ 118 119 static struct pmf_function *pfunc_set_vdnap0; 120 static struct pmf_function *pfunc_vdnap0_complete; 121 122 static void g5_vdnap_switch_volt(int speed_mode) 123 { 124 struct pmf_args args; 125 u32 slew, done = 0; 126 unsigned long timeout; 127 128 slew = (speed_mode == CPUFREQ_LOW) ? 1 : 0; 129 args.count = 1; 130 args.u[0].p = &slew; 131 132 pmf_call_one(pfunc_set_vdnap0, &args); 133 134 /* It's an irq GPIO so we should be able to just block here, 135 * I'll do that later after I've properly tested the IRQ code for 136 * platform functions 137 */ 138 timeout = jiffies + HZ/10; 139 while(!time_after(jiffies, timeout)) { 140 args.count = 1; 141 args.u[0].p = &done; 142 pmf_call_one(pfunc_vdnap0_complete, &args); 143 if (done) 144 break; 145 msleep(1); 146 } 147 if (done == 0) 148 printk(KERN_WARNING "cpufreq: Timeout in clock slewing !\n"); 149 } 150 151 152 /* 153 * SCOM based frequency switching for 970FX rev3 154 */ 155 static int g5_scom_switch_freq(int speed_mode) 156 { 157 unsigned long flags; 158 int to; 159 160 /* If frequency is going up, first ramp up the voltage */ 161 if (speed_mode < g5_pmode_cur) 162 g5_switch_volt(speed_mode); 163 164 local_irq_save(flags); 165 166 /* Clear PCR high */ 167 scom970_write(SCOM_PCR, 0); 168 /* Clear PCR low */ 169 scom970_write(SCOM_PCR, PCR_HILO_SELECT | 0); 170 /* Set PCR low */ 171 scom970_write(SCOM_PCR, PCR_HILO_SELECT | 172 g5_pmode_data[speed_mode]); 173 174 /* Wait for completion */ 175 for (to = 0; to < 10; to++) { 176 unsigned long psr = scom970_read(SCOM_PSR); 177 178 if ((psr & PSR_CMD_RECEIVED) == 0 && 179 (((psr >> PSR_CUR_SPEED_SHIFT) ^ 180 (g5_pmode_data[speed_mode] >> PCR_SPEED_SHIFT)) & 0x3) 181 == 0) 182 break; 183 if (psr & PSR_CMD_COMPLETED) 184 break; 185 udelay(100); 186 } 187 188 local_irq_restore(flags); 189 190 /* If frequency is going down, last ramp the voltage */ 191 if (speed_mode > g5_pmode_cur) 192 g5_switch_volt(speed_mode); 193 194 g5_pmode_cur = speed_mode; 195 ppc_proc_freq = g5_cpu_freqs[speed_mode].frequency * 1000ul; 196 197 return 0; 198 } 199 200 static int g5_scom_query_freq(void) 201 { 202 unsigned long psr = scom970_read(SCOM_PSR); 203 int i; 204 205 for (i = 0; i <= g5_pmode_max; i++) 206 if ((((psr >> PSR_CUR_SPEED_SHIFT) ^ 207 (g5_pmode_data[i] >> PCR_SPEED_SHIFT)) & 0x3) == 0) 208 break; 209 return i; 210 } 211 212 /* 213 * Fake voltage switching for platforms with missing support 214 */ 215 216 static void g5_dummy_switch_volt(int speed_mode) 217 { 218 } 219 220 #endif /* CONFIG_PMAC_SMU */ 221 222 /* 223 * Platform function based voltage switching for PowerMac7,2 & 7,3 224 */ 225 226 static struct pmf_function *pfunc_cpu0_volt_high; 227 static struct pmf_function *pfunc_cpu0_volt_low; 228 static struct pmf_function *pfunc_cpu1_volt_high; 229 static struct pmf_function *pfunc_cpu1_volt_low; 230 231 static void g5_pfunc_switch_volt(int speed_mode) 232 { 233 if (speed_mode == CPUFREQ_HIGH) { 234 if (pfunc_cpu0_volt_high) 235 pmf_call_one(pfunc_cpu0_volt_high, NULL); 236 if (pfunc_cpu1_volt_high) 237 pmf_call_one(pfunc_cpu1_volt_high, NULL); 238 } else { 239 if (pfunc_cpu0_volt_low) 240 pmf_call_one(pfunc_cpu0_volt_low, NULL); 241 if (pfunc_cpu1_volt_low) 242 pmf_call_one(pfunc_cpu1_volt_low, NULL); 243 } 244 msleep(10); /* should be faster , to fix */ 245 } 246 247 /* 248 * Platform function based frequency switching for PowerMac7,2 & 7,3 249 */ 250 251 static struct pmf_function *pfunc_cpu_setfreq_high; 252 static struct pmf_function *pfunc_cpu_setfreq_low; 253 static struct pmf_function *pfunc_cpu_getfreq; 254 static struct pmf_function *pfunc_slewing_done; 255 256 static int g5_pfunc_switch_freq(int speed_mode) 257 { 258 struct pmf_args args; 259 u32 done = 0; 260 unsigned long timeout; 261 int rc; 262 263 DBG("g5_pfunc_switch_freq(%d)\n", speed_mode); 264 265 /* If frequency is going up, first ramp up the voltage */ 266 if (speed_mode < g5_pmode_cur) 267 g5_switch_volt(speed_mode); 268 269 /* Do it */ 270 if (speed_mode == CPUFREQ_HIGH) 271 rc = pmf_call_one(pfunc_cpu_setfreq_high, NULL); 272 else 273 rc = pmf_call_one(pfunc_cpu_setfreq_low, NULL); 274 275 if (rc) 276 printk(KERN_WARNING "cpufreq: pfunc switch error %d\n", rc); 277 278 /* It's an irq GPIO so we should be able to just block here, 279 * I'll do that later after I've properly tested the IRQ code for 280 * platform functions 281 */ 282 timeout = jiffies + HZ/10; 283 while(!time_after(jiffies, timeout)) { 284 args.count = 1; 285 args.u[0].p = &done; 286 pmf_call_one(pfunc_slewing_done, &args); 287 if (done) 288 break; 289 msleep(1); 290 } 291 if (done == 0) 292 printk(KERN_WARNING "cpufreq: Timeout in clock slewing !\n"); 293 294 /* If frequency is going down, last ramp the voltage */ 295 if (speed_mode > g5_pmode_cur) 296 g5_switch_volt(speed_mode); 297 298 g5_pmode_cur = speed_mode; 299 ppc_proc_freq = g5_cpu_freqs[speed_mode].frequency * 1000ul; 300 301 return 0; 302 } 303 304 static int g5_pfunc_query_freq(void) 305 { 306 struct pmf_args args; 307 u32 val = 0; 308 309 args.count = 1; 310 args.u[0].p = &val; 311 pmf_call_one(pfunc_cpu_getfreq, &args); 312 return val ? CPUFREQ_HIGH : CPUFREQ_LOW; 313 } 314 315 316 /* 317 * Common interface to the cpufreq core 318 */ 319 320 static int g5_cpufreq_verify(struct cpufreq_policy *policy) 321 { 322 return cpufreq_frequency_table_verify(policy, g5_cpu_freqs); 323 } 324 325 static int g5_cpufreq_target(struct cpufreq_policy *policy, 326 unsigned int target_freq, unsigned int relation) 327 { 328 unsigned int newstate = 0; 329 struct cpufreq_freqs freqs; 330 int rc; 331 332 if (cpufreq_frequency_table_target(policy, g5_cpu_freqs, 333 target_freq, relation, &newstate)) 334 return -EINVAL; 335 336 if (g5_pmode_cur == newstate) 337 return 0; 338 339 mutex_lock(&g5_switch_mutex); 340 341 freqs.old = g5_cpu_freqs[g5_pmode_cur].frequency; 342 freqs.new = g5_cpu_freqs[newstate].frequency; 343 344 cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE); 345 rc = g5_switch_freq(newstate); 346 cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE); 347 348 mutex_unlock(&g5_switch_mutex); 349 350 return rc; 351 } 352 353 static unsigned int g5_cpufreq_get_speed(unsigned int cpu) 354 { 355 return g5_cpu_freqs[g5_pmode_cur].frequency; 356 } 357 358 static int g5_cpufreq_cpu_init(struct cpufreq_policy *policy) 359 { 360 policy->cpuinfo.transition_latency = transition_latency; 361 policy->cur = g5_cpu_freqs[g5_query_freq()].frequency; 362 /* secondary CPUs are tied to the primary one by the 363 * cpufreq core if in the secondary policy we tell it that 364 * it actually must be one policy together with all others. */ 365 cpumask_copy(policy->cpus, cpu_online_mask); 366 cpufreq_frequency_table_get_attr(g5_cpu_freqs, policy->cpu); 367 368 return cpufreq_frequency_table_cpuinfo(policy, 369 g5_cpu_freqs); 370 } 371 372 373 static struct cpufreq_driver g5_cpufreq_driver = { 374 .name = "powermac", 375 .flags = CPUFREQ_CONST_LOOPS, 376 .init = g5_cpufreq_cpu_init, 377 .verify = g5_cpufreq_verify, 378 .target = g5_cpufreq_target, 379 .get = g5_cpufreq_get_speed, 380 .attr = g5_cpu_freqs_attr, 381 }; 382 383 384 #ifdef CONFIG_PMAC_SMU 385 386 static int __init g5_neo2_cpufreq_init(struct device_node *cpunode) 387 { 388 unsigned int psize, ssize; 389 unsigned long max_freq; 390 char *freq_method, *volt_method; 391 const u32 *valp; 392 u32 pvr_hi; 393 int use_volts_vdnap = 0; 394 int use_volts_smu = 0; 395 int rc = -ENODEV; 396 397 /* Check supported platforms */ 398 if (of_machine_is_compatible("PowerMac8,1") || 399 of_machine_is_compatible("PowerMac8,2") || 400 of_machine_is_compatible("PowerMac9,1")) 401 use_volts_smu = 1; 402 else if (of_machine_is_compatible("PowerMac11,2")) 403 use_volts_vdnap = 1; 404 else 405 return -ENODEV; 406 407 /* Check 970FX for now */ 408 valp = of_get_property(cpunode, "cpu-version", NULL); 409 if (!valp) { 410 DBG("No cpu-version property !\n"); 411 goto bail_noprops; 412 } 413 pvr_hi = (*valp) >> 16; 414 if (pvr_hi != 0x3c && pvr_hi != 0x44) { 415 printk(KERN_ERR "cpufreq: Unsupported CPU version\n"); 416 goto bail_noprops; 417 } 418 419 /* Look for the powertune data in the device-tree */ 420 g5_pmode_data = of_get_property(cpunode, "power-mode-data",&psize); 421 if (!g5_pmode_data) { 422 DBG("No power-mode-data !\n"); 423 goto bail_noprops; 424 } 425 g5_pmode_max = psize / sizeof(u32) - 1; 426 427 if (use_volts_smu) { 428 const struct smu_sdbp_header *shdr; 429 430 /* Look for the FVT table */ 431 shdr = smu_get_sdb_partition(SMU_SDB_FVT_ID, NULL); 432 if (!shdr) 433 goto bail_noprops; 434 g5_fvt_table = (struct smu_sdbp_fvt *)&shdr[1]; 435 ssize = (shdr->len * sizeof(u32)) - sizeof(*shdr); 436 g5_fvt_count = ssize / sizeof(*g5_fvt_table); 437 g5_fvt_cur = 0; 438 439 /* Sanity checking */ 440 if (g5_fvt_count < 1 || g5_pmode_max < 1) 441 goto bail_noprops; 442 443 g5_switch_volt = g5_smu_switch_volt; 444 volt_method = "SMU"; 445 } else if (use_volts_vdnap) { 446 struct device_node *root; 447 448 root = of_find_node_by_path("/"); 449 if (root == NULL) { 450 printk(KERN_ERR "cpufreq: Can't find root of " 451 "device tree\n"); 452 goto bail_noprops; 453 } 454 pfunc_set_vdnap0 = pmf_find_function(root, "set-vdnap0"); 455 pfunc_vdnap0_complete = 456 pmf_find_function(root, "slewing-done"); 457 if (pfunc_set_vdnap0 == NULL || 458 pfunc_vdnap0_complete == NULL) { 459 printk(KERN_ERR "cpufreq: Can't find required " 460 "platform function\n"); 461 goto bail_noprops; 462 } 463 464 g5_switch_volt = g5_vdnap_switch_volt; 465 volt_method = "GPIO"; 466 } else { 467 g5_switch_volt = g5_dummy_switch_volt; 468 volt_method = "none"; 469 } 470 471 /* 472 * From what I see, clock-frequency is always the maximal frequency. 473 * The current driver can not slew sysclk yet, so we really only deal 474 * with powertune steps for now. We also only implement full freq and 475 * half freq in this version. So far, I haven't yet seen a machine 476 * supporting anything else. 477 */ 478 valp = of_get_property(cpunode, "clock-frequency", NULL); 479 if (!valp) 480 return -ENODEV; 481 max_freq = (*valp)/1000; 482 g5_cpu_freqs[0].frequency = max_freq; 483 g5_cpu_freqs[1].frequency = max_freq/2; 484 485 /* Set callbacks */ 486 transition_latency = 12000; 487 g5_switch_freq = g5_scom_switch_freq; 488 g5_query_freq = g5_scom_query_freq; 489 freq_method = "SCOM"; 490 491 /* Force apply current frequency to make sure everything is in 492 * sync (voltage is right for example). Firmware may leave us with 493 * a strange setting ... 494 */ 495 g5_switch_volt(CPUFREQ_HIGH); 496 msleep(10); 497 g5_pmode_cur = -1; 498 g5_switch_freq(g5_query_freq()); 499 500 printk(KERN_INFO "Registering G5 CPU frequency driver\n"); 501 printk(KERN_INFO "Frequency method: %s, Voltage method: %s\n", 502 freq_method, volt_method); 503 printk(KERN_INFO "Low: %d Mhz, High: %d Mhz, Cur: %d MHz\n", 504 g5_cpu_freqs[1].frequency/1000, 505 g5_cpu_freqs[0].frequency/1000, 506 g5_cpu_freqs[g5_pmode_cur].frequency/1000); 507 508 rc = cpufreq_register_driver(&g5_cpufreq_driver); 509 510 /* We keep the CPU node on hold... hopefully, Apple G5 don't have 511 * hotplug CPU with a dynamic device-tree ... 512 */ 513 return rc; 514 515 bail_noprops: 516 of_node_put(cpunode); 517 518 return rc; 519 } 520 521 #endif /* CONFIG_PMAC_SMU */ 522 523 524 static int __init g5_pm72_cpufreq_init(struct device_node *cpunode) 525 { 526 struct device_node *cpuid = NULL, *hwclock = NULL; 527 const u8 *eeprom = NULL; 528 const u32 *valp; 529 u64 max_freq, min_freq, ih, il; 530 int has_volt = 1, rc = 0; 531 532 DBG("cpufreq: Initializing for PowerMac7,2, PowerMac7,3 and" 533 " RackMac3,1...\n"); 534 535 /* Lookup the cpuid eeprom node */ 536 cpuid = of_find_node_by_path("/u3@0,f8000000/i2c@f8001000/cpuid@a0"); 537 if (cpuid != NULL) 538 eeprom = of_get_property(cpuid, "cpuid", NULL); 539 if (eeprom == NULL) { 540 printk(KERN_ERR "cpufreq: Can't find cpuid EEPROM !\n"); 541 rc = -ENODEV; 542 goto bail; 543 } 544 545 /* Lookup the i2c hwclock */ 546 for (hwclock = NULL; 547 (hwclock = of_find_node_by_name(hwclock, "i2c-hwclock")) != NULL;){ 548 const char *loc = of_get_property(hwclock, 549 "hwctrl-location", NULL); 550 if (loc == NULL) 551 continue; 552 if (strcmp(loc, "CPU CLOCK")) 553 continue; 554 if (!of_get_property(hwclock, "platform-get-frequency", NULL)) 555 continue; 556 break; 557 } 558 if (hwclock == NULL) { 559 printk(KERN_ERR "cpufreq: Can't find i2c clock chip !\n"); 560 rc = -ENODEV; 561 goto bail; 562 } 563 564 DBG("cpufreq: i2c clock chip found: %s\n", hwclock->full_name); 565 566 /* Now get all the platform functions */ 567 pfunc_cpu_getfreq = 568 pmf_find_function(hwclock, "get-frequency"); 569 pfunc_cpu_setfreq_high = 570 pmf_find_function(hwclock, "set-frequency-high"); 571 pfunc_cpu_setfreq_low = 572 pmf_find_function(hwclock, "set-frequency-low"); 573 pfunc_slewing_done = 574 pmf_find_function(hwclock, "slewing-done"); 575 pfunc_cpu0_volt_high = 576 pmf_find_function(hwclock, "set-voltage-high-0"); 577 pfunc_cpu0_volt_low = 578 pmf_find_function(hwclock, "set-voltage-low-0"); 579 pfunc_cpu1_volt_high = 580 pmf_find_function(hwclock, "set-voltage-high-1"); 581 pfunc_cpu1_volt_low = 582 pmf_find_function(hwclock, "set-voltage-low-1"); 583 584 /* Check we have minimum requirements */ 585 if (pfunc_cpu_getfreq == NULL || pfunc_cpu_setfreq_high == NULL || 586 pfunc_cpu_setfreq_low == NULL || pfunc_slewing_done == NULL) { 587 printk(KERN_ERR "cpufreq: Can't find platform functions !\n"); 588 rc = -ENODEV; 589 goto bail; 590 } 591 592 /* Check that we have complete sets */ 593 if (pfunc_cpu0_volt_high == NULL || pfunc_cpu0_volt_low == NULL) { 594 pmf_put_function(pfunc_cpu0_volt_high); 595 pmf_put_function(pfunc_cpu0_volt_low); 596 pfunc_cpu0_volt_high = pfunc_cpu0_volt_low = NULL; 597 has_volt = 0; 598 } 599 if (!has_volt || 600 pfunc_cpu1_volt_high == NULL || pfunc_cpu1_volt_low == NULL) { 601 pmf_put_function(pfunc_cpu1_volt_high); 602 pmf_put_function(pfunc_cpu1_volt_low); 603 pfunc_cpu1_volt_high = pfunc_cpu1_volt_low = NULL; 604 } 605 606 /* Note: The device tree also contains a "platform-set-values" 607 * function for which I haven't quite figured out the usage. It 608 * might have to be called on init and/or wakeup, I'm not too sure 609 * but things seem to work fine without it so far ... 610 */ 611 612 /* Get max frequency from device-tree */ 613 valp = of_get_property(cpunode, "clock-frequency", NULL); 614 if (!valp) { 615 printk(KERN_ERR "cpufreq: Can't find CPU frequency !\n"); 616 rc = -ENODEV; 617 goto bail; 618 } 619 620 max_freq = (*valp)/1000; 621 622 /* Now calculate reduced frequency by using the cpuid input freq 623 * ratio. This requires 64 bits math unless we are willing to lose 624 * some precision 625 */ 626 ih = *((u32 *)(eeprom + 0x10)); 627 il = *((u32 *)(eeprom + 0x20)); 628 629 /* Check for machines with no useful settings */ 630 if (il == ih) { 631 printk(KERN_WARNING "cpufreq: No low frequency mode available" 632 " on this model !\n"); 633 rc = -ENODEV; 634 goto bail; 635 } 636 637 min_freq = 0; 638 if (ih != 0 && il != 0) 639 min_freq = (max_freq * il) / ih; 640 641 /* Sanity check */ 642 if (min_freq >= max_freq || min_freq < 1000) { 643 printk(KERN_ERR "cpufreq: Can't calculate low frequency !\n"); 644 rc = -ENXIO; 645 goto bail; 646 } 647 g5_cpu_freqs[0].frequency = max_freq; 648 g5_cpu_freqs[1].frequency = min_freq; 649 650 /* Set callbacks */ 651 transition_latency = CPUFREQ_ETERNAL; 652 g5_switch_volt = g5_pfunc_switch_volt; 653 g5_switch_freq = g5_pfunc_switch_freq; 654 g5_query_freq = g5_pfunc_query_freq; 655 656 /* Force apply current frequency to make sure everything is in 657 * sync (voltage is right for example). Firmware may leave us with 658 * a strange setting ... 659 */ 660 g5_switch_volt(CPUFREQ_HIGH); 661 msleep(10); 662 g5_pmode_cur = -1; 663 g5_switch_freq(g5_query_freq()); 664 665 printk(KERN_INFO "Registering G5 CPU frequency driver\n"); 666 printk(KERN_INFO "Frequency method: i2c/pfunc, " 667 "Voltage method: %s\n", has_volt ? "i2c/pfunc" : "none"); 668 printk(KERN_INFO "Low: %d Mhz, High: %d Mhz, Cur: %d MHz\n", 669 g5_cpu_freqs[1].frequency/1000, 670 g5_cpu_freqs[0].frequency/1000, 671 g5_cpu_freqs[g5_pmode_cur].frequency/1000); 672 673 rc = cpufreq_register_driver(&g5_cpufreq_driver); 674 bail: 675 if (rc != 0) { 676 pmf_put_function(pfunc_cpu_getfreq); 677 pmf_put_function(pfunc_cpu_setfreq_high); 678 pmf_put_function(pfunc_cpu_setfreq_low); 679 pmf_put_function(pfunc_slewing_done); 680 pmf_put_function(pfunc_cpu0_volt_high); 681 pmf_put_function(pfunc_cpu0_volt_low); 682 pmf_put_function(pfunc_cpu1_volt_high); 683 pmf_put_function(pfunc_cpu1_volt_low); 684 } 685 of_node_put(hwclock); 686 of_node_put(cpuid); 687 of_node_put(cpunode); 688 689 return rc; 690 } 691 692 static int __init g5_cpufreq_init(void) 693 { 694 struct device_node *cpunode; 695 int rc = 0; 696 697 /* Get first CPU node */ 698 cpunode = of_cpu_device_node_get(0); 699 if (cpunode == NULL) { 700 pr_err("cpufreq: Can't find any CPU node\n"); 701 return -ENODEV; 702 } 703 704 if (of_machine_is_compatible("PowerMac7,2") || 705 of_machine_is_compatible("PowerMac7,3") || 706 of_machine_is_compatible("RackMac3,1")) 707 rc = g5_pm72_cpufreq_init(cpunode); 708 #ifdef CONFIG_PMAC_SMU 709 else 710 rc = g5_neo2_cpufreq_init(cpunode); 711 #endif /* CONFIG_PMAC_SMU */ 712 713 return rc; 714 } 715 716 module_init(g5_cpufreq_init); 717 718 719 MODULE_LICENSE("GPL"); 720