1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 Linaro Ltd. 4 * Author: Pi-Cheng Chen <pi-cheng.chen@linaro.org> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/cpu.h> 9 #include <linux/cpufreq.h> 10 #include <linux/cpumask.h> 11 #include <linux/minmax.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/of_platform.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_opp.h> 17 #include <linux/regulator/consumer.h> 18 19 struct mtk_cpufreq_platform_data { 20 int min_volt_shift; 21 int max_volt_shift; 22 int proc_max_volt; 23 int sram_min_volt; 24 int sram_max_volt; 25 bool ccifreq_supported; 26 }; 27 28 /* 29 * The struct mtk_cpu_dvfs_info holds necessary information for doing CPU DVFS 30 * on each CPU power/clock domain of Mediatek SoCs. Each CPU cluster in 31 * Mediatek SoCs has two voltage inputs, Vproc and Vsram. In some cases the two 32 * voltage inputs need to be controlled under a hardware limitation: 33 * 100mV < Vsram - Vproc < 200mV 34 * 35 * When scaling the clock frequency of a CPU clock domain, the clock source 36 * needs to be switched to another stable PLL clock temporarily until 37 * the original PLL becomes stable at target frequency. 38 */ 39 struct mtk_cpu_dvfs_info { 40 struct cpumask cpus; 41 struct device *cpu_dev; 42 struct device *cci_dev; 43 struct regulator *proc_reg; 44 struct regulator *sram_reg; 45 struct clk *cpu_clk; 46 struct clk *inter_clk; 47 struct list_head list_head; 48 int intermediate_voltage; 49 bool need_voltage_tracking; 50 int vproc_on_boot; 51 int pre_vproc; 52 /* Avoid race condition for regulators between notify and policy */ 53 struct mutex reg_lock; 54 struct notifier_block opp_nb; 55 unsigned int opp_cpu; 56 unsigned long current_freq; 57 const struct mtk_cpufreq_platform_data *soc_data; 58 int vtrack_max; 59 bool ccifreq_bound; 60 }; 61 62 static struct platform_device *cpufreq_pdev; 63 64 static LIST_HEAD(dvfs_info_list); 65 66 static struct mtk_cpu_dvfs_info *mtk_cpu_dvfs_info_lookup(int cpu) 67 { 68 struct mtk_cpu_dvfs_info *info; 69 70 list_for_each_entry(info, &dvfs_info_list, list_head) { 71 if (cpumask_test_cpu(cpu, &info->cpus)) 72 return info; 73 } 74 75 return NULL; 76 } 77 78 static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info, 79 int new_vproc) 80 { 81 const struct mtk_cpufreq_platform_data *soc_data = info->soc_data; 82 struct regulator *proc_reg = info->proc_reg; 83 struct regulator *sram_reg = info->sram_reg; 84 int pre_vproc, pre_vsram, new_vsram, vsram, vproc, ret; 85 int retry = info->vtrack_max; 86 87 pre_vproc = regulator_get_voltage(proc_reg); 88 if (pre_vproc < 0) { 89 dev_err(info->cpu_dev, 90 "invalid Vproc value: %d\n", pre_vproc); 91 return pre_vproc; 92 } 93 94 pre_vsram = regulator_get_voltage(sram_reg); 95 if (pre_vsram < 0) { 96 dev_err(info->cpu_dev, "invalid Vsram value: %d\n", pre_vsram); 97 return pre_vsram; 98 } 99 100 new_vsram = clamp(new_vproc + soc_data->min_volt_shift, 101 soc_data->sram_min_volt, soc_data->sram_max_volt); 102 103 do { 104 if (pre_vproc <= new_vproc) { 105 vsram = clamp(pre_vproc + soc_data->max_volt_shift, 106 soc_data->sram_min_volt, new_vsram); 107 ret = regulator_set_voltage(sram_reg, vsram, 108 soc_data->sram_max_volt); 109 110 if (ret) 111 return ret; 112 113 if (vsram == soc_data->sram_max_volt || 114 new_vsram == soc_data->sram_min_volt) 115 vproc = new_vproc; 116 else 117 vproc = vsram - soc_data->min_volt_shift; 118 119 ret = regulator_set_voltage(proc_reg, vproc, 120 soc_data->proc_max_volt); 121 if (ret) { 122 regulator_set_voltage(sram_reg, pre_vsram, 123 soc_data->sram_max_volt); 124 return ret; 125 } 126 } else { 127 vproc = max(new_vproc, 128 pre_vsram - soc_data->max_volt_shift); 129 ret = regulator_set_voltage(proc_reg, vproc, 130 soc_data->proc_max_volt); 131 if (ret) 132 return ret; 133 134 if (vproc == new_vproc) 135 vsram = new_vsram; 136 else 137 vsram = max(new_vsram, 138 vproc + soc_data->min_volt_shift); 139 140 ret = regulator_set_voltage(sram_reg, vsram, 141 soc_data->sram_max_volt); 142 if (ret) { 143 regulator_set_voltage(proc_reg, pre_vproc, 144 soc_data->proc_max_volt); 145 return ret; 146 } 147 } 148 149 pre_vproc = vproc; 150 pre_vsram = vsram; 151 152 if (--retry < 0) { 153 dev_err(info->cpu_dev, 154 "over loop count, failed to set voltage\n"); 155 return -EINVAL; 156 } 157 } while (vproc != new_vproc || vsram != new_vsram); 158 159 return 0; 160 } 161 162 static int mtk_cpufreq_set_voltage(struct mtk_cpu_dvfs_info *info, int vproc) 163 { 164 const struct mtk_cpufreq_platform_data *soc_data = info->soc_data; 165 int ret; 166 167 if (info->need_voltage_tracking) 168 ret = mtk_cpufreq_voltage_tracking(info, vproc); 169 else 170 ret = regulator_set_voltage(info->proc_reg, vproc, 171 soc_data->proc_max_volt); 172 if (!ret) 173 info->pre_vproc = vproc; 174 175 return ret; 176 } 177 178 static bool is_ccifreq_ready(struct mtk_cpu_dvfs_info *info) 179 { 180 struct device_link *sup_link; 181 182 if (info->ccifreq_bound) 183 return true; 184 185 sup_link = device_link_add(info->cpu_dev, info->cci_dev, 186 DL_FLAG_AUTOREMOVE_CONSUMER); 187 if (!sup_link) { 188 dev_err(info->cpu_dev, "cpu%d: sup_link is NULL\n", info->opp_cpu); 189 return false; 190 } 191 192 if (sup_link->supplier->links.status != DL_DEV_DRIVER_BOUND) 193 return false; 194 195 info->ccifreq_bound = true; 196 197 return true; 198 } 199 200 static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, 201 unsigned int index) 202 { 203 struct cpufreq_frequency_table *freq_table = policy->freq_table; 204 struct clk *cpu_clk = policy->clk; 205 struct clk *armpll = clk_get_parent(cpu_clk); 206 struct mtk_cpu_dvfs_info *info = policy->driver_data; 207 struct device *cpu_dev = info->cpu_dev; 208 struct dev_pm_opp *opp; 209 long freq_hz, pre_freq_hz; 210 int vproc, pre_vproc, inter_vproc, target_vproc, ret; 211 212 inter_vproc = info->intermediate_voltage; 213 214 pre_freq_hz = clk_get_rate(cpu_clk); 215 216 mutex_lock(&info->reg_lock); 217 218 if (unlikely(info->pre_vproc <= 0)) 219 pre_vproc = regulator_get_voltage(info->proc_reg); 220 else 221 pre_vproc = info->pre_vproc; 222 223 if (pre_vproc < 0) { 224 dev_err(cpu_dev, "invalid Vproc value: %d\n", pre_vproc); 225 ret = pre_vproc; 226 goto out; 227 } 228 229 freq_hz = freq_table[index].frequency * 1000; 230 231 opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz); 232 if (IS_ERR(opp)) { 233 dev_err(cpu_dev, "cpu%d: failed to find OPP for %ld\n", 234 policy->cpu, freq_hz); 235 ret = PTR_ERR(opp); 236 goto out; 237 } 238 vproc = dev_pm_opp_get_voltage(opp); 239 dev_pm_opp_put(opp); 240 241 /* 242 * If MediaTek cci is supported but is not ready, we will use the value 243 * of max(target cpu voltage, booting voltage) to prevent high freqeuncy 244 * low voltage crash. 245 */ 246 if (info->soc_data->ccifreq_supported && !is_ccifreq_ready(info)) 247 vproc = max(vproc, info->vproc_on_boot); 248 249 /* 250 * If the new voltage or the intermediate voltage is higher than the 251 * current voltage, scale up voltage first. 252 */ 253 target_vproc = max(inter_vproc, vproc); 254 if (pre_vproc <= target_vproc) { 255 ret = mtk_cpufreq_set_voltage(info, target_vproc); 256 if (ret) { 257 dev_err(cpu_dev, 258 "cpu%d: failed to scale up voltage!\n", policy->cpu); 259 mtk_cpufreq_set_voltage(info, pre_vproc); 260 goto out; 261 } 262 } 263 264 /* Reparent the CPU clock to intermediate clock. */ 265 ret = clk_set_parent(cpu_clk, info->inter_clk); 266 if (ret) { 267 dev_err(cpu_dev, 268 "cpu%d: failed to re-parent cpu clock!\n", policy->cpu); 269 mtk_cpufreq_set_voltage(info, pre_vproc); 270 goto out; 271 } 272 273 /* Set the original PLL to target rate. */ 274 ret = clk_set_rate(armpll, freq_hz); 275 if (ret) { 276 dev_err(cpu_dev, 277 "cpu%d: failed to scale cpu clock rate!\n", policy->cpu); 278 clk_set_parent(cpu_clk, armpll); 279 mtk_cpufreq_set_voltage(info, pre_vproc); 280 goto out; 281 } 282 283 /* Set parent of CPU clock back to the original PLL. */ 284 ret = clk_set_parent(cpu_clk, armpll); 285 if (ret) { 286 dev_err(cpu_dev, 287 "cpu%d: failed to re-parent cpu clock!\n", policy->cpu); 288 mtk_cpufreq_set_voltage(info, inter_vproc); 289 goto out; 290 } 291 292 /* 293 * If the new voltage is lower than the intermediate voltage or the 294 * original voltage, scale down to the new voltage. 295 */ 296 if (vproc < inter_vproc || vproc < pre_vproc) { 297 ret = mtk_cpufreq_set_voltage(info, vproc); 298 if (ret) { 299 dev_err(cpu_dev, 300 "cpu%d: failed to scale down voltage!\n", policy->cpu); 301 clk_set_parent(cpu_clk, info->inter_clk); 302 clk_set_rate(armpll, pre_freq_hz); 303 clk_set_parent(cpu_clk, armpll); 304 goto out; 305 } 306 } 307 308 info->current_freq = freq_hz; 309 310 out: 311 mutex_unlock(&info->reg_lock); 312 313 return ret; 314 } 315 316 static int mtk_cpufreq_opp_notifier(struct notifier_block *nb, 317 unsigned long event, void *data) 318 { 319 struct dev_pm_opp *opp = data; 320 struct dev_pm_opp *new_opp; 321 struct mtk_cpu_dvfs_info *info; 322 unsigned long freq, volt; 323 int ret = 0; 324 325 info = container_of(nb, struct mtk_cpu_dvfs_info, opp_nb); 326 327 if (event == OPP_EVENT_ADJUST_VOLTAGE) { 328 freq = dev_pm_opp_get_freq(opp); 329 330 mutex_lock(&info->reg_lock); 331 if (info->current_freq == freq) { 332 volt = dev_pm_opp_get_voltage(opp); 333 ret = mtk_cpufreq_set_voltage(info, volt); 334 if (ret) 335 dev_err(info->cpu_dev, 336 "failed to scale voltage: %d\n", ret); 337 } 338 mutex_unlock(&info->reg_lock); 339 } else if (event == OPP_EVENT_DISABLE) { 340 freq = dev_pm_opp_get_freq(opp); 341 342 /* case of current opp item is disabled */ 343 if (info->current_freq == freq) { 344 freq = 1; 345 new_opp = dev_pm_opp_find_freq_ceil(info->cpu_dev, 346 &freq); 347 if (IS_ERR(new_opp)) { 348 dev_err(info->cpu_dev, 349 "all opp items are disabled\n"); 350 ret = PTR_ERR(new_opp); 351 return notifier_from_errno(ret); 352 } 353 354 dev_pm_opp_put(new_opp); 355 356 struct cpufreq_policy *policy __free(put_cpufreq_policy) 357 = cpufreq_cpu_get(info->opp_cpu); 358 if (policy) 359 cpufreq_driver_target(policy, freq / 1000, 360 CPUFREQ_RELATION_L); 361 } 362 } 363 364 return notifier_from_errno(ret); 365 } 366 367 static struct device *of_get_cci(struct device *cpu_dev) 368 { 369 struct device_node *np; 370 struct platform_device *pdev; 371 372 np = of_parse_phandle(cpu_dev->of_node, "mediatek,cci", 0); 373 if (!np) 374 return ERR_PTR(-ENODEV); 375 376 pdev = of_find_device_by_node(np); 377 of_node_put(np); 378 if (!pdev) 379 return ERR_PTR(-ENODEV); 380 381 return &pdev->dev; 382 } 383 384 static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu) 385 { 386 struct device *cpu_dev; 387 struct dev_pm_opp *opp; 388 unsigned long rate; 389 int ret; 390 391 cpu_dev = get_cpu_device(cpu); 392 if (!cpu_dev) 393 return dev_err_probe(cpu_dev, -ENODEV, "failed to get cpu%d device\n", cpu); 394 info->cpu_dev = cpu_dev; 395 396 info->ccifreq_bound = false; 397 if (info->soc_data->ccifreq_supported) { 398 info->cci_dev = of_get_cci(info->cpu_dev); 399 if (IS_ERR(info->cci_dev)) 400 return dev_err_probe(cpu_dev, PTR_ERR(info->cci_dev), 401 "cpu%d: failed to get cci device\n", 402 cpu); 403 } 404 405 info->cpu_clk = clk_get(cpu_dev, "cpu"); 406 if (IS_ERR(info->cpu_clk)) 407 return dev_err_probe(cpu_dev, PTR_ERR(info->cpu_clk), 408 "cpu%d: failed to get cpu clk\n", cpu); 409 410 info->inter_clk = clk_get(cpu_dev, "intermediate"); 411 if (IS_ERR(info->inter_clk)) { 412 ret = PTR_ERR(info->inter_clk); 413 dev_err_probe(cpu_dev, ret, 414 "cpu%d: failed to get intermediate clk\n", cpu); 415 goto out_free_mux_clock; 416 } 417 418 info->proc_reg = regulator_get_optional(cpu_dev, "proc"); 419 if (IS_ERR(info->proc_reg)) { 420 ret = PTR_ERR(info->proc_reg); 421 dev_err_probe(cpu_dev, ret, 422 "cpu%d: failed to get proc regulator\n", cpu); 423 goto out_free_inter_clock; 424 } 425 426 ret = regulator_enable(info->proc_reg); 427 if (ret) { 428 dev_err_probe(cpu_dev, ret, "cpu%d: failed to enable vproc\n", cpu); 429 goto out_free_proc_reg; 430 } 431 432 /* Both presence and absence of sram regulator are valid cases. */ 433 info->sram_reg = regulator_get_optional(cpu_dev, "sram"); 434 if (IS_ERR(info->sram_reg)) { 435 ret = PTR_ERR(info->sram_reg); 436 if (ret == -EPROBE_DEFER) { 437 dev_err_probe(cpu_dev, ret, 438 "cpu%d: Failed to get sram regulator\n", cpu); 439 goto out_disable_proc_reg; 440 } 441 442 info->sram_reg = NULL; 443 } else { 444 ret = regulator_enable(info->sram_reg); 445 if (ret) { 446 dev_err_probe(cpu_dev, ret, "cpu%d: failed to enable vsram\n", cpu); 447 goto out_free_sram_reg; 448 } 449 } 450 451 /* Get OPP-sharing information from "operating-points-v2" bindings */ 452 ret = dev_pm_opp_of_get_sharing_cpus(cpu_dev, &info->cpus); 453 if (ret) { 454 dev_err_probe(cpu_dev, ret, 455 "cpu%d: failed to get OPP-sharing information\n", cpu); 456 goto out_disable_sram_reg; 457 } 458 459 ret = dev_pm_opp_of_cpumask_add_table(&info->cpus); 460 if (ret) { 461 dev_err_probe(cpu_dev, ret, "cpu%d: no OPP table\n", cpu); 462 goto out_disable_sram_reg; 463 } 464 465 ret = clk_prepare_enable(info->cpu_clk); 466 if (ret) { 467 dev_err_probe(cpu_dev, ret, "cpu%d: failed to enable cpu clk\n", cpu); 468 goto out_free_opp_table; 469 } 470 471 ret = clk_prepare_enable(info->inter_clk); 472 if (ret) { 473 dev_err_probe(cpu_dev, ret, "cpu%d: failed to enable inter clk\n", cpu); 474 goto out_disable_mux_clock; 475 } 476 477 if (info->soc_data->ccifreq_supported) { 478 info->vproc_on_boot = regulator_get_voltage(info->proc_reg); 479 if (info->vproc_on_boot < 0) { 480 ret = dev_err_probe(info->cpu_dev, info->vproc_on_boot, 481 "invalid Vproc value\n"); 482 goto out_disable_inter_clock; 483 } 484 } 485 486 /* Search a safe voltage for intermediate frequency. */ 487 rate = clk_get_rate(info->inter_clk); 488 opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate); 489 if (IS_ERR(opp)) { 490 ret = dev_err_probe(cpu_dev, PTR_ERR(opp), 491 "cpu%d: failed to get intermediate opp\n", cpu); 492 goto out_disable_inter_clock; 493 } 494 info->intermediate_voltage = dev_pm_opp_get_voltage(opp); 495 dev_pm_opp_put(opp); 496 497 mutex_init(&info->reg_lock); 498 info->current_freq = clk_get_rate(info->cpu_clk); 499 500 info->opp_cpu = cpu; 501 info->opp_nb.notifier_call = mtk_cpufreq_opp_notifier; 502 ret = dev_pm_opp_register_notifier(cpu_dev, &info->opp_nb); 503 if (ret) { 504 dev_err_probe(cpu_dev, ret, "cpu%d: failed to register opp notifier\n", cpu); 505 goto out_disable_inter_clock; 506 } 507 508 /* 509 * If SRAM regulator is present, software "voltage tracking" is needed 510 * for this CPU power domain. 511 */ 512 info->need_voltage_tracking = (info->sram_reg != NULL); 513 514 /* 515 * We assume min voltage is 0 and tracking target voltage using 516 * min_volt_shift for each iteration. 517 * The vtrack_max is 3 times of expeted iteration count. 518 */ 519 info->vtrack_max = 3 * DIV_ROUND_UP(max(info->soc_data->sram_max_volt, 520 info->soc_data->proc_max_volt), 521 info->soc_data->min_volt_shift); 522 523 return 0; 524 525 out_disable_inter_clock: 526 clk_disable_unprepare(info->inter_clk); 527 528 out_disable_mux_clock: 529 clk_disable_unprepare(info->cpu_clk); 530 531 out_free_opp_table: 532 dev_pm_opp_of_cpumask_remove_table(&info->cpus); 533 534 out_disable_sram_reg: 535 if (info->sram_reg) 536 regulator_disable(info->sram_reg); 537 538 out_free_sram_reg: 539 if (info->sram_reg) 540 regulator_put(info->sram_reg); 541 542 out_disable_proc_reg: 543 regulator_disable(info->proc_reg); 544 545 out_free_proc_reg: 546 regulator_put(info->proc_reg); 547 548 out_free_inter_clock: 549 clk_put(info->inter_clk); 550 551 out_free_mux_clock: 552 clk_put(info->cpu_clk); 553 554 return ret; 555 } 556 557 static void mtk_cpu_dvfs_info_release(struct mtk_cpu_dvfs_info *info) 558 { 559 regulator_disable(info->proc_reg); 560 regulator_put(info->proc_reg); 561 if (info->sram_reg) { 562 regulator_disable(info->sram_reg); 563 regulator_put(info->sram_reg); 564 } 565 clk_disable_unprepare(info->cpu_clk); 566 clk_put(info->cpu_clk); 567 clk_disable_unprepare(info->inter_clk); 568 clk_put(info->inter_clk); 569 dev_pm_opp_of_cpumask_remove_table(&info->cpus); 570 dev_pm_opp_unregister_notifier(info->cpu_dev, &info->opp_nb); 571 } 572 573 static int mtk_cpufreq_init(struct cpufreq_policy *policy) 574 { 575 struct mtk_cpu_dvfs_info *info; 576 struct cpufreq_frequency_table *freq_table; 577 int ret; 578 579 info = mtk_cpu_dvfs_info_lookup(policy->cpu); 580 if (!info) { 581 pr_err("dvfs info for cpu%d is not initialized.\n", 582 policy->cpu); 583 return -EINVAL; 584 } 585 586 ret = dev_pm_opp_init_cpufreq_table(info->cpu_dev, &freq_table); 587 if (ret) { 588 dev_err(info->cpu_dev, 589 "failed to init cpufreq table for cpu%d: %d\n", 590 policy->cpu, ret); 591 return ret; 592 } 593 594 cpumask_copy(policy->cpus, &info->cpus); 595 policy->freq_table = freq_table; 596 policy->driver_data = info; 597 policy->clk = info->cpu_clk; 598 599 return 0; 600 } 601 602 static void mtk_cpufreq_exit(struct cpufreq_policy *policy) 603 { 604 struct mtk_cpu_dvfs_info *info = policy->driver_data; 605 606 dev_pm_opp_free_cpufreq_table(info->cpu_dev, &policy->freq_table); 607 } 608 609 static struct cpufreq_driver mtk_cpufreq_driver = { 610 .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK | 611 CPUFREQ_HAVE_GOVERNOR_PER_POLICY | 612 CPUFREQ_IS_COOLING_DEV, 613 .verify = cpufreq_generic_frequency_table_verify, 614 .target_index = mtk_cpufreq_set_target, 615 .get = cpufreq_generic_get, 616 .init = mtk_cpufreq_init, 617 .exit = mtk_cpufreq_exit, 618 .register_em = cpufreq_register_em_with_opp, 619 .name = "mtk-cpufreq", 620 }; 621 622 static int mtk_cpufreq_probe(struct platform_device *pdev) 623 { 624 const struct mtk_cpufreq_platform_data *data; 625 struct mtk_cpu_dvfs_info *info, *tmp; 626 int cpu, ret; 627 628 data = dev_get_platdata(&pdev->dev); 629 if (!data) 630 return dev_err_probe(&pdev->dev, -ENODEV, 631 "failed to get mtk cpufreq platform data\n"); 632 633 for_each_present_cpu(cpu) { 634 info = mtk_cpu_dvfs_info_lookup(cpu); 635 if (info) 636 continue; 637 638 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); 639 if (!info) { 640 ret = dev_err_probe(&pdev->dev, -ENOMEM, 641 "Failed to allocate dvfs_info\n"); 642 goto release_dvfs_info_list; 643 } 644 645 info->soc_data = data; 646 ret = mtk_cpu_dvfs_info_init(info, cpu); 647 if (ret) 648 goto release_dvfs_info_list; 649 650 list_add(&info->list_head, &dvfs_info_list); 651 } 652 653 ret = cpufreq_register_driver(&mtk_cpufreq_driver); 654 if (ret) { 655 dev_err_probe(&pdev->dev, ret, "failed to register mtk cpufreq driver\n"); 656 goto release_dvfs_info_list; 657 } 658 659 return 0; 660 661 release_dvfs_info_list: 662 list_for_each_entry_safe(info, tmp, &dvfs_info_list, list_head) { 663 mtk_cpu_dvfs_info_release(info); 664 list_del(&info->list_head); 665 } 666 667 return ret; 668 } 669 670 static struct platform_driver mtk_cpufreq_platdrv = { 671 .driver = { 672 .name = "mtk-cpufreq", 673 }, 674 .probe = mtk_cpufreq_probe, 675 }; 676 677 static const struct mtk_cpufreq_platform_data mt2701_platform_data = { 678 .min_volt_shift = 100000, 679 .max_volt_shift = 200000, 680 .proc_max_volt = 1150000, 681 .sram_min_volt = 0, 682 .sram_max_volt = 1150000, 683 .ccifreq_supported = false, 684 }; 685 686 static const struct mtk_cpufreq_platform_data mt7622_platform_data = { 687 .min_volt_shift = 100000, 688 .max_volt_shift = 200000, 689 .proc_max_volt = 1350000, 690 .sram_min_volt = 0, 691 .sram_max_volt = 1350000, 692 .ccifreq_supported = false, 693 }; 694 695 static const struct mtk_cpufreq_platform_data mt7623_platform_data = { 696 .min_volt_shift = 100000, 697 .max_volt_shift = 200000, 698 .proc_max_volt = 1300000, 699 .ccifreq_supported = false, 700 }; 701 702 static const struct mtk_cpufreq_platform_data mt7988_platform_data = { 703 .min_volt_shift = 100000, 704 .max_volt_shift = 200000, 705 .proc_max_volt = 900000, 706 .sram_min_volt = 0, 707 .sram_max_volt = 1150000, 708 .ccifreq_supported = true, 709 }; 710 711 static const struct mtk_cpufreq_platform_data mt8183_platform_data = { 712 .min_volt_shift = 100000, 713 .max_volt_shift = 200000, 714 .proc_max_volt = 1150000, 715 .sram_min_volt = 0, 716 .sram_max_volt = 1150000, 717 .ccifreq_supported = true, 718 }; 719 720 static const struct mtk_cpufreq_platform_data mt8186_platform_data = { 721 .min_volt_shift = 100000, 722 .max_volt_shift = 250000, 723 .proc_max_volt = 1118750, 724 .sram_min_volt = 850000, 725 .sram_max_volt = 1118750, 726 .ccifreq_supported = true, 727 }; 728 729 static const struct mtk_cpufreq_platform_data mt8516_platform_data = { 730 .min_volt_shift = 100000, 731 .max_volt_shift = 200000, 732 .proc_max_volt = 1310000, 733 .sram_min_volt = 0, 734 .sram_max_volt = 1310000, 735 .ccifreq_supported = false, 736 }; 737 738 /* List of machines supported by this driver */ 739 static const struct of_device_id mtk_cpufreq_machines[] __initconst __maybe_unused = { 740 { .compatible = "mediatek,mt2701", .data = &mt2701_platform_data }, 741 { .compatible = "mediatek,mt2712", .data = &mt2701_platform_data }, 742 { .compatible = "mediatek,mt7622", .data = &mt7622_platform_data }, 743 { .compatible = "mediatek,mt7623", .data = &mt7623_platform_data }, 744 { .compatible = "mediatek,mt7988a", .data = &mt7988_platform_data }, 745 { .compatible = "mediatek,mt8167", .data = &mt8516_platform_data }, 746 { .compatible = "mediatek,mt817x", .data = &mt2701_platform_data }, 747 { .compatible = "mediatek,mt8173", .data = &mt2701_platform_data }, 748 { .compatible = "mediatek,mt8176", .data = &mt2701_platform_data }, 749 { .compatible = "mediatek,mt8183", .data = &mt8183_platform_data }, 750 { .compatible = "mediatek,mt8186", .data = &mt8186_platform_data }, 751 { .compatible = "mediatek,mt8365", .data = &mt2701_platform_data }, 752 { .compatible = "mediatek,mt8516", .data = &mt8516_platform_data }, 753 { } 754 }; 755 MODULE_DEVICE_TABLE(of, mtk_cpufreq_machines); 756 757 static int __init mtk_cpufreq_driver_init(void) 758 { 759 struct device_node *np; 760 const struct of_device_id *match; 761 const struct mtk_cpufreq_platform_data *data; 762 int err; 763 764 np = of_find_node_by_path("/"); 765 if (!np) 766 return -ENODEV; 767 768 match = of_match_node(mtk_cpufreq_machines, np); 769 of_node_put(np); 770 if (!match) { 771 pr_debug("Machine is not compatible with mtk-cpufreq\n"); 772 return -ENODEV; 773 } 774 data = match->data; 775 776 err = platform_driver_register(&mtk_cpufreq_platdrv); 777 if (err) 778 return err; 779 780 /* 781 * Since there's no place to hold device registration code and no 782 * device tree based way to match cpufreq driver yet, both the driver 783 * and the device registration codes are put here to handle defer 784 * probing. 785 */ 786 cpufreq_pdev = platform_device_register_data(NULL, "mtk-cpufreq", -1, 787 data, sizeof(*data)); 788 if (IS_ERR(cpufreq_pdev)) { 789 pr_err("failed to register mtk-cpufreq platform device\n"); 790 platform_driver_unregister(&mtk_cpufreq_platdrv); 791 return PTR_ERR(cpufreq_pdev); 792 } 793 794 return 0; 795 } 796 module_init(mtk_cpufreq_driver_init) 797 798 static void __exit mtk_cpufreq_driver_exit(void) 799 { 800 platform_device_unregister(cpufreq_pdev); 801 platform_driver_unregister(&mtk_cpufreq_platdrv); 802 } 803 module_exit(mtk_cpufreq_driver_exit) 804 805 MODULE_DESCRIPTION("MediaTek CPUFreq driver"); 806 MODULE_AUTHOR("Pi-Cheng Chen <pi-cheng.chen@linaro.org>"); 807 MODULE_LICENSE("GPL v2"); 808