1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * intel_pstate.c: Native P state management for Intel processors 4 * 5 * (C) Copyright 2012 Intel Corporation 6 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com> 7 */ 8 9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10 11 #include <linux/kernel.h> 12 #include <linux/kernel_stat.h> 13 #include <linux/module.h> 14 #include <linux/ktime.h> 15 #include <linux/hrtimer.h> 16 #include <linux/tick.h> 17 #include <linux/slab.h> 18 #include <linux/sched/cpufreq.h> 19 #include <linux/sched/smt.h> 20 #include <linux/list.h> 21 #include <linux/cpu.h> 22 #include <linux/cpufreq.h> 23 #include <linux/sysfs.h> 24 #include <linux/types.h> 25 #include <linux/fs.h> 26 #include <linux/acpi.h> 27 #include <linux/vmalloc.h> 28 #include <linux/pm_qos.h> 29 #include <linux/bitfield.h> 30 #include <trace/events/power.h> 31 #include <linux/units.h> 32 33 #include <asm/cpu.h> 34 #include <asm/div64.h> 35 #include <asm/msr.h> 36 #include <asm/cpu_device_id.h> 37 #include <asm/cpufeature.h> 38 #include <asm/intel-family.h> 39 #include "../drivers/thermal/intel/thermal_interrupt.h" 40 41 #define INTEL_PSTATE_SAMPLING_INTERVAL (10 * NSEC_PER_MSEC) 42 43 #define INTEL_CPUFREQ_TRANSITION_LATENCY 20000 44 #define INTEL_CPUFREQ_TRANSITION_DELAY_HWP 5000 45 #define INTEL_CPUFREQ_TRANSITION_DELAY 500 46 47 #ifdef CONFIG_ACPI 48 #include <acpi/processor.h> 49 #include <acpi/cppc_acpi.h> 50 #endif 51 52 #define FRAC_BITS 8 53 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS) 54 #define fp_toint(X) ((X) >> FRAC_BITS) 55 56 #define ONE_EIGHTH_FP ((int64_t)1 << (FRAC_BITS - 3)) 57 58 #define EXT_BITS 6 59 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS) 60 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS) 61 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS) 62 63 static inline int32_t mul_fp(int32_t x, int32_t y) 64 { 65 return ((int64_t)x * (int64_t)y) >> FRAC_BITS; 66 } 67 68 static inline int32_t div_fp(s64 x, s64 y) 69 { 70 return div64_s64((int64_t)x << FRAC_BITS, y); 71 } 72 73 static inline int ceiling_fp(int32_t x) 74 { 75 int mask, ret; 76 77 ret = fp_toint(x); 78 mask = (1 << FRAC_BITS) - 1; 79 if (x & mask) 80 ret += 1; 81 return ret; 82 } 83 84 static inline u64 mul_ext_fp(u64 x, u64 y) 85 { 86 return (x * y) >> EXT_FRAC_BITS; 87 } 88 89 static inline u64 div_ext_fp(u64 x, u64 y) 90 { 91 return div64_u64(x << EXT_FRAC_BITS, y); 92 } 93 94 /** 95 * struct sample - Store performance sample 96 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average 97 * performance during last sample period 98 * @busy_scaled: Scaled busy value which is used to calculate next 99 * P state. This can be different than core_avg_perf 100 * to account for cpu idle period 101 * @aperf: Difference of actual performance frequency clock count 102 * read from APERF MSR between last and current sample 103 * @mperf: Difference of maximum performance frequency clock count 104 * read from MPERF MSR between last and current sample 105 * @tsc: Difference of time stamp counter between last and 106 * current sample 107 * @time: Current time from scheduler 108 * 109 * This structure is used in the cpudata structure to store performance sample 110 * data for choosing next P State. 111 */ 112 struct sample { 113 int32_t core_avg_perf; 114 int32_t busy_scaled; 115 u64 aperf; 116 u64 mperf; 117 u64 tsc; 118 u64 time; 119 }; 120 121 /** 122 * struct pstate_data - Store P state data 123 * @current_pstate: Current requested P state 124 * @min_pstate: Min P state possible for this platform 125 * @max_pstate: Max P state possible for this platform 126 * @max_pstate_physical:This is physical Max P state for a processor 127 * This can be higher than the max_pstate which can 128 * be limited by platform thermal design power limits 129 * @perf_ctl_scaling: PERF_CTL P-state to frequency scaling factor 130 * @scaling: Scaling factor between performance and frequency 131 * @turbo_pstate: Max Turbo P state possible for this platform 132 * @min_freq: @min_pstate frequency in cpufreq units 133 * @max_freq: @max_pstate frequency in cpufreq units 134 * @turbo_freq: @turbo_pstate frequency in cpufreq units 135 * 136 * Stores the per cpu model P state limits and current P state. 137 */ 138 struct pstate_data { 139 int current_pstate; 140 int min_pstate; 141 int max_pstate; 142 int max_pstate_physical; 143 int perf_ctl_scaling; 144 int scaling; 145 int turbo_pstate; 146 unsigned int min_freq; 147 unsigned int max_freq; 148 unsigned int turbo_freq; 149 }; 150 151 /** 152 * struct vid_data - Stores voltage information data 153 * @min: VID data for this platform corresponding to 154 * the lowest P state 155 * @max: VID data corresponding to the highest P State. 156 * @turbo: VID data for turbo P state 157 * @ratio: Ratio of (vid max - vid min) / 158 * (max P state - Min P State) 159 * 160 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling) 161 * This data is used in Atom platforms, where in addition to target P state, 162 * the voltage data needs to be specified to select next P State. 163 */ 164 struct vid_data { 165 int min; 166 int max; 167 int turbo; 168 int32_t ratio; 169 }; 170 171 /** 172 * struct global_params - Global parameters, mostly tunable via sysfs. 173 * @no_turbo: Whether or not to use turbo P-states. 174 * @turbo_disabled: Whether or not turbo P-states are available at all, 175 * based on the MSR_IA32_MISC_ENABLE value and whether or 176 * not the maximum reported turbo P-state is different from 177 * the maximum reported non-turbo one. 178 * @min_perf_pct: Minimum capacity limit in percent of the maximum turbo 179 * P-state capacity. 180 * @max_perf_pct: Maximum capacity limit in percent of the maximum turbo 181 * P-state capacity. 182 */ 183 struct global_params { 184 bool no_turbo; 185 bool turbo_disabled; 186 int max_perf_pct; 187 int min_perf_pct; 188 }; 189 190 /** 191 * struct cpudata - Per CPU instance data storage 192 * @cpu: CPU number for this instance data 193 * @policy: CPUFreq policy value 194 * @update_util: CPUFreq utility callback information 195 * @update_util_set: CPUFreq utility callback is set 196 * @iowait_boost: iowait-related boost fraction 197 * @last_update: Time of the last update. 198 * @pstate: Stores P state limits for this CPU 199 * @vid: Stores VID limits for this CPU 200 * @last_sample_time: Last Sample time 201 * @aperf_mperf_shift: APERF vs MPERF counting frequency difference 202 * @prev_aperf: Last APERF value read from APERF MSR 203 * @prev_mperf: Last MPERF value read from MPERF MSR 204 * @prev_tsc: Last timestamp counter (TSC) value 205 * @sample: Storage for storing last Sample data 206 * @min_perf_ratio: Minimum capacity in terms of PERF or HWP ratios 207 * @max_perf_ratio: Maximum capacity in terms of PERF or HWP ratios 208 * @acpi_perf_data: Stores ACPI perf information read from _PSS 209 * @valid_pss_table: Set to true for valid ACPI _PSS entries found 210 * @epp_powersave: Last saved HWP energy performance preference 211 * (EPP) or energy performance bias (EPB), 212 * when policy switched to performance 213 * @epp_policy: Last saved policy used to set EPP/EPB 214 * @epp_default: Power on default HWP energy performance 215 * preference/bias 216 * @epp_cached: Cached HWP energy-performance preference value 217 * @hwp_req_cached: Cached value of the last HWP Request MSR 218 * @hwp_cap_cached: Cached value of the last HWP Capabilities MSR 219 * @last_io_update: Last time when IO wake flag was set 220 * @capacity_perf: Highest perf used for scale invariance 221 * @sched_flags: Store scheduler flags for possible cross CPU update 222 * @hwp_boost_min: Last HWP boosted min performance 223 * @suspended: Whether or not the driver has been suspended. 224 * @hwp_notify_work: workqueue for HWP notifications. 225 * 226 * This structure stores per CPU instance data for all CPUs. 227 */ 228 struct cpudata { 229 int cpu; 230 231 unsigned int policy; 232 struct update_util_data update_util; 233 bool update_util_set; 234 235 struct pstate_data pstate; 236 struct vid_data vid; 237 238 u64 last_update; 239 u64 last_sample_time; 240 u64 aperf_mperf_shift; 241 u64 prev_aperf; 242 u64 prev_mperf; 243 u64 prev_tsc; 244 struct sample sample; 245 int32_t min_perf_ratio; 246 int32_t max_perf_ratio; 247 #ifdef CONFIG_ACPI 248 struct acpi_processor_performance acpi_perf_data; 249 bool valid_pss_table; 250 #endif 251 unsigned int iowait_boost; 252 s16 epp_powersave; 253 s16 epp_policy; 254 s16 epp_default; 255 s16 epp_cached; 256 u64 hwp_req_cached; 257 u64 hwp_cap_cached; 258 u64 last_io_update; 259 unsigned int capacity_perf; 260 unsigned int sched_flags; 261 u32 hwp_boost_min; 262 bool suspended; 263 struct delayed_work hwp_notify_work; 264 }; 265 266 static struct cpudata **all_cpu_data; 267 268 /** 269 * struct pstate_funcs - Per CPU model specific callbacks 270 * @get_max: Callback to get maximum non turbo effective P state 271 * @get_max_physical: Callback to get maximum non turbo physical P state 272 * @get_min: Callback to get minimum P state 273 * @get_turbo: Callback to get turbo P state 274 * @get_scaling: Callback to get frequency scaling factor 275 * @get_cpu_scaling: Get frequency scaling factor for a given cpu 276 * @get_aperf_mperf_shift: Callback to get the APERF vs MPERF frequency difference 277 * @get_val: Callback to convert P state to actual MSR write value 278 * @get_vid: Callback to get VID data for Atom platforms 279 * 280 * Core and Atom CPU models have different way to get P State limits. This 281 * structure is used to store those callbacks. 282 */ 283 struct pstate_funcs { 284 int (*get_max)(int cpu); 285 int (*get_max_physical)(int cpu); 286 int (*get_min)(int cpu); 287 int (*get_turbo)(int cpu); 288 int (*get_scaling)(void); 289 int (*get_cpu_scaling)(int cpu); 290 int (*get_aperf_mperf_shift)(void); 291 u64 (*get_val)(struct cpudata*, int pstate); 292 void (*get_vid)(struct cpudata *); 293 }; 294 295 static struct pstate_funcs pstate_funcs __read_mostly; 296 297 static bool hwp_active __ro_after_init; 298 static int hwp_mode_bdw __ro_after_init; 299 static bool per_cpu_limits __ro_after_init; 300 static bool hwp_forced __ro_after_init; 301 static bool hwp_boost __read_mostly; 302 static bool hwp_is_hybrid; 303 304 static struct cpufreq_driver *intel_pstate_driver __read_mostly; 305 306 #define HYBRID_SCALING_FACTOR_ADL 78741 307 #define HYBRID_SCALING_FACTOR_MTL 80000 308 #define HYBRID_SCALING_FACTOR_LNL 86957 309 310 static int hybrid_scaling_factor; 311 312 static inline int core_get_scaling(void) 313 { 314 return 100000; 315 } 316 317 #ifdef CONFIG_ACPI 318 static bool acpi_ppc; 319 #endif 320 321 static struct global_params global; 322 323 static DEFINE_MUTEX(intel_pstate_driver_lock); 324 static DEFINE_MUTEX(intel_pstate_limits_lock); 325 326 #ifdef CONFIG_ACPI 327 328 static bool intel_pstate_acpi_pm_profile_server(void) 329 { 330 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER || 331 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER) 332 return true; 333 334 return false; 335 } 336 337 static bool intel_pstate_get_ppc_enable_status(void) 338 { 339 if (intel_pstate_acpi_pm_profile_server()) 340 return true; 341 342 return acpi_ppc; 343 } 344 345 #ifdef CONFIG_ACPI_CPPC_LIB 346 347 /* The work item is needed to avoid CPU hotplug locking issues */ 348 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work) 349 { 350 sched_set_itmt_support(); 351 } 352 353 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn); 354 355 #define CPPC_MAX_PERF U8_MAX 356 357 static void intel_pstate_set_itmt_prio(int cpu) 358 { 359 struct cppc_perf_caps cppc_perf; 360 static u32 max_highest_perf = 0, min_highest_perf = U32_MAX; 361 int ret; 362 363 ret = cppc_get_perf_caps(cpu, &cppc_perf); 364 /* 365 * If CPPC is not available, fall back to MSR_HWP_CAPABILITIES bits [8:0]. 366 * 367 * Also, on some systems with overclocking enabled, CPPC.highest_perf is 368 * hardcoded to 0xff, so CPPC.highest_perf cannot be used to enable ITMT. 369 * Fall back to MSR_HWP_CAPABILITIES then too. 370 */ 371 if (ret || cppc_perf.highest_perf == CPPC_MAX_PERF) 372 cppc_perf.highest_perf = HWP_HIGHEST_PERF(READ_ONCE(all_cpu_data[cpu]->hwp_cap_cached)); 373 374 /* 375 * The priorities can be set regardless of whether or not 376 * sched_set_itmt_support(true) has been called and it is valid to 377 * update them at any time after it has been called. 378 */ 379 sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu); 380 381 if (max_highest_perf <= min_highest_perf) { 382 if (cppc_perf.highest_perf > max_highest_perf) 383 max_highest_perf = cppc_perf.highest_perf; 384 385 if (cppc_perf.highest_perf < min_highest_perf) 386 min_highest_perf = cppc_perf.highest_perf; 387 388 if (max_highest_perf > min_highest_perf) { 389 /* 390 * This code can be run during CPU online under the 391 * CPU hotplug locks, so sched_set_itmt_support() 392 * cannot be called from here. Queue up a work item 393 * to invoke it. 394 */ 395 schedule_work(&sched_itmt_work); 396 } 397 } 398 } 399 400 static int intel_pstate_get_cppc_guaranteed(int cpu) 401 { 402 struct cppc_perf_caps cppc_perf; 403 int ret; 404 405 ret = cppc_get_perf_caps(cpu, &cppc_perf); 406 if (ret) 407 return ret; 408 409 if (cppc_perf.guaranteed_perf) 410 return cppc_perf.guaranteed_perf; 411 412 return cppc_perf.nominal_perf; 413 } 414 415 static int intel_pstate_cppc_get_scaling(int cpu) 416 { 417 struct cppc_perf_caps cppc_perf; 418 419 /* 420 * Compute the perf-to-frequency scaling factor for the given CPU if 421 * possible, unless it would be 0. 422 */ 423 if (!cppc_get_perf_caps(cpu, &cppc_perf) && 424 cppc_perf.nominal_perf && cppc_perf.nominal_freq) 425 return div_u64(cppc_perf.nominal_freq * KHZ_PER_MHZ, 426 cppc_perf.nominal_perf); 427 428 return core_get_scaling(); 429 } 430 431 #else /* CONFIG_ACPI_CPPC_LIB */ 432 static inline void intel_pstate_set_itmt_prio(int cpu) 433 { 434 } 435 #endif /* CONFIG_ACPI_CPPC_LIB */ 436 437 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) 438 { 439 struct cpudata *cpu; 440 int ret; 441 int i; 442 443 if (hwp_active) { 444 intel_pstate_set_itmt_prio(policy->cpu); 445 return; 446 } 447 448 if (!intel_pstate_get_ppc_enable_status()) 449 return; 450 451 cpu = all_cpu_data[policy->cpu]; 452 453 ret = acpi_processor_register_performance(&cpu->acpi_perf_data, 454 policy->cpu); 455 if (ret) 456 return; 457 458 /* 459 * Check if the control value in _PSS is for PERF_CTL MSR, which should 460 * guarantee that the states returned by it map to the states in our 461 * list directly. 462 */ 463 if (cpu->acpi_perf_data.control_register.space_id != 464 ACPI_ADR_SPACE_FIXED_HARDWARE) 465 goto err; 466 467 /* 468 * If there is only one entry _PSS, simply ignore _PSS and continue as 469 * usual without taking _PSS into account 470 */ 471 if (cpu->acpi_perf_data.state_count < 2) 472 goto err; 473 474 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu); 475 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) { 476 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n", 477 (i == cpu->acpi_perf_data.state ? '*' : ' '), i, 478 (u32) cpu->acpi_perf_data.states[i].core_frequency, 479 (u32) cpu->acpi_perf_data.states[i].power, 480 (u32) cpu->acpi_perf_data.states[i].control); 481 } 482 483 cpu->valid_pss_table = true; 484 pr_debug("_PPC limits will be enforced\n"); 485 486 return; 487 488 err: 489 cpu->valid_pss_table = false; 490 acpi_processor_unregister_performance(policy->cpu); 491 } 492 493 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) 494 { 495 struct cpudata *cpu; 496 497 cpu = all_cpu_data[policy->cpu]; 498 if (!cpu->valid_pss_table) 499 return; 500 501 acpi_processor_unregister_performance(policy->cpu); 502 } 503 #else /* CONFIG_ACPI */ 504 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) 505 { 506 } 507 508 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) 509 { 510 } 511 512 static inline bool intel_pstate_acpi_pm_profile_server(void) 513 { 514 return false; 515 } 516 #endif /* CONFIG_ACPI */ 517 518 #ifndef CONFIG_ACPI_CPPC_LIB 519 static inline int intel_pstate_get_cppc_guaranteed(int cpu) 520 { 521 return -ENOTSUPP; 522 } 523 524 static int intel_pstate_cppc_get_scaling(int cpu) 525 { 526 return core_get_scaling(); 527 } 528 #endif /* CONFIG_ACPI_CPPC_LIB */ 529 530 static int intel_pstate_freq_to_hwp_rel(struct cpudata *cpu, int freq, 531 unsigned int relation) 532 { 533 if (freq == cpu->pstate.turbo_freq) 534 return cpu->pstate.turbo_pstate; 535 536 if (freq == cpu->pstate.max_freq) 537 return cpu->pstate.max_pstate; 538 539 switch (relation) { 540 case CPUFREQ_RELATION_H: 541 return freq / cpu->pstate.scaling; 542 case CPUFREQ_RELATION_C: 543 return DIV_ROUND_CLOSEST(freq, cpu->pstate.scaling); 544 } 545 546 return DIV_ROUND_UP(freq, cpu->pstate.scaling); 547 } 548 549 static int intel_pstate_freq_to_hwp(struct cpudata *cpu, int freq) 550 { 551 return intel_pstate_freq_to_hwp_rel(cpu, freq, CPUFREQ_RELATION_L); 552 } 553 554 /** 555 * intel_pstate_hybrid_hwp_adjust - Calibrate HWP performance levels. 556 * @cpu: Target CPU. 557 * 558 * On hybrid processors, HWP may expose more performance levels than there are 559 * P-states accessible through the PERF_CTL interface. If that happens, the 560 * scaling factor between HWP performance levels and CPU frequency will be less 561 * than the scaling factor between P-state values and CPU frequency. 562 * 563 * In that case, adjust the CPU parameters used in computations accordingly. 564 */ 565 static void intel_pstate_hybrid_hwp_adjust(struct cpudata *cpu) 566 { 567 int perf_ctl_max_phys = cpu->pstate.max_pstate_physical; 568 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling; 569 int perf_ctl_turbo = pstate_funcs.get_turbo(cpu->cpu); 570 int scaling = cpu->pstate.scaling; 571 int freq; 572 573 pr_debug("CPU%d: perf_ctl_max_phys = %d\n", cpu->cpu, perf_ctl_max_phys); 574 pr_debug("CPU%d: perf_ctl_turbo = %d\n", cpu->cpu, perf_ctl_turbo); 575 pr_debug("CPU%d: perf_ctl_scaling = %d\n", cpu->cpu, perf_ctl_scaling); 576 pr_debug("CPU%d: HWP_CAP guaranteed = %d\n", cpu->cpu, cpu->pstate.max_pstate); 577 pr_debug("CPU%d: HWP_CAP highest = %d\n", cpu->cpu, cpu->pstate.turbo_pstate); 578 pr_debug("CPU%d: HWP-to-frequency scaling factor: %d\n", cpu->cpu, scaling); 579 580 cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_pstate * scaling, 581 perf_ctl_scaling); 582 cpu->pstate.max_freq = rounddown(cpu->pstate.max_pstate * scaling, 583 perf_ctl_scaling); 584 585 freq = perf_ctl_max_phys * perf_ctl_scaling; 586 cpu->pstate.max_pstate_physical = intel_pstate_freq_to_hwp(cpu, freq); 587 588 freq = cpu->pstate.min_pstate * perf_ctl_scaling; 589 cpu->pstate.min_freq = freq; 590 /* 591 * Cast the min P-state value retrieved via pstate_funcs.get_min() to 592 * the effective range of HWP performance levels. 593 */ 594 cpu->pstate.min_pstate = intel_pstate_freq_to_hwp(cpu, freq); 595 } 596 597 static bool turbo_is_disabled(void) 598 { 599 u64 misc_en; 600 601 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en); 602 603 return !!(misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE); 604 } 605 606 static int min_perf_pct_min(void) 607 { 608 struct cpudata *cpu = all_cpu_data[0]; 609 int turbo_pstate = cpu->pstate.turbo_pstate; 610 611 return turbo_pstate ? 612 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0; 613 } 614 615 static s16 intel_pstate_get_epb(struct cpudata *cpu_data) 616 { 617 u64 epb; 618 int ret; 619 620 if (!boot_cpu_has(X86_FEATURE_EPB)) 621 return -ENXIO; 622 623 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb); 624 if (ret) 625 return (s16)ret; 626 627 return (s16)(epb & 0x0f); 628 } 629 630 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data) 631 { 632 s16 epp; 633 634 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 635 /* 636 * When hwp_req_data is 0, means that caller didn't read 637 * MSR_HWP_REQUEST, so need to read and get EPP. 638 */ 639 if (!hwp_req_data) { 640 epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, 641 &hwp_req_data); 642 if (epp) 643 return epp; 644 } 645 epp = (hwp_req_data >> 24) & 0xff; 646 } else { 647 /* When there is no EPP present, HWP uses EPB settings */ 648 epp = intel_pstate_get_epb(cpu_data); 649 } 650 651 return epp; 652 } 653 654 static int intel_pstate_set_epb(int cpu, s16 pref) 655 { 656 u64 epb; 657 int ret; 658 659 if (!boot_cpu_has(X86_FEATURE_EPB)) 660 return -ENXIO; 661 662 ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb); 663 if (ret) 664 return ret; 665 666 epb = (epb & ~0x0f) | pref; 667 wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb); 668 669 return 0; 670 } 671 672 /* 673 * EPP/EPB display strings corresponding to EPP index in the 674 * energy_perf_strings[] 675 * index String 676 *------------------------------------- 677 * 0 default 678 * 1 performance 679 * 2 balance_performance 680 * 3 balance_power 681 * 4 power 682 */ 683 684 enum energy_perf_value_index { 685 EPP_INDEX_DEFAULT = 0, 686 EPP_INDEX_PERFORMANCE, 687 EPP_INDEX_BALANCE_PERFORMANCE, 688 EPP_INDEX_BALANCE_POWERSAVE, 689 EPP_INDEX_POWERSAVE, 690 }; 691 692 static const char * const energy_perf_strings[] = { 693 [EPP_INDEX_DEFAULT] = "default", 694 [EPP_INDEX_PERFORMANCE] = "performance", 695 [EPP_INDEX_BALANCE_PERFORMANCE] = "balance_performance", 696 [EPP_INDEX_BALANCE_POWERSAVE] = "balance_power", 697 [EPP_INDEX_POWERSAVE] = "power", 698 NULL 699 }; 700 static unsigned int epp_values[] = { 701 [EPP_INDEX_DEFAULT] = 0, /* Unused index */ 702 [EPP_INDEX_PERFORMANCE] = HWP_EPP_PERFORMANCE, 703 [EPP_INDEX_BALANCE_PERFORMANCE] = HWP_EPP_BALANCE_PERFORMANCE, 704 [EPP_INDEX_BALANCE_POWERSAVE] = HWP_EPP_BALANCE_POWERSAVE, 705 [EPP_INDEX_POWERSAVE] = HWP_EPP_POWERSAVE, 706 }; 707 708 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data, int *raw_epp) 709 { 710 s16 epp; 711 int index = -EINVAL; 712 713 *raw_epp = 0; 714 epp = intel_pstate_get_epp(cpu_data, 0); 715 if (epp < 0) 716 return epp; 717 718 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 719 if (epp == epp_values[EPP_INDEX_PERFORMANCE]) 720 return EPP_INDEX_PERFORMANCE; 721 if (epp == epp_values[EPP_INDEX_BALANCE_PERFORMANCE]) 722 return EPP_INDEX_BALANCE_PERFORMANCE; 723 if (epp == epp_values[EPP_INDEX_BALANCE_POWERSAVE]) 724 return EPP_INDEX_BALANCE_POWERSAVE; 725 if (epp == epp_values[EPP_INDEX_POWERSAVE]) 726 return EPP_INDEX_POWERSAVE; 727 *raw_epp = epp; 728 return 0; 729 } else if (boot_cpu_has(X86_FEATURE_EPB)) { 730 /* 731 * Range: 732 * 0x00-0x03 : Performance 733 * 0x04-0x07 : Balance performance 734 * 0x08-0x0B : Balance power 735 * 0x0C-0x0F : Power 736 * The EPB is a 4 bit value, but our ranges restrict the 737 * value which can be set. Here only using top two bits 738 * effectively. 739 */ 740 index = (epp >> 2) + 1; 741 } 742 743 return index; 744 } 745 746 static int intel_pstate_set_epp(struct cpudata *cpu, u32 epp) 747 { 748 int ret; 749 750 /* 751 * Use the cached HWP Request MSR value, because in the active mode the 752 * register itself may be updated by intel_pstate_hwp_boost_up() or 753 * intel_pstate_hwp_boost_down() at any time. 754 */ 755 u64 value = READ_ONCE(cpu->hwp_req_cached); 756 757 value &= ~GENMASK_ULL(31, 24); 758 value |= (u64)epp << 24; 759 /* 760 * The only other updater of hwp_req_cached in the active mode, 761 * intel_pstate_hwp_set(), is called under the same lock as this 762 * function, so it cannot run in parallel with the update below. 763 */ 764 WRITE_ONCE(cpu->hwp_req_cached, value); 765 ret = wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 766 if (!ret) 767 cpu->epp_cached = epp; 768 769 return ret; 770 } 771 772 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data, 773 int pref_index, bool use_raw, 774 u32 raw_epp) 775 { 776 int epp = -EINVAL; 777 int ret; 778 779 if (!pref_index) 780 epp = cpu_data->epp_default; 781 782 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 783 if (use_raw) 784 epp = raw_epp; 785 else if (epp == -EINVAL) 786 epp = epp_values[pref_index]; 787 788 /* 789 * To avoid confusion, refuse to set EPP to any values different 790 * from 0 (performance) if the current policy is "performance", 791 * because those values would be overridden. 792 */ 793 if (epp > 0 && cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) 794 return -EBUSY; 795 796 ret = intel_pstate_set_epp(cpu_data, epp); 797 } else { 798 if (epp == -EINVAL) 799 epp = (pref_index - 1) << 2; 800 ret = intel_pstate_set_epb(cpu_data->cpu, epp); 801 } 802 803 return ret; 804 } 805 806 static ssize_t show_energy_performance_available_preferences( 807 struct cpufreq_policy *policy, char *buf) 808 { 809 int i = 0; 810 int ret = 0; 811 812 while (energy_perf_strings[i] != NULL) 813 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]); 814 815 ret += sprintf(&buf[ret], "\n"); 816 817 return ret; 818 } 819 820 cpufreq_freq_attr_ro(energy_performance_available_preferences); 821 822 static struct cpufreq_driver intel_pstate; 823 824 static ssize_t store_energy_performance_preference( 825 struct cpufreq_policy *policy, const char *buf, size_t count) 826 { 827 struct cpudata *cpu = all_cpu_data[policy->cpu]; 828 char str_preference[21]; 829 bool raw = false; 830 ssize_t ret; 831 u32 epp = 0; 832 833 ret = sscanf(buf, "%20s", str_preference); 834 if (ret != 1) 835 return -EINVAL; 836 837 ret = match_string(energy_perf_strings, -1, str_preference); 838 if (ret < 0) { 839 if (!boot_cpu_has(X86_FEATURE_HWP_EPP)) 840 return ret; 841 842 ret = kstrtouint(buf, 10, &epp); 843 if (ret) 844 return ret; 845 846 if (epp > 255) 847 return -EINVAL; 848 849 raw = true; 850 } 851 852 /* 853 * This function runs with the policy R/W semaphore held, which 854 * guarantees that the driver pointer will not change while it is 855 * running. 856 */ 857 if (!intel_pstate_driver) 858 return -EAGAIN; 859 860 mutex_lock(&intel_pstate_limits_lock); 861 862 if (intel_pstate_driver == &intel_pstate) { 863 ret = intel_pstate_set_energy_pref_index(cpu, ret, raw, epp); 864 } else { 865 /* 866 * In the passive mode the governor needs to be stopped on the 867 * target CPU before the EPP update and restarted after it, 868 * which is super-heavy-weight, so make sure it is worth doing 869 * upfront. 870 */ 871 if (!raw) 872 epp = ret ? epp_values[ret] : cpu->epp_default; 873 874 if (cpu->epp_cached != epp) { 875 int err; 876 877 cpufreq_stop_governor(policy); 878 ret = intel_pstate_set_epp(cpu, epp); 879 err = cpufreq_start_governor(policy); 880 if (!ret) 881 ret = err; 882 } else { 883 ret = 0; 884 } 885 } 886 887 mutex_unlock(&intel_pstate_limits_lock); 888 889 return ret ?: count; 890 } 891 892 static ssize_t show_energy_performance_preference( 893 struct cpufreq_policy *policy, char *buf) 894 { 895 struct cpudata *cpu_data = all_cpu_data[policy->cpu]; 896 int preference, raw_epp; 897 898 preference = intel_pstate_get_energy_pref_index(cpu_data, &raw_epp); 899 if (preference < 0) 900 return preference; 901 902 if (raw_epp) 903 return sprintf(buf, "%d\n", raw_epp); 904 else 905 return sprintf(buf, "%s\n", energy_perf_strings[preference]); 906 } 907 908 cpufreq_freq_attr_rw(energy_performance_preference); 909 910 static ssize_t show_base_frequency(struct cpufreq_policy *policy, char *buf) 911 { 912 struct cpudata *cpu = all_cpu_data[policy->cpu]; 913 int ratio, freq; 914 915 ratio = intel_pstate_get_cppc_guaranteed(policy->cpu); 916 if (ratio <= 0) { 917 u64 cap; 918 919 rdmsrl_on_cpu(policy->cpu, MSR_HWP_CAPABILITIES, &cap); 920 ratio = HWP_GUARANTEED_PERF(cap); 921 } 922 923 freq = ratio * cpu->pstate.scaling; 924 if (cpu->pstate.scaling != cpu->pstate.perf_ctl_scaling) 925 freq = rounddown(freq, cpu->pstate.perf_ctl_scaling); 926 927 return sprintf(buf, "%d\n", freq); 928 } 929 930 cpufreq_freq_attr_ro(base_frequency); 931 932 static struct freq_attr *hwp_cpufreq_attrs[] = { 933 &energy_performance_preference, 934 &energy_performance_available_preferences, 935 &base_frequency, 936 NULL, 937 }; 938 939 static bool no_cas __ro_after_init; 940 941 static struct cpudata *hybrid_max_perf_cpu __read_mostly; 942 /* 943 * Protects hybrid_max_perf_cpu, the capacity_perf fields in struct cpudata, 944 * and the x86 arch scale-invariance information from concurrent updates. 945 */ 946 static DEFINE_MUTEX(hybrid_capacity_lock); 947 948 static void hybrid_set_cpu_capacity(struct cpudata *cpu) 949 { 950 arch_set_cpu_capacity(cpu->cpu, cpu->capacity_perf, 951 hybrid_max_perf_cpu->capacity_perf, 952 cpu->capacity_perf, 953 cpu->pstate.max_pstate_physical); 954 955 pr_debug("CPU%d: perf = %u, max. perf = %u, base perf = %d\n", cpu->cpu, 956 cpu->capacity_perf, hybrid_max_perf_cpu->capacity_perf, 957 cpu->pstate.max_pstate_physical); 958 } 959 960 static void hybrid_clear_cpu_capacity(unsigned int cpunum) 961 { 962 arch_set_cpu_capacity(cpunum, 1, 1, 1, 1); 963 } 964 965 static void hybrid_get_capacity_perf(struct cpudata *cpu) 966 { 967 if (READ_ONCE(global.no_turbo)) { 968 cpu->capacity_perf = cpu->pstate.max_pstate_physical; 969 return; 970 } 971 972 cpu->capacity_perf = HWP_HIGHEST_PERF(READ_ONCE(cpu->hwp_cap_cached)); 973 } 974 975 static void hybrid_set_capacity_of_cpus(void) 976 { 977 int cpunum; 978 979 for_each_online_cpu(cpunum) { 980 struct cpudata *cpu = all_cpu_data[cpunum]; 981 982 if (cpu) 983 hybrid_set_cpu_capacity(cpu); 984 } 985 } 986 987 static void hybrid_update_cpu_capacity_scaling(void) 988 { 989 struct cpudata *max_perf_cpu = NULL; 990 unsigned int max_cap_perf = 0; 991 int cpunum; 992 993 for_each_online_cpu(cpunum) { 994 struct cpudata *cpu = all_cpu_data[cpunum]; 995 996 if (!cpu) 997 continue; 998 999 /* 1000 * During initialization, CPU performance at full capacity needs 1001 * to be determined. 1002 */ 1003 if (!hybrid_max_perf_cpu) 1004 hybrid_get_capacity_perf(cpu); 1005 1006 /* 1007 * If hybrid_max_perf_cpu is not NULL at this point, it is 1008 * being replaced, so don't take it into account when looking 1009 * for the new one. 1010 */ 1011 if (cpu == hybrid_max_perf_cpu) 1012 continue; 1013 1014 if (cpu->capacity_perf > max_cap_perf) { 1015 max_cap_perf = cpu->capacity_perf; 1016 max_perf_cpu = cpu; 1017 } 1018 } 1019 1020 if (max_perf_cpu) { 1021 hybrid_max_perf_cpu = max_perf_cpu; 1022 hybrid_set_capacity_of_cpus(); 1023 } else { 1024 pr_info("Found no CPUs with nonzero maximum performance\n"); 1025 /* Revert to the flat CPU capacity structure. */ 1026 for_each_online_cpu(cpunum) 1027 hybrid_clear_cpu_capacity(cpunum); 1028 } 1029 } 1030 1031 static void __hybrid_refresh_cpu_capacity_scaling(void) 1032 { 1033 hybrid_max_perf_cpu = NULL; 1034 hybrid_update_cpu_capacity_scaling(); 1035 } 1036 1037 static void hybrid_refresh_cpu_capacity_scaling(void) 1038 { 1039 guard(mutex)(&hybrid_capacity_lock); 1040 1041 __hybrid_refresh_cpu_capacity_scaling(); 1042 } 1043 1044 static void hybrid_init_cpu_capacity_scaling(bool refresh) 1045 { 1046 /* Bail out if enabling capacity-aware scheduling is prohibited. */ 1047 if (no_cas) 1048 return; 1049 1050 /* 1051 * If hybrid_max_perf_cpu is set at this point, the hybrid CPU capacity 1052 * scaling has been enabled already and the driver is just changing the 1053 * operation mode. 1054 */ 1055 if (refresh) { 1056 hybrid_refresh_cpu_capacity_scaling(); 1057 return; 1058 } 1059 1060 /* 1061 * On hybrid systems, use asym capacity instead of ITMT, but because 1062 * the capacity of SMT threads is not deterministic even approximately, 1063 * do not do that when SMT is in use. 1064 */ 1065 if (hwp_is_hybrid && !sched_smt_active() && arch_enable_hybrid_capacity_scale()) { 1066 hybrid_refresh_cpu_capacity_scaling(); 1067 /* 1068 * Disabling ITMT causes sched domains to be rebuilt to disable asym 1069 * packing and enable asym capacity. 1070 */ 1071 sched_clear_itmt_support(); 1072 } 1073 } 1074 1075 static bool hybrid_clear_max_perf_cpu(void) 1076 { 1077 bool ret; 1078 1079 guard(mutex)(&hybrid_capacity_lock); 1080 1081 ret = !!hybrid_max_perf_cpu; 1082 hybrid_max_perf_cpu = NULL; 1083 1084 return ret; 1085 } 1086 1087 static void __intel_pstate_get_hwp_cap(struct cpudata *cpu) 1088 { 1089 u64 cap; 1090 1091 rdmsrl_on_cpu(cpu->cpu, MSR_HWP_CAPABILITIES, &cap); 1092 WRITE_ONCE(cpu->hwp_cap_cached, cap); 1093 cpu->pstate.max_pstate = HWP_GUARANTEED_PERF(cap); 1094 cpu->pstate.turbo_pstate = HWP_HIGHEST_PERF(cap); 1095 } 1096 1097 static void intel_pstate_get_hwp_cap(struct cpudata *cpu) 1098 { 1099 int scaling = cpu->pstate.scaling; 1100 1101 __intel_pstate_get_hwp_cap(cpu); 1102 1103 cpu->pstate.max_freq = cpu->pstate.max_pstate * scaling; 1104 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * scaling; 1105 if (scaling != cpu->pstate.perf_ctl_scaling) { 1106 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling; 1107 1108 cpu->pstate.max_freq = rounddown(cpu->pstate.max_freq, 1109 perf_ctl_scaling); 1110 cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_freq, 1111 perf_ctl_scaling); 1112 } 1113 } 1114 1115 static void hybrid_update_capacity(struct cpudata *cpu) 1116 { 1117 unsigned int max_cap_perf; 1118 1119 mutex_lock(&hybrid_capacity_lock); 1120 1121 if (!hybrid_max_perf_cpu) 1122 goto unlock; 1123 1124 /* 1125 * The maximum performance of the CPU may have changed, but assume 1126 * that the performance of the other CPUs has not changed. 1127 */ 1128 max_cap_perf = hybrid_max_perf_cpu->capacity_perf; 1129 1130 intel_pstate_get_hwp_cap(cpu); 1131 1132 hybrid_get_capacity_perf(cpu); 1133 /* Should hybrid_max_perf_cpu be replaced by this CPU? */ 1134 if (cpu->capacity_perf > max_cap_perf) { 1135 hybrid_max_perf_cpu = cpu; 1136 hybrid_set_capacity_of_cpus(); 1137 goto unlock; 1138 } 1139 1140 /* If this CPU is hybrid_max_perf_cpu, should it be replaced? */ 1141 if (cpu == hybrid_max_perf_cpu && cpu->capacity_perf < max_cap_perf) { 1142 hybrid_update_cpu_capacity_scaling(); 1143 goto unlock; 1144 } 1145 1146 hybrid_set_cpu_capacity(cpu); 1147 1148 unlock: 1149 mutex_unlock(&hybrid_capacity_lock); 1150 } 1151 1152 static void intel_pstate_hwp_set(unsigned int cpu) 1153 { 1154 struct cpudata *cpu_data = all_cpu_data[cpu]; 1155 int max, min; 1156 u64 value; 1157 s16 epp; 1158 1159 max = cpu_data->max_perf_ratio; 1160 min = cpu_data->min_perf_ratio; 1161 1162 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) 1163 min = max; 1164 1165 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value); 1166 1167 value &= ~HWP_MIN_PERF(~0L); 1168 value |= HWP_MIN_PERF(min); 1169 1170 value &= ~HWP_MAX_PERF(~0L); 1171 value |= HWP_MAX_PERF(max); 1172 1173 if (cpu_data->epp_policy == cpu_data->policy) 1174 goto skip_epp; 1175 1176 cpu_data->epp_policy = cpu_data->policy; 1177 1178 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) { 1179 epp = intel_pstate_get_epp(cpu_data, value); 1180 cpu_data->epp_powersave = epp; 1181 /* If EPP read was failed, then don't try to write */ 1182 if (epp < 0) 1183 goto skip_epp; 1184 1185 epp = 0; 1186 } else { 1187 /* skip setting EPP, when saved value is invalid */ 1188 if (cpu_data->epp_powersave < 0) 1189 goto skip_epp; 1190 1191 /* 1192 * No need to restore EPP when it is not zero. This 1193 * means: 1194 * - Policy is not changed 1195 * - user has manually changed 1196 * - Error reading EPB 1197 */ 1198 epp = intel_pstate_get_epp(cpu_data, value); 1199 if (epp) 1200 goto skip_epp; 1201 1202 epp = cpu_data->epp_powersave; 1203 } 1204 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 1205 value &= ~GENMASK_ULL(31, 24); 1206 value |= (u64)epp << 24; 1207 } else { 1208 intel_pstate_set_epb(cpu, epp); 1209 } 1210 skip_epp: 1211 WRITE_ONCE(cpu_data->hwp_req_cached, value); 1212 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value); 1213 } 1214 1215 static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata); 1216 1217 static void intel_pstate_hwp_offline(struct cpudata *cpu) 1218 { 1219 u64 value = READ_ONCE(cpu->hwp_req_cached); 1220 int min_perf; 1221 1222 intel_pstate_disable_hwp_interrupt(cpu); 1223 1224 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 1225 /* 1226 * In case the EPP has been set to "performance" by the 1227 * active mode "performance" scaling algorithm, replace that 1228 * temporary value with the cached EPP one. 1229 */ 1230 value &= ~GENMASK_ULL(31, 24); 1231 value |= HWP_ENERGY_PERF_PREFERENCE(cpu->epp_cached); 1232 /* 1233 * However, make sure that EPP will be set to "performance" when 1234 * the CPU is brought back online again and the "performance" 1235 * scaling algorithm is still in effect. 1236 */ 1237 cpu->epp_policy = CPUFREQ_POLICY_UNKNOWN; 1238 } 1239 1240 /* 1241 * Clear the desired perf field in the cached HWP request value to 1242 * prevent nonzero desired values from being leaked into the active 1243 * mode. 1244 */ 1245 value &= ~HWP_DESIRED_PERF(~0L); 1246 WRITE_ONCE(cpu->hwp_req_cached, value); 1247 1248 value &= ~GENMASK_ULL(31, 0); 1249 min_perf = HWP_LOWEST_PERF(READ_ONCE(cpu->hwp_cap_cached)); 1250 1251 /* Set hwp_max = hwp_min */ 1252 value |= HWP_MAX_PERF(min_perf); 1253 value |= HWP_MIN_PERF(min_perf); 1254 1255 /* Set EPP to min */ 1256 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) 1257 value |= HWP_ENERGY_PERF_PREFERENCE(HWP_EPP_POWERSAVE); 1258 1259 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 1260 1261 mutex_lock(&hybrid_capacity_lock); 1262 1263 if (!hybrid_max_perf_cpu) { 1264 mutex_unlock(&hybrid_capacity_lock); 1265 1266 return; 1267 } 1268 1269 if (hybrid_max_perf_cpu == cpu) 1270 hybrid_update_cpu_capacity_scaling(); 1271 1272 mutex_unlock(&hybrid_capacity_lock); 1273 1274 /* Reset the capacity of the CPU going offline to the initial value. */ 1275 hybrid_clear_cpu_capacity(cpu->cpu); 1276 } 1277 1278 #define POWER_CTL_EE_ENABLE 1 1279 #define POWER_CTL_EE_DISABLE 2 1280 1281 static int power_ctl_ee_state; 1282 1283 static void set_power_ctl_ee_state(bool input) 1284 { 1285 u64 power_ctl; 1286 1287 mutex_lock(&intel_pstate_driver_lock); 1288 rdmsrl(MSR_IA32_POWER_CTL, power_ctl); 1289 if (input) { 1290 power_ctl &= ~BIT(MSR_IA32_POWER_CTL_BIT_EE); 1291 power_ctl_ee_state = POWER_CTL_EE_ENABLE; 1292 } else { 1293 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE); 1294 power_ctl_ee_state = POWER_CTL_EE_DISABLE; 1295 } 1296 wrmsrl(MSR_IA32_POWER_CTL, power_ctl); 1297 mutex_unlock(&intel_pstate_driver_lock); 1298 } 1299 1300 static void intel_pstate_hwp_enable(struct cpudata *cpudata); 1301 1302 static void intel_pstate_hwp_reenable(struct cpudata *cpu) 1303 { 1304 intel_pstate_hwp_enable(cpu); 1305 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, READ_ONCE(cpu->hwp_req_cached)); 1306 } 1307 1308 static int intel_pstate_suspend(struct cpufreq_policy *policy) 1309 { 1310 struct cpudata *cpu = all_cpu_data[policy->cpu]; 1311 1312 pr_debug("CPU %d suspending\n", cpu->cpu); 1313 1314 cpu->suspended = true; 1315 1316 /* disable HWP interrupt and cancel any pending work */ 1317 intel_pstate_disable_hwp_interrupt(cpu); 1318 1319 return 0; 1320 } 1321 1322 static int intel_pstate_resume(struct cpufreq_policy *policy) 1323 { 1324 struct cpudata *cpu = all_cpu_data[policy->cpu]; 1325 1326 pr_debug("CPU %d resuming\n", cpu->cpu); 1327 1328 /* Only restore if the system default is changed */ 1329 if (power_ctl_ee_state == POWER_CTL_EE_ENABLE) 1330 set_power_ctl_ee_state(true); 1331 else if (power_ctl_ee_state == POWER_CTL_EE_DISABLE) 1332 set_power_ctl_ee_state(false); 1333 1334 if (cpu->suspended && hwp_active) { 1335 mutex_lock(&intel_pstate_limits_lock); 1336 1337 /* Re-enable HWP, because "online" has not done that. */ 1338 intel_pstate_hwp_reenable(cpu); 1339 1340 mutex_unlock(&intel_pstate_limits_lock); 1341 } 1342 1343 cpu->suspended = false; 1344 1345 return 0; 1346 } 1347 1348 static void intel_pstate_update_policies(void) 1349 { 1350 int cpu; 1351 1352 for_each_possible_cpu(cpu) 1353 cpufreq_update_policy(cpu); 1354 } 1355 1356 static void __intel_pstate_update_max_freq(struct cpudata *cpudata, 1357 struct cpufreq_policy *policy) 1358 { 1359 if (hwp_active) 1360 intel_pstate_get_hwp_cap(cpudata); 1361 1362 policy->cpuinfo.max_freq = READ_ONCE(global.no_turbo) ? 1363 cpudata->pstate.max_freq : cpudata->pstate.turbo_freq; 1364 1365 refresh_frequency_limits(policy); 1366 } 1367 1368 static void intel_pstate_update_limits(unsigned int cpu) 1369 { 1370 struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpu); 1371 struct cpudata *cpudata; 1372 1373 if (!policy) 1374 return; 1375 1376 cpudata = all_cpu_data[cpu]; 1377 1378 __intel_pstate_update_max_freq(cpudata, policy); 1379 1380 /* Prevent the driver from being unregistered now. */ 1381 mutex_lock(&intel_pstate_driver_lock); 1382 1383 cpufreq_cpu_release(policy); 1384 1385 hybrid_update_capacity(cpudata); 1386 1387 mutex_unlock(&intel_pstate_driver_lock); 1388 } 1389 1390 static void intel_pstate_update_limits_for_all(void) 1391 { 1392 int cpu; 1393 1394 for_each_possible_cpu(cpu) { 1395 struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpu); 1396 1397 if (!policy) 1398 continue; 1399 1400 __intel_pstate_update_max_freq(all_cpu_data[cpu], policy); 1401 1402 cpufreq_cpu_release(policy); 1403 } 1404 1405 mutex_lock(&hybrid_capacity_lock); 1406 1407 if (hybrid_max_perf_cpu) 1408 __hybrid_refresh_cpu_capacity_scaling(); 1409 1410 mutex_unlock(&hybrid_capacity_lock); 1411 } 1412 1413 /************************** sysfs begin ************************/ 1414 #define show_one(file_name, object) \ 1415 static ssize_t show_##file_name \ 1416 (struct kobject *kobj, struct kobj_attribute *attr, char *buf) \ 1417 { \ 1418 return sprintf(buf, "%u\n", global.object); \ 1419 } 1420 1421 static ssize_t intel_pstate_show_status(char *buf); 1422 static int intel_pstate_update_status(const char *buf, size_t size); 1423 1424 static ssize_t show_status(struct kobject *kobj, 1425 struct kobj_attribute *attr, char *buf) 1426 { 1427 ssize_t ret; 1428 1429 mutex_lock(&intel_pstate_driver_lock); 1430 ret = intel_pstate_show_status(buf); 1431 mutex_unlock(&intel_pstate_driver_lock); 1432 1433 return ret; 1434 } 1435 1436 static ssize_t store_status(struct kobject *a, struct kobj_attribute *b, 1437 const char *buf, size_t count) 1438 { 1439 char *p = memchr(buf, '\n', count); 1440 int ret; 1441 1442 mutex_lock(&intel_pstate_driver_lock); 1443 ret = intel_pstate_update_status(buf, p ? p - buf : count); 1444 mutex_unlock(&intel_pstate_driver_lock); 1445 1446 return ret < 0 ? ret : count; 1447 } 1448 1449 static ssize_t show_turbo_pct(struct kobject *kobj, 1450 struct kobj_attribute *attr, char *buf) 1451 { 1452 struct cpudata *cpu; 1453 int total, no_turbo, turbo_pct; 1454 uint32_t turbo_fp; 1455 1456 mutex_lock(&intel_pstate_driver_lock); 1457 1458 if (!intel_pstate_driver) { 1459 mutex_unlock(&intel_pstate_driver_lock); 1460 return -EAGAIN; 1461 } 1462 1463 cpu = all_cpu_data[0]; 1464 1465 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; 1466 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1; 1467 turbo_fp = div_fp(no_turbo, total); 1468 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100))); 1469 1470 mutex_unlock(&intel_pstate_driver_lock); 1471 1472 return sprintf(buf, "%u\n", turbo_pct); 1473 } 1474 1475 static ssize_t show_num_pstates(struct kobject *kobj, 1476 struct kobj_attribute *attr, char *buf) 1477 { 1478 struct cpudata *cpu; 1479 int total; 1480 1481 mutex_lock(&intel_pstate_driver_lock); 1482 1483 if (!intel_pstate_driver) { 1484 mutex_unlock(&intel_pstate_driver_lock); 1485 return -EAGAIN; 1486 } 1487 1488 cpu = all_cpu_data[0]; 1489 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; 1490 1491 mutex_unlock(&intel_pstate_driver_lock); 1492 1493 return sprintf(buf, "%u\n", total); 1494 } 1495 1496 static ssize_t show_no_turbo(struct kobject *kobj, 1497 struct kobj_attribute *attr, char *buf) 1498 { 1499 ssize_t ret; 1500 1501 mutex_lock(&intel_pstate_driver_lock); 1502 1503 if (!intel_pstate_driver) { 1504 mutex_unlock(&intel_pstate_driver_lock); 1505 return -EAGAIN; 1506 } 1507 1508 ret = sprintf(buf, "%u\n", global.no_turbo); 1509 1510 mutex_unlock(&intel_pstate_driver_lock); 1511 1512 return ret; 1513 } 1514 1515 static ssize_t store_no_turbo(struct kobject *a, struct kobj_attribute *b, 1516 const char *buf, size_t count) 1517 { 1518 unsigned int input; 1519 bool no_turbo; 1520 1521 if (sscanf(buf, "%u", &input) != 1) 1522 return -EINVAL; 1523 1524 mutex_lock(&intel_pstate_driver_lock); 1525 1526 if (!intel_pstate_driver) { 1527 count = -EAGAIN; 1528 goto unlock_driver; 1529 } 1530 1531 no_turbo = !!clamp_t(int, input, 0, 1); 1532 1533 WRITE_ONCE(global.turbo_disabled, turbo_is_disabled()); 1534 if (global.turbo_disabled && !no_turbo) { 1535 pr_notice("Turbo disabled by BIOS or unavailable on processor\n"); 1536 count = -EPERM; 1537 if (global.no_turbo) 1538 goto unlock_driver; 1539 else 1540 no_turbo = 1; 1541 } 1542 1543 if (no_turbo == global.no_turbo) { 1544 goto unlock_driver; 1545 } 1546 1547 WRITE_ONCE(global.no_turbo, no_turbo); 1548 1549 mutex_lock(&intel_pstate_limits_lock); 1550 1551 if (no_turbo) { 1552 struct cpudata *cpu = all_cpu_data[0]; 1553 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate; 1554 1555 /* Squash the global minimum into the permitted range. */ 1556 if (global.min_perf_pct > pct) 1557 global.min_perf_pct = pct; 1558 } 1559 1560 mutex_unlock(&intel_pstate_limits_lock); 1561 1562 intel_pstate_update_limits_for_all(); 1563 arch_set_max_freq_ratio(no_turbo); 1564 1565 unlock_driver: 1566 mutex_unlock(&intel_pstate_driver_lock); 1567 1568 return count; 1569 } 1570 1571 static void update_qos_request(enum freq_qos_req_type type) 1572 { 1573 struct freq_qos_request *req; 1574 struct cpufreq_policy *policy; 1575 int i; 1576 1577 for_each_possible_cpu(i) { 1578 struct cpudata *cpu = all_cpu_data[i]; 1579 unsigned int freq, perf_pct; 1580 1581 policy = cpufreq_cpu_get(i); 1582 if (!policy) 1583 continue; 1584 1585 req = policy->driver_data; 1586 cpufreq_cpu_put(policy); 1587 1588 if (!req) 1589 continue; 1590 1591 if (hwp_active) 1592 intel_pstate_get_hwp_cap(cpu); 1593 1594 if (type == FREQ_QOS_MIN) { 1595 perf_pct = global.min_perf_pct; 1596 } else { 1597 req++; 1598 perf_pct = global.max_perf_pct; 1599 } 1600 1601 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * perf_pct, 100); 1602 1603 if (freq_qos_update_request(req, freq) < 0) 1604 pr_warn("Failed to update freq constraint: CPU%d\n", i); 1605 } 1606 } 1607 1608 static ssize_t store_max_perf_pct(struct kobject *a, struct kobj_attribute *b, 1609 const char *buf, size_t count) 1610 { 1611 unsigned int input; 1612 int ret; 1613 1614 ret = sscanf(buf, "%u", &input); 1615 if (ret != 1) 1616 return -EINVAL; 1617 1618 mutex_lock(&intel_pstate_driver_lock); 1619 1620 if (!intel_pstate_driver) { 1621 mutex_unlock(&intel_pstate_driver_lock); 1622 return -EAGAIN; 1623 } 1624 1625 mutex_lock(&intel_pstate_limits_lock); 1626 1627 global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100); 1628 1629 mutex_unlock(&intel_pstate_limits_lock); 1630 1631 if (intel_pstate_driver == &intel_pstate) 1632 intel_pstate_update_policies(); 1633 else 1634 update_qos_request(FREQ_QOS_MAX); 1635 1636 mutex_unlock(&intel_pstate_driver_lock); 1637 1638 return count; 1639 } 1640 1641 static ssize_t store_min_perf_pct(struct kobject *a, struct kobj_attribute *b, 1642 const char *buf, size_t count) 1643 { 1644 unsigned int input; 1645 int ret; 1646 1647 ret = sscanf(buf, "%u", &input); 1648 if (ret != 1) 1649 return -EINVAL; 1650 1651 mutex_lock(&intel_pstate_driver_lock); 1652 1653 if (!intel_pstate_driver) { 1654 mutex_unlock(&intel_pstate_driver_lock); 1655 return -EAGAIN; 1656 } 1657 1658 mutex_lock(&intel_pstate_limits_lock); 1659 1660 global.min_perf_pct = clamp_t(int, input, 1661 min_perf_pct_min(), global.max_perf_pct); 1662 1663 mutex_unlock(&intel_pstate_limits_lock); 1664 1665 if (intel_pstate_driver == &intel_pstate) 1666 intel_pstate_update_policies(); 1667 else 1668 update_qos_request(FREQ_QOS_MIN); 1669 1670 mutex_unlock(&intel_pstate_driver_lock); 1671 1672 return count; 1673 } 1674 1675 static ssize_t show_hwp_dynamic_boost(struct kobject *kobj, 1676 struct kobj_attribute *attr, char *buf) 1677 { 1678 return sprintf(buf, "%u\n", hwp_boost); 1679 } 1680 1681 static ssize_t store_hwp_dynamic_boost(struct kobject *a, 1682 struct kobj_attribute *b, 1683 const char *buf, size_t count) 1684 { 1685 unsigned int input; 1686 int ret; 1687 1688 ret = kstrtouint(buf, 10, &input); 1689 if (ret) 1690 return ret; 1691 1692 mutex_lock(&intel_pstate_driver_lock); 1693 hwp_boost = !!input; 1694 intel_pstate_update_policies(); 1695 mutex_unlock(&intel_pstate_driver_lock); 1696 1697 return count; 1698 } 1699 1700 static ssize_t show_energy_efficiency(struct kobject *kobj, struct kobj_attribute *attr, 1701 char *buf) 1702 { 1703 u64 power_ctl; 1704 int enable; 1705 1706 rdmsrl(MSR_IA32_POWER_CTL, power_ctl); 1707 enable = !!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE)); 1708 return sprintf(buf, "%d\n", !enable); 1709 } 1710 1711 static ssize_t store_energy_efficiency(struct kobject *a, struct kobj_attribute *b, 1712 const char *buf, size_t count) 1713 { 1714 bool input; 1715 int ret; 1716 1717 ret = kstrtobool(buf, &input); 1718 if (ret) 1719 return ret; 1720 1721 set_power_ctl_ee_state(input); 1722 1723 return count; 1724 } 1725 1726 show_one(max_perf_pct, max_perf_pct); 1727 show_one(min_perf_pct, min_perf_pct); 1728 1729 define_one_global_rw(status); 1730 define_one_global_rw(no_turbo); 1731 define_one_global_rw(max_perf_pct); 1732 define_one_global_rw(min_perf_pct); 1733 define_one_global_ro(turbo_pct); 1734 define_one_global_ro(num_pstates); 1735 define_one_global_rw(hwp_dynamic_boost); 1736 define_one_global_rw(energy_efficiency); 1737 1738 static struct attribute *intel_pstate_attributes[] = { 1739 &status.attr, 1740 &no_turbo.attr, 1741 NULL 1742 }; 1743 1744 static const struct attribute_group intel_pstate_attr_group = { 1745 .attrs = intel_pstate_attributes, 1746 }; 1747 1748 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[]; 1749 1750 static struct kobject *intel_pstate_kobject; 1751 1752 static void __init intel_pstate_sysfs_expose_params(void) 1753 { 1754 struct device *dev_root = bus_get_dev_root(&cpu_subsys); 1755 int rc; 1756 1757 if (dev_root) { 1758 intel_pstate_kobject = kobject_create_and_add("intel_pstate", &dev_root->kobj); 1759 put_device(dev_root); 1760 } 1761 if (WARN_ON(!intel_pstate_kobject)) 1762 return; 1763 1764 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group); 1765 if (WARN_ON(rc)) 1766 return; 1767 1768 if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) { 1769 rc = sysfs_create_file(intel_pstate_kobject, &turbo_pct.attr); 1770 WARN_ON(rc); 1771 1772 rc = sysfs_create_file(intel_pstate_kobject, &num_pstates.attr); 1773 WARN_ON(rc); 1774 } 1775 1776 /* 1777 * If per cpu limits are enforced there are no global limits, so 1778 * return without creating max/min_perf_pct attributes 1779 */ 1780 if (per_cpu_limits) 1781 return; 1782 1783 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr); 1784 WARN_ON(rc); 1785 1786 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr); 1787 WARN_ON(rc); 1788 1789 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids)) { 1790 rc = sysfs_create_file(intel_pstate_kobject, &energy_efficiency.attr); 1791 WARN_ON(rc); 1792 } 1793 } 1794 1795 static void __init intel_pstate_sysfs_remove(void) 1796 { 1797 if (!intel_pstate_kobject) 1798 return; 1799 1800 sysfs_remove_group(intel_pstate_kobject, &intel_pstate_attr_group); 1801 1802 if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) { 1803 sysfs_remove_file(intel_pstate_kobject, &num_pstates.attr); 1804 sysfs_remove_file(intel_pstate_kobject, &turbo_pct.attr); 1805 } 1806 1807 if (!per_cpu_limits) { 1808 sysfs_remove_file(intel_pstate_kobject, &max_perf_pct.attr); 1809 sysfs_remove_file(intel_pstate_kobject, &min_perf_pct.attr); 1810 1811 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids)) 1812 sysfs_remove_file(intel_pstate_kobject, &energy_efficiency.attr); 1813 } 1814 1815 kobject_put(intel_pstate_kobject); 1816 } 1817 1818 static void intel_pstate_sysfs_expose_hwp_dynamic_boost(void) 1819 { 1820 int rc; 1821 1822 if (!hwp_active) 1823 return; 1824 1825 rc = sysfs_create_file(intel_pstate_kobject, &hwp_dynamic_boost.attr); 1826 WARN_ON_ONCE(rc); 1827 } 1828 1829 static void intel_pstate_sysfs_hide_hwp_dynamic_boost(void) 1830 { 1831 if (!hwp_active) 1832 return; 1833 1834 sysfs_remove_file(intel_pstate_kobject, &hwp_dynamic_boost.attr); 1835 } 1836 1837 /************************** sysfs end ************************/ 1838 1839 static void intel_pstate_notify_work(struct work_struct *work) 1840 { 1841 struct cpudata *cpudata = 1842 container_of(to_delayed_work(work), struct cpudata, hwp_notify_work); 1843 struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpudata->cpu); 1844 1845 if (policy) { 1846 __intel_pstate_update_max_freq(cpudata, policy); 1847 1848 cpufreq_cpu_release(policy); 1849 1850 /* 1851 * The driver will not be unregistered while this function is 1852 * running, so update the capacity without acquiring the driver 1853 * lock. 1854 */ 1855 hybrid_update_capacity(cpudata); 1856 } 1857 1858 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0); 1859 } 1860 1861 static DEFINE_RAW_SPINLOCK(hwp_notify_lock); 1862 static cpumask_t hwp_intr_enable_mask; 1863 1864 #define HWP_GUARANTEED_PERF_CHANGE_STATUS BIT(0) 1865 #define HWP_HIGHEST_PERF_CHANGE_STATUS BIT(3) 1866 1867 void notify_hwp_interrupt(void) 1868 { 1869 unsigned int this_cpu = smp_processor_id(); 1870 u64 value, status_mask; 1871 unsigned long flags; 1872 1873 if (!hwp_active || !cpu_feature_enabled(X86_FEATURE_HWP_NOTIFY)) 1874 return; 1875 1876 status_mask = HWP_GUARANTEED_PERF_CHANGE_STATUS; 1877 if (cpu_feature_enabled(X86_FEATURE_HWP_HIGHEST_PERF_CHANGE)) 1878 status_mask |= HWP_HIGHEST_PERF_CHANGE_STATUS; 1879 1880 rdmsrl_safe(MSR_HWP_STATUS, &value); 1881 if (!(value & status_mask)) 1882 return; 1883 1884 raw_spin_lock_irqsave(&hwp_notify_lock, flags); 1885 1886 if (!cpumask_test_cpu(this_cpu, &hwp_intr_enable_mask)) 1887 goto ack_intr; 1888 1889 schedule_delayed_work(&all_cpu_data[this_cpu]->hwp_notify_work, 1890 msecs_to_jiffies(10)); 1891 1892 raw_spin_unlock_irqrestore(&hwp_notify_lock, flags); 1893 1894 return; 1895 1896 ack_intr: 1897 wrmsrl_safe(MSR_HWP_STATUS, 0); 1898 raw_spin_unlock_irqrestore(&hwp_notify_lock, flags); 1899 } 1900 1901 static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata) 1902 { 1903 bool cancel_work; 1904 1905 if (!cpu_feature_enabled(X86_FEATURE_HWP_NOTIFY)) 1906 return; 1907 1908 /* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */ 1909 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00); 1910 1911 raw_spin_lock_irq(&hwp_notify_lock); 1912 cancel_work = cpumask_test_and_clear_cpu(cpudata->cpu, &hwp_intr_enable_mask); 1913 raw_spin_unlock_irq(&hwp_notify_lock); 1914 1915 if (cancel_work) 1916 cancel_delayed_work_sync(&cpudata->hwp_notify_work); 1917 } 1918 1919 #define HWP_GUARANTEED_PERF_CHANGE_REQ BIT(0) 1920 #define HWP_HIGHEST_PERF_CHANGE_REQ BIT(2) 1921 1922 static void intel_pstate_enable_hwp_interrupt(struct cpudata *cpudata) 1923 { 1924 /* Enable HWP notification interrupt for performance change */ 1925 if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) { 1926 u64 interrupt_mask = HWP_GUARANTEED_PERF_CHANGE_REQ; 1927 1928 raw_spin_lock_irq(&hwp_notify_lock); 1929 INIT_DELAYED_WORK(&cpudata->hwp_notify_work, intel_pstate_notify_work); 1930 cpumask_set_cpu(cpudata->cpu, &hwp_intr_enable_mask); 1931 raw_spin_unlock_irq(&hwp_notify_lock); 1932 1933 if (cpu_feature_enabled(X86_FEATURE_HWP_HIGHEST_PERF_CHANGE)) 1934 interrupt_mask |= HWP_HIGHEST_PERF_CHANGE_REQ; 1935 1936 /* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */ 1937 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, interrupt_mask); 1938 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0); 1939 } 1940 } 1941 1942 static void intel_pstate_update_epp_defaults(struct cpudata *cpudata) 1943 { 1944 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0); 1945 1946 /* 1947 * If the EPP is set by firmware, which means that firmware enabled HWP 1948 * - Is equal or less than 0x80 (default balance_perf EPP) 1949 * - But less performance oriented than performance EPP 1950 * then use this as new balance_perf EPP. 1951 */ 1952 if (hwp_forced && cpudata->epp_default <= HWP_EPP_BALANCE_PERFORMANCE && 1953 cpudata->epp_default > HWP_EPP_PERFORMANCE) { 1954 epp_values[EPP_INDEX_BALANCE_PERFORMANCE] = cpudata->epp_default; 1955 return; 1956 } 1957 1958 /* 1959 * If this CPU gen doesn't call for change in balance_perf 1960 * EPP return. 1961 */ 1962 if (epp_values[EPP_INDEX_BALANCE_PERFORMANCE] == HWP_EPP_BALANCE_PERFORMANCE) 1963 return; 1964 1965 /* 1966 * Use hard coded value per gen to update the balance_perf 1967 * and default EPP. 1968 */ 1969 cpudata->epp_default = epp_values[EPP_INDEX_BALANCE_PERFORMANCE]; 1970 intel_pstate_set_epp(cpudata, cpudata->epp_default); 1971 } 1972 1973 static void intel_pstate_hwp_enable(struct cpudata *cpudata) 1974 { 1975 /* First disable HWP notification interrupt till we activate again */ 1976 if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) 1977 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00); 1978 1979 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1); 1980 1981 intel_pstate_enable_hwp_interrupt(cpudata); 1982 1983 if (cpudata->epp_default >= 0) 1984 return; 1985 1986 intel_pstate_update_epp_defaults(cpudata); 1987 } 1988 1989 static int atom_get_min_pstate(int not_used) 1990 { 1991 u64 value; 1992 1993 rdmsrl(MSR_ATOM_CORE_RATIOS, value); 1994 return (value >> 8) & 0x7F; 1995 } 1996 1997 static int atom_get_max_pstate(int not_used) 1998 { 1999 u64 value; 2000 2001 rdmsrl(MSR_ATOM_CORE_RATIOS, value); 2002 return (value >> 16) & 0x7F; 2003 } 2004 2005 static int atom_get_turbo_pstate(int not_used) 2006 { 2007 u64 value; 2008 2009 rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value); 2010 return value & 0x7F; 2011 } 2012 2013 static u64 atom_get_val(struct cpudata *cpudata, int pstate) 2014 { 2015 u64 val; 2016 int32_t vid_fp; 2017 u32 vid; 2018 2019 val = (u64)pstate << 8; 2020 if (READ_ONCE(global.no_turbo) && !READ_ONCE(global.turbo_disabled)) 2021 val |= (u64)1 << 32; 2022 2023 vid_fp = cpudata->vid.min + mul_fp( 2024 int_tofp(pstate - cpudata->pstate.min_pstate), 2025 cpudata->vid.ratio); 2026 2027 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max); 2028 vid = ceiling_fp(vid_fp); 2029 2030 if (pstate > cpudata->pstate.max_pstate) 2031 vid = cpudata->vid.turbo; 2032 2033 return val | vid; 2034 } 2035 2036 static int silvermont_get_scaling(void) 2037 { 2038 u64 value; 2039 int i; 2040 /* Defined in Table 35-6 from SDM (Sept 2015) */ 2041 static int silvermont_freq_table[] = { 2042 83300, 100000, 133300, 116700, 80000}; 2043 2044 rdmsrl(MSR_FSB_FREQ, value); 2045 i = value & 0x7; 2046 WARN_ON(i > 4); 2047 2048 return silvermont_freq_table[i]; 2049 } 2050 2051 static int airmont_get_scaling(void) 2052 { 2053 u64 value; 2054 int i; 2055 /* Defined in Table 35-10 from SDM (Sept 2015) */ 2056 static int airmont_freq_table[] = { 2057 83300, 100000, 133300, 116700, 80000, 2058 93300, 90000, 88900, 87500}; 2059 2060 rdmsrl(MSR_FSB_FREQ, value); 2061 i = value & 0xF; 2062 WARN_ON(i > 8); 2063 2064 return airmont_freq_table[i]; 2065 } 2066 2067 static void atom_get_vid(struct cpudata *cpudata) 2068 { 2069 u64 value; 2070 2071 rdmsrl(MSR_ATOM_CORE_VIDS, value); 2072 cpudata->vid.min = int_tofp((value >> 8) & 0x7f); 2073 cpudata->vid.max = int_tofp((value >> 16) & 0x7f); 2074 cpudata->vid.ratio = div_fp( 2075 cpudata->vid.max - cpudata->vid.min, 2076 int_tofp(cpudata->pstate.max_pstate - 2077 cpudata->pstate.min_pstate)); 2078 2079 rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value); 2080 cpudata->vid.turbo = value & 0x7f; 2081 } 2082 2083 static int core_get_min_pstate(int cpu) 2084 { 2085 u64 value; 2086 2087 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &value); 2088 return (value >> 40) & 0xFF; 2089 } 2090 2091 static int core_get_max_pstate_physical(int cpu) 2092 { 2093 u64 value; 2094 2095 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &value); 2096 return (value >> 8) & 0xFF; 2097 } 2098 2099 static int core_get_tdp_ratio(int cpu, u64 plat_info) 2100 { 2101 /* Check how many TDP levels present */ 2102 if (plat_info & 0x600000000) { 2103 u64 tdp_ctrl; 2104 u64 tdp_ratio; 2105 int tdp_msr; 2106 int err; 2107 2108 /* Get the TDP level (0, 1, 2) to get ratios */ 2109 err = rdmsrl_safe_on_cpu(cpu, MSR_CONFIG_TDP_CONTROL, &tdp_ctrl); 2110 if (err) 2111 return err; 2112 2113 /* TDP MSR are continuous starting at 0x648 */ 2114 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03); 2115 err = rdmsrl_safe_on_cpu(cpu, tdp_msr, &tdp_ratio); 2116 if (err) 2117 return err; 2118 2119 /* For level 1 and 2, bits[23:16] contain the ratio */ 2120 if (tdp_ctrl & 0x03) 2121 tdp_ratio >>= 16; 2122 2123 tdp_ratio &= 0xff; /* ratios are only 8 bits long */ 2124 pr_debug("tdp_ratio %x\n", (int)tdp_ratio); 2125 2126 return (int)tdp_ratio; 2127 } 2128 2129 return -ENXIO; 2130 } 2131 2132 static int core_get_max_pstate(int cpu) 2133 { 2134 u64 tar; 2135 u64 plat_info; 2136 int max_pstate; 2137 int tdp_ratio; 2138 int err; 2139 2140 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &plat_info); 2141 max_pstate = (plat_info >> 8) & 0xFF; 2142 2143 tdp_ratio = core_get_tdp_ratio(cpu, plat_info); 2144 if (tdp_ratio <= 0) 2145 return max_pstate; 2146 2147 if (hwp_active) { 2148 /* Turbo activation ratio is not used on HWP platforms */ 2149 return tdp_ratio; 2150 } 2151 2152 err = rdmsrl_safe_on_cpu(cpu, MSR_TURBO_ACTIVATION_RATIO, &tar); 2153 if (!err) { 2154 int tar_levels; 2155 2156 /* Do some sanity checking for safety */ 2157 tar_levels = tar & 0xff; 2158 if (tdp_ratio - 1 == tar_levels) { 2159 max_pstate = tar_levels; 2160 pr_debug("max_pstate=TAC %x\n", max_pstate); 2161 } 2162 } 2163 2164 return max_pstate; 2165 } 2166 2167 static int core_get_turbo_pstate(int cpu) 2168 { 2169 u64 value; 2170 int nont, ret; 2171 2172 rdmsrl_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value); 2173 nont = core_get_max_pstate(cpu); 2174 ret = (value) & 255; 2175 if (ret <= nont) 2176 ret = nont; 2177 return ret; 2178 } 2179 2180 static u64 core_get_val(struct cpudata *cpudata, int pstate) 2181 { 2182 u64 val; 2183 2184 val = (u64)pstate << 8; 2185 if (READ_ONCE(global.no_turbo) && !READ_ONCE(global.turbo_disabled)) 2186 val |= (u64)1 << 32; 2187 2188 return val; 2189 } 2190 2191 static int knl_get_aperf_mperf_shift(void) 2192 { 2193 return 10; 2194 } 2195 2196 static int knl_get_turbo_pstate(int cpu) 2197 { 2198 u64 value; 2199 int nont, ret; 2200 2201 rdmsrl_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value); 2202 nont = core_get_max_pstate(cpu); 2203 ret = (((value) >> 8) & 0xFF); 2204 if (ret <= nont) 2205 ret = nont; 2206 return ret; 2207 } 2208 2209 static int hwp_get_cpu_scaling(int cpu) 2210 { 2211 if (hybrid_scaling_factor) { 2212 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id()); 2213 u8 cpu_type = c->topo.intel_type; 2214 2215 /* 2216 * Return the hybrid scaling factor for P-cores and use the 2217 * default core scaling for E-cores. 2218 */ 2219 if (cpu_type == INTEL_CPU_TYPE_CORE) 2220 return hybrid_scaling_factor; 2221 2222 if (cpu_type == INTEL_CPU_TYPE_ATOM) 2223 return core_get_scaling(); 2224 } 2225 2226 /* Use core scaling on non-hybrid systems. */ 2227 if (!cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) 2228 return core_get_scaling(); 2229 2230 /* 2231 * The system is hybrid, but the hybrid scaling factor is not known or 2232 * the CPU type is not one of the above, so use CPPC to compute the 2233 * scaling factor for this CPU. 2234 */ 2235 return intel_pstate_cppc_get_scaling(cpu); 2236 } 2237 2238 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate) 2239 { 2240 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu); 2241 cpu->pstate.current_pstate = pstate; 2242 /* 2243 * Generally, there is no guarantee that this code will always run on 2244 * the CPU being updated, so force the register update to run on the 2245 * right CPU. 2246 */ 2247 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL, 2248 pstate_funcs.get_val(cpu, pstate)); 2249 } 2250 2251 static void intel_pstate_set_min_pstate(struct cpudata *cpu) 2252 { 2253 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate); 2254 } 2255 2256 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu) 2257 { 2258 int perf_ctl_max_phys = pstate_funcs.get_max_physical(cpu->cpu); 2259 int perf_ctl_scaling = pstate_funcs.get_scaling(); 2260 2261 cpu->pstate.min_pstate = pstate_funcs.get_min(cpu->cpu); 2262 cpu->pstate.max_pstate_physical = perf_ctl_max_phys; 2263 cpu->pstate.perf_ctl_scaling = perf_ctl_scaling; 2264 2265 if (hwp_active && !hwp_mode_bdw) { 2266 __intel_pstate_get_hwp_cap(cpu); 2267 2268 if (pstate_funcs.get_cpu_scaling) { 2269 cpu->pstate.scaling = pstate_funcs.get_cpu_scaling(cpu->cpu); 2270 if (cpu->pstate.scaling != perf_ctl_scaling) { 2271 intel_pstate_hybrid_hwp_adjust(cpu); 2272 hwp_is_hybrid = true; 2273 } 2274 } else { 2275 cpu->pstate.scaling = perf_ctl_scaling; 2276 } 2277 /* 2278 * If the CPU is going online for the first time and it was 2279 * offline initially, asym capacity scaling needs to be updated. 2280 */ 2281 hybrid_update_capacity(cpu); 2282 } else { 2283 cpu->pstate.scaling = perf_ctl_scaling; 2284 cpu->pstate.max_pstate = pstate_funcs.get_max(cpu->cpu); 2285 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(cpu->cpu); 2286 } 2287 2288 if (cpu->pstate.scaling == perf_ctl_scaling) { 2289 cpu->pstate.min_freq = cpu->pstate.min_pstate * perf_ctl_scaling; 2290 cpu->pstate.max_freq = cpu->pstate.max_pstate * perf_ctl_scaling; 2291 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * perf_ctl_scaling; 2292 } 2293 2294 if (pstate_funcs.get_aperf_mperf_shift) 2295 cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift(); 2296 2297 if (pstate_funcs.get_vid) 2298 pstate_funcs.get_vid(cpu); 2299 2300 intel_pstate_set_min_pstate(cpu); 2301 } 2302 2303 /* 2304 * Long hold time will keep high perf limits for long time, 2305 * which negatively impacts perf/watt for some workloads, 2306 * like specpower. 3ms is based on experiements on some 2307 * workoads. 2308 */ 2309 static int hwp_boost_hold_time_ns = 3 * NSEC_PER_MSEC; 2310 2311 static inline void intel_pstate_hwp_boost_up(struct cpudata *cpu) 2312 { 2313 u64 hwp_req = READ_ONCE(cpu->hwp_req_cached); 2314 u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached); 2315 u32 max_limit = (hwp_req & 0xff00) >> 8; 2316 u32 min_limit = (hwp_req & 0xff); 2317 u32 boost_level1; 2318 2319 /* 2320 * Cases to consider (User changes via sysfs or boot time): 2321 * If, P0 (Turbo max) = P1 (Guaranteed max) = min: 2322 * No boost, return. 2323 * If, P0 (Turbo max) > P1 (Guaranteed max) = min: 2324 * Should result in one level boost only for P0. 2325 * If, P0 (Turbo max) = P1 (Guaranteed max) > min: 2326 * Should result in two level boost: 2327 * (min + p1)/2 and P1. 2328 * If, P0 (Turbo max) > P1 (Guaranteed max) > min: 2329 * Should result in three level boost: 2330 * (min + p1)/2, P1 and P0. 2331 */ 2332 2333 /* If max and min are equal or already at max, nothing to boost */ 2334 if (max_limit == min_limit || cpu->hwp_boost_min >= max_limit) 2335 return; 2336 2337 if (!cpu->hwp_boost_min) 2338 cpu->hwp_boost_min = min_limit; 2339 2340 /* level at half way mark between min and guranteed */ 2341 boost_level1 = (HWP_GUARANTEED_PERF(hwp_cap) + min_limit) >> 1; 2342 2343 if (cpu->hwp_boost_min < boost_level1) 2344 cpu->hwp_boost_min = boost_level1; 2345 else if (cpu->hwp_boost_min < HWP_GUARANTEED_PERF(hwp_cap)) 2346 cpu->hwp_boost_min = HWP_GUARANTEED_PERF(hwp_cap); 2347 else if (cpu->hwp_boost_min == HWP_GUARANTEED_PERF(hwp_cap) && 2348 max_limit != HWP_GUARANTEED_PERF(hwp_cap)) 2349 cpu->hwp_boost_min = max_limit; 2350 else 2351 return; 2352 2353 hwp_req = (hwp_req & ~GENMASK_ULL(7, 0)) | cpu->hwp_boost_min; 2354 wrmsrl(MSR_HWP_REQUEST, hwp_req); 2355 cpu->last_update = cpu->sample.time; 2356 } 2357 2358 static inline void intel_pstate_hwp_boost_down(struct cpudata *cpu) 2359 { 2360 if (cpu->hwp_boost_min) { 2361 bool expired; 2362 2363 /* Check if we are idle for hold time to boost down */ 2364 expired = time_after64(cpu->sample.time, cpu->last_update + 2365 hwp_boost_hold_time_ns); 2366 if (expired) { 2367 wrmsrl(MSR_HWP_REQUEST, cpu->hwp_req_cached); 2368 cpu->hwp_boost_min = 0; 2369 } 2370 } 2371 cpu->last_update = cpu->sample.time; 2372 } 2373 2374 static inline void intel_pstate_update_util_hwp_local(struct cpudata *cpu, 2375 u64 time) 2376 { 2377 cpu->sample.time = time; 2378 2379 if (cpu->sched_flags & SCHED_CPUFREQ_IOWAIT) { 2380 bool do_io = false; 2381 2382 cpu->sched_flags = 0; 2383 /* 2384 * Set iowait_boost flag and update time. Since IO WAIT flag 2385 * is set all the time, we can't just conclude that there is 2386 * some IO bound activity is scheduled on this CPU with just 2387 * one occurrence. If we receive at least two in two 2388 * consecutive ticks, then we treat as boost candidate. 2389 */ 2390 if (time_before64(time, cpu->last_io_update + 2 * TICK_NSEC)) 2391 do_io = true; 2392 2393 cpu->last_io_update = time; 2394 2395 if (do_io) 2396 intel_pstate_hwp_boost_up(cpu); 2397 2398 } else { 2399 intel_pstate_hwp_boost_down(cpu); 2400 } 2401 } 2402 2403 static inline void intel_pstate_update_util_hwp(struct update_util_data *data, 2404 u64 time, unsigned int flags) 2405 { 2406 struct cpudata *cpu = container_of(data, struct cpudata, update_util); 2407 2408 cpu->sched_flags |= flags; 2409 2410 if (smp_processor_id() == cpu->cpu) 2411 intel_pstate_update_util_hwp_local(cpu, time); 2412 } 2413 2414 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu) 2415 { 2416 struct sample *sample = &cpu->sample; 2417 2418 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf); 2419 } 2420 2421 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time) 2422 { 2423 u64 aperf, mperf; 2424 unsigned long flags; 2425 u64 tsc; 2426 2427 local_irq_save(flags); 2428 rdmsrl(MSR_IA32_APERF, aperf); 2429 rdmsrl(MSR_IA32_MPERF, mperf); 2430 tsc = rdtsc(); 2431 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) { 2432 local_irq_restore(flags); 2433 return false; 2434 } 2435 local_irq_restore(flags); 2436 2437 cpu->last_sample_time = cpu->sample.time; 2438 cpu->sample.time = time; 2439 cpu->sample.aperf = aperf; 2440 cpu->sample.mperf = mperf; 2441 cpu->sample.tsc = tsc; 2442 cpu->sample.aperf -= cpu->prev_aperf; 2443 cpu->sample.mperf -= cpu->prev_mperf; 2444 cpu->sample.tsc -= cpu->prev_tsc; 2445 2446 cpu->prev_aperf = aperf; 2447 cpu->prev_mperf = mperf; 2448 cpu->prev_tsc = tsc; 2449 /* 2450 * First time this function is invoked in a given cycle, all of the 2451 * previous sample data fields are equal to zero or stale and they must 2452 * be populated with meaningful numbers for things to work, so assume 2453 * that sample.time will always be reset before setting the utilization 2454 * update hook and make the caller skip the sample then. 2455 */ 2456 if (cpu->last_sample_time) { 2457 intel_pstate_calc_avg_perf(cpu); 2458 return true; 2459 } 2460 return false; 2461 } 2462 2463 static inline int32_t get_avg_frequency(struct cpudata *cpu) 2464 { 2465 return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz); 2466 } 2467 2468 static inline int32_t get_avg_pstate(struct cpudata *cpu) 2469 { 2470 return mul_ext_fp(cpu->pstate.max_pstate_physical, 2471 cpu->sample.core_avg_perf); 2472 } 2473 2474 static inline int32_t get_target_pstate(struct cpudata *cpu) 2475 { 2476 struct sample *sample = &cpu->sample; 2477 int32_t busy_frac; 2478 int target, avg_pstate; 2479 2480 busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift, 2481 sample->tsc); 2482 2483 if (busy_frac < cpu->iowait_boost) 2484 busy_frac = cpu->iowait_boost; 2485 2486 sample->busy_scaled = busy_frac * 100; 2487 2488 target = READ_ONCE(global.no_turbo) ? 2489 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate; 2490 target += target >> 2; 2491 target = mul_fp(target, busy_frac); 2492 if (target < cpu->pstate.min_pstate) 2493 target = cpu->pstate.min_pstate; 2494 2495 /* 2496 * If the average P-state during the previous cycle was higher than the 2497 * current target, add 50% of the difference to the target to reduce 2498 * possible performance oscillations and offset possible performance 2499 * loss related to moving the workload from one CPU to another within 2500 * a package/module. 2501 */ 2502 avg_pstate = get_avg_pstate(cpu); 2503 if (avg_pstate > target) 2504 target += (avg_pstate - target) >> 1; 2505 2506 return target; 2507 } 2508 2509 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate) 2510 { 2511 int min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio); 2512 int max_pstate = max(min_pstate, cpu->max_perf_ratio); 2513 2514 return clamp_t(int, pstate, min_pstate, max_pstate); 2515 } 2516 2517 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate) 2518 { 2519 if (pstate == cpu->pstate.current_pstate) 2520 return; 2521 2522 cpu->pstate.current_pstate = pstate; 2523 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate)); 2524 } 2525 2526 static void intel_pstate_adjust_pstate(struct cpudata *cpu) 2527 { 2528 int from = cpu->pstate.current_pstate; 2529 struct sample *sample; 2530 int target_pstate; 2531 2532 target_pstate = get_target_pstate(cpu); 2533 target_pstate = intel_pstate_prepare_request(cpu, target_pstate); 2534 trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu); 2535 intel_pstate_update_pstate(cpu, target_pstate); 2536 2537 sample = &cpu->sample; 2538 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf), 2539 fp_toint(sample->busy_scaled), 2540 from, 2541 cpu->pstate.current_pstate, 2542 sample->mperf, 2543 sample->aperf, 2544 sample->tsc, 2545 get_avg_frequency(cpu), 2546 fp_toint(cpu->iowait_boost * 100)); 2547 } 2548 2549 static void intel_pstate_update_util(struct update_util_data *data, u64 time, 2550 unsigned int flags) 2551 { 2552 struct cpudata *cpu = container_of(data, struct cpudata, update_util); 2553 u64 delta_ns; 2554 2555 /* Don't allow remote callbacks */ 2556 if (smp_processor_id() != cpu->cpu) 2557 return; 2558 2559 delta_ns = time - cpu->last_update; 2560 if (flags & SCHED_CPUFREQ_IOWAIT) { 2561 /* Start over if the CPU may have been idle. */ 2562 if (delta_ns > TICK_NSEC) { 2563 cpu->iowait_boost = ONE_EIGHTH_FP; 2564 } else if (cpu->iowait_boost >= ONE_EIGHTH_FP) { 2565 cpu->iowait_boost <<= 1; 2566 if (cpu->iowait_boost > int_tofp(1)) 2567 cpu->iowait_boost = int_tofp(1); 2568 } else { 2569 cpu->iowait_boost = ONE_EIGHTH_FP; 2570 } 2571 } else if (cpu->iowait_boost) { 2572 /* Clear iowait_boost if the CPU may have been idle. */ 2573 if (delta_ns > TICK_NSEC) 2574 cpu->iowait_boost = 0; 2575 else 2576 cpu->iowait_boost >>= 1; 2577 } 2578 cpu->last_update = time; 2579 delta_ns = time - cpu->sample.time; 2580 if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL) 2581 return; 2582 2583 if (intel_pstate_sample(cpu, time)) 2584 intel_pstate_adjust_pstate(cpu); 2585 } 2586 2587 static struct pstate_funcs core_funcs = { 2588 .get_max = core_get_max_pstate, 2589 .get_max_physical = core_get_max_pstate_physical, 2590 .get_min = core_get_min_pstate, 2591 .get_turbo = core_get_turbo_pstate, 2592 .get_scaling = core_get_scaling, 2593 .get_val = core_get_val, 2594 }; 2595 2596 static const struct pstate_funcs silvermont_funcs = { 2597 .get_max = atom_get_max_pstate, 2598 .get_max_physical = atom_get_max_pstate, 2599 .get_min = atom_get_min_pstate, 2600 .get_turbo = atom_get_turbo_pstate, 2601 .get_val = atom_get_val, 2602 .get_scaling = silvermont_get_scaling, 2603 .get_vid = atom_get_vid, 2604 }; 2605 2606 static const struct pstate_funcs airmont_funcs = { 2607 .get_max = atom_get_max_pstate, 2608 .get_max_physical = atom_get_max_pstate, 2609 .get_min = atom_get_min_pstate, 2610 .get_turbo = atom_get_turbo_pstate, 2611 .get_val = atom_get_val, 2612 .get_scaling = airmont_get_scaling, 2613 .get_vid = atom_get_vid, 2614 }; 2615 2616 static const struct pstate_funcs knl_funcs = { 2617 .get_max = core_get_max_pstate, 2618 .get_max_physical = core_get_max_pstate_physical, 2619 .get_min = core_get_min_pstate, 2620 .get_turbo = knl_get_turbo_pstate, 2621 .get_aperf_mperf_shift = knl_get_aperf_mperf_shift, 2622 .get_scaling = core_get_scaling, 2623 .get_val = core_get_val, 2624 }; 2625 2626 #define X86_MATCH(vfm, policy) \ 2627 X86_MATCH_VFM_FEATURE(vfm, X86_FEATURE_APERFMPERF, &policy) 2628 2629 static const struct x86_cpu_id intel_pstate_cpu_ids[] = { 2630 X86_MATCH(INTEL_SANDYBRIDGE, core_funcs), 2631 X86_MATCH(INTEL_SANDYBRIDGE_X, core_funcs), 2632 X86_MATCH(INTEL_ATOM_SILVERMONT, silvermont_funcs), 2633 X86_MATCH(INTEL_IVYBRIDGE, core_funcs), 2634 X86_MATCH(INTEL_HASWELL, core_funcs), 2635 X86_MATCH(INTEL_BROADWELL, core_funcs), 2636 X86_MATCH(INTEL_IVYBRIDGE_X, core_funcs), 2637 X86_MATCH(INTEL_HASWELL_X, core_funcs), 2638 X86_MATCH(INTEL_HASWELL_L, core_funcs), 2639 X86_MATCH(INTEL_HASWELL_G, core_funcs), 2640 X86_MATCH(INTEL_BROADWELL_G, core_funcs), 2641 X86_MATCH(INTEL_ATOM_AIRMONT, airmont_funcs), 2642 X86_MATCH(INTEL_SKYLAKE_L, core_funcs), 2643 X86_MATCH(INTEL_BROADWELL_X, core_funcs), 2644 X86_MATCH(INTEL_SKYLAKE, core_funcs), 2645 X86_MATCH(INTEL_BROADWELL_D, core_funcs), 2646 X86_MATCH(INTEL_XEON_PHI_KNL, knl_funcs), 2647 X86_MATCH(INTEL_XEON_PHI_KNM, knl_funcs), 2648 X86_MATCH(INTEL_ATOM_GOLDMONT, core_funcs), 2649 X86_MATCH(INTEL_ATOM_GOLDMONT_PLUS, core_funcs), 2650 X86_MATCH(INTEL_SKYLAKE_X, core_funcs), 2651 X86_MATCH(INTEL_COMETLAKE, core_funcs), 2652 X86_MATCH(INTEL_ICELAKE_X, core_funcs), 2653 X86_MATCH(INTEL_TIGERLAKE, core_funcs), 2654 X86_MATCH(INTEL_SAPPHIRERAPIDS_X, core_funcs), 2655 X86_MATCH(INTEL_EMERALDRAPIDS_X, core_funcs), 2656 {} 2657 }; 2658 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids); 2659 2660 #ifdef CONFIG_ACPI 2661 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = { 2662 X86_MATCH(INTEL_BROADWELL_D, core_funcs), 2663 X86_MATCH(INTEL_BROADWELL_X, core_funcs), 2664 X86_MATCH(INTEL_SKYLAKE_X, core_funcs), 2665 X86_MATCH(INTEL_ICELAKE_X, core_funcs), 2666 X86_MATCH(INTEL_SAPPHIRERAPIDS_X, core_funcs), 2667 X86_MATCH(INTEL_EMERALDRAPIDS_X, core_funcs), 2668 X86_MATCH(INTEL_GRANITERAPIDS_D, core_funcs), 2669 X86_MATCH(INTEL_GRANITERAPIDS_X, core_funcs), 2670 X86_MATCH(INTEL_ATOM_CRESTMONT, core_funcs), 2671 X86_MATCH(INTEL_ATOM_CRESTMONT_X, core_funcs), 2672 {} 2673 }; 2674 #endif 2675 2676 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = { 2677 X86_MATCH(INTEL_KABYLAKE, core_funcs), 2678 {} 2679 }; 2680 2681 static int intel_pstate_init_cpu(unsigned int cpunum) 2682 { 2683 struct cpudata *cpu; 2684 2685 cpu = all_cpu_data[cpunum]; 2686 2687 if (!cpu) { 2688 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL); 2689 if (!cpu) 2690 return -ENOMEM; 2691 2692 WRITE_ONCE(all_cpu_data[cpunum], cpu); 2693 2694 cpu->cpu = cpunum; 2695 2696 cpu->epp_default = -EINVAL; 2697 2698 if (hwp_active) { 2699 intel_pstate_hwp_enable(cpu); 2700 2701 if (intel_pstate_acpi_pm_profile_server()) 2702 hwp_boost = true; 2703 } 2704 } else if (hwp_active) { 2705 /* 2706 * Re-enable HWP in case this happens after a resume from ACPI 2707 * S3 if the CPU was offline during the whole system/resume 2708 * cycle. 2709 */ 2710 intel_pstate_hwp_reenable(cpu); 2711 } 2712 2713 cpu->epp_powersave = -EINVAL; 2714 cpu->epp_policy = CPUFREQ_POLICY_UNKNOWN; 2715 2716 intel_pstate_get_cpu_pstates(cpu); 2717 2718 pr_debug("controlling: cpu %d\n", cpunum); 2719 2720 return 0; 2721 } 2722 2723 static void intel_pstate_set_update_util_hook(unsigned int cpu_num) 2724 { 2725 struct cpudata *cpu = all_cpu_data[cpu_num]; 2726 2727 if (hwp_active && !hwp_boost) 2728 return; 2729 2730 if (cpu->update_util_set) 2731 return; 2732 2733 /* Prevent intel_pstate_update_util() from using stale data. */ 2734 cpu->sample.time = 0; 2735 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util, 2736 (hwp_active ? 2737 intel_pstate_update_util_hwp : 2738 intel_pstate_update_util)); 2739 cpu->update_util_set = true; 2740 } 2741 2742 static void intel_pstate_clear_update_util_hook(unsigned int cpu) 2743 { 2744 struct cpudata *cpu_data = all_cpu_data[cpu]; 2745 2746 if (!cpu_data->update_util_set) 2747 return; 2748 2749 cpufreq_remove_update_util_hook(cpu); 2750 cpu_data->update_util_set = false; 2751 synchronize_rcu(); 2752 } 2753 2754 static int intel_pstate_get_max_freq(struct cpudata *cpu) 2755 { 2756 return READ_ONCE(global.no_turbo) ? 2757 cpu->pstate.max_freq : cpu->pstate.turbo_freq; 2758 } 2759 2760 static void intel_pstate_update_perf_limits(struct cpudata *cpu, 2761 unsigned int policy_min, 2762 unsigned int policy_max) 2763 { 2764 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling; 2765 int32_t max_policy_perf, min_policy_perf; 2766 2767 max_policy_perf = policy_max / perf_ctl_scaling; 2768 if (policy_max == policy_min) { 2769 min_policy_perf = max_policy_perf; 2770 } else { 2771 min_policy_perf = policy_min / perf_ctl_scaling; 2772 min_policy_perf = clamp_t(int32_t, min_policy_perf, 2773 0, max_policy_perf); 2774 } 2775 2776 /* 2777 * HWP needs some special consideration, because HWP_REQUEST uses 2778 * abstract values to represent performance rather than pure ratios. 2779 */ 2780 if (hwp_active && cpu->pstate.scaling != perf_ctl_scaling) { 2781 int freq; 2782 2783 freq = max_policy_perf * perf_ctl_scaling; 2784 max_policy_perf = intel_pstate_freq_to_hwp(cpu, freq); 2785 freq = min_policy_perf * perf_ctl_scaling; 2786 min_policy_perf = intel_pstate_freq_to_hwp(cpu, freq); 2787 } 2788 2789 pr_debug("cpu:%d min_policy_perf:%d max_policy_perf:%d\n", 2790 cpu->cpu, min_policy_perf, max_policy_perf); 2791 2792 /* Normalize user input to [min_perf, max_perf] */ 2793 if (per_cpu_limits) { 2794 cpu->min_perf_ratio = min_policy_perf; 2795 cpu->max_perf_ratio = max_policy_perf; 2796 } else { 2797 int turbo_max = cpu->pstate.turbo_pstate; 2798 int32_t global_min, global_max; 2799 2800 /* Global limits are in percent of the maximum turbo P-state. */ 2801 global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100); 2802 global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100); 2803 global_min = clamp_t(int32_t, global_min, 0, global_max); 2804 2805 pr_debug("cpu:%d global_min:%d global_max:%d\n", cpu->cpu, 2806 global_min, global_max); 2807 2808 cpu->min_perf_ratio = max(min_policy_perf, global_min); 2809 cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf); 2810 cpu->max_perf_ratio = min(max_policy_perf, global_max); 2811 cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio); 2812 2813 /* Make sure min_perf <= max_perf */ 2814 cpu->min_perf_ratio = min(cpu->min_perf_ratio, 2815 cpu->max_perf_ratio); 2816 2817 } 2818 pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", cpu->cpu, 2819 cpu->max_perf_ratio, 2820 cpu->min_perf_ratio); 2821 } 2822 2823 static int intel_pstate_set_policy(struct cpufreq_policy *policy) 2824 { 2825 struct cpudata *cpu; 2826 2827 if (!policy->cpuinfo.max_freq) 2828 return -ENODEV; 2829 2830 pr_debug("set_policy cpuinfo.max %u policy->max %u\n", 2831 policy->cpuinfo.max_freq, policy->max); 2832 2833 cpu = all_cpu_data[policy->cpu]; 2834 cpu->policy = policy->policy; 2835 2836 mutex_lock(&intel_pstate_limits_lock); 2837 2838 intel_pstate_update_perf_limits(cpu, policy->min, policy->max); 2839 2840 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) { 2841 int pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio); 2842 2843 /* 2844 * NOHZ_FULL CPUs need this as the governor callback may not 2845 * be invoked on them. 2846 */ 2847 intel_pstate_clear_update_util_hook(policy->cpu); 2848 intel_pstate_set_pstate(cpu, pstate); 2849 } else { 2850 intel_pstate_set_update_util_hook(policy->cpu); 2851 } 2852 2853 if (hwp_active) { 2854 /* 2855 * When hwp_boost was active before and dynamically it 2856 * was turned off, in that case we need to clear the 2857 * update util hook. 2858 */ 2859 if (!hwp_boost) 2860 intel_pstate_clear_update_util_hook(policy->cpu); 2861 intel_pstate_hwp_set(policy->cpu); 2862 } 2863 /* 2864 * policy->cur is never updated with the intel_pstate driver, but it 2865 * is used as a stale frequency value. So, keep it within limits. 2866 */ 2867 policy->cur = policy->min; 2868 2869 mutex_unlock(&intel_pstate_limits_lock); 2870 2871 return 0; 2872 } 2873 2874 static void intel_pstate_adjust_policy_max(struct cpudata *cpu, 2875 struct cpufreq_policy_data *policy) 2876 { 2877 if (!hwp_active && 2878 cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate && 2879 policy->max < policy->cpuinfo.max_freq && 2880 policy->max > cpu->pstate.max_freq) { 2881 pr_debug("policy->max > max non turbo frequency\n"); 2882 policy->max = policy->cpuinfo.max_freq; 2883 } 2884 } 2885 2886 static void intel_pstate_verify_cpu_policy(struct cpudata *cpu, 2887 struct cpufreq_policy_data *policy) 2888 { 2889 int max_freq; 2890 2891 if (hwp_active) { 2892 intel_pstate_get_hwp_cap(cpu); 2893 max_freq = READ_ONCE(global.no_turbo) ? 2894 cpu->pstate.max_freq : cpu->pstate.turbo_freq; 2895 } else { 2896 max_freq = intel_pstate_get_max_freq(cpu); 2897 } 2898 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, max_freq); 2899 2900 intel_pstate_adjust_policy_max(cpu, policy); 2901 } 2902 2903 static int intel_pstate_verify_policy(struct cpufreq_policy_data *policy) 2904 { 2905 intel_pstate_verify_cpu_policy(all_cpu_data[policy->cpu], policy); 2906 2907 return 0; 2908 } 2909 2910 static int intel_cpufreq_cpu_offline(struct cpufreq_policy *policy) 2911 { 2912 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2913 2914 pr_debug("CPU %d going offline\n", cpu->cpu); 2915 2916 if (cpu->suspended) 2917 return 0; 2918 2919 /* 2920 * If the CPU is an SMT thread and it goes offline with the performance 2921 * settings different from the minimum, it will prevent its sibling 2922 * from getting to lower performance levels, so force the minimum 2923 * performance on CPU offline to prevent that from happening. 2924 */ 2925 if (hwp_active) 2926 intel_pstate_hwp_offline(cpu); 2927 else 2928 intel_pstate_set_min_pstate(cpu); 2929 2930 intel_pstate_exit_perf_limits(policy); 2931 2932 return 0; 2933 } 2934 2935 static int intel_pstate_cpu_online(struct cpufreq_policy *policy) 2936 { 2937 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2938 2939 pr_debug("CPU %d going online\n", cpu->cpu); 2940 2941 intel_pstate_init_acpi_perf_limits(policy); 2942 2943 if (hwp_active) { 2944 /* 2945 * Re-enable HWP and clear the "suspended" flag to let "resume" 2946 * know that it need not do that. 2947 */ 2948 intel_pstate_hwp_reenable(cpu); 2949 cpu->suspended = false; 2950 2951 hybrid_update_capacity(cpu); 2952 } 2953 2954 return 0; 2955 } 2956 2957 static int intel_pstate_cpu_offline(struct cpufreq_policy *policy) 2958 { 2959 intel_pstate_clear_update_util_hook(policy->cpu); 2960 2961 return intel_cpufreq_cpu_offline(policy); 2962 } 2963 2964 static void intel_pstate_cpu_exit(struct cpufreq_policy *policy) 2965 { 2966 pr_debug("CPU %d exiting\n", policy->cpu); 2967 2968 policy->fast_switch_possible = false; 2969 } 2970 2971 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy) 2972 { 2973 struct cpudata *cpu; 2974 int rc; 2975 2976 rc = intel_pstate_init_cpu(policy->cpu); 2977 if (rc) 2978 return rc; 2979 2980 cpu = all_cpu_data[policy->cpu]; 2981 2982 cpu->max_perf_ratio = 0xFF; 2983 cpu->min_perf_ratio = 0; 2984 2985 /* cpuinfo and default policy values */ 2986 policy->cpuinfo.min_freq = cpu->pstate.min_freq; 2987 policy->cpuinfo.max_freq = READ_ONCE(global.no_turbo) ? 2988 cpu->pstate.max_freq : cpu->pstate.turbo_freq; 2989 2990 policy->min = policy->cpuinfo.min_freq; 2991 policy->max = policy->cpuinfo.max_freq; 2992 2993 intel_pstate_init_acpi_perf_limits(policy); 2994 2995 policy->fast_switch_possible = true; 2996 2997 return 0; 2998 } 2999 3000 static int intel_pstate_cpu_init(struct cpufreq_policy *policy) 3001 { 3002 int ret = __intel_pstate_cpu_init(policy); 3003 3004 if (ret) 3005 return ret; 3006 3007 /* 3008 * Set the policy to powersave to provide a valid fallback value in case 3009 * the default cpufreq governor is neither powersave nor performance. 3010 */ 3011 policy->policy = CPUFREQ_POLICY_POWERSAVE; 3012 3013 if (hwp_active) { 3014 struct cpudata *cpu = all_cpu_data[policy->cpu]; 3015 3016 cpu->epp_cached = intel_pstate_get_epp(cpu, 0); 3017 } 3018 3019 return 0; 3020 } 3021 3022 static struct cpufreq_driver intel_pstate = { 3023 .flags = CPUFREQ_CONST_LOOPS, 3024 .verify = intel_pstate_verify_policy, 3025 .setpolicy = intel_pstate_set_policy, 3026 .suspend = intel_pstate_suspend, 3027 .resume = intel_pstate_resume, 3028 .init = intel_pstate_cpu_init, 3029 .exit = intel_pstate_cpu_exit, 3030 .offline = intel_pstate_cpu_offline, 3031 .online = intel_pstate_cpu_online, 3032 .update_limits = intel_pstate_update_limits, 3033 .name = "intel_pstate", 3034 }; 3035 3036 static int intel_cpufreq_verify_policy(struct cpufreq_policy_data *policy) 3037 { 3038 struct cpudata *cpu = all_cpu_data[policy->cpu]; 3039 3040 intel_pstate_verify_cpu_policy(cpu, policy); 3041 intel_pstate_update_perf_limits(cpu, policy->min, policy->max); 3042 3043 return 0; 3044 } 3045 3046 /* Use of trace in passive mode: 3047 * 3048 * In passive mode the trace core_busy field (also known as the 3049 * performance field, and lablelled as such on the graphs; also known as 3050 * core_avg_perf) is not needed and so is re-assigned to indicate if the 3051 * driver call was via the normal or fast switch path. Various graphs 3052 * output from the intel_pstate_tracer.py utility that include core_busy 3053 * (or performance or core_avg_perf) have a fixed y-axis from 0 to 100%, 3054 * so we use 10 to indicate the normal path through the driver, and 3055 * 90 to indicate the fast switch path through the driver. 3056 * The scaled_busy field is not used, and is set to 0. 3057 */ 3058 3059 #define INTEL_PSTATE_TRACE_TARGET 10 3060 #define INTEL_PSTATE_TRACE_FAST_SWITCH 90 3061 3062 static void intel_cpufreq_trace(struct cpudata *cpu, unsigned int trace_type, int old_pstate) 3063 { 3064 struct sample *sample; 3065 3066 if (!trace_pstate_sample_enabled()) 3067 return; 3068 3069 if (!intel_pstate_sample(cpu, ktime_get())) 3070 return; 3071 3072 sample = &cpu->sample; 3073 trace_pstate_sample(trace_type, 3074 0, 3075 old_pstate, 3076 cpu->pstate.current_pstate, 3077 sample->mperf, 3078 sample->aperf, 3079 sample->tsc, 3080 get_avg_frequency(cpu), 3081 fp_toint(cpu->iowait_boost * 100)); 3082 } 3083 3084 static void intel_cpufreq_hwp_update(struct cpudata *cpu, u32 min, u32 max, 3085 u32 desired, bool fast_switch) 3086 { 3087 u64 prev = READ_ONCE(cpu->hwp_req_cached), value = prev; 3088 3089 value &= ~HWP_MIN_PERF(~0L); 3090 value |= HWP_MIN_PERF(min); 3091 3092 value &= ~HWP_MAX_PERF(~0L); 3093 value |= HWP_MAX_PERF(max); 3094 3095 value &= ~HWP_DESIRED_PERF(~0L); 3096 value |= HWP_DESIRED_PERF(desired); 3097 3098 if (value == prev) 3099 return; 3100 3101 WRITE_ONCE(cpu->hwp_req_cached, value); 3102 if (fast_switch) 3103 wrmsrl(MSR_HWP_REQUEST, value); 3104 else 3105 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 3106 } 3107 3108 static void intel_cpufreq_perf_ctl_update(struct cpudata *cpu, 3109 u32 target_pstate, bool fast_switch) 3110 { 3111 if (fast_switch) 3112 wrmsrl(MSR_IA32_PERF_CTL, 3113 pstate_funcs.get_val(cpu, target_pstate)); 3114 else 3115 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL, 3116 pstate_funcs.get_val(cpu, target_pstate)); 3117 } 3118 3119 static int intel_cpufreq_update_pstate(struct cpufreq_policy *policy, 3120 int target_pstate, bool fast_switch) 3121 { 3122 struct cpudata *cpu = all_cpu_data[policy->cpu]; 3123 int old_pstate = cpu->pstate.current_pstate; 3124 3125 target_pstate = intel_pstate_prepare_request(cpu, target_pstate); 3126 if (hwp_active) { 3127 int max_pstate = policy->strict_target ? 3128 target_pstate : cpu->max_perf_ratio; 3129 3130 intel_cpufreq_hwp_update(cpu, target_pstate, max_pstate, 0, 3131 fast_switch); 3132 } else if (target_pstate != old_pstate) { 3133 intel_cpufreq_perf_ctl_update(cpu, target_pstate, fast_switch); 3134 } 3135 3136 cpu->pstate.current_pstate = target_pstate; 3137 3138 intel_cpufreq_trace(cpu, fast_switch ? INTEL_PSTATE_TRACE_FAST_SWITCH : 3139 INTEL_PSTATE_TRACE_TARGET, old_pstate); 3140 3141 return target_pstate; 3142 } 3143 3144 static int intel_cpufreq_target(struct cpufreq_policy *policy, 3145 unsigned int target_freq, 3146 unsigned int relation) 3147 { 3148 struct cpudata *cpu = all_cpu_data[policy->cpu]; 3149 struct cpufreq_freqs freqs; 3150 int target_pstate; 3151 3152 freqs.old = policy->cur; 3153 freqs.new = target_freq; 3154 3155 cpufreq_freq_transition_begin(policy, &freqs); 3156 3157 target_pstate = intel_pstate_freq_to_hwp_rel(cpu, freqs.new, relation); 3158 target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, false); 3159 3160 freqs.new = target_pstate * cpu->pstate.scaling; 3161 3162 cpufreq_freq_transition_end(policy, &freqs, false); 3163 3164 return 0; 3165 } 3166 3167 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy, 3168 unsigned int target_freq) 3169 { 3170 struct cpudata *cpu = all_cpu_data[policy->cpu]; 3171 int target_pstate; 3172 3173 target_pstate = intel_pstate_freq_to_hwp(cpu, target_freq); 3174 3175 target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, true); 3176 3177 return target_pstate * cpu->pstate.scaling; 3178 } 3179 3180 static void intel_cpufreq_adjust_perf(unsigned int cpunum, 3181 unsigned long min_perf, 3182 unsigned long target_perf, 3183 unsigned long capacity) 3184 { 3185 struct cpudata *cpu = all_cpu_data[cpunum]; 3186 u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached); 3187 int old_pstate = cpu->pstate.current_pstate; 3188 int cap_pstate, min_pstate, max_pstate, target_pstate; 3189 3190 cap_pstate = READ_ONCE(global.no_turbo) ? 3191 HWP_GUARANTEED_PERF(hwp_cap) : 3192 HWP_HIGHEST_PERF(hwp_cap); 3193 3194 /* Optimization: Avoid unnecessary divisions. */ 3195 3196 target_pstate = cap_pstate; 3197 if (target_perf < capacity) 3198 target_pstate = DIV_ROUND_UP(cap_pstate * target_perf, capacity); 3199 3200 min_pstate = cap_pstate; 3201 if (min_perf < capacity) 3202 min_pstate = DIV_ROUND_UP(cap_pstate * min_perf, capacity); 3203 3204 if (min_pstate < cpu->pstate.min_pstate) 3205 min_pstate = cpu->pstate.min_pstate; 3206 3207 if (min_pstate < cpu->min_perf_ratio) 3208 min_pstate = cpu->min_perf_ratio; 3209 3210 if (min_pstate > cpu->max_perf_ratio) 3211 min_pstate = cpu->max_perf_ratio; 3212 3213 max_pstate = min(cap_pstate, cpu->max_perf_ratio); 3214 if (max_pstate < min_pstate) 3215 max_pstate = min_pstate; 3216 3217 target_pstate = clamp_t(int, target_pstate, min_pstate, max_pstate); 3218 3219 intel_cpufreq_hwp_update(cpu, min_pstate, max_pstate, target_pstate, true); 3220 3221 cpu->pstate.current_pstate = target_pstate; 3222 intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_FAST_SWITCH, old_pstate); 3223 } 3224 3225 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy) 3226 { 3227 struct freq_qos_request *req; 3228 struct cpudata *cpu; 3229 struct device *dev; 3230 int ret, freq; 3231 3232 dev = get_cpu_device(policy->cpu); 3233 if (!dev) 3234 return -ENODEV; 3235 3236 ret = __intel_pstate_cpu_init(policy); 3237 if (ret) 3238 return ret; 3239 3240 policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY; 3241 /* This reflects the intel_pstate_get_cpu_pstates() setting. */ 3242 policy->cur = policy->cpuinfo.min_freq; 3243 3244 req = kcalloc(2, sizeof(*req), GFP_KERNEL); 3245 if (!req) { 3246 ret = -ENOMEM; 3247 goto pstate_exit; 3248 } 3249 3250 cpu = all_cpu_data[policy->cpu]; 3251 3252 if (hwp_active) { 3253 u64 value; 3254 3255 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY_HWP; 3256 3257 intel_pstate_get_hwp_cap(cpu); 3258 3259 rdmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, &value); 3260 WRITE_ONCE(cpu->hwp_req_cached, value); 3261 3262 cpu->epp_cached = intel_pstate_get_epp(cpu, value); 3263 } else { 3264 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY; 3265 } 3266 3267 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.min_perf_pct, 100); 3268 3269 ret = freq_qos_add_request(&policy->constraints, req, FREQ_QOS_MIN, 3270 freq); 3271 if (ret < 0) { 3272 dev_err(dev, "Failed to add min-freq constraint (%d)\n", ret); 3273 goto free_req; 3274 } 3275 3276 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.max_perf_pct, 100); 3277 3278 ret = freq_qos_add_request(&policy->constraints, req + 1, FREQ_QOS_MAX, 3279 freq); 3280 if (ret < 0) { 3281 dev_err(dev, "Failed to add max-freq constraint (%d)\n", ret); 3282 goto remove_min_req; 3283 } 3284 3285 policy->driver_data = req; 3286 3287 return 0; 3288 3289 remove_min_req: 3290 freq_qos_remove_request(req); 3291 free_req: 3292 kfree(req); 3293 pstate_exit: 3294 intel_pstate_exit_perf_limits(policy); 3295 3296 return ret; 3297 } 3298 3299 static void intel_cpufreq_cpu_exit(struct cpufreq_policy *policy) 3300 { 3301 struct freq_qos_request *req; 3302 3303 req = policy->driver_data; 3304 3305 freq_qos_remove_request(req + 1); 3306 freq_qos_remove_request(req); 3307 kfree(req); 3308 3309 intel_pstate_cpu_exit(policy); 3310 } 3311 3312 static int intel_cpufreq_suspend(struct cpufreq_policy *policy) 3313 { 3314 intel_pstate_suspend(policy); 3315 3316 if (hwp_active) { 3317 struct cpudata *cpu = all_cpu_data[policy->cpu]; 3318 u64 value = READ_ONCE(cpu->hwp_req_cached); 3319 3320 /* 3321 * Clear the desired perf field in MSR_HWP_REQUEST in case 3322 * intel_cpufreq_adjust_perf() is in use and the last value 3323 * written by it may not be suitable. 3324 */ 3325 value &= ~HWP_DESIRED_PERF(~0L); 3326 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 3327 WRITE_ONCE(cpu->hwp_req_cached, value); 3328 } 3329 3330 return 0; 3331 } 3332 3333 static struct cpufreq_driver intel_cpufreq = { 3334 .flags = CPUFREQ_CONST_LOOPS, 3335 .verify = intel_cpufreq_verify_policy, 3336 .target = intel_cpufreq_target, 3337 .fast_switch = intel_cpufreq_fast_switch, 3338 .init = intel_cpufreq_cpu_init, 3339 .exit = intel_cpufreq_cpu_exit, 3340 .offline = intel_cpufreq_cpu_offline, 3341 .online = intel_pstate_cpu_online, 3342 .suspend = intel_cpufreq_suspend, 3343 .resume = intel_pstate_resume, 3344 .update_limits = intel_pstate_update_limits, 3345 .name = "intel_cpufreq", 3346 }; 3347 3348 static struct cpufreq_driver *default_driver; 3349 3350 static void intel_pstate_driver_cleanup(void) 3351 { 3352 unsigned int cpu; 3353 3354 cpus_read_lock(); 3355 for_each_online_cpu(cpu) { 3356 if (all_cpu_data[cpu]) { 3357 if (intel_pstate_driver == &intel_pstate) 3358 intel_pstate_clear_update_util_hook(cpu); 3359 3360 kfree(all_cpu_data[cpu]); 3361 WRITE_ONCE(all_cpu_data[cpu], NULL); 3362 } 3363 } 3364 cpus_read_unlock(); 3365 3366 intel_pstate_driver = NULL; 3367 } 3368 3369 static int intel_pstate_register_driver(struct cpufreq_driver *driver) 3370 { 3371 bool refresh_cpu_cap_scaling; 3372 int ret; 3373 3374 if (driver == &intel_pstate) 3375 intel_pstate_sysfs_expose_hwp_dynamic_boost(); 3376 3377 memset(&global, 0, sizeof(global)); 3378 global.max_perf_pct = 100; 3379 global.turbo_disabled = turbo_is_disabled(); 3380 global.no_turbo = global.turbo_disabled; 3381 3382 arch_set_max_freq_ratio(global.turbo_disabled); 3383 3384 refresh_cpu_cap_scaling = hybrid_clear_max_perf_cpu(); 3385 3386 intel_pstate_driver = driver; 3387 ret = cpufreq_register_driver(intel_pstate_driver); 3388 if (ret) { 3389 intel_pstate_driver_cleanup(); 3390 return ret; 3391 } 3392 3393 global.min_perf_pct = min_perf_pct_min(); 3394 3395 hybrid_init_cpu_capacity_scaling(refresh_cpu_cap_scaling); 3396 3397 return 0; 3398 } 3399 3400 static ssize_t intel_pstate_show_status(char *buf) 3401 { 3402 if (!intel_pstate_driver) 3403 return sprintf(buf, "off\n"); 3404 3405 return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ? 3406 "active" : "passive"); 3407 } 3408 3409 static int intel_pstate_update_status(const char *buf, size_t size) 3410 { 3411 if (size == 3 && !strncmp(buf, "off", size)) { 3412 if (!intel_pstate_driver) 3413 return -EINVAL; 3414 3415 if (hwp_active) 3416 return -EBUSY; 3417 3418 cpufreq_unregister_driver(intel_pstate_driver); 3419 intel_pstate_driver_cleanup(); 3420 return 0; 3421 } 3422 3423 if (size == 6 && !strncmp(buf, "active", size)) { 3424 if (intel_pstate_driver) { 3425 if (intel_pstate_driver == &intel_pstate) 3426 return 0; 3427 3428 cpufreq_unregister_driver(intel_pstate_driver); 3429 } 3430 3431 return intel_pstate_register_driver(&intel_pstate); 3432 } 3433 3434 if (size == 7 && !strncmp(buf, "passive", size)) { 3435 if (intel_pstate_driver) { 3436 if (intel_pstate_driver == &intel_cpufreq) 3437 return 0; 3438 3439 cpufreq_unregister_driver(intel_pstate_driver); 3440 intel_pstate_sysfs_hide_hwp_dynamic_boost(); 3441 } 3442 3443 return intel_pstate_register_driver(&intel_cpufreq); 3444 } 3445 3446 return -EINVAL; 3447 } 3448 3449 static int no_load __initdata; 3450 static int no_hwp __initdata; 3451 static int hwp_only __initdata; 3452 static unsigned int force_load __initdata; 3453 3454 static int __init intel_pstate_msrs_not_valid(void) 3455 { 3456 if (!pstate_funcs.get_max(0) || 3457 !pstate_funcs.get_min(0) || 3458 !pstate_funcs.get_turbo(0)) 3459 return -ENODEV; 3460 3461 return 0; 3462 } 3463 3464 static void __init copy_cpu_funcs(struct pstate_funcs *funcs) 3465 { 3466 pstate_funcs.get_max = funcs->get_max; 3467 pstate_funcs.get_max_physical = funcs->get_max_physical; 3468 pstate_funcs.get_min = funcs->get_min; 3469 pstate_funcs.get_turbo = funcs->get_turbo; 3470 pstate_funcs.get_scaling = funcs->get_scaling; 3471 pstate_funcs.get_val = funcs->get_val; 3472 pstate_funcs.get_vid = funcs->get_vid; 3473 pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift; 3474 } 3475 3476 #ifdef CONFIG_ACPI 3477 3478 static bool __init intel_pstate_no_acpi_pss(void) 3479 { 3480 int i; 3481 3482 for_each_possible_cpu(i) { 3483 acpi_status status; 3484 union acpi_object *pss; 3485 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; 3486 struct acpi_processor *pr = per_cpu(processors, i); 3487 3488 if (!pr) 3489 continue; 3490 3491 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer); 3492 if (ACPI_FAILURE(status)) 3493 continue; 3494 3495 pss = buffer.pointer; 3496 if (pss && pss->type == ACPI_TYPE_PACKAGE) { 3497 kfree(pss); 3498 return false; 3499 } 3500 3501 kfree(pss); 3502 } 3503 3504 pr_debug("ACPI _PSS not found\n"); 3505 return true; 3506 } 3507 3508 static bool __init intel_pstate_no_acpi_pcch(void) 3509 { 3510 acpi_status status; 3511 acpi_handle handle; 3512 3513 status = acpi_get_handle(NULL, "\\_SB", &handle); 3514 if (ACPI_FAILURE(status)) 3515 goto not_found; 3516 3517 if (acpi_has_method(handle, "PCCH")) 3518 return false; 3519 3520 not_found: 3521 pr_debug("ACPI PCCH not found\n"); 3522 return true; 3523 } 3524 3525 static bool __init intel_pstate_has_acpi_ppc(void) 3526 { 3527 int i; 3528 3529 for_each_possible_cpu(i) { 3530 struct acpi_processor *pr = per_cpu(processors, i); 3531 3532 if (!pr) 3533 continue; 3534 if (acpi_has_method(pr->handle, "_PPC")) 3535 return true; 3536 } 3537 pr_debug("ACPI _PPC not found\n"); 3538 return false; 3539 } 3540 3541 enum { 3542 PSS, 3543 PPC, 3544 }; 3545 3546 /* Hardware vendor-specific info that has its own power management modes */ 3547 static struct acpi_platform_list plat_info[] __initdata = { 3548 {"HP ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, NULL, PSS}, 3549 {"ORACLE", "X4-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3550 {"ORACLE", "X4-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3551 {"ORACLE", "X4-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3552 {"ORACLE", "X3-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3553 {"ORACLE", "X3-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3554 {"ORACLE", "X3-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3555 {"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3556 {"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3557 {"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3558 {"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3559 {"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3560 {"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3561 {"ORACLE", "X6-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3562 {"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3563 { } /* End */ 3564 }; 3565 3566 #define BITMASK_OOB (BIT(8) | BIT(18)) 3567 3568 static bool __init intel_pstate_platform_pwr_mgmt_exists(void) 3569 { 3570 const struct x86_cpu_id *id; 3571 u64 misc_pwr; 3572 int idx; 3573 3574 id = x86_match_cpu(intel_pstate_cpu_oob_ids); 3575 if (id) { 3576 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr); 3577 if (misc_pwr & BITMASK_OOB) { 3578 pr_debug("Bit 8 or 18 in the MISC_PWR_MGMT MSR set\n"); 3579 pr_debug("P states are controlled in Out of Band mode by the firmware/hardware\n"); 3580 return true; 3581 } 3582 } 3583 3584 idx = acpi_match_platform_list(plat_info); 3585 if (idx < 0) 3586 return false; 3587 3588 switch (plat_info[idx].data) { 3589 case PSS: 3590 if (!intel_pstate_no_acpi_pss()) 3591 return false; 3592 3593 return intel_pstate_no_acpi_pcch(); 3594 case PPC: 3595 return intel_pstate_has_acpi_ppc() && !force_load; 3596 } 3597 3598 return false; 3599 } 3600 3601 static void intel_pstate_request_control_from_smm(void) 3602 { 3603 /* 3604 * It may be unsafe to request P-states control from SMM if _PPC support 3605 * has not been enabled. 3606 */ 3607 if (acpi_ppc) 3608 acpi_processor_pstate_control(); 3609 } 3610 #else /* CONFIG_ACPI not enabled */ 3611 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; } 3612 static inline bool intel_pstate_has_acpi_ppc(void) { return false; } 3613 static inline void intel_pstate_request_control_from_smm(void) {} 3614 #endif /* CONFIG_ACPI */ 3615 3616 #define INTEL_PSTATE_HWP_BROADWELL 0x01 3617 3618 #define X86_MATCH_HWP(vfm, hwp_mode) \ 3619 X86_MATCH_VFM_FEATURE(vfm, X86_FEATURE_HWP, hwp_mode) 3620 3621 static const struct x86_cpu_id hwp_support_ids[] __initconst = { 3622 X86_MATCH_HWP(INTEL_BROADWELL_X, INTEL_PSTATE_HWP_BROADWELL), 3623 X86_MATCH_HWP(INTEL_BROADWELL_D, INTEL_PSTATE_HWP_BROADWELL), 3624 X86_MATCH_HWP(INTEL_ANY, 0), 3625 {} 3626 }; 3627 3628 static bool intel_pstate_hwp_is_enabled(void) 3629 { 3630 u64 value; 3631 3632 rdmsrl(MSR_PM_ENABLE, value); 3633 return !!(value & 0x1); 3634 } 3635 3636 #define POWERSAVE_MASK GENMASK(7, 0) 3637 #define BALANCE_POWER_MASK GENMASK(15, 8) 3638 #define BALANCE_PERFORMANCE_MASK GENMASK(23, 16) 3639 #define PERFORMANCE_MASK GENMASK(31, 24) 3640 3641 #define HWP_SET_EPP_VALUES(powersave, balance_power, balance_perf, performance) \ 3642 (FIELD_PREP_CONST(POWERSAVE_MASK, powersave) |\ 3643 FIELD_PREP_CONST(BALANCE_POWER_MASK, balance_power) |\ 3644 FIELD_PREP_CONST(BALANCE_PERFORMANCE_MASK, balance_perf) |\ 3645 FIELD_PREP_CONST(PERFORMANCE_MASK, performance)) 3646 3647 #define HWP_SET_DEF_BALANCE_PERF_EPP(balance_perf) \ 3648 (HWP_SET_EPP_VALUES(HWP_EPP_POWERSAVE, HWP_EPP_BALANCE_POWERSAVE,\ 3649 balance_perf, HWP_EPP_PERFORMANCE)) 3650 3651 static const struct x86_cpu_id intel_epp_default[] = { 3652 /* 3653 * Set EPP value as 102, this is the max suggested EPP 3654 * which can result in one core turbo frequency for 3655 * AlderLake Mobile CPUs. 3656 */ 3657 X86_MATCH_VFM(INTEL_ALDERLAKE_L, HWP_SET_DEF_BALANCE_PERF_EPP(102)), 3658 X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, HWP_SET_DEF_BALANCE_PERF_EPP(32)), 3659 X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, HWP_SET_DEF_BALANCE_PERF_EPP(32)), 3660 X86_MATCH_VFM(INTEL_GRANITERAPIDS_X, HWP_SET_DEF_BALANCE_PERF_EPP(32)), 3661 X86_MATCH_VFM(INTEL_GRANITERAPIDS_D, HWP_SET_DEF_BALANCE_PERF_EPP(32)), 3662 X86_MATCH_VFM(INTEL_METEORLAKE_L, HWP_SET_EPP_VALUES(HWP_EPP_POWERSAVE, 3663 179, 64, 16)), 3664 X86_MATCH_VFM(INTEL_ARROWLAKE, HWP_SET_EPP_VALUES(HWP_EPP_POWERSAVE, 3665 179, 64, 16)), 3666 {} 3667 }; 3668 3669 static const struct x86_cpu_id intel_hybrid_scaling_factor[] = { 3670 X86_MATCH_VFM(INTEL_ALDERLAKE, HYBRID_SCALING_FACTOR_ADL), 3671 X86_MATCH_VFM(INTEL_ALDERLAKE_L, HYBRID_SCALING_FACTOR_ADL), 3672 X86_MATCH_VFM(INTEL_RAPTORLAKE, HYBRID_SCALING_FACTOR_ADL), 3673 X86_MATCH_VFM(INTEL_RAPTORLAKE_P, HYBRID_SCALING_FACTOR_ADL), 3674 X86_MATCH_VFM(INTEL_RAPTORLAKE_S, HYBRID_SCALING_FACTOR_ADL), 3675 X86_MATCH_VFM(INTEL_METEORLAKE_L, HYBRID_SCALING_FACTOR_MTL), 3676 X86_MATCH_VFM(INTEL_LUNARLAKE_M, HYBRID_SCALING_FACTOR_LNL), 3677 {} 3678 }; 3679 3680 static int __init intel_pstate_init(void) 3681 { 3682 static struct cpudata **_all_cpu_data; 3683 const struct x86_cpu_id *id; 3684 int rc; 3685 3686 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) 3687 return -ENODEV; 3688 3689 /* 3690 * The Intel pstate driver will be ignored if the platform 3691 * firmware has its own power management modes. 3692 */ 3693 if (intel_pstate_platform_pwr_mgmt_exists()) { 3694 pr_info("P-states controlled by the platform\n"); 3695 return -ENODEV; 3696 } 3697 3698 id = x86_match_cpu(hwp_support_ids); 3699 if (id) { 3700 hwp_forced = intel_pstate_hwp_is_enabled(); 3701 3702 if (hwp_forced) 3703 pr_info("HWP enabled by BIOS\n"); 3704 else if (no_load) 3705 return -ENODEV; 3706 3707 copy_cpu_funcs(&core_funcs); 3708 /* 3709 * Avoid enabling HWP for processors without EPP support, 3710 * because that means incomplete HWP implementation which is a 3711 * corner case and supporting it is generally problematic. 3712 * 3713 * If HWP is enabled already, though, there is no choice but to 3714 * deal with it. 3715 */ 3716 if ((!no_hwp && boot_cpu_has(X86_FEATURE_HWP_EPP)) || hwp_forced) { 3717 hwp_active = true; 3718 hwp_mode_bdw = id->driver_data; 3719 intel_pstate.attr = hwp_cpufreq_attrs; 3720 intel_cpufreq.attr = hwp_cpufreq_attrs; 3721 intel_cpufreq.flags |= CPUFREQ_NEED_UPDATE_LIMITS; 3722 intel_cpufreq.adjust_perf = intel_cpufreq_adjust_perf; 3723 if (!default_driver) 3724 default_driver = &intel_pstate; 3725 3726 pstate_funcs.get_cpu_scaling = hwp_get_cpu_scaling; 3727 3728 goto hwp_cpu_matched; 3729 } 3730 pr_info("HWP not enabled\n"); 3731 } else { 3732 if (no_load) 3733 return -ENODEV; 3734 3735 id = x86_match_cpu(intel_pstate_cpu_ids); 3736 if (!id) { 3737 pr_info("CPU model not supported\n"); 3738 return -ENODEV; 3739 } 3740 3741 copy_cpu_funcs((struct pstate_funcs *)id->driver_data); 3742 } 3743 3744 if (intel_pstate_msrs_not_valid()) { 3745 pr_info("Invalid MSRs\n"); 3746 return -ENODEV; 3747 } 3748 /* Without HWP start in the passive mode. */ 3749 if (!default_driver) 3750 default_driver = &intel_cpufreq; 3751 3752 hwp_cpu_matched: 3753 if (!hwp_active && hwp_only) 3754 return -ENOTSUPP; 3755 3756 pr_info("Intel P-state driver initializing\n"); 3757 3758 _all_cpu_data = vzalloc(array_size(sizeof(void *), num_possible_cpus())); 3759 if (!_all_cpu_data) 3760 return -ENOMEM; 3761 3762 WRITE_ONCE(all_cpu_data, _all_cpu_data); 3763 3764 intel_pstate_request_control_from_smm(); 3765 3766 intel_pstate_sysfs_expose_params(); 3767 3768 if (hwp_active) { 3769 const struct x86_cpu_id *id = x86_match_cpu(intel_epp_default); 3770 const struct x86_cpu_id *hybrid_id = x86_match_cpu(intel_hybrid_scaling_factor); 3771 3772 if (id) { 3773 epp_values[EPP_INDEX_POWERSAVE] = 3774 FIELD_GET(POWERSAVE_MASK, id->driver_data); 3775 epp_values[EPP_INDEX_BALANCE_POWERSAVE] = 3776 FIELD_GET(BALANCE_POWER_MASK, id->driver_data); 3777 epp_values[EPP_INDEX_BALANCE_PERFORMANCE] = 3778 FIELD_GET(BALANCE_PERFORMANCE_MASK, id->driver_data); 3779 epp_values[EPP_INDEX_PERFORMANCE] = 3780 FIELD_GET(PERFORMANCE_MASK, id->driver_data); 3781 pr_debug("Updated EPPs powersave:%x balanced power:%x balanced perf:%x performance:%x\n", 3782 epp_values[EPP_INDEX_POWERSAVE], 3783 epp_values[EPP_INDEX_BALANCE_POWERSAVE], 3784 epp_values[EPP_INDEX_BALANCE_PERFORMANCE], 3785 epp_values[EPP_INDEX_PERFORMANCE]); 3786 } 3787 3788 if (hybrid_id) { 3789 hybrid_scaling_factor = hybrid_id->driver_data; 3790 pr_debug("hybrid scaling factor: %d\n", hybrid_scaling_factor); 3791 } 3792 3793 } 3794 3795 mutex_lock(&intel_pstate_driver_lock); 3796 rc = intel_pstate_register_driver(default_driver); 3797 mutex_unlock(&intel_pstate_driver_lock); 3798 if (rc) { 3799 intel_pstate_sysfs_remove(); 3800 return rc; 3801 } 3802 3803 if (hwp_active) { 3804 const struct x86_cpu_id *id; 3805 3806 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids); 3807 if (id) { 3808 set_power_ctl_ee_state(false); 3809 pr_info("Disabling energy efficiency optimization\n"); 3810 } 3811 3812 pr_info("HWP enabled\n"); 3813 } else if (boot_cpu_has(X86_FEATURE_HYBRID_CPU)) { 3814 pr_warn("Problematic setup: Hybrid processor with disabled HWP\n"); 3815 } 3816 3817 return 0; 3818 } 3819 device_initcall(intel_pstate_init); 3820 3821 static int __init intel_pstate_setup(char *str) 3822 { 3823 if (!str) 3824 return -EINVAL; 3825 3826 if (!strcmp(str, "disable")) 3827 no_load = 1; 3828 else if (!strcmp(str, "active")) 3829 default_driver = &intel_pstate; 3830 else if (!strcmp(str, "passive")) 3831 default_driver = &intel_cpufreq; 3832 3833 if (!strcmp(str, "no_hwp")) 3834 no_hwp = 1; 3835 3836 if (!strcmp(str, "no_cas")) 3837 no_cas = true; 3838 3839 if (!strcmp(str, "force")) 3840 force_load = 1; 3841 if (!strcmp(str, "hwp_only")) 3842 hwp_only = 1; 3843 if (!strcmp(str, "per_cpu_perf_limits")) 3844 per_cpu_limits = true; 3845 3846 #ifdef CONFIG_ACPI 3847 if (!strcmp(str, "support_acpi_ppc")) 3848 acpi_ppc = true; 3849 #endif 3850 3851 return 0; 3852 } 3853 early_param("intel_pstate", intel_pstate_setup); 3854 3855 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>"); 3856 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors"); 3857