1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * intel_pstate.c: Native P state management for Intel processors 4 * 5 * (C) Copyright 2012 Intel Corporation 6 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com> 7 */ 8 9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10 11 #include <linux/kernel.h> 12 #include <linux/kernel_stat.h> 13 #include <linux/module.h> 14 #include <linux/ktime.h> 15 #include <linux/hrtimer.h> 16 #include <linux/tick.h> 17 #include <linux/slab.h> 18 #include <linux/sched/cpufreq.h> 19 #include <linux/sched/smt.h> 20 #include <linux/list.h> 21 #include <linux/cpu.h> 22 #include <linux/cpufreq.h> 23 #include <linux/sysfs.h> 24 #include <linux/types.h> 25 #include <linux/fs.h> 26 #include <linux/acpi.h> 27 #include <linux/vmalloc.h> 28 #include <linux/pm_qos.h> 29 #include <linux/bitfield.h> 30 #include <trace/events/power.h> 31 #include <linux/units.h> 32 33 #include <asm/cpu.h> 34 #include <asm/div64.h> 35 #include <asm/msr.h> 36 #include <asm/cpu_device_id.h> 37 #include <asm/cpufeature.h> 38 #include <asm/intel-family.h> 39 #include "../drivers/thermal/intel/thermal_interrupt.h" 40 41 #define INTEL_PSTATE_SAMPLING_INTERVAL (10 * NSEC_PER_MSEC) 42 43 #define INTEL_CPUFREQ_TRANSITION_LATENCY 20000 44 #define INTEL_CPUFREQ_TRANSITION_DELAY_HWP 5000 45 #define INTEL_CPUFREQ_TRANSITION_DELAY 500 46 47 #ifdef CONFIG_ACPI 48 #include <acpi/processor.h> 49 #include <acpi/cppc_acpi.h> 50 #endif 51 52 #define FRAC_BITS 8 53 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS) 54 #define fp_toint(X) ((X) >> FRAC_BITS) 55 56 #define ONE_EIGHTH_FP ((int64_t)1 << (FRAC_BITS - 3)) 57 58 #define EXT_BITS 6 59 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS) 60 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS) 61 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS) 62 63 static inline int32_t mul_fp(int32_t x, int32_t y) 64 { 65 return ((int64_t)x * (int64_t)y) >> FRAC_BITS; 66 } 67 68 static inline int32_t div_fp(s64 x, s64 y) 69 { 70 return div64_s64((int64_t)x << FRAC_BITS, y); 71 } 72 73 static inline int ceiling_fp(int32_t x) 74 { 75 int mask, ret; 76 77 ret = fp_toint(x); 78 mask = (1 << FRAC_BITS) - 1; 79 if (x & mask) 80 ret += 1; 81 return ret; 82 } 83 84 static inline u64 mul_ext_fp(u64 x, u64 y) 85 { 86 return (x * y) >> EXT_FRAC_BITS; 87 } 88 89 static inline u64 div_ext_fp(u64 x, u64 y) 90 { 91 return div64_u64(x << EXT_FRAC_BITS, y); 92 } 93 94 /** 95 * struct sample - Store performance sample 96 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average 97 * performance during last sample period 98 * @busy_scaled: Scaled busy value which is used to calculate next 99 * P state. This can be different than core_avg_perf 100 * to account for cpu idle period 101 * @aperf: Difference of actual performance frequency clock count 102 * read from APERF MSR between last and current sample 103 * @mperf: Difference of maximum performance frequency clock count 104 * read from MPERF MSR between last and current sample 105 * @tsc: Difference of time stamp counter between last and 106 * current sample 107 * @time: Current time from scheduler 108 * 109 * This structure is used in the cpudata structure to store performance sample 110 * data for choosing next P State. 111 */ 112 struct sample { 113 int32_t core_avg_perf; 114 int32_t busy_scaled; 115 u64 aperf; 116 u64 mperf; 117 u64 tsc; 118 u64 time; 119 }; 120 121 /** 122 * struct pstate_data - Store P state data 123 * @current_pstate: Current requested P state 124 * @min_pstate: Min P state possible for this platform 125 * @max_pstate: Max P state possible for this platform 126 * @max_pstate_physical:This is physical Max P state for a processor 127 * This can be higher than the max_pstate which can 128 * be limited by platform thermal design power limits 129 * @perf_ctl_scaling: PERF_CTL P-state to frequency scaling factor 130 * @scaling: Scaling factor between performance and frequency 131 * @turbo_pstate: Max Turbo P state possible for this platform 132 * @min_freq: @min_pstate frequency in cpufreq units 133 * @max_freq: @max_pstate frequency in cpufreq units 134 * @turbo_freq: @turbo_pstate frequency in cpufreq units 135 * 136 * Stores the per cpu model P state limits and current P state. 137 */ 138 struct pstate_data { 139 int current_pstate; 140 int min_pstate; 141 int max_pstate; 142 int max_pstate_physical; 143 int perf_ctl_scaling; 144 int scaling; 145 int turbo_pstate; 146 unsigned int min_freq; 147 unsigned int max_freq; 148 unsigned int turbo_freq; 149 }; 150 151 /** 152 * struct vid_data - Stores voltage information data 153 * @min: VID data for this platform corresponding to 154 * the lowest P state 155 * @max: VID data corresponding to the highest P State. 156 * @turbo: VID data for turbo P state 157 * @ratio: Ratio of (vid max - vid min) / 158 * (max P state - Min P State) 159 * 160 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling) 161 * This data is used in Atom platforms, where in addition to target P state, 162 * the voltage data needs to be specified to select next P State. 163 */ 164 struct vid_data { 165 int min; 166 int max; 167 int turbo; 168 int32_t ratio; 169 }; 170 171 /** 172 * struct global_params - Global parameters, mostly tunable via sysfs. 173 * @no_turbo: Whether or not to use turbo P-states. 174 * @turbo_disabled: Whether or not turbo P-states are available at all, 175 * based on the MSR_IA32_MISC_ENABLE value and whether or 176 * not the maximum reported turbo P-state is different from 177 * the maximum reported non-turbo one. 178 * @min_perf_pct: Minimum capacity limit in percent of the maximum turbo 179 * P-state capacity. 180 * @max_perf_pct: Maximum capacity limit in percent of the maximum turbo 181 * P-state capacity. 182 */ 183 struct global_params { 184 bool no_turbo; 185 bool turbo_disabled; 186 int max_perf_pct; 187 int min_perf_pct; 188 }; 189 190 /** 191 * struct cpudata - Per CPU instance data storage 192 * @cpu: CPU number for this instance data 193 * @policy: CPUFreq policy value 194 * @update_util: CPUFreq utility callback information 195 * @update_util_set: CPUFreq utility callback is set 196 * @iowait_boost: iowait-related boost fraction 197 * @last_update: Time of the last update. 198 * @pstate: Stores P state limits for this CPU 199 * @vid: Stores VID limits for this CPU 200 * @last_sample_time: Last Sample time 201 * @aperf_mperf_shift: APERF vs MPERF counting frequency difference 202 * @prev_aperf: Last APERF value read from APERF MSR 203 * @prev_mperf: Last MPERF value read from MPERF MSR 204 * @prev_tsc: Last timestamp counter (TSC) value 205 * @sample: Storage for storing last Sample data 206 * @min_perf_ratio: Minimum capacity in terms of PERF or HWP ratios 207 * @max_perf_ratio: Maximum capacity in terms of PERF or HWP ratios 208 * @acpi_perf_data: Stores ACPI perf information read from _PSS 209 * @valid_pss_table: Set to true for valid ACPI _PSS entries found 210 * @epp_powersave: Last saved HWP energy performance preference 211 * (EPP) or energy performance bias (EPB), 212 * when policy switched to performance 213 * @epp_policy: Last saved policy used to set EPP/EPB 214 * @epp_default: Power on default HWP energy performance 215 * preference/bias 216 * @epp_cached: Cached HWP energy-performance preference value 217 * @hwp_req_cached: Cached value of the last HWP Request MSR 218 * @hwp_cap_cached: Cached value of the last HWP Capabilities MSR 219 * @last_io_update: Last time when IO wake flag was set 220 * @capacity_perf: Highest perf used for scale invariance 221 * @sched_flags: Store scheduler flags for possible cross CPU update 222 * @hwp_boost_min: Last HWP boosted min performance 223 * @suspended: Whether or not the driver has been suspended. 224 * @pd_registered: Set when a perf domain is registered for this CPU. 225 * @hwp_notify_work: workqueue for HWP notifications. 226 * 227 * This structure stores per CPU instance data for all CPUs. 228 */ 229 struct cpudata { 230 int cpu; 231 232 unsigned int policy; 233 struct update_util_data update_util; 234 bool update_util_set; 235 236 struct pstate_data pstate; 237 struct vid_data vid; 238 239 u64 last_update; 240 u64 last_sample_time; 241 u64 aperf_mperf_shift; 242 u64 prev_aperf; 243 u64 prev_mperf; 244 u64 prev_tsc; 245 struct sample sample; 246 int32_t min_perf_ratio; 247 int32_t max_perf_ratio; 248 #ifdef CONFIG_ACPI 249 struct acpi_processor_performance acpi_perf_data; 250 bool valid_pss_table; 251 #endif 252 unsigned int iowait_boost; 253 s16 epp_powersave; 254 s16 epp_policy; 255 s16 epp_default; 256 s16 epp_cached; 257 u64 hwp_req_cached; 258 u64 hwp_cap_cached; 259 u64 last_io_update; 260 unsigned int capacity_perf; 261 unsigned int sched_flags; 262 u32 hwp_boost_min; 263 bool suspended; 264 #ifdef CONFIG_ENERGY_MODEL 265 bool pd_registered; 266 #endif 267 struct delayed_work hwp_notify_work; 268 }; 269 270 static struct cpudata **all_cpu_data; 271 272 /** 273 * struct pstate_funcs - Per CPU model specific callbacks 274 * @get_max: Callback to get maximum non turbo effective P state 275 * @get_max_physical: Callback to get maximum non turbo physical P state 276 * @get_min: Callback to get minimum P state 277 * @get_turbo: Callback to get turbo P state 278 * @get_scaling: Callback to get frequency scaling factor 279 * @get_cpu_scaling: Get frequency scaling factor for a given cpu 280 * @get_aperf_mperf_shift: Callback to get the APERF vs MPERF frequency difference 281 * @get_val: Callback to convert P state to actual MSR write value 282 * @get_vid: Callback to get VID data for Atom platforms 283 * 284 * Core and Atom CPU models have different way to get P State limits. This 285 * structure is used to store those callbacks. 286 */ 287 struct pstate_funcs { 288 int (*get_max)(int cpu); 289 int (*get_max_physical)(int cpu); 290 int (*get_min)(int cpu); 291 int (*get_turbo)(int cpu); 292 int (*get_scaling)(void); 293 int (*get_cpu_scaling)(int cpu); 294 int (*get_aperf_mperf_shift)(void); 295 u64 (*get_val)(struct cpudata*, int pstate); 296 void (*get_vid)(struct cpudata *); 297 }; 298 299 static struct pstate_funcs pstate_funcs __read_mostly; 300 301 static bool hwp_active __ro_after_init; 302 static bool per_cpu_limits __ro_after_init; 303 static bool hwp_forced __ro_after_init; 304 static bool hwp_boost __read_mostly; 305 static bool hwp_is_hybrid; 306 307 static struct cpufreq_driver *intel_pstate_driver __read_mostly; 308 309 #define INTEL_PSTATE_CORE_SCALING 100000 310 #define HYBRID_SCALING_FACTOR_ADL 78741 311 #define HYBRID_SCALING_FACTOR_MTL 80000 312 #define HYBRID_SCALING_FACTOR_LNL 86957 313 314 static int hybrid_scaling_factor; 315 316 static inline int core_get_scaling(void) 317 { 318 return INTEL_PSTATE_CORE_SCALING; 319 } 320 321 #ifdef CONFIG_ACPI 322 static bool acpi_ppc; 323 #endif 324 325 static struct global_params global; 326 327 static DEFINE_MUTEX(intel_pstate_driver_lock); 328 static DEFINE_MUTEX(intel_pstate_limits_lock); 329 330 #ifdef CONFIG_ACPI 331 332 static bool intel_pstate_acpi_pm_profile_server(void) 333 { 334 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER || 335 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER) 336 return true; 337 338 return false; 339 } 340 341 static bool intel_pstate_get_ppc_enable_status(void) 342 { 343 if (intel_pstate_acpi_pm_profile_server()) 344 return true; 345 346 return acpi_ppc; 347 } 348 349 #ifdef CONFIG_ACPI_CPPC_LIB 350 351 /* The work item is needed to avoid CPU hotplug locking issues */ 352 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work) 353 { 354 sched_set_itmt_support(); 355 } 356 357 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn); 358 359 #define CPPC_MAX_PERF U8_MAX 360 361 static void intel_pstate_set_itmt_prio(int cpu) 362 { 363 struct cppc_perf_caps cppc_perf; 364 static u32 max_highest_perf = 0, min_highest_perf = U32_MAX; 365 int ret; 366 367 ret = cppc_get_perf_caps(cpu, &cppc_perf); 368 /* 369 * If CPPC is not available, fall back to MSR_HWP_CAPABILITIES bits [8:0]. 370 * 371 * Also, on some systems with overclocking enabled, CPPC.highest_perf is 372 * hardcoded to 0xff, so CPPC.highest_perf cannot be used to enable ITMT. 373 * Fall back to MSR_HWP_CAPABILITIES then too. 374 */ 375 if (ret || cppc_perf.highest_perf == CPPC_MAX_PERF) 376 cppc_perf.highest_perf = HWP_HIGHEST_PERF(READ_ONCE(all_cpu_data[cpu]->hwp_cap_cached)); 377 378 /* 379 * The priorities can be set regardless of whether or not 380 * sched_set_itmt_support(true) has been called and it is valid to 381 * update them at any time after it has been called. 382 */ 383 sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu); 384 385 if (max_highest_perf <= min_highest_perf) { 386 if (cppc_perf.highest_perf > max_highest_perf) 387 max_highest_perf = cppc_perf.highest_perf; 388 389 if (cppc_perf.highest_perf < min_highest_perf) 390 min_highest_perf = cppc_perf.highest_perf; 391 392 if (max_highest_perf > min_highest_perf) { 393 /* 394 * This code can be run during CPU online under the 395 * CPU hotplug locks, so sched_set_itmt_support() 396 * cannot be called from here. Queue up a work item 397 * to invoke it. 398 */ 399 schedule_work(&sched_itmt_work); 400 } 401 } 402 } 403 404 static int intel_pstate_get_cppc_guaranteed(int cpu) 405 { 406 struct cppc_perf_caps cppc_perf; 407 int ret; 408 409 ret = cppc_get_perf_caps(cpu, &cppc_perf); 410 if (ret) 411 return ret; 412 413 if (cppc_perf.guaranteed_perf) 414 return cppc_perf.guaranteed_perf; 415 416 return cppc_perf.nominal_perf; 417 } 418 419 static int intel_pstate_cppc_get_scaling(int cpu) 420 { 421 struct cppc_perf_caps cppc_perf; 422 423 /* 424 * Compute the perf-to-frequency scaling factor for the given CPU if 425 * possible, unless it would be 0. 426 */ 427 if (!cppc_get_perf_caps(cpu, &cppc_perf) && 428 cppc_perf.nominal_perf && cppc_perf.nominal_freq) 429 return div_u64(cppc_perf.nominal_freq * KHZ_PER_MHZ, 430 cppc_perf.nominal_perf); 431 432 return core_get_scaling(); 433 } 434 435 #else /* CONFIG_ACPI_CPPC_LIB */ 436 static inline void intel_pstate_set_itmt_prio(int cpu) 437 { 438 } 439 #endif /* CONFIG_ACPI_CPPC_LIB */ 440 441 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) 442 { 443 struct cpudata *cpu; 444 int ret; 445 int i; 446 447 if (hwp_active) { 448 intel_pstate_set_itmt_prio(policy->cpu); 449 return; 450 } 451 452 if (!intel_pstate_get_ppc_enable_status()) 453 return; 454 455 cpu = all_cpu_data[policy->cpu]; 456 457 ret = acpi_processor_register_performance(&cpu->acpi_perf_data, 458 policy->cpu); 459 if (ret) 460 return; 461 462 /* 463 * Check if the control value in _PSS is for PERF_CTL MSR, which should 464 * guarantee that the states returned by it map to the states in our 465 * list directly. 466 */ 467 if (cpu->acpi_perf_data.control_register.space_id != 468 ACPI_ADR_SPACE_FIXED_HARDWARE) 469 goto err; 470 471 /* 472 * If there is only one entry _PSS, simply ignore _PSS and continue as 473 * usual without taking _PSS into account 474 */ 475 if (cpu->acpi_perf_data.state_count < 2) 476 goto err; 477 478 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu); 479 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) { 480 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n", 481 (i == cpu->acpi_perf_data.state ? '*' : ' '), i, 482 (u32) cpu->acpi_perf_data.states[i].core_frequency, 483 (u32) cpu->acpi_perf_data.states[i].power, 484 (u32) cpu->acpi_perf_data.states[i].control); 485 } 486 487 cpu->valid_pss_table = true; 488 pr_debug("_PPC limits will be enforced\n"); 489 490 return; 491 492 err: 493 cpu->valid_pss_table = false; 494 acpi_processor_unregister_performance(policy->cpu); 495 } 496 497 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) 498 { 499 struct cpudata *cpu; 500 501 cpu = all_cpu_data[policy->cpu]; 502 if (!cpu->valid_pss_table) 503 return; 504 505 acpi_processor_unregister_performance(policy->cpu); 506 } 507 #else /* CONFIG_ACPI */ 508 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) 509 { 510 } 511 512 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) 513 { 514 } 515 516 static inline bool intel_pstate_acpi_pm_profile_server(void) 517 { 518 return false; 519 } 520 #endif /* CONFIG_ACPI */ 521 522 #ifndef CONFIG_ACPI_CPPC_LIB 523 static inline int intel_pstate_get_cppc_guaranteed(int cpu) 524 { 525 return -ENOTSUPP; 526 } 527 528 static int intel_pstate_cppc_get_scaling(int cpu) 529 { 530 return core_get_scaling(); 531 } 532 #endif /* CONFIG_ACPI_CPPC_LIB */ 533 534 static int intel_pstate_freq_to_hwp_rel(struct cpudata *cpu, int freq, 535 unsigned int relation) 536 { 537 if (freq == cpu->pstate.turbo_freq) 538 return cpu->pstate.turbo_pstate; 539 540 if (freq == cpu->pstate.max_freq) 541 return cpu->pstate.max_pstate; 542 543 switch (relation) { 544 case CPUFREQ_RELATION_H: 545 return freq / cpu->pstate.scaling; 546 case CPUFREQ_RELATION_C: 547 return DIV_ROUND_CLOSEST(freq, cpu->pstate.scaling); 548 } 549 550 return DIV_ROUND_UP(freq, cpu->pstate.scaling); 551 } 552 553 static int intel_pstate_freq_to_hwp(struct cpudata *cpu, int freq) 554 { 555 return intel_pstate_freq_to_hwp_rel(cpu, freq, CPUFREQ_RELATION_L); 556 } 557 558 /** 559 * intel_pstate_hybrid_hwp_adjust - Calibrate HWP performance levels. 560 * @cpu: Target CPU. 561 * 562 * On hybrid processors, HWP may expose more performance levels than there are 563 * P-states accessible through the PERF_CTL interface. If that happens, the 564 * scaling factor between HWP performance levels and CPU frequency will be less 565 * than the scaling factor between P-state values and CPU frequency. 566 * 567 * In that case, adjust the CPU parameters used in computations accordingly. 568 */ 569 static void intel_pstate_hybrid_hwp_adjust(struct cpudata *cpu) 570 { 571 int perf_ctl_max_phys = cpu->pstate.max_pstate_physical; 572 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling; 573 int perf_ctl_turbo = pstate_funcs.get_turbo(cpu->cpu); 574 int scaling = cpu->pstate.scaling; 575 int freq; 576 577 pr_debug("CPU%d: PERF_CTL max_phys = %d\n", cpu->cpu, perf_ctl_max_phys); 578 pr_debug("CPU%d: PERF_CTL turbo = %d\n", cpu->cpu, perf_ctl_turbo); 579 pr_debug("CPU%d: PERF_CTL scaling = %d\n", cpu->cpu, perf_ctl_scaling); 580 pr_debug("CPU%d: HWP_CAP guaranteed = %d\n", cpu->cpu, cpu->pstate.max_pstate); 581 pr_debug("CPU%d: HWP_CAP highest = %d\n", cpu->cpu, cpu->pstate.turbo_pstate); 582 pr_debug("CPU%d: HWP-to-frequency scaling factor: %d\n", cpu->cpu, scaling); 583 584 if (scaling == perf_ctl_scaling) 585 return; 586 587 hwp_is_hybrid = true; 588 589 freq = perf_ctl_max_phys * perf_ctl_scaling; 590 cpu->pstate.max_pstate_physical = intel_pstate_freq_to_hwp(cpu, freq); 591 592 /* 593 * Cast the min P-state value retrieved via pstate_funcs.get_min() to 594 * the effective range of HWP performance levels. 595 */ 596 cpu->pstate.min_pstate = intel_pstate_freq_to_hwp(cpu, cpu->pstate.min_freq); 597 } 598 599 static bool turbo_is_disabled(void) 600 { 601 u64 misc_en; 602 603 rdmsrq(MSR_IA32_MISC_ENABLE, misc_en); 604 605 return !!(misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE); 606 } 607 608 static int min_perf_pct_min(void) 609 { 610 struct cpudata *cpu = all_cpu_data[0]; 611 int turbo_pstate = cpu->pstate.turbo_pstate; 612 613 return turbo_pstate ? 614 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0; 615 } 616 617 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data) 618 { 619 s16 epp = -EOPNOTSUPP; 620 621 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 622 /* 623 * When hwp_req_data is 0, means that caller didn't read 624 * MSR_HWP_REQUEST, so need to read and get EPP. 625 */ 626 if (!hwp_req_data) { 627 epp = rdmsrq_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, 628 &hwp_req_data); 629 if (epp) 630 return epp; 631 } 632 epp = (hwp_req_data >> 24) & 0xff; 633 } 634 635 return epp; 636 } 637 638 /* 639 * EPP display strings corresponding to EPP index in the 640 * energy_perf_strings[] 641 * index String 642 *------------------------------------- 643 * 0 default 644 * 1 performance 645 * 2 balance_performance 646 * 3 balance_power 647 * 4 power 648 */ 649 650 enum energy_perf_value_index { 651 EPP_INDEX_DEFAULT = 0, 652 EPP_INDEX_PERFORMANCE, 653 EPP_INDEX_BALANCE_PERFORMANCE, 654 EPP_INDEX_BALANCE_POWERSAVE, 655 EPP_INDEX_POWERSAVE, 656 }; 657 658 static const char * const energy_perf_strings[] = { 659 [EPP_INDEX_DEFAULT] = "default", 660 [EPP_INDEX_PERFORMANCE] = "performance", 661 [EPP_INDEX_BALANCE_PERFORMANCE] = "balance_performance", 662 [EPP_INDEX_BALANCE_POWERSAVE] = "balance_power", 663 [EPP_INDEX_POWERSAVE] = "power", 664 NULL 665 }; 666 static unsigned int epp_values[] = { 667 [EPP_INDEX_DEFAULT] = 0, /* Unused index */ 668 [EPP_INDEX_PERFORMANCE] = HWP_EPP_PERFORMANCE, 669 [EPP_INDEX_BALANCE_PERFORMANCE] = HWP_EPP_BALANCE_PERFORMANCE, 670 [EPP_INDEX_BALANCE_POWERSAVE] = HWP_EPP_BALANCE_POWERSAVE, 671 [EPP_INDEX_POWERSAVE] = HWP_EPP_POWERSAVE, 672 }; 673 674 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data, int *raw_epp) 675 { 676 s16 epp; 677 int index = -EINVAL; 678 679 *raw_epp = 0; 680 epp = intel_pstate_get_epp(cpu_data, 0); 681 if (epp < 0) 682 return epp; 683 684 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 685 if (epp == epp_values[EPP_INDEX_PERFORMANCE]) 686 return EPP_INDEX_PERFORMANCE; 687 if (epp == epp_values[EPP_INDEX_BALANCE_PERFORMANCE]) 688 return EPP_INDEX_BALANCE_PERFORMANCE; 689 if (epp == epp_values[EPP_INDEX_BALANCE_POWERSAVE]) 690 return EPP_INDEX_BALANCE_POWERSAVE; 691 if (epp == epp_values[EPP_INDEX_POWERSAVE]) 692 return EPP_INDEX_POWERSAVE; 693 *raw_epp = epp; 694 return 0; 695 } else if (boot_cpu_has(X86_FEATURE_EPB)) { 696 /* 697 * Range: 698 * 0x00-0x03 : Performance 699 * 0x04-0x07 : Balance performance 700 * 0x08-0x0B : Balance power 701 * 0x0C-0x0F : Power 702 * The EPB is a 4 bit value, but our ranges restrict the 703 * value which can be set. Here only using top two bits 704 * effectively. 705 */ 706 index = (epp >> 2) + 1; 707 } 708 709 return index; 710 } 711 712 static int intel_pstate_set_epp(struct cpudata *cpu, u32 epp) 713 { 714 int ret; 715 716 /* 717 * Use the cached HWP Request MSR value, because in the active mode the 718 * register itself may be updated by intel_pstate_hwp_boost_up() or 719 * intel_pstate_hwp_boost_down() at any time. 720 */ 721 u64 value = READ_ONCE(cpu->hwp_req_cached); 722 723 value &= ~GENMASK_ULL(31, 24); 724 value |= (u64)epp << 24; 725 /* 726 * The only other updater of hwp_req_cached in the active mode, 727 * intel_pstate_hwp_set(), is called under the same lock as this 728 * function, so it cannot run in parallel with the update below. 729 */ 730 WRITE_ONCE(cpu->hwp_req_cached, value); 731 ret = wrmsrq_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 732 if (!ret) 733 cpu->epp_cached = epp; 734 735 return ret; 736 } 737 738 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data, 739 int pref_index, bool use_raw, 740 u32 raw_epp) 741 { 742 int epp = -EINVAL; 743 int ret = -EOPNOTSUPP; 744 745 if (!pref_index) 746 epp = cpu_data->epp_default; 747 748 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 749 if (use_raw) 750 epp = raw_epp; 751 else if (epp == -EINVAL) 752 epp = epp_values[pref_index]; 753 754 /* 755 * To avoid confusion, refuse to set EPP to any values different 756 * from 0 (performance) if the current policy is "performance", 757 * because those values would be overridden. 758 */ 759 if (epp > 0 && cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) 760 return -EBUSY; 761 762 ret = intel_pstate_set_epp(cpu_data, epp); 763 } 764 765 return ret; 766 } 767 768 static ssize_t show_energy_performance_available_preferences( 769 struct cpufreq_policy *policy, char *buf) 770 { 771 int i = 0; 772 int ret = 0; 773 774 while (energy_perf_strings[i] != NULL) 775 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]); 776 777 ret += sprintf(&buf[ret], "\n"); 778 779 return ret; 780 } 781 782 cpufreq_freq_attr_ro(energy_performance_available_preferences); 783 784 static struct cpufreq_driver intel_pstate; 785 786 static ssize_t store_energy_performance_preference( 787 struct cpufreq_policy *policy, const char *buf, size_t count) 788 { 789 struct cpudata *cpu = all_cpu_data[policy->cpu]; 790 char str_preference[21]; 791 bool raw = false; 792 ssize_t ret; 793 u32 epp = 0; 794 795 ret = sscanf(buf, "%20s", str_preference); 796 if (ret != 1) 797 return -EINVAL; 798 799 ret = match_string(energy_perf_strings, -1, str_preference); 800 if (ret < 0) { 801 if (!boot_cpu_has(X86_FEATURE_HWP_EPP)) 802 return ret; 803 804 ret = kstrtouint(buf, 10, &epp); 805 if (ret) 806 return ret; 807 808 if (epp > 255) 809 return -EINVAL; 810 811 raw = true; 812 } 813 814 /* 815 * This function runs with the policy R/W semaphore held, which 816 * guarantees that the driver pointer will not change while it is 817 * running. 818 */ 819 if (!intel_pstate_driver) 820 return -EAGAIN; 821 822 mutex_lock(&intel_pstate_limits_lock); 823 824 if (intel_pstate_driver == &intel_pstate) { 825 ret = intel_pstate_set_energy_pref_index(cpu, ret, raw, epp); 826 } else { 827 /* 828 * In the passive mode the governor needs to be stopped on the 829 * target CPU before the EPP update and restarted after it, 830 * which is super-heavy-weight, so make sure it is worth doing 831 * upfront. 832 */ 833 if (!raw) 834 epp = ret ? epp_values[ret] : cpu->epp_default; 835 836 if (cpu->epp_cached != epp) { 837 int err; 838 839 cpufreq_stop_governor(policy); 840 ret = intel_pstate_set_epp(cpu, epp); 841 err = cpufreq_start_governor(policy); 842 if (!ret) 843 ret = err; 844 } else { 845 ret = 0; 846 } 847 } 848 849 mutex_unlock(&intel_pstate_limits_lock); 850 851 return ret ?: count; 852 } 853 854 static ssize_t show_energy_performance_preference( 855 struct cpufreq_policy *policy, char *buf) 856 { 857 struct cpudata *cpu_data = all_cpu_data[policy->cpu]; 858 int preference, raw_epp; 859 860 preference = intel_pstate_get_energy_pref_index(cpu_data, &raw_epp); 861 if (preference < 0) 862 return preference; 863 864 if (raw_epp) 865 return sprintf(buf, "%d\n", raw_epp); 866 else 867 return sprintf(buf, "%s\n", energy_perf_strings[preference]); 868 } 869 870 cpufreq_freq_attr_rw(energy_performance_preference); 871 872 static ssize_t show_base_frequency(struct cpufreq_policy *policy, char *buf) 873 { 874 struct cpudata *cpu = all_cpu_data[policy->cpu]; 875 int ratio, freq; 876 877 ratio = intel_pstate_get_cppc_guaranteed(policy->cpu); 878 if (ratio <= 0) { 879 u64 cap; 880 881 rdmsrq_on_cpu(policy->cpu, MSR_HWP_CAPABILITIES, &cap); 882 ratio = HWP_GUARANTEED_PERF(cap); 883 } 884 885 freq = ratio * cpu->pstate.scaling; 886 if (cpu->pstate.scaling != cpu->pstate.perf_ctl_scaling) 887 freq = rounddown(freq, cpu->pstate.perf_ctl_scaling); 888 889 return sprintf(buf, "%d\n", freq); 890 } 891 892 cpufreq_freq_attr_ro(base_frequency); 893 894 enum hwp_cpufreq_attr_index { 895 HWP_BASE_FREQUENCY_INDEX = 0, 896 HWP_PERFORMANCE_PREFERENCE_INDEX, 897 HWP_PERFORMANCE_AVAILABLE_PREFERENCES_INDEX, 898 HWP_CPUFREQ_ATTR_COUNT, 899 }; 900 901 static struct freq_attr *hwp_cpufreq_attrs[] = { 902 [HWP_BASE_FREQUENCY_INDEX] = &base_frequency, 903 [HWP_PERFORMANCE_PREFERENCE_INDEX] = &energy_performance_preference, 904 [HWP_PERFORMANCE_AVAILABLE_PREFERENCES_INDEX] = 905 &energy_performance_available_preferences, 906 [HWP_CPUFREQ_ATTR_COUNT] = NULL, 907 }; 908 909 static u8 hybrid_get_cpu_type(unsigned int cpu) 910 { 911 return cpu_data(cpu).topo.intel_type; 912 } 913 914 static bool no_cas __ro_after_init; 915 916 static struct cpudata *hybrid_max_perf_cpu __read_mostly; 917 /* 918 * Protects hybrid_max_perf_cpu, the capacity_perf fields in struct cpudata, 919 * and the x86 arch scale-invariance information from concurrent updates. 920 */ 921 static DEFINE_MUTEX(hybrid_capacity_lock); 922 923 #ifdef CONFIG_ENERGY_MODEL 924 #define HYBRID_EM_STATE_COUNT 4 925 926 static int hybrid_active_power(struct device *dev, unsigned long *power, 927 unsigned long *freq) 928 { 929 /* 930 * Create four "states" corresponding to 40%, 60%, 80%, and 100% of the 931 * full capacity. 932 * 933 * For this purpose, return the "frequency" of 2 for the first 934 * performance level and otherwise leave the value set by the caller. 935 */ 936 if (!*freq) 937 *freq = 2; 938 939 /* No power information. */ 940 *power = EM_MAX_POWER; 941 942 return 0; 943 } 944 945 static bool hybrid_has_l3(unsigned int cpu) 946 { 947 struct cpu_cacheinfo *cacheinfo = get_cpu_cacheinfo(cpu); 948 unsigned int i; 949 950 if (!cacheinfo) 951 return false; 952 953 for (i = 0; i < cacheinfo->num_leaves; i++) { 954 if (cacheinfo->info_list[i].level == 3) 955 return true; 956 } 957 958 return false; 959 } 960 961 static int hybrid_get_cost(struct device *dev, unsigned long freq, 962 unsigned long *cost) 963 { 964 /* Facilitate load balancing between CPUs of the same type. */ 965 *cost = freq; 966 /* 967 * Adjust the cost depending on CPU type. 968 * 969 * The idea is to start loading up LPE-cores before E-cores and start 970 * to populate E-cores when LPE-cores are utilized above 60% of the 971 * capacity. Similarly, P-cores start to be populated when E-cores are 972 * utilized above 60% of the capacity. 973 */ 974 if (hybrid_get_cpu_type(dev->id) == INTEL_CPU_TYPE_CORE) /* P-core */ 975 *cost += 2; 976 else if (hybrid_has_l3(dev->id)) /* E-core */ 977 *cost += 1; 978 979 return 0; 980 } 981 982 static bool hybrid_register_perf_domain(unsigned int cpu) 983 { 984 static const struct em_data_callback cb 985 = EM_ADV_DATA_CB(hybrid_active_power, hybrid_get_cost); 986 struct cpudata *cpudata = all_cpu_data[cpu]; 987 struct device *cpu_dev; 988 989 /* 990 * Registering EM perf domains without enabling asymmetric CPU capacity 991 * support is not really useful and one domain should not be registered 992 * more than once. 993 */ 994 if (!hybrid_max_perf_cpu || cpudata->pd_registered) 995 return false; 996 997 cpu_dev = get_cpu_device(cpu); 998 if (!cpu_dev) 999 return false; 1000 1001 if (em_dev_register_pd_no_update(cpu_dev, HYBRID_EM_STATE_COUNT, &cb, 1002 cpumask_of(cpu), false)) 1003 return false; 1004 1005 cpudata->pd_registered = true; 1006 1007 return true; 1008 } 1009 1010 static void hybrid_register_all_perf_domains(void) 1011 { 1012 unsigned int cpu; 1013 1014 for_each_online_cpu(cpu) 1015 hybrid_register_perf_domain(cpu); 1016 } 1017 1018 static void hybrid_update_perf_domain(struct cpudata *cpu) 1019 { 1020 if (cpu->pd_registered) 1021 em_adjust_cpu_capacity(cpu->cpu); 1022 } 1023 #else /* !CONFIG_ENERGY_MODEL */ 1024 static inline bool hybrid_register_perf_domain(unsigned int cpu) { return false; } 1025 static inline void hybrid_register_all_perf_domains(void) {} 1026 static inline void hybrid_update_perf_domain(struct cpudata *cpu) {} 1027 #endif /* CONFIG_ENERGY_MODEL */ 1028 1029 static void hybrid_set_cpu_capacity(struct cpudata *cpu) 1030 { 1031 arch_set_cpu_capacity(cpu->cpu, cpu->capacity_perf, 1032 hybrid_max_perf_cpu->capacity_perf, 1033 cpu->capacity_perf, 1034 cpu->pstate.max_pstate_physical); 1035 hybrid_update_perf_domain(cpu); 1036 1037 topology_set_cpu_scale(cpu->cpu, arch_scale_cpu_capacity(cpu->cpu)); 1038 1039 pr_debug("CPU%d: capacity perf = %u, base perf = %u, sys max perf = %u\n", 1040 cpu->cpu, cpu->capacity_perf, cpu->pstate.max_pstate_physical, 1041 hybrid_max_perf_cpu->capacity_perf); 1042 } 1043 1044 static void hybrid_clear_cpu_capacity(unsigned int cpunum) 1045 { 1046 arch_set_cpu_capacity(cpunum, 1, 1, 1, 1); 1047 } 1048 1049 static void hybrid_get_capacity_perf(struct cpudata *cpu) 1050 { 1051 u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached); 1052 1053 if (READ_ONCE(global.no_turbo)) { 1054 cpu->capacity_perf = HWP_GUARANTEED_PERF(hwp_cap); 1055 return; 1056 } 1057 1058 cpu->capacity_perf = HWP_HIGHEST_PERF(hwp_cap); 1059 } 1060 1061 static void hybrid_set_capacity_of_cpus(void) 1062 { 1063 int cpunum; 1064 1065 for_each_online_cpu(cpunum) { 1066 struct cpudata *cpu = all_cpu_data[cpunum]; 1067 1068 if (cpu) 1069 hybrid_set_cpu_capacity(cpu); 1070 } 1071 } 1072 1073 static void hybrid_update_cpu_capacity_scaling(void) 1074 { 1075 struct cpudata *max_perf_cpu = NULL; 1076 unsigned int max_cap_perf = 0; 1077 int cpunum; 1078 1079 for_each_online_cpu(cpunum) { 1080 struct cpudata *cpu = all_cpu_data[cpunum]; 1081 1082 if (!cpu) 1083 continue; 1084 1085 /* 1086 * During initialization, CPU performance at full capacity needs 1087 * to be determined. 1088 */ 1089 if (!hybrid_max_perf_cpu) 1090 hybrid_get_capacity_perf(cpu); 1091 1092 /* 1093 * If hybrid_max_perf_cpu is not NULL at this point, it is 1094 * being replaced, so don't take it into account when looking 1095 * for the new one. 1096 */ 1097 if (cpu == hybrid_max_perf_cpu) 1098 continue; 1099 1100 if (cpu->capacity_perf > max_cap_perf) { 1101 max_cap_perf = cpu->capacity_perf; 1102 max_perf_cpu = cpu; 1103 } 1104 } 1105 1106 if (max_perf_cpu) { 1107 hybrid_max_perf_cpu = max_perf_cpu; 1108 hybrid_set_capacity_of_cpus(); 1109 } else { 1110 pr_info("Found no CPUs with nonzero maximum performance\n"); 1111 /* Revert to the flat CPU capacity structure. */ 1112 for_each_online_cpu(cpunum) 1113 hybrid_clear_cpu_capacity(cpunum); 1114 } 1115 } 1116 1117 static void __hybrid_refresh_cpu_capacity_scaling(void) 1118 { 1119 hybrid_max_perf_cpu = NULL; 1120 hybrid_update_cpu_capacity_scaling(); 1121 } 1122 1123 static void hybrid_refresh_cpu_capacity_scaling(void) 1124 { 1125 guard(mutex)(&hybrid_capacity_lock); 1126 1127 __hybrid_refresh_cpu_capacity_scaling(); 1128 /* 1129 * Perf domains are not registered before setting hybrid_max_perf_cpu, 1130 * so register them all after setting up CPU capacity scaling. 1131 */ 1132 hybrid_register_all_perf_domains(); 1133 } 1134 1135 static void hybrid_init_cpu_capacity_scaling(bool refresh) 1136 { 1137 /* Bail out if enabling capacity-aware scheduling is prohibited. */ 1138 if (no_cas) 1139 return; 1140 1141 /* 1142 * If hybrid_max_perf_cpu is set at this point, the hybrid CPU capacity 1143 * scaling has been enabled already and the driver is just changing the 1144 * operation mode. 1145 */ 1146 if (refresh) { 1147 hybrid_refresh_cpu_capacity_scaling(); 1148 return; 1149 } 1150 1151 /* 1152 * On hybrid systems, use asym capacity instead of ITMT, but because 1153 * the capacity of SMT threads is not deterministic even approximately, 1154 * do not do that when SMT is in use. 1155 */ 1156 if (hwp_is_hybrid && !cpu_smt_possible() && arch_enable_hybrid_capacity_scale()) { 1157 hybrid_refresh_cpu_capacity_scaling(); 1158 /* 1159 * Disabling ITMT causes sched domains to be rebuilt to disable asym 1160 * packing and enable asym capacity and EAS. 1161 */ 1162 sched_clear_itmt_support(); 1163 } 1164 } 1165 1166 static bool hybrid_clear_max_perf_cpu(void) 1167 { 1168 bool ret; 1169 1170 guard(mutex)(&hybrid_capacity_lock); 1171 1172 ret = !!hybrid_max_perf_cpu; 1173 hybrid_max_perf_cpu = NULL; 1174 1175 return ret; 1176 } 1177 1178 static void intel_pstate_update_freq_limits(struct cpudata *cpu) 1179 { 1180 int scaling = cpu->pstate.scaling; 1181 unsigned int turbo_freq = cpu->pstate.turbo_pstate * scaling; 1182 unsigned int max_freq = cpu->pstate.max_pstate * scaling; 1183 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling; 1184 1185 if (scaling != perf_ctl_scaling) { 1186 turbo_freq = rounddown(turbo_freq, perf_ctl_scaling); 1187 max_freq = rounddown(max_freq, perf_ctl_scaling); 1188 } 1189 1190 cpu->pstate.turbo_freq = turbo_freq; 1191 cpu->pstate.max_freq = max_freq; 1192 } 1193 1194 static void __intel_pstate_get_hwp_cap(struct cpudata *cpu) 1195 { 1196 u64 cap; 1197 1198 rdmsrq_on_cpu(cpu->cpu, MSR_HWP_CAPABILITIES, &cap); 1199 WRITE_ONCE(cpu->hwp_cap_cached, cap); 1200 cpu->pstate.max_pstate = HWP_GUARANTEED_PERF(cap); 1201 cpu->pstate.turbo_pstate = HWP_HIGHEST_PERF(cap); 1202 } 1203 1204 static void intel_pstate_get_hwp_cap(struct cpudata *cpu) 1205 { 1206 __intel_pstate_get_hwp_cap(cpu); 1207 intel_pstate_update_freq_limits(cpu); 1208 } 1209 1210 static void hybrid_update_capacity(struct cpudata *cpu) 1211 { 1212 unsigned int max_cap_perf; 1213 1214 mutex_lock(&hybrid_capacity_lock); 1215 1216 if (!hybrid_max_perf_cpu) 1217 goto unlock; 1218 1219 /* 1220 * The maximum performance of the CPU may have changed, but assume 1221 * that the performance of the other CPUs has not changed. 1222 */ 1223 max_cap_perf = hybrid_max_perf_cpu->capacity_perf; 1224 1225 intel_pstate_get_hwp_cap(cpu); 1226 1227 hybrid_get_capacity_perf(cpu); 1228 /* Should hybrid_max_perf_cpu be replaced by this CPU? */ 1229 if (cpu->capacity_perf > max_cap_perf) { 1230 hybrid_max_perf_cpu = cpu; 1231 hybrid_set_capacity_of_cpus(); 1232 goto unlock; 1233 } 1234 1235 /* If this CPU is hybrid_max_perf_cpu, should it be replaced? */ 1236 if (cpu == hybrid_max_perf_cpu && cpu->capacity_perf < max_cap_perf) { 1237 hybrid_update_cpu_capacity_scaling(); 1238 goto unlock; 1239 } 1240 1241 hybrid_set_cpu_capacity(cpu); 1242 /* 1243 * If the CPU was offline to start with and it is going online for the 1244 * first time, a perf domain needs to be registered for it if hybrid 1245 * capacity scaling has been enabled already. In that case, sched 1246 * domains need to be rebuilt to take the new perf domain into account. 1247 */ 1248 if (hybrid_register_perf_domain(cpu->cpu)) 1249 em_rebuild_sched_domains(); 1250 1251 unlock: 1252 mutex_unlock(&hybrid_capacity_lock); 1253 } 1254 1255 static void intel_pstate_hwp_set(unsigned int cpu) 1256 { 1257 struct cpudata *cpu_data = all_cpu_data[cpu]; 1258 int max, min; 1259 u64 value; 1260 s16 epp; 1261 1262 max = cpu_data->max_perf_ratio; 1263 min = cpu_data->min_perf_ratio; 1264 1265 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) 1266 min = max; 1267 1268 rdmsrq_on_cpu(cpu, MSR_HWP_REQUEST, &value); 1269 1270 value &= ~HWP_MIN_PERF(~0L); 1271 value |= HWP_MIN_PERF(min); 1272 1273 value &= ~HWP_MAX_PERF(~0L); 1274 value |= HWP_MAX_PERF(max); 1275 1276 if (cpu_data->epp_policy == cpu_data->policy) 1277 goto skip_epp; 1278 1279 cpu_data->epp_policy = cpu_data->policy; 1280 1281 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) { 1282 epp = intel_pstate_get_epp(cpu_data, value); 1283 cpu_data->epp_powersave = epp; 1284 /* If EPP read was failed, then don't try to write */ 1285 if (epp < 0) 1286 goto skip_epp; 1287 1288 epp = 0; 1289 } else { 1290 /* skip setting EPP, when saved value is invalid */ 1291 if (cpu_data->epp_powersave < 0) 1292 goto skip_epp; 1293 1294 /* 1295 * No need to restore EPP when it is not zero. This 1296 * means: 1297 * - Policy is not changed 1298 * - user has manually changed 1299 * - Error reading EPB 1300 */ 1301 epp = intel_pstate_get_epp(cpu_data, value); 1302 if (epp) 1303 goto skip_epp; 1304 1305 epp = cpu_data->epp_powersave; 1306 } 1307 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 1308 value &= ~GENMASK_ULL(31, 24); 1309 value |= (u64)epp << 24; 1310 } 1311 1312 skip_epp: 1313 WRITE_ONCE(cpu_data->hwp_req_cached, value); 1314 wrmsrq_on_cpu(cpu, MSR_HWP_REQUEST, value); 1315 } 1316 1317 static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata); 1318 1319 static void intel_pstate_hwp_offline(struct cpudata *cpu) 1320 { 1321 u64 value = READ_ONCE(cpu->hwp_req_cached); 1322 int min_perf; 1323 1324 intel_pstate_disable_hwp_interrupt(cpu); 1325 1326 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 1327 /* 1328 * In case the EPP has been set to "performance" by the 1329 * active mode "performance" scaling algorithm, replace that 1330 * temporary value with the cached EPP one. 1331 */ 1332 value &= ~GENMASK_ULL(31, 24); 1333 value |= HWP_ENERGY_PERF_PREFERENCE(cpu->epp_cached); 1334 /* 1335 * However, make sure that EPP will be set to "performance" when 1336 * the CPU is brought back online again and the "performance" 1337 * scaling algorithm is still in effect. 1338 */ 1339 cpu->epp_policy = CPUFREQ_POLICY_UNKNOWN; 1340 } 1341 1342 /* 1343 * Clear the desired perf field in the cached HWP request value to 1344 * prevent nonzero desired values from being leaked into the active 1345 * mode. 1346 */ 1347 value &= ~HWP_DESIRED_PERF(~0L); 1348 WRITE_ONCE(cpu->hwp_req_cached, value); 1349 1350 value &= ~GENMASK_ULL(31, 0); 1351 min_perf = HWP_LOWEST_PERF(READ_ONCE(cpu->hwp_cap_cached)); 1352 1353 /* Set hwp_max = hwp_min */ 1354 value |= HWP_MAX_PERF(min_perf); 1355 value |= HWP_MIN_PERF(min_perf); 1356 1357 /* Set EPP to min */ 1358 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) 1359 value |= HWP_ENERGY_PERF_PREFERENCE(HWP_EPP_POWERSAVE); 1360 1361 wrmsrq_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 1362 1363 mutex_lock(&hybrid_capacity_lock); 1364 1365 if (!hybrid_max_perf_cpu) { 1366 mutex_unlock(&hybrid_capacity_lock); 1367 1368 return; 1369 } 1370 1371 if (hybrid_max_perf_cpu == cpu) 1372 hybrid_update_cpu_capacity_scaling(); 1373 1374 mutex_unlock(&hybrid_capacity_lock); 1375 1376 /* Reset the capacity of the CPU going offline to the initial value. */ 1377 hybrid_clear_cpu_capacity(cpu->cpu); 1378 } 1379 1380 #define POWER_CTL_EE_ENABLE 1 1381 #define POWER_CTL_EE_DISABLE 2 1382 1383 /* Enable bit for Dynamic Efficiency Control (DEC) */ 1384 #define POWER_CTL_DEC_ENABLE 27 1385 1386 static int power_ctl_ee_state; 1387 1388 static void set_power_ctl_ee_state(bool input) 1389 { 1390 u64 power_ctl; 1391 1392 guard(mutex)(&intel_pstate_driver_lock); 1393 1394 rdmsrq(MSR_IA32_POWER_CTL, power_ctl); 1395 if (input) { 1396 power_ctl &= ~BIT(MSR_IA32_POWER_CTL_BIT_EE); 1397 power_ctl_ee_state = POWER_CTL_EE_ENABLE; 1398 } else { 1399 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE); 1400 power_ctl_ee_state = POWER_CTL_EE_DISABLE; 1401 } 1402 wrmsrq(MSR_IA32_POWER_CTL, power_ctl); 1403 } 1404 1405 static void intel_pstate_hwp_enable(struct cpudata *cpudata); 1406 1407 static void intel_pstate_hwp_reenable(struct cpudata *cpu) 1408 { 1409 intel_pstate_hwp_enable(cpu); 1410 wrmsrq_on_cpu(cpu->cpu, MSR_HWP_REQUEST, READ_ONCE(cpu->hwp_req_cached)); 1411 } 1412 1413 static int intel_pstate_suspend(struct cpufreq_policy *policy) 1414 { 1415 struct cpudata *cpu = all_cpu_data[policy->cpu]; 1416 1417 pr_debug("CPU %d suspending\n", cpu->cpu); 1418 1419 cpu->suspended = true; 1420 1421 /* disable HWP interrupt and cancel any pending work */ 1422 intel_pstate_disable_hwp_interrupt(cpu); 1423 1424 return 0; 1425 } 1426 1427 static int intel_pstate_resume(struct cpufreq_policy *policy) 1428 { 1429 struct cpudata *cpu = all_cpu_data[policy->cpu]; 1430 1431 pr_debug("CPU %d resuming\n", cpu->cpu); 1432 1433 /* Only restore if the system default is changed */ 1434 if (power_ctl_ee_state == POWER_CTL_EE_ENABLE) 1435 set_power_ctl_ee_state(true); 1436 else if (power_ctl_ee_state == POWER_CTL_EE_DISABLE) 1437 set_power_ctl_ee_state(false); 1438 1439 if (cpu->suspended && hwp_active) { 1440 mutex_lock(&intel_pstate_limits_lock); 1441 1442 /* Re-enable HWP, because "online" has not done that. */ 1443 intel_pstate_hwp_reenable(cpu); 1444 1445 mutex_unlock(&intel_pstate_limits_lock); 1446 } 1447 1448 cpu->suspended = false; 1449 1450 return 0; 1451 } 1452 1453 static void intel_pstate_update_policies(void) 1454 { 1455 int cpu; 1456 1457 for_each_possible_cpu(cpu) 1458 cpufreq_update_policy(cpu); 1459 } 1460 1461 static void __intel_pstate_update_max_freq(struct cpufreq_policy *policy, 1462 struct cpudata *cpudata) 1463 { 1464 guard(cpufreq_policy_write)(policy); 1465 1466 if (hwp_active) 1467 intel_pstate_get_hwp_cap(cpudata); 1468 1469 policy->cpuinfo.max_freq = READ_ONCE(global.no_turbo) ? 1470 cpudata->pstate.max_freq : cpudata->pstate.turbo_freq; 1471 1472 refresh_frequency_limits(policy); 1473 } 1474 1475 static bool intel_pstate_update_max_freq(int cpu) 1476 { 1477 struct cpufreq_policy *policy __free(put_cpufreq_policy) = cpufreq_cpu_get(cpu); 1478 if (!policy) 1479 return false; 1480 1481 __intel_pstate_update_max_freq(policy, all_cpu_data[cpu]); 1482 1483 return true; 1484 } 1485 1486 static void intel_pstate_update_limits(struct cpufreq_policy *policy) 1487 { 1488 struct cpudata *cpudata = all_cpu_data[policy->cpu]; 1489 1490 __intel_pstate_update_max_freq(policy, cpudata); 1491 1492 hybrid_update_capacity(cpudata); 1493 } 1494 1495 static void intel_pstate_update_limits_for_all(void) 1496 { 1497 int cpu; 1498 1499 for_each_possible_cpu(cpu) 1500 intel_pstate_update_max_freq(cpu); 1501 1502 mutex_lock(&hybrid_capacity_lock); 1503 1504 if (hybrid_max_perf_cpu) 1505 __hybrid_refresh_cpu_capacity_scaling(); 1506 1507 mutex_unlock(&hybrid_capacity_lock); 1508 } 1509 1510 /************************** sysfs begin ************************/ 1511 #define show_one(file_name, object) \ 1512 static ssize_t show_##file_name \ 1513 (struct kobject *kobj, struct kobj_attribute *attr, char *buf) \ 1514 { \ 1515 return sprintf(buf, "%u\n", global.object); \ 1516 } 1517 1518 static ssize_t intel_pstate_show_status(char *buf); 1519 static int intel_pstate_update_status(const char *buf, size_t size); 1520 1521 static ssize_t show_status(struct kobject *kobj, 1522 struct kobj_attribute *attr, char *buf) 1523 { 1524 guard(mutex)(&intel_pstate_driver_lock); 1525 1526 return intel_pstate_show_status(buf); 1527 } 1528 1529 static ssize_t store_status(struct kobject *a, struct kobj_attribute *b, 1530 const char *buf, size_t count) 1531 { 1532 char *p = memchr(buf, '\n', count); 1533 int ret; 1534 1535 guard(mutex)(&intel_pstate_driver_lock); 1536 1537 ret = intel_pstate_update_status(buf, p ? p - buf : count); 1538 if (ret < 0) 1539 return ret; 1540 1541 return count; 1542 } 1543 1544 static ssize_t show_turbo_pct(struct kobject *kobj, 1545 struct kobj_attribute *attr, char *buf) 1546 { 1547 struct cpudata *cpu; 1548 int total, no_turbo, turbo_pct; 1549 uint32_t turbo_fp; 1550 1551 guard(mutex)(&intel_pstate_driver_lock); 1552 1553 if (!intel_pstate_driver) 1554 return -EAGAIN; 1555 1556 cpu = all_cpu_data[0]; 1557 1558 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; 1559 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1; 1560 turbo_fp = div_fp(no_turbo, total); 1561 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100))); 1562 1563 return sprintf(buf, "%u\n", turbo_pct); 1564 } 1565 1566 static ssize_t show_num_pstates(struct kobject *kobj, 1567 struct kobj_attribute *attr, char *buf) 1568 { 1569 struct cpudata *cpu; 1570 int total; 1571 1572 guard(mutex)(&intel_pstate_driver_lock); 1573 1574 if (!intel_pstate_driver) 1575 return -EAGAIN; 1576 1577 cpu = all_cpu_data[0]; 1578 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; 1579 1580 return sprintf(buf, "%u\n", total); 1581 } 1582 1583 static ssize_t show_no_turbo(struct kobject *kobj, 1584 struct kobj_attribute *attr, char *buf) 1585 { 1586 guard(mutex)(&intel_pstate_driver_lock); 1587 1588 if (!intel_pstate_driver) 1589 return -EAGAIN; 1590 1591 return sprintf(buf, "%u\n", global.no_turbo); 1592 } 1593 1594 static ssize_t store_no_turbo(struct kobject *a, struct kobj_attribute *b, 1595 const char *buf, size_t count) 1596 { 1597 unsigned int input; 1598 bool no_turbo; 1599 1600 if (sscanf(buf, "%u", &input) != 1) 1601 return -EINVAL; 1602 1603 guard(mutex)(&intel_pstate_driver_lock); 1604 1605 if (!intel_pstate_driver) 1606 return -EAGAIN; 1607 1608 no_turbo = !!clamp_t(int, input, 0, 1); 1609 1610 WRITE_ONCE(global.turbo_disabled, turbo_is_disabled()); 1611 if (global.turbo_disabled && !no_turbo) { 1612 pr_notice("Turbo disabled by BIOS or unavailable on processor\n"); 1613 if (global.no_turbo) 1614 return -EPERM; 1615 1616 no_turbo = 1; 1617 } 1618 1619 if (no_turbo == global.no_turbo) 1620 return count; 1621 1622 WRITE_ONCE(global.no_turbo, no_turbo); 1623 1624 mutex_lock(&intel_pstate_limits_lock); 1625 1626 if (no_turbo) { 1627 struct cpudata *cpu = all_cpu_data[0]; 1628 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate; 1629 1630 /* Squash the global minimum into the permitted range. */ 1631 if (global.min_perf_pct > pct) 1632 global.min_perf_pct = pct; 1633 } 1634 1635 mutex_unlock(&intel_pstate_limits_lock); 1636 1637 intel_pstate_update_limits_for_all(); 1638 arch_set_max_freq_ratio(no_turbo); 1639 1640 return count; 1641 } 1642 1643 static void update_cpu_qos_request(int cpu, enum freq_qos_req_type type) 1644 { 1645 struct cpudata *cpudata = all_cpu_data[cpu]; 1646 struct freq_qos_request *req; 1647 unsigned int freq; 1648 1649 struct cpufreq_policy *policy __free(put_cpufreq_policy) = cpufreq_cpu_get(cpu); 1650 if (!policy) 1651 return; 1652 1653 req = policy->driver_data; 1654 if (!req) 1655 return; 1656 1657 if (hwp_active) 1658 intel_pstate_get_hwp_cap(cpudata); 1659 1660 freq = cpudata->pstate.turbo_freq; 1661 1662 if (type == FREQ_QOS_MIN) { 1663 freq = DIV_ROUND_UP(freq * global.min_perf_pct, 100); 1664 } else { 1665 req++; 1666 freq = (freq * global.max_perf_pct) / 100; 1667 } 1668 1669 if (freq_qos_update_request(req, freq) < 0) 1670 pr_warn("Failed to update freq constraint: CPU%d\n", cpu); 1671 } 1672 1673 static void update_qos_requests(enum freq_qos_req_type type) 1674 { 1675 int i; 1676 1677 for_each_possible_cpu(i) 1678 update_cpu_qos_request(i, type); 1679 } 1680 1681 static ssize_t store_max_perf_pct(struct kobject *a, struct kobj_attribute *b, 1682 const char *buf, size_t count) 1683 { 1684 unsigned int input; 1685 int ret; 1686 1687 ret = sscanf(buf, "%u", &input); 1688 if (ret != 1) 1689 return -EINVAL; 1690 1691 guard(mutex)(&intel_pstate_driver_lock); 1692 1693 if (!intel_pstate_driver) 1694 return -EAGAIN; 1695 1696 mutex_lock(&intel_pstate_limits_lock); 1697 1698 global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100); 1699 1700 mutex_unlock(&intel_pstate_limits_lock); 1701 1702 if (intel_pstate_driver == &intel_pstate) 1703 intel_pstate_update_policies(); 1704 else 1705 update_qos_requests(FREQ_QOS_MAX); 1706 1707 return count; 1708 } 1709 1710 static ssize_t store_min_perf_pct(struct kobject *a, struct kobj_attribute *b, 1711 const char *buf, size_t count) 1712 { 1713 unsigned int input; 1714 int ret; 1715 1716 ret = sscanf(buf, "%u", &input); 1717 if (ret != 1) 1718 return -EINVAL; 1719 1720 guard(mutex)(&intel_pstate_driver_lock); 1721 1722 if (!intel_pstate_driver) 1723 return -EAGAIN; 1724 1725 mutex_lock(&intel_pstate_limits_lock); 1726 1727 global.min_perf_pct = clamp_t(int, input, 1728 min_perf_pct_min(), global.max_perf_pct); 1729 1730 mutex_unlock(&intel_pstate_limits_lock); 1731 1732 if (intel_pstate_driver == &intel_pstate) 1733 intel_pstate_update_policies(); 1734 else 1735 update_qos_requests(FREQ_QOS_MIN); 1736 1737 return count; 1738 } 1739 1740 static ssize_t show_hwp_dynamic_boost(struct kobject *kobj, 1741 struct kobj_attribute *attr, char *buf) 1742 { 1743 return sprintf(buf, "%u\n", hwp_boost); 1744 } 1745 1746 static ssize_t store_hwp_dynamic_boost(struct kobject *a, 1747 struct kobj_attribute *b, 1748 const char *buf, size_t count) 1749 { 1750 unsigned int input; 1751 int ret; 1752 1753 ret = kstrtouint(buf, 10, &input); 1754 if (ret) 1755 return ret; 1756 1757 guard(mutex)(&intel_pstate_driver_lock); 1758 1759 hwp_boost = !!input; 1760 intel_pstate_update_policies(); 1761 1762 return count; 1763 } 1764 1765 static ssize_t show_energy_efficiency(struct kobject *kobj, struct kobj_attribute *attr, 1766 char *buf) 1767 { 1768 u64 power_ctl; 1769 int enable; 1770 1771 rdmsrq(MSR_IA32_POWER_CTL, power_ctl); 1772 enable = !!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE)); 1773 return sprintf(buf, "%d\n", !enable); 1774 } 1775 1776 static ssize_t store_energy_efficiency(struct kobject *a, struct kobj_attribute *b, 1777 const char *buf, size_t count) 1778 { 1779 bool input; 1780 int ret; 1781 1782 ret = kstrtobool(buf, &input); 1783 if (ret) 1784 return ret; 1785 1786 set_power_ctl_ee_state(input); 1787 1788 return count; 1789 } 1790 1791 show_one(max_perf_pct, max_perf_pct); 1792 show_one(min_perf_pct, min_perf_pct); 1793 1794 define_one_global_rw(status); 1795 define_one_global_rw(no_turbo); 1796 define_one_global_rw(max_perf_pct); 1797 define_one_global_rw(min_perf_pct); 1798 define_one_global_ro(turbo_pct); 1799 define_one_global_ro(num_pstates); 1800 define_one_global_rw(hwp_dynamic_boost); 1801 define_one_global_rw(energy_efficiency); 1802 1803 static struct attribute *intel_pstate_attributes[] = { 1804 &status.attr, 1805 &no_turbo.attr, 1806 NULL 1807 }; 1808 1809 static const struct attribute_group intel_pstate_attr_group = { 1810 .attrs = intel_pstate_attributes, 1811 }; 1812 1813 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[]; 1814 1815 static struct kobject *intel_pstate_kobject; 1816 1817 static void __init intel_pstate_sysfs_expose_params(void) 1818 { 1819 struct device *dev_root = bus_get_dev_root(&cpu_subsys); 1820 int rc; 1821 1822 if (dev_root) { 1823 intel_pstate_kobject = kobject_create_and_add("intel_pstate", &dev_root->kobj); 1824 put_device(dev_root); 1825 } 1826 if (WARN_ON(!intel_pstate_kobject)) 1827 return; 1828 1829 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group); 1830 if (WARN_ON(rc)) 1831 return; 1832 1833 if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) { 1834 rc = sysfs_create_file(intel_pstate_kobject, &turbo_pct.attr); 1835 WARN_ON(rc); 1836 1837 rc = sysfs_create_file(intel_pstate_kobject, &num_pstates.attr); 1838 WARN_ON(rc); 1839 } 1840 1841 /* 1842 * If per cpu limits are enforced there are no global limits, so 1843 * return without creating max/min_perf_pct attributes 1844 */ 1845 if (per_cpu_limits) 1846 return; 1847 1848 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr); 1849 WARN_ON(rc); 1850 1851 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr); 1852 WARN_ON(rc); 1853 1854 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids)) { 1855 rc = sysfs_create_file(intel_pstate_kobject, &energy_efficiency.attr); 1856 WARN_ON(rc); 1857 } 1858 } 1859 1860 static void __init intel_pstate_sysfs_remove(void) 1861 { 1862 if (!intel_pstate_kobject) 1863 return; 1864 1865 sysfs_remove_group(intel_pstate_kobject, &intel_pstate_attr_group); 1866 1867 if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) { 1868 sysfs_remove_file(intel_pstate_kobject, &num_pstates.attr); 1869 sysfs_remove_file(intel_pstate_kobject, &turbo_pct.attr); 1870 } 1871 1872 if (!per_cpu_limits) { 1873 sysfs_remove_file(intel_pstate_kobject, &max_perf_pct.attr); 1874 sysfs_remove_file(intel_pstate_kobject, &min_perf_pct.attr); 1875 1876 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids)) 1877 sysfs_remove_file(intel_pstate_kobject, &energy_efficiency.attr); 1878 } 1879 1880 kobject_put(intel_pstate_kobject); 1881 } 1882 1883 static void intel_pstate_sysfs_expose_hwp_dynamic_boost(void) 1884 { 1885 int rc; 1886 1887 if (!hwp_active) 1888 return; 1889 1890 rc = sysfs_create_file(intel_pstate_kobject, &hwp_dynamic_boost.attr); 1891 WARN_ON_ONCE(rc); 1892 } 1893 1894 static void intel_pstate_sysfs_hide_hwp_dynamic_boost(void) 1895 { 1896 if (!hwp_active) 1897 return; 1898 1899 sysfs_remove_file(intel_pstate_kobject, &hwp_dynamic_boost.attr); 1900 } 1901 1902 /************************** sysfs end ************************/ 1903 1904 static void intel_pstate_notify_work(struct work_struct *work) 1905 { 1906 struct cpudata *cpudata = 1907 container_of(to_delayed_work(work), struct cpudata, hwp_notify_work); 1908 1909 if (intel_pstate_update_max_freq(cpudata->cpu)) { 1910 /* 1911 * The driver will not be unregistered while this function is 1912 * running, so update the capacity without acquiring the driver 1913 * lock. 1914 */ 1915 hybrid_update_capacity(cpudata); 1916 } 1917 1918 wrmsrq_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0); 1919 } 1920 1921 static DEFINE_RAW_SPINLOCK(hwp_notify_lock); 1922 static cpumask_t hwp_intr_enable_mask; 1923 1924 #define HWP_GUARANTEED_PERF_CHANGE_STATUS BIT(0) 1925 #define HWP_HIGHEST_PERF_CHANGE_STATUS BIT(3) 1926 1927 void notify_hwp_interrupt(void) 1928 { 1929 unsigned int this_cpu = smp_processor_id(); 1930 u64 value, status_mask; 1931 unsigned long flags; 1932 1933 if (!hwp_active || !cpu_feature_enabled(X86_FEATURE_HWP_NOTIFY)) 1934 return; 1935 1936 status_mask = HWP_GUARANTEED_PERF_CHANGE_STATUS; 1937 if (cpu_feature_enabled(X86_FEATURE_HWP_HIGHEST_PERF_CHANGE)) 1938 status_mask |= HWP_HIGHEST_PERF_CHANGE_STATUS; 1939 1940 rdmsrq_safe(MSR_HWP_STATUS, &value); 1941 if (!(value & status_mask)) 1942 return; 1943 1944 raw_spin_lock_irqsave(&hwp_notify_lock, flags); 1945 1946 if (!cpumask_test_cpu(this_cpu, &hwp_intr_enable_mask)) 1947 goto ack_intr; 1948 1949 schedule_delayed_work(&all_cpu_data[this_cpu]->hwp_notify_work, 1950 msecs_to_jiffies(10)); 1951 1952 raw_spin_unlock_irqrestore(&hwp_notify_lock, flags); 1953 1954 return; 1955 1956 ack_intr: 1957 wrmsrq_safe(MSR_HWP_STATUS, 0); 1958 raw_spin_unlock_irqrestore(&hwp_notify_lock, flags); 1959 } 1960 1961 static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata) 1962 { 1963 bool cancel_work; 1964 1965 if (!cpu_feature_enabled(X86_FEATURE_HWP_NOTIFY)) 1966 return; 1967 1968 /* wrmsrq_on_cpu has to be outside spinlock as this can result in IPC */ 1969 wrmsrq_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00); 1970 1971 raw_spin_lock_irq(&hwp_notify_lock); 1972 cancel_work = cpumask_test_and_clear_cpu(cpudata->cpu, &hwp_intr_enable_mask); 1973 raw_spin_unlock_irq(&hwp_notify_lock); 1974 1975 if (cancel_work) 1976 cancel_delayed_work_sync(&cpudata->hwp_notify_work); 1977 } 1978 1979 #define HWP_GUARANTEED_PERF_CHANGE_REQ BIT(0) 1980 #define HWP_HIGHEST_PERF_CHANGE_REQ BIT(2) 1981 1982 static void intel_pstate_enable_hwp_interrupt(struct cpudata *cpudata) 1983 { 1984 /* Enable HWP notification interrupt for performance change */ 1985 if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) { 1986 u64 interrupt_mask = HWP_GUARANTEED_PERF_CHANGE_REQ; 1987 1988 raw_spin_lock_irq(&hwp_notify_lock); 1989 INIT_DELAYED_WORK(&cpudata->hwp_notify_work, intel_pstate_notify_work); 1990 cpumask_set_cpu(cpudata->cpu, &hwp_intr_enable_mask); 1991 raw_spin_unlock_irq(&hwp_notify_lock); 1992 1993 if (cpu_feature_enabled(X86_FEATURE_HWP_HIGHEST_PERF_CHANGE)) 1994 interrupt_mask |= HWP_HIGHEST_PERF_CHANGE_REQ; 1995 1996 /* wrmsrq_on_cpu has to be outside spinlock as this can result in IPC */ 1997 wrmsrq_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, interrupt_mask); 1998 wrmsrq_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0); 1999 } 2000 } 2001 2002 static void intel_pstate_update_epp_defaults(struct cpudata *cpudata) 2003 { 2004 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0); 2005 2006 /* 2007 * If the EPP is set by firmware, which means that firmware enabled HWP 2008 * - Is equal or less than 0x80 (default balance_perf EPP) 2009 * - But less performance oriented than performance EPP 2010 * then use this as new balance_perf EPP. 2011 */ 2012 if (hwp_forced && cpudata->epp_default <= HWP_EPP_BALANCE_PERFORMANCE && 2013 cpudata->epp_default > HWP_EPP_PERFORMANCE) { 2014 epp_values[EPP_INDEX_BALANCE_PERFORMANCE] = cpudata->epp_default; 2015 return; 2016 } 2017 2018 /* 2019 * If this CPU gen doesn't call for change in balance_perf 2020 * EPP return. 2021 */ 2022 if (epp_values[EPP_INDEX_BALANCE_PERFORMANCE] == HWP_EPP_BALANCE_PERFORMANCE) 2023 return; 2024 2025 /* 2026 * Use hard coded value per gen to update the balance_perf 2027 * and default EPP. 2028 */ 2029 cpudata->epp_default = epp_values[EPP_INDEX_BALANCE_PERFORMANCE]; 2030 intel_pstate_set_epp(cpudata, cpudata->epp_default); 2031 } 2032 2033 static void intel_pstate_hwp_enable(struct cpudata *cpudata) 2034 { 2035 /* First disable HWP notification interrupt till we activate again */ 2036 if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) 2037 wrmsrq_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00); 2038 2039 wrmsrq_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1); 2040 2041 intel_pstate_enable_hwp_interrupt(cpudata); 2042 2043 if (cpudata->epp_default >= 0) 2044 return; 2045 2046 intel_pstate_update_epp_defaults(cpudata); 2047 } 2048 2049 static u64 get_perf_ctl_val(int pstate) 2050 { 2051 u64 val; 2052 2053 val = (u64)pstate << 8; 2054 if (READ_ONCE(global.no_turbo) && !READ_ONCE(global.turbo_disabled) && 2055 cpu_feature_enabled(X86_FEATURE_IDA)) 2056 val |= (u64)1 << 32; 2057 2058 return val; 2059 } 2060 2061 static int atom_get_min_pstate(int not_used) 2062 { 2063 u64 value; 2064 2065 rdmsrq(MSR_ATOM_CORE_RATIOS, value); 2066 return (value >> 8) & 0x7F; 2067 } 2068 2069 static int atom_get_max_pstate(int not_used) 2070 { 2071 u64 value; 2072 2073 rdmsrq(MSR_ATOM_CORE_RATIOS, value); 2074 return (value >> 16) & 0x7F; 2075 } 2076 2077 static int atom_get_turbo_pstate(int not_used) 2078 { 2079 u64 value; 2080 2081 rdmsrq(MSR_ATOM_CORE_TURBO_RATIOS, value); 2082 return value & 0x7F; 2083 } 2084 2085 static u64 atom_get_val(struct cpudata *cpudata, int pstate) 2086 { 2087 u64 val = get_perf_ctl_val(pstate); 2088 int32_t vid_fp; 2089 u32 vid; 2090 2091 vid_fp = cpudata->vid.min + mul_fp( 2092 int_tofp(pstate - cpudata->pstate.min_pstate), 2093 cpudata->vid.ratio); 2094 2095 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max); 2096 vid = ceiling_fp(vid_fp); 2097 2098 if (pstate > cpudata->pstate.max_pstate) 2099 vid = cpudata->vid.turbo; 2100 2101 return val | vid; 2102 } 2103 2104 static int silvermont_get_scaling(void) 2105 { 2106 u64 value; 2107 int i; 2108 /* Defined in Table 35-6 from SDM (Sept 2015) */ 2109 static int silvermont_freq_table[] = { 2110 83300, 100000, 133300, 116700, 80000}; 2111 2112 rdmsrq(MSR_FSB_FREQ, value); 2113 i = value & 0x7; 2114 WARN_ON(i > 4); 2115 2116 return silvermont_freq_table[i]; 2117 } 2118 2119 static int airmont_get_scaling(void) 2120 { 2121 u64 value; 2122 int i; 2123 /* Defined in Table 35-10 from SDM (Sept 2015) */ 2124 static int airmont_freq_table[] = { 2125 83300, 100000, 133300, 116700, 80000, 2126 93300, 90000, 88900, 87500}; 2127 2128 rdmsrq(MSR_FSB_FREQ, value); 2129 i = value & 0xF; 2130 WARN_ON(i > 8); 2131 2132 return airmont_freq_table[i]; 2133 } 2134 2135 static void atom_get_vid(struct cpudata *cpudata) 2136 { 2137 u64 value; 2138 2139 rdmsrq(MSR_ATOM_CORE_VIDS, value); 2140 cpudata->vid.min = int_tofp((value >> 8) & 0x7f); 2141 cpudata->vid.max = int_tofp((value >> 16) & 0x7f); 2142 cpudata->vid.ratio = div_fp( 2143 cpudata->vid.max - cpudata->vid.min, 2144 int_tofp(cpudata->pstate.max_pstate - 2145 cpudata->pstate.min_pstate)); 2146 2147 rdmsrq(MSR_ATOM_CORE_TURBO_VIDS, value); 2148 cpudata->vid.turbo = value & 0x7f; 2149 } 2150 2151 static int core_get_min_pstate(int cpu) 2152 { 2153 u64 value; 2154 2155 rdmsrq_on_cpu(cpu, MSR_PLATFORM_INFO, &value); 2156 return (value >> 40) & 0xFF; 2157 } 2158 2159 static int core_get_max_pstate_physical(int cpu) 2160 { 2161 u64 value; 2162 2163 rdmsrq_on_cpu(cpu, MSR_PLATFORM_INFO, &value); 2164 return (value >> 8) & 0xFF; 2165 } 2166 2167 static int core_get_tdp_ratio(int cpu, u64 plat_info) 2168 { 2169 /* Check how many TDP levels present */ 2170 if (plat_info & 0x600000000) { 2171 u64 tdp_ctrl; 2172 u64 tdp_ratio; 2173 int tdp_msr; 2174 int err; 2175 2176 /* Get the TDP level (0, 1, 2) to get ratios */ 2177 err = rdmsrq_safe_on_cpu(cpu, MSR_CONFIG_TDP_CONTROL, &tdp_ctrl); 2178 if (err) 2179 return err; 2180 2181 /* TDP MSR are continuous starting at 0x648 */ 2182 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03); 2183 err = rdmsrq_safe_on_cpu(cpu, tdp_msr, &tdp_ratio); 2184 if (err) 2185 return err; 2186 2187 /* For level 1 and 2, bits[23:16] contain the ratio */ 2188 if (tdp_ctrl & 0x03) 2189 tdp_ratio >>= 16; 2190 2191 tdp_ratio &= 0xff; /* ratios are only 8 bits long */ 2192 pr_debug("tdp_ratio %x\n", (int)tdp_ratio); 2193 2194 return (int)tdp_ratio; 2195 } 2196 2197 return -ENXIO; 2198 } 2199 2200 static int core_get_max_pstate(int cpu) 2201 { 2202 u64 tar; 2203 u64 plat_info; 2204 int max_pstate; 2205 int tdp_ratio; 2206 int err; 2207 2208 rdmsrq_on_cpu(cpu, MSR_PLATFORM_INFO, &plat_info); 2209 max_pstate = (plat_info >> 8) & 0xFF; 2210 2211 tdp_ratio = core_get_tdp_ratio(cpu, plat_info); 2212 if (tdp_ratio <= 0) 2213 return max_pstate; 2214 2215 if (hwp_active) { 2216 /* Turbo activation ratio is not used on HWP platforms */ 2217 return tdp_ratio; 2218 } 2219 2220 err = rdmsrq_safe_on_cpu(cpu, MSR_TURBO_ACTIVATION_RATIO, &tar); 2221 if (!err) { 2222 int tar_levels; 2223 2224 /* Do some sanity checking for safety */ 2225 tar_levels = tar & 0xff; 2226 if (tdp_ratio - 1 == tar_levels) { 2227 max_pstate = tar_levels; 2228 pr_debug("max_pstate=TAC %x\n", max_pstate); 2229 } 2230 } 2231 2232 return max_pstate; 2233 } 2234 2235 static int core_get_turbo_pstate(int cpu) 2236 { 2237 u64 value; 2238 int nont, ret; 2239 2240 rdmsrq_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value); 2241 nont = core_get_max_pstate(cpu); 2242 ret = (value) & 255; 2243 if (ret <= nont) 2244 ret = nont; 2245 return ret; 2246 } 2247 2248 static u64 core_get_val(struct cpudata *cpudata, int pstate) 2249 { 2250 return get_perf_ctl_val(pstate); 2251 } 2252 2253 static int knl_get_aperf_mperf_shift(void) 2254 { 2255 return 10; 2256 } 2257 2258 static int knl_get_turbo_pstate(int cpu) 2259 { 2260 u64 value; 2261 int nont, ret; 2262 2263 rdmsrq_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value); 2264 nont = core_get_max_pstate(cpu); 2265 ret = (((value) >> 8) & 0xFF); 2266 if (ret <= nont) 2267 ret = nont; 2268 return ret; 2269 } 2270 2271 static int hwp_get_cpu_scaling(int cpu) 2272 { 2273 if (hybrid_scaling_factor) { 2274 /* 2275 * Return the hybrid scaling factor for P-cores and use the 2276 * default core scaling for E-cores. 2277 */ 2278 if (hybrid_get_cpu_type(cpu) != INTEL_CPU_TYPE_ATOM) 2279 return hybrid_scaling_factor; 2280 2281 return core_get_scaling(); 2282 } 2283 2284 /* Use core scaling on non-hybrid systems. */ 2285 if (!cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) 2286 return core_get_scaling(); 2287 2288 /* 2289 * The system is hybrid, but the hybrid scaling factor is not known or 2290 * the CPU type is not one of the above, so use CPPC to compute the 2291 * scaling factor for this CPU. 2292 */ 2293 return intel_pstate_cppc_get_scaling(cpu); 2294 } 2295 2296 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu) 2297 { 2298 int perf_ctl_scaling = pstate_funcs.get_scaling(); 2299 2300 cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical(cpu->cpu); 2301 cpu->pstate.min_pstate = pstate_funcs.get_min(cpu->cpu); 2302 cpu->pstate.min_freq = cpu->pstate.min_pstate * perf_ctl_scaling; 2303 cpu->pstate.perf_ctl_scaling = perf_ctl_scaling; 2304 2305 if (hwp_active) { 2306 __intel_pstate_get_hwp_cap(cpu); 2307 2308 if (pstate_funcs.get_cpu_scaling) { 2309 cpu->pstate.scaling = pstate_funcs.get_cpu_scaling(cpu->cpu); 2310 intel_pstate_hybrid_hwp_adjust(cpu); 2311 } else { 2312 cpu->pstate.scaling = perf_ctl_scaling; 2313 } 2314 /* 2315 * If the CPU is going online for the first time and it was 2316 * offline initially, asym capacity scaling needs to be updated. 2317 */ 2318 hybrid_update_capacity(cpu); 2319 } else { 2320 cpu->pstate.scaling = perf_ctl_scaling; 2321 cpu->pstate.max_pstate = pstate_funcs.get_max(cpu->cpu); 2322 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(cpu->cpu); 2323 } 2324 2325 intel_pstate_update_freq_limits(cpu); 2326 2327 if (pstate_funcs.get_aperf_mperf_shift) 2328 cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift(); 2329 2330 if (pstate_funcs.get_vid) 2331 pstate_funcs.get_vid(cpu); 2332 } 2333 2334 /* 2335 * Long hold time will keep high perf limits for long time, 2336 * which negatively impacts perf/watt for some workloads, 2337 * like specpower. 3ms is based on experiements on some 2338 * workoads. 2339 */ 2340 static int hwp_boost_hold_time_ns = 3 * NSEC_PER_MSEC; 2341 2342 static inline void intel_pstate_hwp_boost_up(struct cpudata *cpu) 2343 { 2344 u64 hwp_req = READ_ONCE(cpu->hwp_req_cached); 2345 u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached); 2346 u32 max_limit = (hwp_req & 0xff00) >> 8; 2347 u32 min_limit = (hwp_req & 0xff); 2348 u32 boost_level1; 2349 2350 /* 2351 * Cases to consider (User changes via sysfs or boot time): 2352 * If, P0 (Turbo max) = P1 (Guaranteed max) = min: 2353 * No boost, return. 2354 * If, P0 (Turbo max) > P1 (Guaranteed max) = min: 2355 * Should result in one level boost only for P0. 2356 * If, P0 (Turbo max) = P1 (Guaranteed max) > min: 2357 * Should result in two level boost: 2358 * (min + p1)/2 and P1. 2359 * If, P0 (Turbo max) > P1 (Guaranteed max) > min: 2360 * Should result in three level boost: 2361 * (min + p1)/2, P1 and P0. 2362 */ 2363 2364 /* If max and min are equal or already at max, nothing to boost */ 2365 if (max_limit == min_limit || cpu->hwp_boost_min >= max_limit) 2366 return; 2367 2368 if (!cpu->hwp_boost_min) 2369 cpu->hwp_boost_min = min_limit; 2370 2371 /* level at half way mark between min and guranteed */ 2372 boost_level1 = (HWP_GUARANTEED_PERF(hwp_cap) + min_limit) >> 1; 2373 2374 if (cpu->hwp_boost_min < boost_level1) 2375 cpu->hwp_boost_min = boost_level1; 2376 else if (cpu->hwp_boost_min < HWP_GUARANTEED_PERF(hwp_cap)) 2377 cpu->hwp_boost_min = HWP_GUARANTEED_PERF(hwp_cap); 2378 else if (cpu->hwp_boost_min == HWP_GUARANTEED_PERF(hwp_cap) && 2379 max_limit != HWP_GUARANTEED_PERF(hwp_cap)) 2380 cpu->hwp_boost_min = max_limit; 2381 else 2382 return; 2383 2384 hwp_req = (hwp_req & ~GENMASK_ULL(7, 0)) | cpu->hwp_boost_min; 2385 wrmsrq(MSR_HWP_REQUEST, hwp_req); 2386 cpu->last_update = cpu->sample.time; 2387 } 2388 2389 static inline void intel_pstate_hwp_boost_down(struct cpudata *cpu) 2390 { 2391 if (cpu->hwp_boost_min) { 2392 bool expired; 2393 2394 /* Check if we are idle for hold time to boost down */ 2395 expired = time_after64(cpu->sample.time, cpu->last_update + 2396 hwp_boost_hold_time_ns); 2397 if (expired) { 2398 wrmsrq(MSR_HWP_REQUEST, cpu->hwp_req_cached); 2399 cpu->hwp_boost_min = 0; 2400 } 2401 } 2402 cpu->last_update = cpu->sample.time; 2403 } 2404 2405 static inline void intel_pstate_update_util_hwp_local(struct cpudata *cpu, 2406 u64 time) 2407 { 2408 cpu->sample.time = time; 2409 2410 if (cpu->sched_flags & SCHED_CPUFREQ_IOWAIT) { 2411 bool do_io = false; 2412 2413 cpu->sched_flags = 0; 2414 /* 2415 * Set iowait_boost flag and update time. Since IO WAIT flag 2416 * is set all the time, we can't just conclude that there is 2417 * some IO bound activity is scheduled on this CPU with just 2418 * one occurrence. If we receive at least two in two 2419 * consecutive ticks, then we treat as boost candidate. 2420 */ 2421 if (time_before64(time, cpu->last_io_update + 2 * TICK_NSEC)) 2422 do_io = true; 2423 2424 cpu->last_io_update = time; 2425 2426 if (do_io) 2427 intel_pstate_hwp_boost_up(cpu); 2428 2429 } else { 2430 intel_pstate_hwp_boost_down(cpu); 2431 } 2432 } 2433 2434 static inline void intel_pstate_update_util_hwp(struct update_util_data *data, 2435 u64 time, unsigned int flags) 2436 { 2437 struct cpudata *cpu = container_of(data, struct cpudata, update_util); 2438 2439 cpu->sched_flags |= flags; 2440 2441 if (smp_processor_id() == cpu->cpu) 2442 intel_pstate_update_util_hwp_local(cpu, time); 2443 } 2444 2445 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu) 2446 { 2447 struct sample *sample = &cpu->sample; 2448 2449 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf); 2450 } 2451 2452 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time) 2453 { 2454 u64 aperf, mperf; 2455 unsigned long flags; 2456 u64 tsc; 2457 2458 local_irq_save(flags); 2459 rdmsrq(MSR_IA32_APERF, aperf); 2460 rdmsrq(MSR_IA32_MPERF, mperf); 2461 tsc = rdtsc(); 2462 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) { 2463 local_irq_restore(flags); 2464 return false; 2465 } 2466 local_irq_restore(flags); 2467 2468 cpu->last_sample_time = cpu->sample.time; 2469 cpu->sample.time = time; 2470 cpu->sample.aperf = aperf; 2471 cpu->sample.mperf = mperf; 2472 cpu->sample.tsc = tsc; 2473 cpu->sample.aperf -= cpu->prev_aperf; 2474 cpu->sample.mperf -= cpu->prev_mperf; 2475 cpu->sample.tsc -= cpu->prev_tsc; 2476 2477 cpu->prev_aperf = aperf; 2478 cpu->prev_mperf = mperf; 2479 cpu->prev_tsc = tsc; 2480 /* 2481 * First time this function is invoked in a given cycle, all of the 2482 * previous sample data fields are equal to zero or stale and they must 2483 * be populated with meaningful numbers for things to work, so assume 2484 * that sample.time will always be reset before setting the utilization 2485 * update hook and make the caller skip the sample then. 2486 */ 2487 if (likely(cpu->last_sample_time)) { 2488 intel_pstate_calc_avg_perf(cpu); 2489 return true; 2490 } 2491 return false; 2492 } 2493 2494 static inline int32_t get_avg_frequency(struct cpudata *cpu) 2495 { 2496 return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz); 2497 } 2498 2499 static inline int32_t get_avg_pstate(struct cpudata *cpu) 2500 { 2501 return mul_ext_fp(cpu->pstate.max_pstate_physical, 2502 cpu->sample.core_avg_perf); 2503 } 2504 2505 static inline int32_t get_target_pstate(struct cpudata *cpu) 2506 { 2507 struct sample *sample = &cpu->sample; 2508 int32_t busy_frac; 2509 int target, avg_pstate; 2510 2511 busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift, 2512 sample->tsc); 2513 2514 if (busy_frac < cpu->iowait_boost) 2515 busy_frac = cpu->iowait_boost; 2516 2517 sample->busy_scaled = busy_frac * 100; 2518 2519 target = READ_ONCE(global.no_turbo) ? 2520 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate; 2521 target += target >> 2; 2522 target = mul_fp(target, busy_frac); 2523 if (target < cpu->pstate.min_pstate) 2524 target = cpu->pstate.min_pstate; 2525 2526 /* 2527 * If the average P-state during the previous cycle was higher than the 2528 * current target, add 50% of the difference to the target to reduce 2529 * possible performance oscillations and offset possible performance 2530 * loss related to moving the workload from one CPU to another within 2531 * a package/module. 2532 */ 2533 avg_pstate = get_avg_pstate(cpu); 2534 if (avg_pstate > target) 2535 target += (avg_pstate - target) >> 1; 2536 2537 return target; 2538 } 2539 2540 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate) 2541 { 2542 int min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio); 2543 int max_pstate = max(min_pstate, cpu->max_perf_ratio); 2544 2545 return clamp_t(int, pstate, min_pstate, max_pstate); 2546 } 2547 2548 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate) 2549 { 2550 if (pstate == cpu->pstate.current_pstate) 2551 return; 2552 2553 cpu->pstate.current_pstate = pstate; 2554 wrmsrq(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate)); 2555 } 2556 2557 static void intel_pstate_adjust_pstate(struct cpudata *cpu) 2558 { 2559 int from = cpu->pstate.current_pstate; 2560 struct sample *sample; 2561 int target_pstate; 2562 2563 target_pstate = get_target_pstate(cpu); 2564 target_pstate = intel_pstate_prepare_request(cpu, target_pstate); 2565 trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu); 2566 intel_pstate_update_pstate(cpu, target_pstate); 2567 2568 sample = &cpu->sample; 2569 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf), 2570 fp_toint(sample->busy_scaled), 2571 from, 2572 cpu->pstate.current_pstate, 2573 sample->mperf, 2574 sample->aperf, 2575 sample->tsc, 2576 get_avg_frequency(cpu), 2577 fp_toint(cpu->iowait_boost * 100)); 2578 } 2579 2580 static void intel_pstate_update_util(struct update_util_data *data, u64 time, 2581 unsigned int flags) 2582 { 2583 struct cpudata *cpu = container_of(data, struct cpudata, update_util); 2584 u64 delta_ns; 2585 2586 /* Don't allow remote callbacks */ 2587 if (smp_processor_id() != cpu->cpu) 2588 return; 2589 2590 delta_ns = time - cpu->last_update; 2591 if (flags & SCHED_CPUFREQ_IOWAIT) { 2592 /* Start over if the CPU may have been idle. */ 2593 if (delta_ns > TICK_NSEC) { 2594 cpu->iowait_boost = ONE_EIGHTH_FP; 2595 } else if (cpu->iowait_boost >= ONE_EIGHTH_FP) { 2596 cpu->iowait_boost <<= 1; 2597 if (cpu->iowait_boost > int_tofp(1)) 2598 cpu->iowait_boost = int_tofp(1); 2599 } else { 2600 cpu->iowait_boost = ONE_EIGHTH_FP; 2601 } 2602 } else if (cpu->iowait_boost) { 2603 /* Clear iowait_boost if the CPU may have been idle. */ 2604 if (delta_ns > TICK_NSEC) 2605 cpu->iowait_boost = 0; 2606 else 2607 cpu->iowait_boost >>= 1; 2608 } 2609 cpu->last_update = time; 2610 delta_ns = time - cpu->sample.time; 2611 if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL) 2612 return; 2613 2614 if (intel_pstate_sample(cpu, time)) 2615 intel_pstate_adjust_pstate(cpu); 2616 } 2617 2618 static struct pstate_funcs core_funcs = { 2619 .get_max = core_get_max_pstate, 2620 .get_max_physical = core_get_max_pstate_physical, 2621 .get_min = core_get_min_pstate, 2622 .get_turbo = core_get_turbo_pstate, 2623 .get_scaling = core_get_scaling, 2624 .get_val = core_get_val, 2625 }; 2626 2627 static const struct pstate_funcs silvermont_funcs = { 2628 .get_max = atom_get_max_pstate, 2629 .get_max_physical = atom_get_max_pstate, 2630 .get_min = atom_get_min_pstate, 2631 .get_turbo = atom_get_turbo_pstate, 2632 .get_val = atom_get_val, 2633 .get_scaling = silvermont_get_scaling, 2634 .get_vid = atom_get_vid, 2635 }; 2636 2637 static const struct pstate_funcs airmont_funcs = { 2638 .get_max = atom_get_max_pstate, 2639 .get_max_physical = atom_get_max_pstate, 2640 .get_min = atom_get_min_pstate, 2641 .get_turbo = atom_get_turbo_pstate, 2642 .get_val = atom_get_val, 2643 .get_scaling = airmont_get_scaling, 2644 .get_vid = atom_get_vid, 2645 }; 2646 2647 static const struct pstate_funcs knl_funcs = { 2648 .get_max = core_get_max_pstate, 2649 .get_max_physical = core_get_max_pstate_physical, 2650 .get_min = core_get_min_pstate, 2651 .get_turbo = knl_get_turbo_pstate, 2652 .get_aperf_mperf_shift = knl_get_aperf_mperf_shift, 2653 .get_scaling = core_get_scaling, 2654 .get_val = core_get_val, 2655 }; 2656 2657 #define X86_MATCH(vfm, policy) \ 2658 X86_MATCH_VFM_FEATURE(vfm, X86_FEATURE_APERFMPERF, &policy) 2659 2660 static const struct x86_cpu_id intel_pstate_cpu_ids[] = { 2661 X86_MATCH(INTEL_SANDYBRIDGE, core_funcs), 2662 X86_MATCH(INTEL_SANDYBRIDGE_X, core_funcs), 2663 X86_MATCH(INTEL_ATOM_SILVERMONT, silvermont_funcs), 2664 X86_MATCH(INTEL_IVYBRIDGE, core_funcs), 2665 X86_MATCH(INTEL_HASWELL, core_funcs), 2666 X86_MATCH(INTEL_BROADWELL, core_funcs), 2667 X86_MATCH(INTEL_IVYBRIDGE_X, core_funcs), 2668 X86_MATCH(INTEL_HASWELL_X, core_funcs), 2669 X86_MATCH(INTEL_HASWELL_L, core_funcs), 2670 X86_MATCH(INTEL_HASWELL_G, core_funcs), 2671 X86_MATCH(INTEL_BROADWELL_G, core_funcs), 2672 X86_MATCH(INTEL_ATOM_AIRMONT, airmont_funcs), 2673 X86_MATCH(INTEL_SKYLAKE_L, core_funcs), 2674 X86_MATCH(INTEL_BROADWELL_X, core_funcs), 2675 X86_MATCH(INTEL_SKYLAKE, core_funcs), 2676 X86_MATCH(INTEL_BROADWELL_D, core_funcs), 2677 X86_MATCH(INTEL_XEON_PHI_KNL, knl_funcs), 2678 X86_MATCH(INTEL_XEON_PHI_KNM, knl_funcs), 2679 X86_MATCH(INTEL_ATOM_GOLDMONT, core_funcs), 2680 X86_MATCH(INTEL_ATOM_GOLDMONT_PLUS, core_funcs), 2681 X86_MATCH(INTEL_SKYLAKE_X, core_funcs), 2682 X86_MATCH(INTEL_COMETLAKE, core_funcs), 2683 X86_MATCH(INTEL_ICELAKE_X, core_funcs), 2684 X86_MATCH(INTEL_TIGERLAKE, core_funcs), 2685 X86_MATCH(INTEL_SAPPHIRERAPIDS_X, core_funcs), 2686 X86_MATCH(INTEL_EMERALDRAPIDS_X, core_funcs), 2687 X86_MATCH(INTEL_GRANITERAPIDS_D, core_funcs), 2688 X86_MATCH(INTEL_GRANITERAPIDS_X, core_funcs), 2689 {} 2690 }; 2691 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids); 2692 2693 #ifdef CONFIG_ACPI 2694 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = { 2695 X86_MATCH(INTEL_BROADWELL_D, core_funcs), 2696 X86_MATCH(INTEL_BROADWELL_X, core_funcs), 2697 X86_MATCH(INTEL_SKYLAKE_X, core_funcs), 2698 X86_MATCH(INTEL_ICELAKE_X, core_funcs), 2699 X86_MATCH(INTEL_SAPPHIRERAPIDS_X, core_funcs), 2700 X86_MATCH(INTEL_EMERALDRAPIDS_X, core_funcs), 2701 X86_MATCH(INTEL_GRANITERAPIDS_D, core_funcs), 2702 X86_MATCH(INTEL_GRANITERAPIDS_X, core_funcs), 2703 X86_MATCH(INTEL_ATOM_CRESTMONT, core_funcs), 2704 X86_MATCH(INTEL_ATOM_CRESTMONT_X, core_funcs), 2705 X86_MATCH(INTEL_ATOM_DARKMONT_X, core_funcs), 2706 X86_MATCH(INTEL_DIAMONDRAPIDS_X, core_funcs), 2707 {} 2708 }; 2709 #endif 2710 2711 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = { 2712 X86_MATCH(INTEL_KABYLAKE, core_funcs), 2713 {} 2714 }; 2715 2716 static int intel_pstate_init_cpu(unsigned int cpunum) 2717 { 2718 struct cpudata *cpu; 2719 2720 cpu = all_cpu_data[cpunum]; 2721 2722 if (!cpu) { 2723 cpu = kzalloc_obj(*cpu); 2724 if (!cpu) 2725 return -ENOMEM; 2726 2727 WRITE_ONCE(all_cpu_data[cpunum], cpu); 2728 2729 cpu->cpu = cpunum; 2730 2731 cpu->epp_default = -EINVAL; 2732 2733 if (hwp_active) { 2734 intel_pstate_hwp_enable(cpu); 2735 2736 if (intel_pstate_acpi_pm_profile_server()) 2737 hwp_boost = true; 2738 } 2739 } else if (hwp_active) { 2740 /* 2741 * Re-enable HWP in case this happens after a resume from ACPI 2742 * S3 if the CPU was offline during the whole system/resume 2743 * cycle. 2744 */ 2745 intel_pstate_hwp_reenable(cpu); 2746 } 2747 2748 cpu->epp_powersave = -EINVAL; 2749 cpu->epp_policy = CPUFREQ_POLICY_UNKNOWN; 2750 2751 intel_pstate_get_cpu_pstates(cpu); 2752 2753 pr_debug("controlling: cpu %d\n", cpunum); 2754 2755 return 0; 2756 } 2757 2758 static void intel_pstate_set_update_util_hook(unsigned int cpu_num) 2759 { 2760 struct cpudata *cpu = all_cpu_data[cpu_num]; 2761 2762 if (hwp_active && !hwp_boost) 2763 return; 2764 2765 if (cpu->update_util_set) 2766 return; 2767 2768 /* Prevent intel_pstate_update_util() from using stale data. */ 2769 cpu->sample.time = 0; 2770 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util, 2771 (hwp_active ? 2772 intel_pstate_update_util_hwp : 2773 intel_pstate_update_util)); 2774 cpu->update_util_set = true; 2775 } 2776 2777 static void intel_pstate_clear_update_util_hook(unsigned int cpu) 2778 { 2779 struct cpudata *cpu_data = all_cpu_data[cpu]; 2780 2781 if (!cpu_data->update_util_set) 2782 return; 2783 2784 cpufreq_remove_update_util_hook(cpu); 2785 cpu_data->update_util_set = false; 2786 synchronize_rcu(); 2787 } 2788 2789 static int intel_pstate_get_max_freq(struct cpudata *cpu) 2790 { 2791 return READ_ONCE(global.no_turbo) ? 2792 cpu->pstate.max_freq : cpu->pstate.turbo_freq; 2793 } 2794 2795 static void intel_pstate_update_perf_limits(struct cpudata *cpu, 2796 unsigned int policy_min, 2797 unsigned int policy_max) 2798 { 2799 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling; 2800 int32_t max_policy_perf, min_policy_perf; 2801 2802 max_policy_perf = policy_max / perf_ctl_scaling; 2803 if (policy_max == policy_min) { 2804 min_policy_perf = max_policy_perf; 2805 } else { 2806 min_policy_perf = policy_min / perf_ctl_scaling; 2807 min_policy_perf = clamp_t(int32_t, min_policy_perf, 2808 0, max_policy_perf); 2809 } 2810 2811 /* 2812 * HWP needs some special consideration, because HWP_REQUEST uses 2813 * abstract values to represent performance rather than pure ratios. 2814 */ 2815 if (hwp_active && cpu->pstate.scaling != perf_ctl_scaling) { 2816 int freq; 2817 2818 freq = max_policy_perf * perf_ctl_scaling; 2819 max_policy_perf = intel_pstate_freq_to_hwp(cpu, freq); 2820 freq = min_policy_perf * perf_ctl_scaling; 2821 min_policy_perf = intel_pstate_freq_to_hwp(cpu, freq); 2822 } 2823 2824 pr_debug("cpu:%d min_policy_perf:%d max_policy_perf:%d\n", 2825 cpu->cpu, min_policy_perf, max_policy_perf); 2826 2827 /* Normalize user input to [min_perf, max_perf] */ 2828 if (per_cpu_limits) { 2829 cpu->min_perf_ratio = min_policy_perf; 2830 cpu->max_perf_ratio = max_policy_perf; 2831 } else { 2832 int turbo_max = cpu->pstate.turbo_pstate; 2833 int32_t global_min, global_max; 2834 2835 /* Global limits are in percent of the maximum turbo P-state. */ 2836 global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100); 2837 global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100); 2838 global_min = clamp_t(int32_t, global_min, 0, global_max); 2839 2840 pr_debug("cpu:%d global_min:%d global_max:%d\n", cpu->cpu, 2841 global_min, global_max); 2842 2843 cpu->min_perf_ratio = max(min_policy_perf, global_min); 2844 cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf); 2845 cpu->max_perf_ratio = min(max_policy_perf, global_max); 2846 cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio); 2847 2848 /* Make sure min_perf <= max_perf */ 2849 cpu->min_perf_ratio = min(cpu->min_perf_ratio, 2850 cpu->max_perf_ratio); 2851 2852 } 2853 pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", cpu->cpu, 2854 cpu->max_perf_ratio, 2855 cpu->min_perf_ratio); 2856 } 2857 2858 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate) 2859 { 2860 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu); 2861 cpu->pstate.current_pstate = pstate; 2862 /* 2863 * Generally, there is no guarantee that this code will always run on 2864 * the CPU being updated, so force the register update to run on the 2865 * right CPU. 2866 */ 2867 wrmsrq_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL, 2868 pstate_funcs.get_val(cpu, pstate)); 2869 } 2870 2871 static int intel_pstate_set_policy(struct cpufreq_policy *policy) 2872 { 2873 unsigned int freq = policy->min; 2874 struct cpudata *cpu; 2875 2876 if (!policy->cpuinfo.max_freq) 2877 return -ENODEV; 2878 2879 pr_debug("set_policy cpuinfo.max %u policy->max %u\n", 2880 policy->cpuinfo.max_freq, policy->max); 2881 2882 cpu = all_cpu_data[policy->cpu]; 2883 cpu->policy = policy->policy; 2884 2885 mutex_lock(&intel_pstate_limits_lock); 2886 2887 intel_pstate_update_perf_limits(cpu, policy->min, policy->max); 2888 2889 if (hwp_active) { 2890 /* 2891 * The active mode only requires an update util hook if HWP 2892 * boost is used and the policy is not "performance". 2893 */ 2894 if (hwp_boost && cpu->policy != CPUFREQ_POLICY_PERFORMANCE) { 2895 intel_pstate_set_update_util_hook(policy->cpu); 2896 } else { 2897 intel_pstate_clear_update_util_hook(policy->cpu); 2898 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) { 2899 freq = cpu->max_perf_ratio * cpu->pstate.scaling; 2900 if (cpu->pstate.scaling != cpu->pstate.perf_ctl_scaling) 2901 freq = rounddown(freq, cpu->pstate.perf_ctl_scaling); 2902 } 2903 } 2904 intel_pstate_hwp_set(policy->cpu); 2905 } else if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) { 2906 int pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio); 2907 2908 /* 2909 * NOHZ_FULL CPUs need this as the governor callback may not 2910 * be invoked on them. 2911 */ 2912 intel_pstate_clear_update_util_hook(policy->cpu); 2913 intel_pstate_set_pstate(cpu, pstate); 2914 freq = pstate * cpu->pstate.scaling; 2915 } else { 2916 intel_pstate_set_update_util_hook(policy->cpu); 2917 } 2918 /* 2919 * policy->cur is never updated in the intel_pstate driver, but it is 2920 * used as a stale frequency value, so set it to reflect the actual 2921 * requested P-state in the "performance" policy case and to the min 2922 * otherwise. 2923 */ 2924 policy->cur = freq; 2925 2926 mutex_unlock(&intel_pstate_limits_lock); 2927 2928 return 0; 2929 } 2930 2931 static void intel_pstate_adjust_policy_max(struct cpudata *cpu, 2932 struct cpufreq_policy_data *policy) 2933 { 2934 if (!hwp_active && 2935 cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate && 2936 policy->max < policy->cpuinfo.max_freq && 2937 policy->max > cpu->pstate.max_freq) { 2938 pr_debug("policy->max > max non turbo frequency\n"); 2939 policy->max = policy->cpuinfo.max_freq; 2940 } 2941 } 2942 2943 static void intel_pstate_verify_cpu_policy(struct cpudata *cpu, 2944 struct cpufreq_policy_data *policy) 2945 { 2946 int max_freq; 2947 2948 if (hwp_active) { 2949 intel_pstate_get_hwp_cap(cpu); 2950 max_freq = READ_ONCE(global.no_turbo) ? 2951 cpu->pstate.max_freq : cpu->pstate.turbo_freq; 2952 } else { 2953 max_freq = intel_pstate_get_max_freq(cpu); 2954 } 2955 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, max_freq); 2956 2957 intel_pstate_adjust_policy_max(cpu, policy); 2958 } 2959 2960 static int intel_pstate_verify_policy(struct cpufreq_policy_data *policy) 2961 { 2962 intel_pstate_verify_cpu_policy(all_cpu_data[policy->cpu], policy); 2963 2964 return 0; 2965 } 2966 2967 static void intel_pstate_set_min_pstate(struct cpudata *cpu) 2968 { 2969 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate); 2970 } 2971 2972 static int intel_cpufreq_cpu_offline(struct cpufreq_policy *policy) 2973 { 2974 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2975 2976 pr_debug("CPU %d going offline\n", cpu->cpu); 2977 2978 if (cpu->suspended) 2979 return 0; 2980 2981 /* 2982 * If the CPU is an SMT thread and it goes offline with the performance 2983 * settings different from the minimum, it will prevent its sibling 2984 * from getting to lower performance levels, so force the minimum 2985 * performance on CPU offline to prevent that from happening. 2986 */ 2987 if (hwp_active) { 2988 intel_pstate_hwp_offline(cpu); 2989 } else { 2990 intel_pstate_set_min_pstate(cpu); 2991 policy->cur = cpu->pstate.min_freq; 2992 } 2993 2994 intel_pstate_exit_perf_limits(policy); 2995 2996 return 0; 2997 } 2998 2999 static int intel_pstate_cpu_online(struct cpufreq_policy *policy) 3000 { 3001 struct cpudata *cpu = all_cpu_data[policy->cpu]; 3002 3003 pr_debug("CPU %d going online\n", cpu->cpu); 3004 3005 intel_pstate_init_acpi_perf_limits(policy); 3006 3007 if (hwp_active) { 3008 /* 3009 * Re-enable HWP and clear the "suspended" flag to let "resume" 3010 * know that it need not do that. 3011 */ 3012 intel_pstate_hwp_reenable(cpu); 3013 cpu->suspended = false; 3014 3015 hybrid_update_capacity(cpu); 3016 } 3017 3018 return 0; 3019 } 3020 3021 static int intel_pstate_cpu_offline(struct cpufreq_policy *policy) 3022 { 3023 intel_pstate_clear_update_util_hook(policy->cpu); 3024 3025 return intel_cpufreq_cpu_offline(policy); 3026 } 3027 3028 static void intel_pstate_cpu_exit(struct cpufreq_policy *policy) 3029 { 3030 pr_debug("CPU %d exiting\n", policy->cpu); 3031 3032 policy->fast_switch_possible = false; 3033 } 3034 3035 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy) 3036 { 3037 struct cpudata *cpu; 3038 int rc; 3039 3040 rc = intel_pstate_init_cpu(policy->cpu); 3041 if (rc) 3042 return rc; 3043 3044 cpu = all_cpu_data[policy->cpu]; 3045 3046 cpu->max_perf_ratio = 0xFF; 3047 cpu->min_perf_ratio = 0; 3048 3049 /* cpuinfo and default policy values */ 3050 policy->cpuinfo.min_freq = cpu->pstate.min_freq; 3051 policy->cpuinfo.max_freq = READ_ONCE(global.no_turbo) ? 3052 cpu->pstate.max_freq : cpu->pstate.turbo_freq; 3053 3054 intel_pstate_init_acpi_perf_limits(policy); 3055 3056 policy->fast_switch_possible = true; 3057 3058 return 0; 3059 } 3060 3061 static int intel_pstate_cpu_init(struct cpufreq_policy *policy) 3062 { 3063 int ret = __intel_pstate_cpu_init(policy); 3064 struct cpudata *cpu; 3065 3066 if (ret) 3067 return ret; 3068 3069 /* 3070 * Set the policy to powersave to provide a valid fallback value in case 3071 * the default cpufreq governor is neither powersave nor performance. 3072 */ 3073 policy->policy = CPUFREQ_POLICY_POWERSAVE; 3074 3075 cpu = all_cpu_data[policy->cpu]; 3076 if (hwp_active) 3077 cpu->epp_cached = intel_pstate_get_epp(cpu, 0); 3078 else 3079 intel_pstate_set_min_pstate(cpu); 3080 3081 return 0; 3082 } 3083 3084 static struct cpufreq_driver intel_pstate = { 3085 .flags = CPUFREQ_CONST_LOOPS, 3086 .verify = intel_pstate_verify_policy, 3087 .setpolicy = intel_pstate_set_policy, 3088 .suspend = intel_pstate_suspend, 3089 .resume = intel_pstate_resume, 3090 .init = intel_pstate_cpu_init, 3091 .exit = intel_pstate_cpu_exit, 3092 .offline = intel_pstate_cpu_offline, 3093 .online = intel_pstate_cpu_online, 3094 .update_limits = intel_pstate_update_limits, 3095 .name = "intel_pstate", 3096 }; 3097 3098 static int intel_cpufreq_verify_policy(struct cpufreq_policy_data *policy) 3099 { 3100 struct cpudata *cpu = all_cpu_data[policy->cpu]; 3101 3102 intel_pstate_verify_cpu_policy(cpu, policy); 3103 intel_pstate_update_perf_limits(cpu, policy->min, policy->max); 3104 3105 return 0; 3106 } 3107 3108 /* Use of trace in passive mode: 3109 * 3110 * In passive mode the trace core_busy field (also known as the 3111 * performance field, and lablelled as such on the graphs; also known as 3112 * core_avg_perf) is not needed and so is re-assigned to indicate if the 3113 * driver call was via the normal or fast switch path. Various graphs 3114 * output from the intel_pstate_tracer.py utility that include core_busy 3115 * (or performance or core_avg_perf) have a fixed y-axis from 0 to 100%, 3116 * so we use 10 to indicate the normal path through the driver, and 3117 * 90 to indicate the fast switch path through the driver. 3118 * The scaled_busy field is not used, and is set to 0. 3119 */ 3120 3121 #define INTEL_PSTATE_TRACE_TARGET 10 3122 #define INTEL_PSTATE_TRACE_FAST_SWITCH 90 3123 3124 static void intel_cpufreq_trace(struct cpudata *cpu, unsigned int trace_type, int old_pstate) 3125 { 3126 struct sample *sample; 3127 3128 if (!trace_pstate_sample_enabled()) 3129 return; 3130 3131 if (!intel_pstate_sample(cpu, ktime_get())) 3132 return; 3133 3134 sample = &cpu->sample; 3135 trace_call__pstate_sample(trace_type, 3136 0, 3137 old_pstate, 3138 cpu->pstate.current_pstate, 3139 sample->mperf, 3140 sample->aperf, 3141 sample->tsc, 3142 get_avg_frequency(cpu), 3143 fp_toint(cpu->iowait_boost * 100)); 3144 } 3145 3146 static void intel_cpufreq_hwp_update(struct cpudata *cpu, u32 min, u32 max, 3147 u32 desired, bool fast_switch) 3148 { 3149 u64 prev = READ_ONCE(cpu->hwp_req_cached), value = prev; 3150 3151 value &= ~HWP_MIN_PERF(~0L); 3152 value |= HWP_MIN_PERF(min); 3153 3154 value &= ~HWP_MAX_PERF(~0L); 3155 value |= HWP_MAX_PERF(max); 3156 3157 value &= ~HWP_DESIRED_PERF(~0L); 3158 value |= HWP_DESIRED_PERF(desired); 3159 3160 if (value == prev) 3161 return; 3162 3163 WRITE_ONCE(cpu->hwp_req_cached, value); 3164 if (fast_switch) 3165 wrmsrq(MSR_HWP_REQUEST, value); 3166 else 3167 wrmsrq_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 3168 } 3169 3170 static void intel_cpufreq_perf_ctl_update(struct cpudata *cpu, 3171 u32 target_pstate, bool fast_switch) 3172 { 3173 if (fast_switch) 3174 wrmsrq(MSR_IA32_PERF_CTL, 3175 pstate_funcs.get_val(cpu, target_pstate)); 3176 else 3177 wrmsrq_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL, 3178 pstate_funcs.get_val(cpu, target_pstate)); 3179 } 3180 3181 static int intel_cpufreq_update_pstate(struct cpufreq_policy *policy, 3182 int target_pstate, bool fast_switch) 3183 { 3184 struct cpudata *cpu = all_cpu_data[policy->cpu]; 3185 int old_pstate = cpu->pstate.current_pstate; 3186 3187 target_pstate = intel_pstate_prepare_request(cpu, target_pstate); 3188 if (hwp_active) { 3189 int max_pstate = policy->strict_target ? 3190 target_pstate : cpu->max_perf_ratio; 3191 3192 intel_cpufreq_hwp_update(cpu, target_pstate, max_pstate, 3193 target_pstate, fast_switch); 3194 } else if (target_pstate != old_pstate) { 3195 intel_cpufreq_perf_ctl_update(cpu, target_pstate, fast_switch); 3196 } 3197 3198 cpu->pstate.current_pstate = target_pstate; 3199 3200 intel_cpufreq_trace(cpu, fast_switch ? INTEL_PSTATE_TRACE_FAST_SWITCH : 3201 INTEL_PSTATE_TRACE_TARGET, old_pstate); 3202 3203 return target_pstate; 3204 } 3205 3206 static int intel_cpufreq_target(struct cpufreq_policy *policy, 3207 unsigned int target_freq, 3208 unsigned int relation) 3209 { 3210 struct cpudata *cpu = all_cpu_data[policy->cpu]; 3211 struct cpufreq_freqs freqs; 3212 int target_pstate; 3213 3214 freqs.old = policy->cur; 3215 freqs.new = target_freq; 3216 3217 cpufreq_freq_transition_begin(policy, &freqs); 3218 3219 target_pstate = intel_pstate_freq_to_hwp_rel(cpu, freqs.new, relation); 3220 target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, false); 3221 3222 freqs.new = target_pstate * cpu->pstate.scaling; 3223 3224 cpufreq_freq_transition_end(policy, &freqs, false); 3225 3226 return 0; 3227 } 3228 3229 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy, 3230 unsigned int target_freq) 3231 { 3232 struct cpudata *cpu = all_cpu_data[policy->cpu]; 3233 int target_pstate; 3234 3235 target_pstate = intel_pstate_freq_to_hwp(cpu, target_freq); 3236 3237 target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, true); 3238 3239 return target_pstate * cpu->pstate.scaling; 3240 } 3241 3242 static void intel_cpufreq_adjust_perf(struct cpufreq_policy *policy, 3243 unsigned long min_perf, 3244 unsigned long target_perf, 3245 unsigned long max_perf, 3246 unsigned long capacity) 3247 { 3248 struct cpudata *cpu = all_cpu_data[policy->cpu]; 3249 u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached); 3250 int old_pstate = cpu->pstate.current_pstate; 3251 int cap_pstate, min_pstate, max_pstate, target_pstate; 3252 3253 cap_pstate = READ_ONCE(global.no_turbo) ? 3254 HWP_GUARANTEED_PERF(hwp_cap) : 3255 HWP_HIGHEST_PERF(hwp_cap); 3256 3257 /* Optimization: Avoid unnecessary divisions. */ 3258 3259 target_pstate = cap_pstate; 3260 if (target_perf < capacity) 3261 target_pstate = DIV_ROUND_UP(cap_pstate * target_perf, capacity); 3262 3263 min_pstate = cap_pstate; 3264 if (min_perf < capacity) 3265 min_pstate = DIV_ROUND_UP(cap_pstate * min_perf, capacity); 3266 3267 if (min_pstate < cpu->pstate.min_pstate) 3268 min_pstate = cpu->pstate.min_pstate; 3269 3270 if (min_pstate < cpu->min_perf_ratio) 3271 min_pstate = cpu->min_perf_ratio; 3272 3273 if (min_pstate > cpu->max_perf_ratio) 3274 min_pstate = cpu->max_perf_ratio; 3275 3276 max_pstate = cap_pstate; 3277 if (max_perf < capacity) 3278 max_pstate = DIV_ROUND_UP(cap_pstate * max_perf, capacity); 3279 3280 if (max_pstate > cpu->max_perf_ratio) 3281 max_pstate = cpu->max_perf_ratio; 3282 3283 if (max_pstate < min_pstate) 3284 max_pstate = min_pstate; 3285 3286 target_pstate = clamp_t(int, target_pstate, min_pstate, max_pstate); 3287 3288 intel_cpufreq_hwp_update(cpu, min_pstate, max_pstate, target_pstate, true); 3289 3290 cpu->pstate.current_pstate = target_pstate; 3291 intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_FAST_SWITCH, old_pstate); 3292 } 3293 3294 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy) 3295 { 3296 struct freq_qos_request *req; 3297 struct cpudata *cpu; 3298 struct device *dev; 3299 int ret, freq; 3300 3301 dev = get_cpu_device(policy->cpu); 3302 if (!dev) 3303 return -ENODEV; 3304 3305 ret = __intel_pstate_cpu_init(policy); 3306 if (ret) 3307 return ret; 3308 3309 policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY; 3310 3311 req = kzalloc_objs(*req, 2); 3312 if (!req) { 3313 ret = -ENOMEM; 3314 goto pstate_exit; 3315 } 3316 3317 cpu = all_cpu_data[policy->cpu]; 3318 3319 if (hwp_active) { 3320 u64 value; 3321 3322 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY_HWP; 3323 3324 intel_pstate_get_hwp_cap(cpu); 3325 3326 rdmsrq_on_cpu(cpu->cpu, MSR_HWP_REQUEST, &value); 3327 WRITE_ONCE(cpu->hwp_req_cached, value); 3328 3329 cpu->epp_cached = intel_pstate_get_epp(cpu, value); 3330 3331 intel_cpufreq_hwp_update(cpu, cpu->pstate.min_pstate, 3332 cpu->pstate.max_pstate, 3333 cpu->pstate.min_pstate, false); 3334 } else { 3335 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY; 3336 intel_pstate_set_min_pstate(cpu); 3337 } 3338 policy->cur = policy->cpuinfo.min_freq; 3339 3340 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.min_perf_pct, 100); 3341 3342 ret = freq_qos_add_request(&policy->constraints, req, FREQ_QOS_MIN, 3343 freq); 3344 if (ret < 0) { 3345 dev_err(dev, "Failed to add min-freq constraint (%d)\n", ret); 3346 goto free_req; 3347 } 3348 3349 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.max_perf_pct, 100); 3350 3351 ret = freq_qos_add_request(&policy->constraints, req + 1, FREQ_QOS_MAX, 3352 freq); 3353 if (ret < 0) { 3354 dev_err(dev, "Failed to add max-freq constraint (%d)\n", ret); 3355 goto remove_min_req; 3356 } 3357 3358 policy->driver_data = req; 3359 3360 return 0; 3361 3362 remove_min_req: 3363 freq_qos_remove_request(req); 3364 free_req: 3365 kfree(req); 3366 pstate_exit: 3367 intel_pstate_exit_perf_limits(policy); 3368 3369 return ret; 3370 } 3371 3372 static void intel_cpufreq_cpu_exit(struct cpufreq_policy *policy) 3373 { 3374 struct freq_qos_request *req; 3375 3376 req = policy->driver_data; 3377 3378 freq_qos_remove_request(req + 1); 3379 freq_qos_remove_request(req); 3380 kfree(req); 3381 3382 intel_pstate_cpu_exit(policy); 3383 } 3384 3385 static int intel_cpufreq_suspend(struct cpufreq_policy *policy) 3386 { 3387 intel_pstate_suspend(policy); 3388 3389 if (hwp_active) { 3390 struct cpudata *cpu = all_cpu_data[policy->cpu]; 3391 u64 value = READ_ONCE(cpu->hwp_req_cached); 3392 3393 /* 3394 * Clear the desired perf field in MSR_HWP_REQUEST in case 3395 * intel_cpufreq_adjust_perf() is in use and the last value 3396 * written by it may not be suitable. 3397 */ 3398 value &= ~HWP_DESIRED_PERF(~0L); 3399 wrmsrq_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 3400 WRITE_ONCE(cpu->hwp_req_cached, value); 3401 } 3402 3403 return 0; 3404 } 3405 3406 static struct cpufreq_driver intel_cpufreq = { 3407 .flags = CPUFREQ_CONST_LOOPS, 3408 .verify = intel_cpufreq_verify_policy, 3409 .target = intel_cpufreq_target, 3410 .fast_switch = intel_cpufreq_fast_switch, 3411 .init = intel_cpufreq_cpu_init, 3412 .exit = intel_cpufreq_cpu_exit, 3413 .offline = intel_cpufreq_cpu_offline, 3414 .online = intel_pstate_cpu_online, 3415 .suspend = intel_cpufreq_suspend, 3416 .resume = intel_pstate_resume, 3417 .update_limits = intel_pstate_update_limits, 3418 .name = "intel_cpufreq", 3419 }; 3420 3421 static struct cpufreq_driver *default_driver; 3422 3423 static void intel_pstate_driver_cleanup(void) 3424 { 3425 unsigned int cpu; 3426 3427 cpus_read_lock(); 3428 for_each_online_cpu(cpu) { 3429 if (all_cpu_data[cpu]) { 3430 if (intel_pstate_driver == &intel_pstate) 3431 intel_pstate_clear_update_util_hook(cpu); 3432 3433 kfree(all_cpu_data[cpu]); 3434 WRITE_ONCE(all_cpu_data[cpu], NULL); 3435 } 3436 } 3437 cpus_read_unlock(); 3438 3439 intel_pstate_driver = NULL; 3440 } 3441 3442 static int intel_pstate_register_driver(struct cpufreq_driver *driver) 3443 { 3444 bool refresh_cpu_cap_scaling; 3445 int ret; 3446 3447 if (driver == &intel_pstate) 3448 intel_pstate_sysfs_expose_hwp_dynamic_boost(); 3449 3450 memset(&global, 0, sizeof(global)); 3451 global.max_perf_pct = 100; 3452 global.turbo_disabled = turbo_is_disabled(); 3453 global.no_turbo = global.turbo_disabled; 3454 3455 arch_set_max_freq_ratio(global.turbo_disabled); 3456 3457 refresh_cpu_cap_scaling = hybrid_clear_max_perf_cpu(); 3458 3459 intel_pstate_driver = driver; 3460 ret = cpufreq_register_driver(intel_pstate_driver); 3461 if (ret) { 3462 intel_pstate_driver_cleanup(); 3463 return ret; 3464 } 3465 3466 global.min_perf_pct = min_perf_pct_min(); 3467 3468 hybrid_init_cpu_capacity_scaling(refresh_cpu_cap_scaling); 3469 3470 return 0; 3471 } 3472 3473 static ssize_t intel_pstate_show_status(char *buf) 3474 { 3475 if (!intel_pstate_driver) 3476 return sprintf(buf, "off\n"); 3477 3478 return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ? 3479 "active" : "passive"); 3480 } 3481 3482 static int intel_pstate_update_status(const char *buf, size_t size) 3483 { 3484 if (size == 3 && !strncmp(buf, "off", size)) { 3485 if (!intel_pstate_driver) 3486 return 0; 3487 3488 if (hwp_active) 3489 return -EBUSY; 3490 3491 cpufreq_unregister_driver(intel_pstate_driver); 3492 intel_pstate_driver_cleanup(); 3493 return 0; 3494 } 3495 3496 if (size == 6 && !strncmp(buf, "active", size)) { 3497 if (intel_pstate_driver) { 3498 if (intel_pstate_driver == &intel_pstate) 3499 return 0; 3500 3501 cpufreq_unregister_driver(intel_pstate_driver); 3502 } 3503 3504 return intel_pstate_register_driver(&intel_pstate); 3505 } 3506 3507 if (size == 7 && !strncmp(buf, "passive", size)) { 3508 if (intel_pstate_driver) { 3509 if (intel_pstate_driver == &intel_cpufreq) 3510 return 0; 3511 3512 cpufreq_unregister_driver(intel_pstate_driver); 3513 intel_pstate_sysfs_hide_hwp_dynamic_boost(); 3514 } 3515 3516 return intel_pstate_register_driver(&intel_cpufreq); 3517 } 3518 3519 return -EINVAL; 3520 } 3521 3522 static int no_load __initdata; 3523 static int no_hwp __initdata; 3524 static int hwp_only __initdata; 3525 static unsigned int force_load __initdata; 3526 3527 static int __init intel_pstate_msrs_not_valid(void) 3528 { 3529 if (!pstate_funcs.get_max(0) || 3530 !pstate_funcs.get_min(0) || 3531 !pstate_funcs.get_turbo(0)) 3532 return -ENODEV; 3533 3534 return 0; 3535 } 3536 3537 static void __init copy_cpu_funcs(struct pstate_funcs *funcs) 3538 { 3539 pstate_funcs.get_max = funcs->get_max; 3540 pstate_funcs.get_max_physical = funcs->get_max_physical; 3541 pstate_funcs.get_min = funcs->get_min; 3542 pstate_funcs.get_turbo = funcs->get_turbo; 3543 pstate_funcs.get_scaling = funcs->get_scaling; 3544 pstate_funcs.get_val = funcs->get_val; 3545 pstate_funcs.get_vid = funcs->get_vid; 3546 pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift; 3547 } 3548 3549 #ifdef CONFIG_ACPI 3550 3551 static bool __init intel_pstate_no_acpi_pss(void) 3552 { 3553 int i; 3554 3555 for_each_possible_cpu(i) { 3556 acpi_status status; 3557 union acpi_object *pss; 3558 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; 3559 struct acpi_processor *pr = per_cpu(processors, i); 3560 3561 if (!pr) 3562 continue; 3563 3564 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer); 3565 if (ACPI_FAILURE(status)) 3566 continue; 3567 3568 pss = buffer.pointer; 3569 if (pss && pss->type == ACPI_TYPE_PACKAGE) { 3570 kfree(pss); 3571 return false; 3572 } 3573 3574 kfree(pss); 3575 } 3576 3577 pr_debug("ACPI _PSS not found\n"); 3578 return true; 3579 } 3580 3581 static bool __init intel_pstate_no_acpi_pcch(void) 3582 { 3583 acpi_status status; 3584 acpi_handle handle; 3585 3586 status = acpi_get_handle(NULL, "\\_SB", &handle); 3587 if (ACPI_FAILURE(status)) 3588 goto not_found; 3589 3590 if (acpi_has_method(handle, "PCCH")) 3591 return false; 3592 3593 not_found: 3594 pr_debug("ACPI PCCH not found\n"); 3595 return true; 3596 } 3597 3598 static bool __init intel_pstate_has_acpi_ppc(void) 3599 { 3600 int i; 3601 3602 for_each_possible_cpu(i) { 3603 struct acpi_processor *pr = per_cpu(processors, i); 3604 3605 if (!pr) 3606 continue; 3607 if (acpi_has_method(pr->handle, "_PPC")) 3608 return true; 3609 } 3610 pr_debug("ACPI _PPC not found\n"); 3611 return false; 3612 } 3613 3614 enum { 3615 PSS, 3616 PPC, 3617 }; 3618 3619 /* Hardware vendor-specific info that has its own power management modes */ 3620 static struct acpi_platform_list plat_info[] __initdata = { 3621 {"HP ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, NULL, PSS}, 3622 {"ORACLE", "X4-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3623 {"ORACLE", "X4-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3624 {"ORACLE", "X4-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3625 {"ORACLE", "X3-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3626 {"ORACLE", "X3-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3627 {"ORACLE", "X3-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3628 {"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3629 {"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3630 {"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3631 {"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3632 {"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3633 {"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3634 {"ORACLE", "X6-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3635 {"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3636 { } /* End */ 3637 }; 3638 3639 #define BITMASK_OOB (BIT(8) | BIT(18)) 3640 3641 static bool __init intel_pstate_platform_pwr_mgmt_exists(void) 3642 { 3643 const struct x86_cpu_id *id; 3644 u64 misc_pwr; 3645 int idx; 3646 3647 id = x86_match_cpu(intel_pstate_cpu_oob_ids); 3648 if (id) { 3649 rdmsrq(MSR_MISC_PWR_MGMT, misc_pwr); 3650 if (misc_pwr & BITMASK_OOB) { 3651 pr_debug("Bit 8 or 18 in the MISC_PWR_MGMT MSR set\n"); 3652 pr_debug("P states are controlled in Out of Band mode by the firmware/hardware\n"); 3653 return true; 3654 } 3655 } 3656 3657 idx = acpi_match_platform_list(plat_info); 3658 if (idx < 0) 3659 return false; 3660 3661 switch (plat_info[idx].data) { 3662 case PSS: 3663 if (!intel_pstate_no_acpi_pss()) 3664 return false; 3665 3666 return intel_pstate_no_acpi_pcch(); 3667 case PPC: 3668 return intel_pstate_has_acpi_ppc() && !force_load; 3669 } 3670 3671 return false; 3672 } 3673 3674 static void intel_pstate_request_control_from_smm(void) 3675 { 3676 /* 3677 * It may be unsafe to request P-states control from SMM if _PPC support 3678 * has not been enabled. 3679 */ 3680 if (acpi_ppc) 3681 acpi_processor_pstate_control(); 3682 } 3683 #else /* CONFIG_ACPI not enabled */ 3684 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; } 3685 static inline bool intel_pstate_has_acpi_ppc(void) { return false; } 3686 static inline void intel_pstate_request_control_from_smm(void) {} 3687 #endif /* CONFIG_ACPI */ 3688 3689 #define INTEL_PSTATE_HWP_NOT_HYBRID 0x01 3690 3691 #define X86_MATCH_HWP(vfm, hwp_mode) \ 3692 X86_MATCH_VFM_FEATURE(vfm, X86_FEATURE_HWP, hwp_mode) 3693 3694 static const struct x86_cpu_id hwp_support_ids[] __initconst = { 3695 X86_MATCH_HWP(INTEL_BROADWELL_X, INTEL_PSTATE_HWP_NOT_HYBRID), 3696 X86_MATCH_HWP(INTEL_BROADWELL_D, INTEL_PSTATE_HWP_NOT_HYBRID), 3697 X86_MATCH_HWP(INTEL_ANY, 0), 3698 {} 3699 }; 3700 3701 static bool intel_pstate_hwp_is_enabled(void) 3702 { 3703 u64 value; 3704 3705 rdmsrq(MSR_PM_ENABLE, value); 3706 return !!(value & 0x1); 3707 } 3708 3709 #define POWERSAVE_MASK GENMASK(7, 0) 3710 #define BALANCE_POWER_MASK GENMASK(15, 8) 3711 #define BALANCE_PERFORMANCE_MASK GENMASK(23, 16) 3712 #define PERFORMANCE_MASK GENMASK(31, 24) 3713 3714 #define HWP_SET_EPP_VALUES(powersave, balance_power, balance_perf, performance) \ 3715 (FIELD_PREP_CONST(POWERSAVE_MASK, powersave) |\ 3716 FIELD_PREP_CONST(BALANCE_POWER_MASK, balance_power) |\ 3717 FIELD_PREP_CONST(BALANCE_PERFORMANCE_MASK, balance_perf) |\ 3718 FIELD_PREP_CONST(PERFORMANCE_MASK, performance)) 3719 3720 #define HWP_SET_DEF_BALANCE_PERF_EPP(balance_perf) \ 3721 (HWP_SET_EPP_VALUES(HWP_EPP_POWERSAVE, HWP_EPP_BALANCE_POWERSAVE,\ 3722 balance_perf, HWP_EPP_PERFORMANCE)) 3723 3724 static const struct x86_cpu_id intel_epp_default[] = { 3725 /* 3726 * Set EPP value as 102, this is the max suggested EPP 3727 * which can result in one core turbo frequency for 3728 * AlderLake Mobile CPUs. 3729 */ 3730 X86_MATCH_VFM(INTEL_ALDERLAKE_L, HWP_SET_DEF_BALANCE_PERF_EPP(102)), 3731 X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, HWP_SET_DEF_BALANCE_PERF_EPP(32)), 3732 X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, HWP_SET_DEF_BALANCE_PERF_EPP(32)), 3733 X86_MATCH_VFM(INTEL_GRANITERAPIDS_X, HWP_SET_DEF_BALANCE_PERF_EPP(32)), 3734 X86_MATCH_VFM(INTEL_GRANITERAPIDS_D, HWP_SET_DEF_BALANCE_PERF_EPP(32)), 3735 X86_MATCH_VFM(INTEL_METEORLAKE_L, HWP_SET_EPP_VALUES(HWP_EPP_POWERSAVE, 3736 179, 64, 16)), 3737 X86_MATCH_VFM(INTEL_ARROWLAKE, HWP_SET_EPP_VALUES(HWP_EPP_POWERSAVE, 3738 179, 64, 16)), 3739 {} 3740 }; 3741 3742 static const struct x86_cpu_id intel_hybrid_scaling_factor[] = { 3743 X86_MATCH_VFM(INTEL_ALDERLAKE, HYBRID_SCALING_FACTOR_ADL), 3744 X86_MATCH_VFM(INTEL_ALDERLAKE_L, HYBRID_SCALING_FACTOR_ADL), 3745 X86_MATCH_VFM(INTEL_RAPTORLAKE, HYBRID_SCALING_FACTOR_ADL), 3746 X86_MATCH_VFM(INTEL_RAPTORLAKE_P, HYBRID_SCALING_FACTOR_ADL), 3747 X86_MATCH_VFM(INTEL_RAPTORLAKE_S, HYBRID_SCALING_FACTOR_ADL), 3748 X86_MATCH_VFM(INTEL_BARTLETTLAKE, HYBRID_SCALING_FACTOR_ADL), 3749 X86_MATCH_VFM(INTEL_METEORLAKE_L, HYBRID_SCALING_FACTOR_MTL), 3750 X86_MATCH_VFM(INTEL_LUNARLAKE_M, HYBRID_SCALING_FACTOR_LNL), 3751 {} 3752 }; 3753 3754 static bool hwp_check_epp(void) 3755 { 3756 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) 3757 return true; 3758 3759 /* Without EPP support, don't expose EPP-related sysfs attributes. */ 3760 hwp_cpufreq_attrs[HWP_PERFORMANCE_PREFERENCE_INDEX] = NULL; 3761 hwp_cpufreq_attrs[HWP_PERFORMANCE_AVAILABLE_PREFERENCES_INDEX] = NULL; 3762 3763 return false; 3764 } 3765 3766 static bool hwp_check_dec(void) 3767 { 3768 u64 power_ctl; 3769 3770 rdmsrq(MSR_IA32_POWER_CTL, power_ctl); 3771 return !!(power_ctl & BIT(POWER_CTL_DEC_ENABLE)); 3772 } 3773 3774 static int __init intel_pstate_init(void) 3775 { 3776 static struct cpudata **_all_cpu_data; 3777 const struct x86_cpu_id *id; 3778 int rc; 3779 3780 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) 3781 return -ENODEV; 3782 3783 /* 3784 * The Intel pstate driver will be ignored if the platform 3785 * firmware has its own power management modes. 3786 */ 3787 if (intel_pstate_platform_pwr_mgmt_exists()) { 3788 pr_info("P-states controlled by the platform\n"); 3789 return -ENODEV; 3790 } 3791 3792 id = x86_match_cpu(hwp_support_ids); 3793 if (id) { 3794 bool epp_present = hwp_check_epp(); 3795 3796 /* 3797 * If HWP is enabled already, there is no choice but to deal 3798 * with it. 3799 */ 3800 hwp_forced = intel_pstate_hwp_is_enabled(); 3801 if (hwp_forced) { 3802 pr_info("HWP enabled by BIOS\n"); 3803 no_hwp = 0; 3804 } else if (no_load) { 3805 return -ENODEV; 3806 } else if (!epp_present && !hwp_check_dec()) { 3807 /* 3808 * Avoid enabling HWP for processors without EPP support 3809 * unless the Dynamic Efficiency Control (DEC) enable 3810 * bit (MSR_IA32_POWER_CTL, bit 27) is set because that 3811 * means incomplete HWP implementation which is a corner 3812 * case and supporting it is generally problematic. 3813 */ 3814 no_hwp = 1; 3815 } 3816 3817 copy_cpu_funcs(&core_funcs); 3818 3819 if (!no_hwp) { 3820 hwp_active = true; 3821 intel_pstate.attr = hwp_cpufreq_attrs; 3822 intel_cpufreq.attr = hwp_cpufreq_attrs; 3823 intel_cpufreq.flags |= CPUFREQ_NEED_UPDATE_LIMITS; 3824 intel_cpufreq.adjust_perf = intel_cpufreq_adjust_perf; 3825 if (!default_driver) 3826 default_driver = &intel_pstate; 3827 3828 if (!id->driver_data) 3829 pstate_funcs.get_cpu_scaling = hwp_get_cpu_scaling; 3830 3831 goto hwp_cpu_matched; 3832 } 3833 pr_info("HWP not enabled\n"); 3834 } else { 3835 if (no_load) 3836 return -ENODEV; 3837 3838 id = x86_match_cpu(intel_hybrid_scaling_factor); 3839 if (id) { 3840 pr_info("HWP-disabled hybrid CPU is not supported\n"); 3841 return -ENODEV; 3842 } 3843 3844 id = x86_match_cpu(intel_pstate_cpu_ids); 3845 if (!id) { 3846 pr_info("CPU model not supported\n"); 3847 return -ENODEV; 3848 } 3849 3850 copy_cpu_funcs((struct pstate_funcs *)id->driver_data); 3851 } 3852 3853 if (intel_pstate_msrs_not_valid()) { 3854 pr_info("Invalid MSRs\n"); 3855 return -ENODEV; 3856 } 3857 /* Without HWP start in the passive mode. */ 3858 if (!default_driver) 3859 default_driver = &intel_cpufreq; 3860 3861 hwp_cpu_matched: 3862 if (!hwp_active && hwp_only) 3863 return -ENOTSUPP; 3864 3865 pr_info("Intel P-state driver initializing\n"); 3866 3867 _all_cpu_data = vzalloc(array_size(sizeof(void *), num_possible_cpus())); 3868 if (!_all_cpu_data) 3869 return -ENOMEM; 3870 3871 WRITE_ONCE(all_cpu_data, _all_cpu_data); 3872 3873 intel_pstate_request_control_from_smm(); 3874 3875 intel_pstate_sysfs_expose_params(); 3876 3877 if (hwp_active) { 3878 const struct x86_cpu_id *id = x86_match_cpu(intel_epp_default); 3879 const struct x86_cpu_id *hybrid_id = x86_match_cpu(intel_hybrid_scaling_factor); 3880 3881 if (id) { 3882 epp_values[EPP_INDEX_POWERSAVE] = 3883 FIELD_GET(POWERSAVE_MASK, id->driver_data); 3884 epp_values[EPP_INDEX_BALANCE_POWERSAVE] = 3885 FIELD_GET(BALANCE_POWER_MASK, id->driver_data); 3886 epp_values[EPP_INDEX_BALANCE_PERFORMANCE] = 3887 FIELD_GET(BALANCE_PERFORMANCE_MASK, id->driver_data); 3888 epp_values[EPP_INDEX_PERFORMANCE] = 3889 FIELD_GET(PERFORMANCE_MASK, id->driver_data); 3890 pr_debug("Updated EPPs powersave:%x balanced power:%x balanced perf:%x performance:%x\n", 3891 epp_values[EPP_INDEX_POWERSAVE], 3892 epp_values[EPP_INDEX_BALANCE_POWERSAVE], 3893 epp_values[EPP_INDEX_BALANCE_PERFORMANCE], 3894 epp_values[EPP_INDEX_PERFORMANCE]); 3895 } 3896 3897 if (hybrid_id) { 3898 hybrid_scaling_factor = hybrid_id->driver_data; 3899 pr_debug("hybrid scaling factor: %d\n", hybrid_scaling_factor); 3900 } 3901 3902 } 3903 3904 scoped_guard(mutex, &intel_pstate_driver_lock) { 3905 rc = intel_pstate_register_driver(default_driver); 3906 } 3907 if (rc) { 3908 intel_pstate_sysfs_remove(); 3909 return rc; 3910 } 3911 3912 if (hwp_active) { 3913 const struct x86_cpu_id *id; 3914 3915 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids); 3916 if (id) { 3917 set_power_ctl_ee_state(false); 3918 pr_info("Disabling energy efficiency optimization\n"); 3919 } 3920 3921 pr_info("HWP enabled\n"); 3922 } else if (boot_cpu_has(X86_FEATURE_HYBRID_CPU)) { 3923 pr_warn("Problematic setup: Hybrid processor with disabled HWP\n"); 3924 } 3925 3926 return 0; 3927 } 3928 device_initcall(intel_pstate_init); 3929 3930 static int __init intel_pstate_setup(char *str) 3931 { 3932 if (!str) 3933 return -EINVAL; 3934 3935 if (!strcmp(str, "disable")) 3936 no_load = 1; 3937 else if (!strcmp(str, "active")) 3938 default_driver = &intel_pstate; 3939 else if (!strcmp(str, "passive")) 3940 default_driver = &intel_cpufreq; 3941 3942 if (!strcmp(str, "no_hwp")) 3943 no_hwp = 1; 3944 3945 if (!strcmp(str, "no_cas")) 3946 no_cas = true; 3947 3948 if (!strcmp(str, "force")) 3949 force_load = 1; 3950 if (!strcmp(str, "hwp_only")) 3951 hwp_only = 1; 3952 if (!strcmp(str, "per_cpu_perf_limits")) 3953 per_cpu_limits = true; 3954 3955 #ifdef CONFIG_ACPI 3956 if (!strcmp(str, "support_acpi_ppc")) 3957 acpi_ppc = true; 3958 #endif 3959 3960 return 0; 3961 } 3962 early_param("intel_pstate", intel_pstate_setup); 3963 3964 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>"); 3965 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors"); 3966