1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * intel_pstate.c: Native P state management for Intel processors 4 * 5 * (C) Copyright 2012 Intel Corporation 6 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com> 7 */ 8 9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10 11 #include <linux/kernel.h> 12 #include <linux/kernel_stat.h> 13 #include <linux/module.h> 14 #include <linux/ktime.h> 15 #include <linux/hrtimer.h> 16 #include <linux/tick.h> 17 #include <linux/slab.h> 18 #include <linux/sched/cpufreq.h> 19 #include <linux/sched/smt.h> 20 #include <linux/list.h> 21 #include <linux/cpu.h> 22 #include <linux/cpufreq.h> 23 #include <linux/sysfs.h> 24 #include <linux/types.h> 25 #include <linux/fs.h> 26 #include <linux/acpi.h> 27 #include <linux/vmalloc.h> 28 #include <linux/pm_qos.h> 29 #include <linux/bitfield.h> 30 #include <trace/events/power.h> 31 32 #include <asm/cpu.h> 33 #include <asm/div64.h> 34 #include <asm/msr.h> 35 #include <asm/cpu_device_id.h> 36 #include <asm/cpufeature.h> 37 #include <asm/intel-family.h> 38 #include "../drivers/thermal/intel/thermal_interrupt.h" 39 40 #define INTEL_PSTATE_SAMPLING_INTERVAL (10 * NSEC_PER_MSEC) 41 42 #define INTEL_CPUFREQ_TRANSITION_LATENCY 20000 43 #define INTEL_CPUFREQ_TRANSITION_DELAY_HWP 5000 44 #define INTEL_CPUFREQ_TRANSITION_DELAY 500 45 46 #ifdef CONFIG_ACPI 47 #include <acpi/processor.h> 48 #include <acpi/cppc_acpi.h> 49 #endif 50 51 #define FRAC_BITS 8 52 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS) 53 #define fp_toint(X) ((X) >> FRAC_BITS) 54 55 #define ONE_EIGHTH_FP ((int64_t)1 << (FRAC_BITS - 3)) 56 57 #define EXT_BITS 6 58 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS) 59 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS) 60 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS) 61 62 static inline int32_t mul_fp(int32_t x, int32_t y) 63 { 64 return ((int64_t)x * (int64_t)y) >> FRAC_BITS; 65 } 66 67 static inline int32_t div_fp(s64 x, s64 y) 68 { 69 return div64_s64((int64_t)x << FRAC_BITS, y); 70 } 71 72 static inline int ceiling_fp(int32_t x) 73 { 74 int mask, ret; 75 76 ret = fp_toint(x); 77 mask = (1 << FRAC_BITS) - 1; 78 if (x & mask) 79 ret += 1; 80 return ret; 81 } 82 83 static inline u64 mul_ext_fp(u64 x, u64 y) 84 { 85 return (x * y) >> EXT_FRAC_BITS; 86 } 87 88 static inline u64 div_ext_fp(u64 x, u64 y) 89 { 90 return div64_u64(x << EXT_FRAC_BITS, y); 91 } 92 93 /** 94 * struct sample - Store performance sample 95 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average 96 * performance during last sample period 97 * @busy_scaled: Scaled busy value which is used to calculate next 98 * P state. This can be different than core_avg_perf 99 * to account for cpu idle period 100 * @aperf: Difference of actual performance frequency clock count 101 * read from APERF MSR between last and current sample 102 * @mperf: Difference of maximum performance frequency clock count 103 * read from MPERF MSR between last and current sample 104 * @tsc: Difference of time stamp counter between last and 105 * current sample 106 * @time: Current time from scheduler 107 * 108 * This structure is used in the cpudata structure to store performance sample 109 * data for choosing next P State. 110 */ 111 struct sample { 112 int32_t core_avg_perf; 113 int32_t busy_scaled; 114 u64 aperf; 115 u64 mperf; 116 u64 tsc; 117 u64 time; 118 }; 119 120 /** 121 * struct pstate_data - Store P state data 122 * @current_pstate: Current requested P state 123 * @min_pstate: Min P state possible for this platform 124 * @max_pstate: Max P state possible for this platform 125 * @max_pstate_physical:This is physical Max P state for a processor 126 * This can be higher than the max_pstate which can 127 * be limited by platform thermal design power limits 128 * @perf_ctl_scaling: PERF_CTL P-state to frequency scaling factor 129 * @scaling: Scaling factor between performance and frequency 130 * @turbo_pstate: Max Turbo P state possible for this platform 131 * @min_freq: @min_pstate frequency in cpufreq units 132 * @max_freq: @max_pstate frequency in cpufreq units 133 * @turbo_freq: @turbo_pstate frequency in cpufreq units 134 * 135 * Stores the per cpu model P state limits and current P state. 136 */ 137 struct pstate_data { 138 int current_pstate; 139 int min_pstate; 140 int max_pstate; 141 int max_pstate_physical; 142 int perf_ctl_scaling; 143 int scaling; 144 int turbo_pstate; 145 unsigned int min_freq; 146 unsigned int max_freq; 147 unsigned int turbo_freq; 148 }; 149 150 /** 151 * struct vid_data - Stores voltage information data 152 * @min: VID data for this platform corresponding to 153 * the lowest P state 154 * @max: VID data corresponding to the highest P State. 155 * @turbo: VID data for turbo P state 156 * @ratio: Ratio of (vid max - vid min) / 157 * (max P state - Min P State) 158 * 159 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling) 160 * This data is used in Atom platforms, where in addition to target P state, 161 * the voltage data needs to be specified to select next P State. 162 */ 163 struct vid_data { 164 int min; 165 int max; 166 int turbo; 167 int32_t ratio; 168 }; 169 170 /** 171 * struct global_params - Global parameters, mostly tunable via sysfs. 172 * @no_turbo: Whether or not to use turbo P-states. 173 * @turbo_disabled: Whether or not turbo P-states are available at all, 174 * based on the MSR_IA32_MISC_ENABLE value and whether or 175 * not the maximum reported turbo P-state is different from 176 * the maximum reported non-turbo one. 177 * @min_perf_pct: Minimum capacity limit in percent of the maximum turbo 178 * P-state capacity. 179 * @max_perf_pct: Maximum capacity limit in percent of the maximum turbo 180 * P-state capacity. 181 */ 182 struct global_params { 183 bool no_turbo; 184 bool turbo_disabled; 185 int max_perf_pct; 186 int min_perf_pct; 187 }; 188 189 /** 190 * struct cpudata - Per CPU instance data storage 191 * @cpu: CPU number for this instance data 192 * @policy: CPUFreq policy value 193 * @update_util: CPUFreq utility callback information 194 * @update_util_set: CPUFreq utility callback is set 195 * @iowait_boost: iowait-related boost fraction 196 * @last_update: Time of the last update. 197 * @pstate: Stores P state limits for this CPU 198 * @vid: Stores VID limits for this CPU 199 * @last_sample_time: Last Sample time 200 * @aperf_mperf_shift: APERF vs MPERF counting frequency difference 201 * @prev_aperf: Last APERF value read from APERF MSR 202 * @prev_mperf: Last MPERF value read from MPERF MSR 203 * @prev_tsc: Last timestamp counter (TSC) value 204 * @sample: Storage for storing last Sample data 205 * @min_perf_ratio: Minimum capacity in terms of PERF or HWP ratios 206 * @max_perf_ratio: Maximum capacity in terms of PERF or HWP ratios 207 * @acpi_perf_data: Stores ACPI perf information read from _PSS 208 * @valid_pss_table: Set to true for valid ACPI _PSS entries found 209 * @epp_powersave: Last saved HWP energy performance preference 210 * (EPP) or energy performance bias (EPB), 211 * when policy switched to performance 212 * @epp_policy: Last saved policy used to set EPP/EPB 213 * @epp_default: Power on default HWP energy performance 214 * preference/bias 215 * @epp_cached: Cached HWP energy-performance preference value 216 * @hwp_req_cached: Cached value of the last HWP Request MSR 217 * @hwp_cap_cached: Cached value of the last HWP Capabilities MSR 218 * @last_io_update: Last time when IO wake flag was set 219 * @capacity_perf: Highest perf used for scale invariance 220 * @sched_flags: Store scheduler flags for possible cross CPU update 221 * @hwp_boost_min: Last HWP boosted min performance 222 * @suspended: Whether or not the driver has been suspended. 223 * @hwp_notify_work: workqueue for HWP notifications. 224 * 225 * This structure stores per CPU instance data for all CPUs. 226 */ 227 struct cpudata { 228 int cpu; 229 230 unsigned int policy; 231 struct update_util_data update_util; 232 bool update_util_set; 233 234 struct pstate_data pstate; 235 struct vid_data vid; 236 237 u64 last_update; 238 u64 last_sample_time; 239 u64 aperf_mperf_shift; 240 u64 prev_aperf; 241 u64 prev_mperf; 242 u64 prev_tsc; 243 struct sample sample; 244 int32_t min_perf_ratio; 245 int32_t max_perf_ratio; 246 #ifdef CONFIG_ACPI 247 struct acpi_processor_performance acpi_perf_data; 248 bool valid_pss_table; 249 #endif 250 unsigned int iowait_boost; 251 s16 epp_powersave; 252 s16 epp_policy; 253 s16 epp_default; 254 s16 epp_cached; 255 u64 hwp_req_cached; 256 u64 hwp_cap_cached; 257 u64 last_io_update; 258 unsigned int capacity_perf; 259 unsigned int sched_flags; 260 u32 hwp_boost_min; 261 bool suspended; 262 struct delayed_work hwp_notify_work; 263 }; 264 265 static struct cpudata **all_cpu_data; 266 267 /** 268 * struct pstate_funcs - Per CPU model specific callbacks 269 * @get_max: Callback to get maximum non turbo effective P state 270 * @get_max_physical: Callback to get maximum non turbo physical P state 271 * @get_min: Callback to get minimum P state 272 * @get_turbo: Callback to get turbo P state 273 * @get_scaling: Callback to get frequency scaling factor 274 * @get_cpu_scaling: Get frequency scaling factor for a given cpu 275 * @get_aperf_mperf_shift: Callback to get the APERF vs MPERF frequency difference 276 * @get_val: Callback to convert P state to actual MSR write value 277 * @get_vid: Callback to get VID data for Atom platforms 278 * 279 * Core and Atom CPU models have different way to get P State limits. This 280 * structure is used to store those callbacks. 281 */ 282 struct pstate_funcs { 283 int (*get_max)(int cpu); 284 int (*get_max_physical)(int cpu); 285 int (*get_min)(int cpu); 286 int (*get_turbo)(int cpu); 287 int (*get_scaling)(void); 288 int (*get_cpu_scaling)(int cpu); 289 int (*get_aperf_mperf_shift)(void); 290 u64 (*get_val)(struct cpudata*, int pstate); 291 void (*get_vid)(struct cpudata *); 292 }; 293 294 static struct pstate_funcs pstate_funcs __read_mostly; 295 296 static bool hwp_active __ro_after_init; 297 static int hwp_mode_bdw __ro_after_init; 298 static bool per_cpu_limits __ro_after_init; 299 static bool hwp_forced __ro_after_init; 300 static bool hwp_boost __read_mostly; 301 static bool hwp_is_hybrid; 302 303 static struct cpufreq_driver *intel_pstate_driver __read_mostly; 304 305 #define HYBRID_SCALING_FACTOR 78741 306 #define HYBRID_SCALING_FACTOR_MTL 80000 307 #define HYBRID_SCALING_FACTOR_LNL 86957 308 309 static int hybrid_scaling_factor = HYBRID_SCALING_FACTOR; 310 311 static inline int core_get_scaling(void) 312 { 313 return 100000; 314 } 315 316 #ifdef CONFIG_ACPI 317 static bool acpi_ppc; 318 #endif 319 320 static struct global_params global; 321 322 static DEFINE_MUTEX(intel_pstate_driver_lock); 323 static DEFINE_MUTEX(intel_pstate_limits_lock); 324 325 #ifdef CONFIG_ACPI 326 327 static bool intel_pstate_acpi_pm_profile_server(void) 328 { 329 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER || 330 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER) 331 return true; 332 333 return false; 334 } 335 336 static bool intel_pstate_get_ppc_enable_status(void) 337 { 338 if (intel_pstate_acpi_pm_profile_server()) 339 return true; 340 341 return acpi_ppc; 342 } 343 344 #ifdef CONFIG_ACPI_CPPC_LIB 345 346 /* The work item is needed to avoid CPU hotplug locking issues */ 347 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work) 348 { 349 sched_set_itmt_support(); 350 } 351 352 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn); 353 354 #define CPPC_MAX_PERF U8_MAX 355 356 static void intel_pstate_set_itmt_prio(int cpu) 357 { 358 struct cppc_perf_caps cppc_perf; 359 static u32 max_highest_perf = 0, min_highest_perf = U32_MAX; 360 int ret; 361 362 ret = cppc_get_perf_caps(cpu, &cppc_perf); 363 /* 364 * If CPPC is not available, fall back to MSR_HWP_CAPABILITIES bits [8:0]. 365 * 366 * Also, on some systems with overclocking enabled, CPPC.highest_perf is 367 * hardcoded to 0xff, so CPPC.highest_perf cannot be used to enable ITMT. 368 * Fall back to MSR_HWP_CAPABILITIES then too. 369 */ 370 if (ret || cppc_perf.highest_perf == CPPC_MAX_PERF) 371 cppc_perf.highest_perf = HWP_HIGHEST_PERF(READ_ONCE(all_cpu_data[cpu]->hwp_cap_cached)); 372 373 /* 374 * The priorities can be set regardless of whether or not 375 * sched_set_itmt_support(true) has been called and it is valid to 376 * update them at any time after it has been called. 377 */ 378 sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu); 379 380 if (max_highest_perf <= min_highest_perf) { 381 if (cppc_perf.highest_perf > max_highest_perf) 382 max_highest_perf = cppc_perf.highest_perf; 383 384 if (cppc_perf.highest_perf < min_highest_perf) 385 min_highest_perf = cppc_perf.highest_perf; 386 387 if (max_highest_perf > min_highest_perf) { 388 /* 389 * This code can be run during CPU online under the 390 * CPU hotplug locks, so sched_set_itmt_support() 391 * cannot be called from here. Queue up a work item 392 * to invoke it. 393 */ 394 schedule_work(&sched_itmt_work); 395 } 396 } 397 } 398 399 static int intel_pstate_get_cppc_guaranteed(int cpu) 400 { 401 struct cppc_perf_caps cppc_perf; 402 int ret; 403 404 ret = cppc_get_perf_caps(cpu, &cppc_perf); 405 if (ret) 406 return ret; 407 408 if (cppc_perf.guaranteed_perf) 409 return cppc_perf.guaranteed_perf; 410 411 return cppc_perf.nominal_perf; 412 } 413 414 static int intel_pstate_cppc_get_scaling(int cpu) 415 { 416 struct cppc_perf_caps cppc_perf; 417 int ret; 418 419 ret = cppc_get_perf_caps(cpu, &cppc_perf); 420 421 /* 422 * If the nominal frequency and the nominal performance are not 423 * zero and the ratio between them is not 100, return the hybrid 424 * scaling factor. 425 */ 426 if (!ret && cppc_perf.nominal_perf && cppc_perf.nominal_freq && 427 cppc_perf.nominal_perf * 100 != cppc_perf.nominal_freq) 428 return hybrid_scaling_factor; 429 430 return core_get_scaling(); 431 } 432 433 #else /* CONFIG_ACPI_CPPC_LIB */ 434 static inline void intel_pstate_set_itmt_prio(int cpu) 435 { 436 } 437 #endif /* CONFIG_ACPI_CPPC_LIB */ 438 439 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) 440 { 441 struct cpudata *cpu; 442 int ret; 443 int i; 444 445 if (hwp_active) { 446 intel_pstate_set_itmt_prio(policy->cpu); 447 return; 448 } 449 450 if (!intel_pstate_get_ppc_enable_status()) 451 return; 452 453 cpu = all_cpu_data[policy->cpu]; 454 455 ret = acpi_processor_register_performance(&cpu->acpi_perf_data, 456 policy->cpu); 457 if (ret) 458 return; 459 460 /* 461 * Check if the control value in _PSS is for PERF_CTL MSR, which should 462 * guarantee that the states returned by it map to the states in our 463 * list directly. 464 */ 465 if (cpu->acpi_perf_data.control_register.space_id != 466 ACPI_ADR_SPACE_FIXED_HARDWARE) 467 goto err; 468 469 /* 470 * If there is only one entry _PSS, simply ignore _PSS and continue as 471 * usual without taking _PSS into account 472 */ 473 if (cpu->acpi_perf_data.state_count < 2) 474 goto err; 475 476 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu); 477 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) { 478 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n", 479 (i == cpu->acpi_perf_data.state ? '*' : ' '), i, 480 (u32) cpu->acpi_perf_data.states[i].core_frequency, 481 (u32) cpu->acpi_perf_data.states[i].power, 482 (u32) cpu->acpi_perf_data.states[i].control); 483 } 484 485 cpu->valid_pss_table = true; 486 pr_debug("_PPC limits will be enforced\n"); 487 488 return; 489 490 err: 491 cpu->valid_pss_table = false; 492 acpi_processor_unregister_performance(policy->cpu); 493 } 494 495 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) 496 { 497 struct cpudata *cpu; 498 499 cpu = all_cpu_data[policy->cpu]; 500 if (!cpu->valid_pss_table) 501 return; 502 503 acpi_processor_unregister_performance(policy->cpu); 504 } 505 #else /* CONFIG_ACPI */ 506 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) 507 { 508 } 509 510 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) 511 { 512 } 513 514 static inline bool intel_pstate_acpi_pm_profile_server(void) 515 { 516 return false; 517 } 518 #endif /* CONFIG_ACPI */ 519 520 #ifndef CONFIG_ACPI_CPPC_LIB 521 static inline int intel_pstate_get_cppc_guaranteed(int cpu) 522 { 523 return -ENOTSUPP; 524 } 525 526 static int intel_pstate_cppc_get_scaling(int cpu) 527 { 528 return core_get_scaling(); 529 } 530 #endif /* CONFIG_ACPI_CPPC_LIB */ 531 532 static int intel_pstate_freq_to_hwp_rel(struct cpudata *cpu, int freq, 533 unsigned int relation) 534 { 535 if (freq == cpu->pstate.turbo_freq) 536 return cpu->pstate.turbo_pstate; 537 538 if (freq == cpu->pstate.max_freq) 539 return cpu->pstate.max_pstate; 540 541 switch (relation) { 542 case CPUFREQ_RELATION_H: 543 return freq / cpu->pstate.scaling; 544 case CPUFREQ_RELATION_C: 545 return DIV_ROUND_CLOSEST(freq, cpu->pstate.scaling); 546 } 547 548 return DIV_ROUND_UP(freq, cpu->pstate.scaling); 549 } 550 551 static int intel_pstate_freq_to_hwp(struct cpudata *cpu, int freq) 552 { 553 return intel_pstate_freq_to_hwp_rel(cpu, freq, CPUFREQ_RELATION_L); 554 } 555 556 /** 557 * intel_pstate_hybrid_hwp_adjust - Calibrate HWP performance levels. 558 * @cpu: Target CPU. 559 * 560 * On hybrid processors, HWP may expose more performance levels than there are 561 * P-states accessible through the PERF_CTL interface. If that happens, the 562 * scaling factor between HWP performance levels and CPU frequency will be less 563 * than the scaling factor between P-state values and CPU frequency. 564 * 565 * In that case, adjust the CPU parameters used in computations accordingly. 566 */ 567 static void intel_pstate_hybrid_hwp_adjust(struct cpudata *cpu) 568 { 569 int perf_ctl_max_phys = cpu->pstate.max_pstate_physical; 570 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling; 571 int perf_ctl_turbo = pstate_funcs.get_turbo(cpu->cpu); 572 int scaling = cpu->pstate.scaling; 573 int freq; 574 575 pr_debug("CPU%d: perf_ctl_max_phys = %d\n", cpu->cpu, perf_ctl_max_phys); 576 pr_debug("CPU%d: perf_ctl_turbo = %d\n", cpu->cpu, perf_ctl_turbo); 577 pr_debug("CPU%d: perf_ctl_scaling = %d\n", cpu->cpu, perf_ctl_scaling); 578 pr_debug("CPU%d: HWP_CAP guaranteed = %d\n", cpu->cpu, cpu->pstate.max_pstate); 579 pr_debug("CPU%d: HWP_CAP highest = %d\n", cpu->cpu, cpu->pstate.turbo_pstate); 580 pr_debug("CPU%d: HWP-to-frequency scaling factor: %d\n", cpu->cpu, scaling); 581 582 cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_pstate * scaling, 583 perf_ctl_scaling); 584 cpu->pstate.max_freq = rounddown(cpu->pstate.max_pstate * scaling, 585 perf_ctl_scaling); 586 587 freq = perf_ctl_max_phys * perf_ctl_scaling; 588 cpu->pstate.max_pstate_physical = intel_pstate_freq_to_hwp(cpu, freq); 589 590 freq = cpu->pstate.min_pstate * perf_ctl_scaling; 591 cpu->pstate.min_freq = freq; 592 /* 593 * Cast the min P-state value retrieved via pstate_funcs.get_min() to 594 * the effective range of HWP performance levels. 595 */ 596 cpu->pstate.min_pstate = intel_pstate_freq_to_hwp(cpu, freq); 597 } 598 599 static bool turbo_is_disabled(void) 600 { 601 u64 misc_en; 602 603 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en); 604 605 return !!(misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE); 606 } 607 608 static int min_perf_pct_min(void) 609 { 610 struct cpudata *cpu = all_cpu_data[0]; 611 int turbo_pstate = cpu->pstate.turbo_pstate; 612 613 return turbo_pstate ? 614 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0; 615 } 616 617 static s16 intel_pstate_get_epb(struct cpudata *cpu_data) 618 { 619 u64 epb; 620 int ret; 621 622 if (!boot_cpu_has(X86_FEATURE_EPB)) 623 return -ENXIO; 624 625 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb); 626 if (ret) 627 return (s16)ret; 628 629 return (s16)(epb & 0x0f); 630 } 631 632 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data) 633 { 634 s16 epp; 635 636 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 637 /* 638 * When hwp_req_data is 0, means that caller didn't read 639 * MSR_HWP_REQUEST, so need to read and get EPP. 640 */ 641 if (!hwp_req_data) { 642 epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, 643 &hwp_req_data); 644 if (epp) 645 return epp; 646 } 647 epp = (hwp_req_data >> 24) & 0xff; 648 } else { 649 /* When there is no EPP present, HWP uses EPB settings */ 650 epp = intel_pstate_get_epb(cpu_data); 651 } 652 653 return epp; 654 } 655 656 static int intel_pstate_set_epb(int cpu, s16 pref) 657 { 658 u64 epb; 659 int ret; 660 661 if (!boot_cpu_has(X86_FEATURE_EPB)) 662 return -ENXIO; 663 664 ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb); 665 if (ret) 666 return ret; 667 668 epb = (epb & ~0x0f) | pref; 669 wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb); 670 671 return 0; 672 } 673 674 /* 675 * EPP/EPB display strings corresponding to EPP index in the 676 * energy_perf_strings[] 677 * index String 678 *------------------------------------- 679 * 0 default 680 * 1 performance 681 * 2 balance_performance 682 * 3 balance_power 683 * 4 power 684 */ 685 686 enum energy_perf_value_index { 687 EPP_INDEX_DEFAULT = 0, 688 EPP_INDEX_PERFORMANCE, 689 EPP_INDEX_BALANCE_PERFORMANCE, 690 EPP_INDEX_BALANCE_POWERSAVE, 691 EPP_INDEX_POWERSAVE, 692 }; 693 694 static const char * const energy_perf_strings[] = { 695 [EPP_INDEX_DEFAULT] = "default", 696 [EPP_INDEX_PERFORMANCE] = "performance", 697 [EPP_INDEX_BALANCE_PERFORMANCE] = "balance_performance", 698 [EPP_INDEX_BALANCE_POWERSAVE] = "balance_power", 699 [EPP_INDEX_POWERSAVE] = "power", 700 NULL 701 }; 702 static unsigned int epp_values[] = { 703 [EPP_INDEX_DEFAULT] = 0, /* Unused index */ 704 [EPP_INDEX_PERFORMANCE] = HWP_EPP_PERFORMANCE, 705 [EPP_INDEX_BALANCE_PERFORMANCE] = HWP_EPP_BALANCE_PERFORMANCE, 706 [EPP_INDEX_BALANCE_POWERSAVE] = HWP_EPP_BALANCE_POWERSAVE, 707 [EPP_INDEX_POWERSAVE] = HWP_EPP_POWERSAVE, 708 }; 709 710 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data, int *raw_epp) 711 { 712 s16 epp; 713 int index = -EINVAL; 714 715 *raw_epp = 0; 716 epp = intel_pstate_get_epp(cpu_data, 0); 717 if (epp < 0) 718 return epp; 719 720 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 721 if (epp == epp_values[EPP_INDEX_PERFORMANCE]) 722 return EPP_INDEX_PERFORMANCE; 723 if (epp == epp_values[EPP_INDEX_BALANCE_PERFORMANCE]) 724 return EPP_INDEX_BALANCE_PERFORMANCE; 725 if (epp == epp_values[EPP_INDEX_BALANCE_POWERSAVE]) 726 return EPP_INDEX_BALANCE_POWERSAVE; 727 if (epp == epp_values[EPP_INDEX_POWERSAVE]) 728 return EPP_INDEX_POWERSAVE; 729 *raw_epp = epp; 730 return 0; 731 } else if (boot_cpu_has(X86_FEATURE_EPB)) { 732 /* 733 * Range: 734 * 0x00-0x03 : Performance 735 * 0x04-0x07 : Balance performance 736 * 0x08-0x0B : Balance power 737 * 0x0C-0x0F : Power 738 * The EPB is a 4 bit value, but our ranges restrict the 739 * value which can be set. Here only using top two bits 740 * effectively. 741 */ 742 index = (epp >> 2) + 1; 743 } 744 745 return index; 746 } 747 748 static int intel_pstate_set_epp(struct cpudata *cpu, u32 epp) 749 { 750 int ret; 751 752 /* 753 * Use the cached HWP Request MSR value, because in the active mode the 754 * register itself may be updated by intel_pstate_hwp_boost_up() or 755 * intel_pstate_hwp_boost_down() at any time. 756 */ 757 u64 value = READ_ONCE(cpu->hwp_req_cached); 758 759 value &= ~GENMASK_ULL(31, 24); 760 value |= (u64)epp << 24; 761 /* 762 * The only other updater of hwp_req_cached in the active mode, 763 * intel_pstate_hwp_set(), is called under the same lock as this 764 * function, so it cannot run in parallel with the update below. 765 */ 766 WRITE_ONCE(cpu->hwp_req_cached, value); 767 ret = wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 768 if (!ret) 769 cpu->epp_cached = epp; 770 771 return ret; 772 } 773 774 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data, 775 int pref_index, bool use_raw, 776 u32 raw_epp) 777 { 778 int epp = -EINVAL; 779 int ret; 780 781 if (!pref_index) 782 epp = cpu_data->epp_default; 783 784 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 785 if (use_raw) 786 epp = raw_epp; 787 else if (epp == -EINVAL) 788 epp = epp_values[pref_index]; 789 790 /* 791 * To avoid confusion, refuse to set EPP to any values different 792 * from 0 (performance) if the current policy is "performance", 793 * because those values would be overridden. 794 */ 795 if (epp > 0 && cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) 796 return -EBUSY; 797 798 ret = intel_pstate_set_epp(cpu_data, epp); 799 } else { 800 if (epp == -EINVAL) 801 epp = (pref_index - 1) << 2; 802 ret = intel_pstate_set_epb(cpu_data->cpu, epp); 803 } 804 805 return ret; 806 } 807 808 static ssize_t show_energy_performance_available_preferences( 809 struct cpufreq_policy *policy, char *buf) 810 { 811 int i = 0; 812 int ret = 0; 813 814 while (energy_perf_strings[i] != NULL) 815 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]); 816 817 ret += sprintf(&buf[ret], "\n"); 818 819 return ret; 820 } 821 822 cpufreq_freq_attr_ro(energy_performance_available_preferences); 823 824 static struct cpufreq_driver intel_pstate; 825 826 static ssize_t store_energy_performance_preference( 827 struct cpufreq_policy *policy, const char *buf, size_t count) 828 { 829 struct cpudata *cpu = all_cpu_data[policy->cpu]; 830 char str_preference[21]; 831 bool raw = false; 832 ssize_t ret; 833 u32 epp = 0; 834 835 ret = sscanf(buf, "%20s", str_preference); 836 if (ret != 1) 837 return -EINVAL; 838 839 ret = match_string(energy_perf_strings, -1, str_preference); 840 if (ret < 0) { 841 if (!boot_cpu_has(X86_FEATURE_HWP_EPP)) 842 return ret; 843 844 ret = kstrtouint(buf, 10, &epp); 845 if (ret) 846 return ret; 847 848 if (epp > 255) 849 return -EINVAL; 850 851 raw = true; 852 } 853 854 /* 855 * This function runs with the policy R/W semaphore held, which 856 * guarantees that the driver pointer will not change while it is 857 * running. 858 */ 859 if (!intel_pstate_driver) 860 return -EAGAIN; 861 862 mutex_lock(&intel_pstate_limits_lock); 863 864 if (intel_pstate_driver == &intel_pstate) { 865 ret = intel_pstate_set_energy_pref_index(cpu, ret, raw, epp); 866 } else { 867 /* 868 * In the passive mode the governor needs to be stopped on the 869 * target CPU before the EPP update and restarted after it, 870 * which is super-heavy-weight, so make sure it is worth doing 871 * upfront. 872 */ 873 if (!raw) 874 epp = ret ? epp_values[ret] : cpu->epp_default; 875 876 if (cpu->epp_cached != epp) { 877 int err; 878 879 cpufreq_stop_governor(policy); 880 ret = intel_pstate_set_epp(cpu, epp); 881 err = cpufreq_start_governor(policy); 882 if (!ret) 883 ret = err; 884 } else { 885 ret = 0; 886 } 887 } 888 889 mutex_unlock(&intel_pstate_limits_lock); 890 891 return ret ?: count; 892 } 893 894 static ssize_t show_energy_performance_preference( 895 struct cpufreq_policy *policy, char *buf) 896 { 897 struct cpudata *cpu_data = all_cpu_data[policy->cpu]; 898 int preference, raw_epp; 899 900 preference = intel_pstate_get_energy_pref_index(cpu_data, &raw_epp); 901 if (preference < 0) 902 return preference; 903 904 if (raw_epp) 905 return sprintf(buf, "%d\n", raw_epp); 906 else 907 return sprintf(buf, "%s\n", energy_perf_strings[preference]); 908 } 909 910 cpufreq_freq_attr_rw(energy_performance_preference); 911 912 static ssize_t show_base_frequency(struct cpufreq_policy *policy, char *buf) 913 { 914 struct cpudata *cpu = all_cpu_data[policy->cpu]; 915 int ratio, freq; 916 917 ratio = intel_pstate_get_cppc_guaranteed(policy->cpu); 918 if (ratio <= 0) { 919 u64 cap; 920 921 rdmsrl_on_cpu(policy->cpu, MSR_HWP_CAPABILITIES, &cap); 922 ratio = HWP_GUARANTEED_PERF(cap); 923 } 924 925 freq = ratio * cpu->pstate.scaling; 926 if (cpu->pstate.scaling != cpu->pstate.perf_ctl_scaling) 927 freq = rounddown(freq, cpu->pstate.perf_ctl_scaling); 928 929 return sprintf(buf, "%d\n", freq); 930 } 931 932 cpufreq_freq_attr_ro(base_frequency); 933 934 static struct freq_attr *hwp_cpufreq_attrs[] = { 935 &energy_performance_preference, 936 &energy_performance_available_preferences, 937 &base_frequency, 938 NULL, 939 }; 940 941 static struct cpudata *hybrid_max_perf_cpu __read_mostly; 942 /* 943 * Protects hybrid_max_perf_cpu, the capacity_perf fields in struct cpudata, 944 * and the x86 arch scale-invariance information from concurrent updates. 945 */ 946 static DEFINE_MUTEX(hybrid_capacity_lock); 947 948 static void hybrid_set_cpu_capacity(struct cpudata *cpu) 949 { 950 arch_set_cpu_capacity(cpu->cpu, cpu->capacity_perf, 951 hybrid_max_perf_cpu->capacity_perf, 952 cpu->capacity_perf, 953 cpu->pstate.max_pstate_physical); 954 955 pr_debug("CPU%d: perf = %u, max. perf = %u, base perf = %d\n", cpu->cpu, 956 cpu->capacity_perf, hybrid_max_perf_cpu->capacity_perf, 957 cpu->pstate.max_pstate_physical); 958 } 959 960 static void hybrid_clear_cpu_capacity(unsigned int cpunum) 961 { 962 arch_set_cpu_capacity(cpunum, 1, 1, 1, 1); 963 } 964 965 static void hybrid_get_capacity_perf(struct cpudata *cpu) 966 { 967 if (READ_ONCE(global.no_turbo)) { 968 cpu->capacity_perf = cpu->pstate.max_pstate_physical; 969 return; 970 } 971 972 cpu->capacity_perf = HWP_HIGHEST_PERF(READ_ONCE(cpu->hwp_cap_cached)); 973 } 974 975 static void hybrid_set_capacity_of_cpus(void) 976 { 977 int cpunum; 978 979 for_each_online_cpu(cpunum) { 980 struct cpudata *cpu = all_cpu_data[cpunum]; 981 982 if (cpu) 983 hybrid_set_cpu_capacity(cpu); 984 } 985 } 986 987 static void hybrid_update_cpu_capacity_scaling(void) 988 { 989 struct cpudata *max_perf_cpu = NULL; 990 unsigned int max_cap_perf = 0; 991 int cpunum; 992 993 for_each_online_cpu(cpunum) { 994 struct cpudata *cpu = all_cpu_data[cpunum]; 995 996 if (!cpu) 997 continue; 998 999 /* 1000 * During initialization, CPU performance at full capacity needs 1001 * to be determined. 1002 */ 1003 if (!hybrid_max_perf_cpu) 1004 hybrid_get_capacity_perf(cpu); 1005 1006 /* 1007 * If hybrid_max_perf_cpu is not NULL at this point, it is 1008 * being replaced, so don't take it into account when looking 1009 * for the new one. 1010 */ 1011 if (cpu == hybrid_max_perf_cpu) 1012 continue; 1013 1014 if (cpu->capacity_perf > max_cap_perf) { 1015 max_cap_perf = cpu->capacity_perf; 1016 max_perf_cpu = cpu; 1017 } 1018 } 1019 1020 if (max_perf_cpu) { 1021 hybrid_max_perf_cpu = max_perf_cpu; 1022 hybrid_set_capacity_of_cpus(); 1023 } else { 1024 pr_info("Found no CPUs with nonzero maximum performance\n"); 1025 /* Revert to the flat CPU capacity structure. */ 1026 for_each_online_cpu(cpunum) 1027 hybrid_clear_cpu_capacity(cpunum); 1028 } 1029 } 1030 1031 static void __hybrid_init_cpu_capacity_scaling(void) 1032 { 1033 hybrid_max_perf_cpu = NULL; 1034 hybrid_update_cpu_capacity_scaling(); 1035 } 1036 1037 static void hybrid_init_cpu_capacity_scaling(bool refresh) 1038 { 1039 bool disable_itmt = false; 1040 1041 mutex_lock(&hybrid_capacity_lock); 1042 1043 /* 1044 * If hybrid_max_perf_cpu is set at this point, the hybrid CPU capacity 1045 * scaling has been enabled already and the driver is just changing the 1046 * operation mode. 1047 */ 1048 if (refresh) { 1049 __hybrid_init_cpu_capacity_scaling(); 1050 goto unlock; 1051 } 1052 1053 /* 1054 * On hybrid systems, use asym capacity instead of ITMT, but because 1055 * the capacity of SMT threads is not deterministic even approximately, 1056 * do not do that when SMT is in use. 1057 */ 1058 if (hwp_is_hybrid && !sched_smt_active() && arch_enable_hybrid_capacity_scale()) { 1059 __hybrid_init_cpu_capacity_scaling(); 1060 disable_itmt = true; 1061 } 1062 1063 unlock: 1064 mutex_unlock(&hybrid_capacity_lock); 1065 1066 /* 1067 * Disabling ITMT causes sched domains to be rebuilt to disable asym 1068 * packing and enable asym capacity. 1069 */ 1070 if (disable_itmt) 1071 sched_clear_itmt_support(); 1072 } 1073 1074 static bool hybrid_clear_max_perf_cpu(void) 1075 { 1076 bool ret; 1077 1078 guard(mutex)(&hybrid_capacity_lock); 1079 1080 ret = !!hybrid_max_perf_cpu; 1081 hybrid_max_perf_cpu = NULL; 1082 1083 return ret; 1084 } 1085 1086 static void __intel_pstate_get_hwp_cap(struct cpudata *cpu) 1087 { 1088 u64 cap; 1089 1090 rdmsrl_on_cpu(cpu->cpu, MSR_HWP_CAPABILITIES, &cap); 1091 WRITE_ONCE(cpu->hwp_cap_cached, cap); 1092 cpu->pstate.max_pstate = HWP_GUARANTEED_PERF(cap); 1093 cpu->pstate.turbo_pstate = HWP_HIGHEST_PERF(cap); 1094 } 1095 1096 static void intel_pstate_get_hwp_cap(struct cpudata *cpu) 1097 { 1098 int scaling = cpu->pstate.scaling; 1099 1100 __intel_pstate_get_hwp_cap(cpu); 1101 1102 cpu->pstate.max_freq = cpu->pstate.max_pstate * scaling; 1103 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * scaling; 1104 if (scaling != cpu->pstate.perf_ctl_scaling) { 1105 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling; 1106 1107 cpu->pstate.max_freq = rounddown(cpu->pstate.max_freq, 1108 perf_ctl_scaling); 1109 cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_freq, 1110 perf_ctl_scaling); 1111 } 1112 } 1113 1114 static void hybrid_update_capacity(struct cpudata *cpu) 1115 { 1116 unsigned int max_cap_perf; 1117 1118 mutex_lock(&hybrid_capacity_lock); 1119 1120 if (!hybrid_max_perf_cpu) 1121 goto unlock; 1122 1123 /* 1124 * The maximum performance of the CPU may have changed, but assume 1125 * that the performance of the other CPUs has not changed. 1126 */ 1127 max_cap_perf = hybrid_max_perf_cpu->capacity_perf; 1128 1129 intel_pstate_get_hwp_cap(cpu); 1130 1131 hybrid_get_capacity_perf(cpu); 1132 /* Should hybrid_max_perf_cpu be replaced by this CPU? */ 1133 if (cpu->capacity_perf > max_cap_perf) { 1134 hybrid_max_perf_cpu = cpu; 1135 hybrid_set_capacity_of_cpus(); 1136 goto unlock; 1137 } 1138 1139 /* If this CPU is hybrid_max_perf_cpu, should it be replaced? */ 1140 if (cpu == hybrid_max_perf_cpu && cpu->capacity_perf < max_cap_perf) { 1141 hybrid_update_cpu_capacity_scaling(); 1142 goto unlock; 1143 } 1144 1145 hybrid_set_cpu_capacity(cpu); 1146 1147 unlock: 1148 mutex_unlock(&hybrid_capacity_lock); 1149 } 1150 1151 static void intel_pstate_hwp_set(unsigned int cpu) 1152 { 1153 struct cpudata *cpu_data = all_cpu_data[cpu]; 1154 int max, min; 1155 u64 value; 1156 s16 epp; 1157 1158 max = cpu_data->max_perf_ratio; 1159 min = cpu_data->min_perf_ratio; 1160 1161 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) 1162 min = max; 1163 1164 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value); 1165 1166 value &= ~HWP_MIN_PERF(~0L); 1167 value |= HWP_MIN_PERF(min); 1168 1169 value &= ~HWP_MAX_PERF(~0L); 1170 value |= HWP_MAX_PERF(max); 1171 1172 if (cpu_data->epp_policy == cpu_data->policy) 1173 goto skip_epp; 1174 1175 cpu_data->epp_policy = cpu_data->policy; 1176 1177 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) { 1178 epp = intel_pstate_get_epp(cpu_data, value); 1179 cpu_data->epp_powersave = epp; 1180 /* If EPP read was failed, then don't try to write */ 1181 if (epp < 0) 1182 goto skip_epp; 1183 1184 epp = 0; 1185 } else { 1186 /* skip setting EPP, when saved value is invalid */ 1187 if (cpu_data->epp_powersave < 0) 1188 goto skip_epp; 1189 1190 /* 1191 * No need to restore EPP when it is not zero. This 1192 * means: 1193 * - Policy is not changed 1194 * - user has manually changed 1195 * - Error reading EPB 1196 */ 1197 epp = intel_pstate_get_epp(cpu_data, value); 1198 if (epp) 1199 goto skip_epp; 1200 1201 epp = cpu_data->epp_powersave; 1202 } 1203 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 1204 value &= ~GENMASK_ULL(31, 24); 1205 value |= (u64)epp << 24; 1206 } else { 1207 intel_pstate_set_epb(cpu, epp); 1208 } 1209 skip_epp: 1210 WRITE_ONCE(cpu_data->hwp_req_cached, value); 1211 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value); 1212 } 1213 1214 static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata); 1215 1216 static void intel_pstate_hwp_offline(struct cpudata *cpu) 1217 { 1218 u64 value = READ_ONCE(cpu->hwp_req_cached); 1219 int min_perf; 1220 1221 intel_pstate_disable_hwp_interrupt(cpu); 1222 1223 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 1224 /* 1225 * In case the EPP has been set to "performance" by the 1226 * active mode "performance" scaling algorithm, replace that 1227 * temporary value with the cached EPP one. 1228 */ 1229 value &= ~GENMASK_ULL(31, 24); 1230 value |= HWP_ENERGY_PERF_PREFERENCE(cpu->epp_cached); 1231 /* 1232 * However, make sure that EPP will be set to "performance" when 1233 * the CPU is brought back online again and the "performance" 1234 * scaling algorithm is still in effect. 1235 */ 1236 cpu->epp_policy = CPUFREQ_POLICY_UNKNOWN; 1237 } 1238 1239 /* 1240 * Clear the desired perf field in the cached HWP request value to 1241 * prevent nonzero desired values from being leaked into the active 1242 * mode. 1243 */ 1244 value &= ~HWP_DESIRED_PERF(~0L); 1245 WRITE_ONCE(cpu->hwp_req_cached, value); 1246 1247 value &= ~GENMASK_ULL(31, 0); 1248 min_perf = HWP_LOWEST_PERF(READ_ONCE(cpu->hwp_cap_cached)); 1249 1250 /* Set hwp_max = hwp_min */ 1251 value |= HWP_MAX_PERF(min_perf); 1252 value |= HWP_MIN_PERF(min_perf); 1253 1254 /* Set EPP to min */ 1255 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) 1256 value |= HWP_ENERGY_PERF_PREFERENCE(HWP_EPP_POWERSAVE); 1257 1258 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 1259 1260 mutex_lock(&hybrid_capacity_lock); 1261 1262 if (!hybrid_max_perf_cpu) { 1263 mutex_unlock(&hybrid_capacity_lock); 1264 1265 return; 1266 } 1267 1268 if (hybrid_max_perf_cpu == cpu) 1269 hybrid_update_cpu_capacity_scaling(); 1270 1271 mutex_unlock(&hybrid_capacity_lock); 1272 1273 /* Reset the capacity of the CPU going offline to the initial value. */ 1274 hybrid_clear_cpu_capacity(cpu->cpu); 1275 } 1276 1277 #define POWER_CTL_EE_ENABLE 1 1278 #define POWER_CTL_EE_DISABLE 2 1279 1280 static int power_ctl_ee_state; 1281 1282 static void set_power_ctl_ee_state(bool input) 1283 { 1284 u64 power_ctl; 1285 1286 mutex_lock(&intel_pstate_driver_lock); 1287 rdmsrl(MSR_IA32_POWER_CTL, power_ctl); 1288 if (input) { 1289 power_ctl &= ~BIT(MSR_IA32_POWER_CTL_BIT_EE); 1290 power_ctl_ee_state = POWER_CTL_EE_ENABLE; 1291 } else { 1292 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE); 1293 power_ctl_ee_state = POWER_CTL_EE_DISABLE; 1294 } 1295 wrmsrl(MSR_IA32_POWER_CTL, power_ctl); 1296 mutex_unlock(&intel_pstate_driver_lock); 1297 } 1298 1299 static void intel_pstate_hwp_enable(struct cpudata *cpudata); 1300 1301 static void intel_pstate_hwp_reenable(struct cpudata *cpu) 1302 { 1303 intel_pstate_hwp_enable(cpu); 1304 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, READ_ONCE(cpu->hwp_req_cached)); 1305 } 1306 1307 static int intel_pstate_suspend(struct cpufreq_policy *policy) 1308 { 1309 struct cpudata *cpu = all_cpu_data[policy->cpu]; 1310 1311 pr_debug("CPU %d suspending\n", cpu->cpu); 1312 1313 cpu->suspended = true; 1314 1315 /* disable HWP interrupt and cancel any pending work */ 1316 intel_pstate_disable_hwp_interrupt(cpu); 1317 1318 return 0; 1319 } 1320 1321 static int intel_pstate_resume(struct cpufreq_policy *policy) 1322 { 1323 struct cpudata *cpu = all_cpu_data[policy->cpu]; 1324 1325 pr_debug("CPU %d resuming\n", cpu->cpu); 1326 1327 /* Only restore if the system default is changed */ 1328 if (power_ctl_ee_state == POWER_CTL_EE_ENABLE) 1329 set_power_ctl_ee_state(true); 1330 else if (power_ctl_ee_state == POWER_CTL_EE_DISABLE) 1331 set_power_ctl_ee_state(false); 1332 1333 if (cpu->suspended && hwp_active) { 1334 mutex_lock(&intel_pstate_limits_lock); 1335 1336 /* Re-enable HWP, because "online" has not done that. */ 1337 intel_pstate_hwp_reenable(cpu); 1338 1339 mutex_unlock(&intel_pstate_limits_lock); 1340 } 1341 1342 cpu->suspended = false; 1343 1344 return 0; 1345 } 1346 1347 static void intel_pstate_update_policies(void) 1348 { 1349 int cpu; 1350 1351 for_each_possible_cpu(cpu) 1352 cpufreq_update_policy(cpu); 1353 } 1354 1355 static void __intel_pstate_update_max_freq(struct cpudata *cpudata, 1356 struct cpufreq_policy *policy) 1357 { 1358 if (hwp_active) 1359 intel_pstate_get_hwp_cap(cpudata); 1360 1361 policy->cpuinfo.max_freq = READ_ONCE(global.no_turbo) ? 1362 cpudata->pstate.max_freq : cpudata->pstate.turbo_freq; 1363 1364 refresh_frequency_limits(policy); 1365 } 1366 1367 static void intel_pstate_update_limits(unsigned int cpu) 1368 { 1369 struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpu); 1370 struct cpudata *cpudata; 1371 1372 if (!policy) 1373 return; 1374 1375 cpudata = all_cpu_data[cpu]; 1376 1377 __intel_pstate_update_max_freq(cpudata, policy); 1378 1379 /* Prevent the driver from being unregistered now. */ 1380 mutex_lock(&intel_pstate_driver_lock); 1381 1382 cpufreq_cpu_release(policy); 1383 1384 hybrid_update_capacity(cpudata); 1385 1386 mutex_unlock(&intel_pstate_driver_lock); 1387 } 1388 1389 static void intel_pstate_update_limits_for_all(void) 1390 { 1391 int cpu; 1392 1393 for_each_possible_cpu(cpu) { 1394 struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpu); 1395 1396 if (!policy) 1397 continue; 1398 1399 __intel_pstate_update_max_freq(all_cpu_data[cpu], policy); 1400 1401 cpufreq_cpu_release(policy); 1402 } 1403 1404 mutex_lock(&hybrid_capacity_lock); 1405 1406 if (hybrid_max_perf_cpu) 1407 __hybrid_init_cpu_capacity_scaling(); 1408 1409 mutex_unlock(&hybrid_capacity_lock); 1410 } 1411 1412 /************************** sysfs begin ************************/ 1413 #define show_one(file_name, object) \ 1414 static ssize_t show_##file_name \ 1415 (struct kobject *kobj, struct kobj_attribute *attr, char *buf) \ 1416 { \ 1417 return sprintf(buf, "%u\n", global.object); \ 1418 } 1419 1420 static ssize_t intel_pstate_show_status(char *buf); 1421 static int intel_pstate_update_status(const char *buf, size_t size); 1422 1423 static ssize_t show_status(struct kobject *kobj, 1424 struct kobj_attribute *attr, char *buf) 1425 { 1426 ssize_t ret; 1427 1428 mutex_lock(&intel_pstate_driver_lock); 1429 ret = intel_pstate_show_status(buf); 1430 mutex_unlock(&intel_pstate_driver_lock); 1431 1432 return ret; 1433 } 1434 1435 static ssize_t store_status(struct kobject *a, struct kobj_attribute *b, 1436 const char *buf, size_t count) 1437 { 1438 char *p = memchr(buf, '\n', count); 1439 int ret; 1440 1441 mutex_lock(&intel_pstate_driver_lock); 1442 ret = intel_pstate_update_status(buf, p ? p - buf : count); 1443 mutex_unlock(&intel_pstate_driver_lock); 1444 1445 return ret < 0 ? ret : count; 1446 } 1447 1448 static ssize_t show_turbo_pct(struct kobject *kobj, 1449 struct kobj_attribute *attr, char *buf) 1450 { 1451 struct cpudata *cpu; 1452 int total, no_turbo, turbo_pct; 1453 uint32_t turbo_fp; 1454 1455 mutex_lock(&intel_pstate_driver_lock); 1456 1457 if (!intel_pstate_driver) { 1458 mutex_unlock(&intel_pstate_driver_lock); 1459 return -EAGAIN; 1460 } 1461 1462 cpu = all_cpu_data[0]; 1463 1464 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; 1465 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1; 1466 turbo_fp = div_fp(no_turbo, total); 1467 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100))); 1468 1469 mutex_unlock(&intel_pstate_driver_lock); 1470 1471 return sprintf(buf, "%u\n", turbo_pct); 1472 } 1473 1474 static ssize_t show_num_pstates(struct kobject *kobj, 1475 struct kobj_attribute *attr, char *buf) 1476 { 1477 struct cpudata *cpu; 1478 int total; 1479 1480 mutex_lock(&intel_pstate_driver_lock); 1481 1482 if (!intel_pstate_driver) { 1483 mutex_unlock(&intel_pstate_driver_lock); 1484 return -EAGAIN; 1485 } 1486 1487 cpu = all_cpu_data[0]; 1488 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; 1489 1490 mutex_unlock(&intel_pstate_driver_lock); 1491 1492 return sprintf(buf, "%u\n", total); 1493 } 1494 1495 static ssize_t show_no_turbo(struct kobject *kobj, 1496 struct kobj_attribute *attr, char *buf) 1497 { 1498 ssize_t ret; 1499 1500 mutex_lock(&intel_pstate_driver_lock); 1501 1502 if (!intel_pstate_driver) { 1503 mutex_unlock(&intel_pstate_driver_lock); 1504 return -EAGAIN; 1505 } 1506 1507 ret = sprintf(buf, "%u\n", global.no_turbo); 1508 1509 mutex_unlock(&intel_pstate_driver_lock); 1510 1511 return ret; 1512 } 1513 1514 static ssize_t store_no_turbo(struct kobject *a, struct kobj_attribute *b, 1515 const char *buf, size_t count) 1516 { 1517 unsigned int input; 1518 bool no_turbo; 1519 1520 if (sscanf(buf, "%u", &input) != 1) 1521 return -EINVAL; 1522 1523 mutex_lock(&intel_pstate_driver_lock); 1524 1525 if (!intel_pstate_driver) { 1526 count = -EAGAIN; 1527 goto unlock_driver; 1528 } 1529 1530 no_turbo = !!clamp_t(int, input, 0, 1); 1531 1532 WRITE_ONCE(global.turbo_disabled, turbo_is_disabled()); 1533 if (global.turbo_disabled && !no_turbo) { 1534 pr_notice("Turbo disabled by BIOS or unavailable on processor\n"); 1535 count = -EPERM; 1536 if (global.no_turbo) 1537 goto unlock_driver; 1538 else 1539 no_turbo = 1; 1540 } 1541 1542 if (no_turbo == global.no_turbo) { 1543 goto unlock_driver; 1544 } 1545 1546 WRITE_ONCE(global.no_turbo, no_turbo); 1547 1548 mutex_lock(&intel_pstate_limits_lock); 1549 1550 if (no_turbo) { 1551 struct cpudata *cpu = all_cpu_data[0]; 1552 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate; 1553 1554 /* Squash the global minimum into the permitted range. */ 1555 if (global.min_perf_pct > pct) 1556 global.min_perf_pct = pct; 1557 } 1558 1559 mutex_unlock(&intel_pstate_limits_lock); 1560 1561 intel_pstate_update_limits_for_all(); 1562 arch_set_max_freq_ratio(no_turbo); 1563 1564 unlock_driver: 1565 mutex_unlock(&intel_pstate_driver_lock); 1566 1567 return count; 1568 } 1569 1570 static void update_qos_request(enum freq_qos_req_type type) 1571 { 1572 struct freq_qos_request *req; 1573 struct cpufreq_policy *policy; 1574 int i; 1575 1576 for_each_possible_cpu(i) { 1577 struct cpudata *cpu = all_cpu_data[i]; 1578 unsigned int freq, perf_pct; 1579 1580 policy = cpufreq_cpu_get(i); 1581 if (!policy) 1582 continue; 1583 1584 req = policy->driver_data; 1585 cpufreq_cpu_put(policy); 1586 1587 if (!req) 1588 continue; 1589 1590 if (hwp_active) 1591 intel_pstate_get_hwp_cap(cpu); 1592 1593 if (type == FREQ_QOS_MIN) { 1594 perf_pct = global.min_perf_pct; 1595 } else { 1596 req++; 1597 perf_pct = global.max_perf_pct; 1598 } 1599 1600 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * perf_pct, 100); 1601 1602 if (freq_qos_update_request(req, freq) < 0) 1603 pr_warn("Failed to update freq constraint: CPU%d\n", i); 1604 } 1605 } 1606 1607 static ssize_t store_max_perf_pct(struct kobject *a, struct kobj_attribute *b, 1608 const char *buf, size_t count) 1609 { 1610 unsigned int input; 1611 int ret; 1612 1613 ret = sscanf(buf, "%u", &input); 1614 if (ret != 1) 1615 return -EINVAL; 1616 1617 mutex_lock(&intel_pstate_driver_lock); 1618 1619 if (!intel_pstate_driver) { 1620 mutex_unlock(&intel_pstate_driver_lock); 1621 return -EAGAIN; 1622 } 1623 1624 mutex_lock(&intel_pstate_limits_lock); 1625 1626 global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100); 1627 1628 mutex_unlock(&intel_pstate_limits_lock); 1629 1630 if (intel_pstate_driver == &intel_pstate) 1631 intel_pstate_update_policies(); 1632 else 1633 update_qos_request(FREQ_QOS_MAX); 1634 1635 mutex_unlock(&intel_pstate_driver_lock); 1636 1637 return count; 1638 } 1639 1640 static ssize_t store_min_perf_pct(struct kobject *a, struct kobj_attribute *b, 1641 const char *buf, size_t count) 1642 { 1643 unsigned int input; 1644 int ret; 1645 1646 ret = sscanf(buf, "%u", &input); 1647 if (ret != 1) 1648 return -EINVAL; 1649 1650 mutex_lock(&intel_pstate_driver_lock); 1651 1652 if (!intel_pstate_driver) { 1653 mutex_unlock(&intel_pstate_driver_lock); 1654 return -EAGAIN; 1655 } 1656 1657 mutex_lock(&intel_pstate_limits_lock); 1658 1659 global.min_perf_pct = clamp_t(int, input, 1660 min_perf_pct_min(), global.max_perf_pct); 1661 1662 mutex_unlock(&intel_pstate_limits_lock); 1663 1664 if (intel_pstate_driver == &intel_pstate) 1665 intel_pstate_update_policies(); 1666 else 1667 update_qos_request(FREQ_QOS_MIN); 1668 1669 mutex_unlock(&intel_pstate_driver_lock); 1670 1671 return count; 1672 } 1673 1674 static ssize_t show_hwp_dynamic_boost(struct kobject *kobj, 1675 struct kobj_attribute *attr, char *buf) 1676 { 1677 return sprintf(buf, "%u\n", hwp_boost); 1678 } 1679 1680 static ssize_t store_hwp_dynamic_boost(struct kobject *a, 1681 struct kobj_attribute *b, 1682 const char *buf, size_t count) 1683 { 1684 unsigned int input; 1685 int ret; 1686 1687 ret = kstrtouint(buf, 10, &input); 1688 if (ret) 1689 return ret; 1690 1691 mutex_lock(&intel_pstate_driver_lock); 1692 hwp_boost = !!input; 1693 intel_pstate_update_policies(); 1694 mutex_unlock(&intel_pstate_driver_lock); 1695 1696 return count; 1697 } 1698 1699 static ssize_t show_energy_efficiency(struct kobject *kobj, struct kobj_attribute *attr, 1700 char *buf) 1701 { 1702 u64 power_ctl; 1703 int enable; 1704 1705 rdmsrl(MSR_IA32_POWER_CTL, power_ctl); 1706 enable = !!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE)); 1707 return sprintf(buf, "%d\n", !enable); 1708 } 1709 1710 static ssize_t store_energy_efficiency(struct kobject *a, struct kobj_attribute *b, 1711 const char *buf, size_t count) 1712 { 1713 bool input; 1714 int ret; 1715 1716 ret = kstrtobool(buf, &input); 1717 if (ret) 1718 return ret; 1719 1720 set_power_ctl_ee_state(input); 1721 1722 return count; 1723 } 1724 1725 show_one(max_perf_pct, max_perf_pct); 1726 show_one(min_perf_pct, min_perf_pct); 1727 1728 define_one_global_rw(status); 1729 define_one_global_rw(no_turbo); 1730 define_one_global_rw(max_perf_pct); 1731 define_one_global_rw(min_perf_pct); 1732 define_one_global_ro(turbo_pct); 1733 define_one_global_ro(num_pstates); 1734 define_one_global_rw(hwp_dynamic_boost); 1735 define_one_global_rw(energy_efficiency); 1736 1737 static struct attribute *intel_pstate_attributes[] = { 1738 &status.attr, 1739 &no_turbo.attr, 1740 NULL 1741 }; 1742 1743 static const struct attribute_group intel_pstate_attr_group = { 1744 .attrs = intel_pstate_attributes, 1745 }; 1746 1747 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[]; 1748 1749 static struct kobject *intel_pstate_kobject; 1750 1751 static void __init intel_pstate_sysfs_expose_params(void) 1752 { 1753 struct device *dev_root = bus_get_dev_root(&cpu_subsys); 1754 int rc; 1755 1756 if (dev_root) { 1757 intel_pstate_kobject = kobject_create_and_add("intel_pstate", &dev_root->kobj); 1758 put_device(dev_root); 1759 } 1760 if (WARN_ON(!intel_pstate_kobject)) 1761 return; 1762 1763 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group); 1764 if (WARN_ON(rc)) 1765 return; 1766 1767 if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) { 1768 rc = sysfs_create_file(intel_pstate_kobject, &turbo_pct.attr); 1769 WARN_ON(rc); 1770 1771 rc = sysfs_create_file(intel_pstate_kobject, &num_pstates.attr); 1772 WARN_ON(rc); 1773 } 1774 1775 /* 1776 * If per cpu limits are enforced there are no global limits, so 1777 * return without creating max/min_perf_pct attributes 1778 */ 1779 if (per_cpu_limits) 1780 return; 1781 1782 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr); 1783 WARN_ON(rc); 1784 1785 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr); 1786 WARN_ON(rc); 1787 1788 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids)) { 1789 rc = sysfs_create_file(intel_pstate_kobject, &energy_efficiency.attr); 1790 WARN_ON(rc); 1791 } 1792 } 1793 1794 static void __init intel_pstate_sysfs_remove(void) 1795 { 1796 if (!intel_pstate_kobject) 1797 return; 1798 1799 sysfs_remove_group(intel_pstate_kobject, &intel_pstate_attr_group); 1800 1801 if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) { 1802 sysfs_remove_file(intel_pstate_kobject, &num_pstates.attr); 1803 sysfs_remove_file(intel_pstate_kobject, &turbo_pct.attr); 1804 } 1805 1806 if (!per_cpu_limits) { 1807 sysfs_remove_file(intel_pstate_kobject, &max_perf_pct.attr); 1808 sysfs_remove_file(intel_pstate_kobject, &min_perf_pct.attr); 1809 1810 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids)) 1811 sysfs_remove_file(intel_pstate_kobject, &energy_efficiency.attr); 1812 } 1813 1814 kobject_put(intel_pstate_kobject); 1815 } 1816 1817 static void intel_pstate_sysfs_expose_hwp_dynamic_boost(void) 1818 { 1819 int rc; 1820 1821 if (!hwp_active) 1822 return; 1823 1824 rc = sysfs_create_file(intel_pstate_kobject, &hwp_dynamic_boost.attr); 1825 WARN_ON_ONCE(rc); 1826 } 1827 1828 static void intel_pstate_sysfs_hide_hwp_dynamic_boost(void) 1829 { 1830 if (!hwp_active) 1831 return; 1832 1833 sysfs_remove_file(intel_pstate_kobject, &hwp_dynamic_boost.attr); 1834 } 1835 1836 /************************** sysfs end ************************/ 1837 1838 static void intel_pstate_notify_work(struct work_struct *work) 1839 { 1840 struct cpudata *cpudata = 1841 container_of(to_delayed_work(work), struct cpudata, hwp_notify_work); 1842 struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpudata->cpu); 1843 1844 if (policy) { 1845 __intel_pstate_update_max_freq(cpudata, policy); 1846 1847 cpufreq_cpu_release(policy); 1848 1849 /* 1850 * The driver will not be unregistered while this function is 1851 * running, so update the capacity without acquiring the driver 1852 * lock. 1853 */ 1854 hybrid_update_capacity(cpudata); 1855 } 1856 1857 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0); 1858 } 1859 1860 static DEFINE_RAW_SPINLOCK(hwp_notify_lock); 1861 static cpumask_t hwp_intr_enable_mask; 1862 1863 #define HWP_GUARANTEED_PERF_CHANGE_STATUS BIT(0) 1864 #define HWP_HIGHEST_PERF_CHANGE_STATUS BIT(3) 1865 1866 void notify_hwp_interrupt(void) 1867 { 1868 unsigned int this_cpu = smp_processor_id(); 1869 u64 value, status_mask; 1870 unsigned long flags; 1871 1872 if (!hwp_active || !cpu_feature_enabled(X86_FEATURE_HWP_NOTIFY)) 1873 return; 1874 1875 status_mask = HWP_GUARANTEED_PERF_CHANGE_STATUS; 1876 if (cpu_feature_enabled(X86_FEATURE_HWP_HIGHEST_PERF_CHANGE)) 1877 status_mask |= HWP_HIGHEST_PERF_CHANGE_STATUS; 1878 1879 rdmsrl_safe(MSR_HWP_STATUS, &value); 1880 if (!(value & status_mask)) 1881 return; 1882 1883 raw_spin_lock_irqsave(&hwp_notify_lock, flags); 1884 1885 if (!cpumask_test_cpu(this_cpu, &hwp_intr_enable_mask)) 1886 goto ack_intr; 1887 1888 schedule_delayed_work(&all_cpu_data[this_cpu]->hwp_notify_work, 1889 msecs_to_jiffies(10)); 1890 1891 raw_spin_unlock_irqrestore(&hwp_notify_lock, flags); 1892 1893 return; 1894 1895 ack_intr: 1896 wrmsrl_safe(MSR_HWP_STATUS, 0); 1897 raw_spin_unlock_irqrestore(&hwp_notify_lock, flags); 1898 } 1899 1900 static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata) 1901 { 1902 bool cancel_work; 1903 1904 if (!cpu_feature_enabled(X86_FEATURE_HWP_NOTIFY)) 1905 return; 1906 1907 /* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */ 1908 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00); 1909 1910 raw_spin_lock_irq(&hwp_notify_lock); 1911 cancel_work = cpumask_test_and_clear_cpu(cpudata->cpu, &hwp_intr_enable_mask); 1912 raw_spin_unlock_irq(&hwp_notify_lock); 1913 1914 if (cancel_work) 1915 cancel_delayed_work_sync(&cpudata->hwp_notify_work); 1916 } 1917 1918 #define HWP_GUARANTEED_PERF_CHANGE_REQ BIT(0) 1919 #define HWP_HIGHEST_PERF_CHANGE_REQ BIT(2) 1920 1921 static void intel_pstate_enable_hwp_interrupt(struct cpudata *cpudata) 1922 { 1923 /* Enable HWP notification interrupt for performance change */ 1924 if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) { 1925 u64 interrupt_mask = HWP_GUARANTEED_PERF_CHANGE_REQ; 1926 1927 raw_spin_lock_irq(&hwp_notify_lock); 1928 INIT_DELAYED_WORK(&cpudata->hwp_notify_work, intel_pstate_notify_work); 1929 cpumask_set_cpu(cpudata->cpu, &hwp_intr_enable_mask); 1930 raw_spin_unlock_irq(&hwp_notify_lock); 1931 1932 if (cpu_feature_enabled(X86_FEATURE_HWP_HIGHEST_PERF_CHANGE)) 1933 interrupt_mask |= HWP_HIGHEST_PERF_CHANGE_REQ; 1934 1935 /* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */ 1936 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, interrupt_mask); 1937 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0); 1938 } 1939 } 1940 1941 static void intel_pstate_update_epp_defaults(struct cpudata *cpudata) 1942 { 1943 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0); 1944 1945 /* 1946 * If the EPP is set by firmware, which means that firmware enabled HWP 1947 * - Is equal or less than 0x80 (default balance_perf EPP) 1948 * - But less performance oriented than performance EPP 1949 * then use this as new balance_perf EPP. 1950 */ 1951 if (hwp_forced && cpudata->epp_default <= HWP_EPP_BALANCE_PERFORMANCE && 1952 cpudata->epp_default > HWP_EPP_PERFORMANCE) { 1953 epp_values[EPP_INDEX_BALANCE_PERFORMANCE] = cpudata->epp_default; 1954 return; 1955 } 1956 1957 /* 1958 * If this CPU gen doesn't call for change in balance_perf 1959 * EPP return. 1960 */ 1961 if (epp_values[EPP_INDEX_BALANCE_PERFORMANCE] == HWP_EPP_BALANCE_PERFORMANCE) 1962 return; 1963 1964 /* 1965 * Use hard coded value per gen to update the balance_perf 1966 * and default EPP. 1967 */ 1968 cpudata->epp_default = epp_values[EPP_INDEX_BALANCE_PERFORMANCE]; 1969 intel_pstate_set_epp(cpudata, cpudata->epp_default); 1970 } 1971 1972 static void intel_pstate_hwp_enable(struct cpudata *cpudata) 1973 { 1974 /* First disable HWP notification interrupt till we activate again */ 1975 if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) 1976 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00); 1977 1978 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1); 1979 1980 intel_pstate_enable_hwp_interrupt(cpudata); 1981 1982 if (cpudata->epp_default >= 0) 1983 return; 1984 1985 intel_pstate_update_epp_defaults(cpudata); 1986 } 1987 1988 static int atom_get_min_pstate(int not_used) 1989 { 1990 u64 value; 1991 1992 rdmsrl(MSR_ATOM_CORE_RATIOS, value); 1993 return (value >> 8) & 0x7F; 1994 } 1995 1996 static int atom_get_max_pstate(int not_used) 1997 { 1998 u64 value; 1999 2000 rdmsrl(MSR_ATOM_CORE_RATIOS, value); 2001 return (value >> 16) & 0x7F; 2002 } 2003 2004 static int atom_get_turbo_pstate(int not_used) 2005 { 2006 u64 value; 2007 2008 rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value); 2009 return value & 0x7F; 2010 } 2011 2012 static u64 atom_get_val(struct cpudata *cpudata, int pstate) 2013 { 2014 u64 val; 2015 int32_t vid_fp; 2016 u32 vid; 2017 2018 val = (u64)pstate << 8; 2019 if (READ_ONCE(global.no_turbo) && !READ_ONCE(global.turbo_disabled)) 2020 val |= (u64)1 << 32; 2021 2022 vid_fp = cpudata->vid.min + mul_fp( 2023 int_tofp(pstate - cpudata->pstate.min_pstate), 2024 cpudata->vid.ratio); 2025 2026 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max); 2027 vid = ceiling_fp(vid_fp); 2028 2029 if (pstate > cpudata->pstate.max_pstate) 2030 vid = cpudata->vid.turbo; 2031 2032 return val | vid; 2033 } 2034 2035 static int silvermont_get_scaling(void) 2036 { 2037 u64 value; 2038 int i; 2039 /* Defined in Table 35-6 from SDM (Sept 2015) */ 2040 static int silvermont_freq_table[] = { 2041 83300, 100000, 133300, 116700, 80000}; 2042 2043 rdmsrl(MSR_FSB_FREQ, value); 2044 i = value & 0x7; 2045 WARN_ON(i > 4); 2046 2047 return silvermont_freq_table[i]; 2048 } 2049 2050 static int airmont_get_scaling(void) 2051 { 2052 u64 value; 2053 int i; 2054 /* Defined in Table 35-10 from SDM (Sept 2015) */ 2055 static int airmont_freq_table[] = { 2056 83300, 100000, 133300, 116700, 80000, 2057 93300, 90000, 88900, 87500}; 2058 2059 rdmsrl(MSR_FSB_FREQ, value); 2060 i = value & 0xF; 2061 WARN_ON(i > 8); 2062 2063 return airmont_freq_table[i]; 2064 } 2065 2066 static void atom_get_vid(struct cpudata *cpudata) 2067 { 2068 u64 value; 2069 2070 rdmsrl(MSR_ATOM_CORE_VIDS, value); 2071 cpudata->vid.min = int_tofp((value >> 8) & 0x7f); 2072 cpudata->vid.max = int_tofp((value >> 16) & 0x7f); 2073 cpudata->vid.ratio = div_fp( 2074 cpudata->vid.max - cpudata->vid.min, 2075 int_tofp(cpudata->pstate.max_pstate - 2076 cpudata->pstate.min_pstate)); 2077 2078 rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value); 2079 cpudata->vid.turbo = value & 0x7f; 2080 } 2081 2082 static int core_get_min_pstate(int cpu) 2083 { 2084 u64 value; 2085 2086 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &value); 2087 return (value >> 40) & 0xFF; 2088 } 2089 2090 static int core_get_max_pstate_physical(int cpu) 2091 { 2092 u64 value; 2093 2094 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &value); 2095 return (value >> 8) & 0xFF; 2096 } 2097 2098 static int core_get_tdp_ratio(int cpu, u64 plat_info) 2099 { 2100 /* Check how many TDP levels present */ 2101 if (plat_info & 0x600000000) { 2102 u64 tdp_ctrl; 2103 u64 tdp_ratio; 2104 int tdp_msr; 2105 int err; 2106 2107 /* Get the TDP level (0, 1, 2) to get ratios */ 2108 err = rdmsrl_safe_on_cpu(cpu, MSR_CONFIG_TDP_CONTROL, &tdp_ctrl); 2109 if (err) 2110 return err; 2111 2112 /* TDP MSR are continuous starting at 0x648 */ 2113 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03); 2114 err = rdmsrl_safe_on_cpu(cpu, tdp_msr, &tdp_ratio); 2115 if (err) 2116 return err; 2117 2118 /* For level 1 and 2, bits[23:16] contain the ratio */ 2119 if (tdp_ctrl & 0x03) 2120 tdp_ratio >>= 16; 2121 2122 tdp_ratio &= 0xff; /* ratios are only 8 bits long */ 2123 pr_debug("tdp_ratio %x\n", (int)tdp_ratio); 2124 2125 return (int)tdp_ratio; 2126 } 2127 2128 return -ENXIO; 2129 } 2130 2131 static int core_get_max_pstate(int cpu) 2132 { 2133 u64 tar; 2134 u64 plat_info; 2135 int max_pstate; 2136 int tdp_ratio; 2137 int err; 2138 2139 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &plat_info); 2140 max_pstate = (plat_info >> 8) & 0xFF; 2141 2142 tdp_ratio = core_get_tdp_ratio(cpu, plat_info); 2143 if (tdp_ratio <= 0) 2144 return max_pstate; 2145 2146 if (hwp_active) { 2147 /* Turbo activation ratio is not used on HWP platforms */ 2148 return tdp_ratio; 2149 } 2150 2151 err = rdmsrl_safe_on_cpu(cpu, MSR_TURBO_ACTIVATION_RATIO, &tar); 2152 if (!err) { 2153 int tar_levels; 2154 2155 /* Do some sanity checking for safety */ 2156 tar_levels = tar & 0xff; 2157 if (tdp_ratio - 1 == tar_levels) { 2158 max_pstate = tar_levels; 2159 pr_debug("max_pstate=TAC %x\n", max_pstate); 2160 } 2161 } 2162 2163 return max_pstate; 2164 } 2165 2166 static int core_get_turbo_pstate(int cpu) 2167 { 2168 u64 value; 2169 int nont, ret; 2170 2171 rdmsrl_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value); 2172 nont = core_get_max_pstate(cpu); 2173 ret = (value) & 255; 2174 if (ret <= nont) 2175 ret = nont; 2176 return ret; 2177 } 2178 2179 static u64 core_get_val(struct cpudata *cpudata, int pstate) 2180 { 2181 u64 val; 2182 2183 val = (u64)pstate << 8; 2184 if (READ_ONCE(global.no_turbo) && !READ_ONCE(global.turbo_disabled)) 2185 val |= (u64)1 << 32; 2186 2187 return val; 2188 } 2189 2190 static int knl_get_aperf_mperf_shift(void) 2191 { 2192 return 10; 2193 } 2194 2195 static int knl_get_turbo_pstate(int cpu) 2196 { 2197 u64 value; 2198 int nont, ret; 2199 2200 rdmsrl_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value); 2201 nont = core_get_max_pstate(cpu); 2202 ret = (((value) >> 8) & 0xFF); 2203 if (ret <= nont) 2204 ret = nont; 2205 return ret; 2206 } 2207 2208 static void hybrid_get_type(void *data) 2209 { 2210 u8 *cpu_type = data; 2211 2212 *cpu_type = get_this_hybrid_cpu_type(); 2213 } 2214 2215 static int hwp_get_cpu_scaling(int cpu) 2216 { 2217 u8 cpu_type = 0; 2218 2219 smp_call_function_single(cpu, hybrid_get_type, &cpu_type, 1); 2220 /* P-cores have a smaller perf level-to-freqency scaling factor. */ 2221 if (cpu_type == 0x40) 2222 return hybrid_scaling_factor; 2223 2224 /* Use default core scaling for E-cores */ 2225 if (cpu_type == 0x20) 2226 return core_get_scaling(); 2227 2228 /* 2229 * If reached here, this system is either non-hybrid (like Tiger 2230 * Lake) or hybrid-capable (like Alder Lake or Raptor Lake) with 2231 * no E cores (in which case CPUID for hybrid support is 0). 2232 * 2233 * The CPPC nominal_frequency field is 0 for non-hybrid systems, 2234 * so the default core scaling will be used for them. 2235 */ 2236 return intel_pstate_cppc_get_scaling(cpu); 2237 } 2238 2239 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate) 2240 { 2241 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu); 2242 cpu->pstate.current_pstate = pstate; 2243 /* 2244 * Generally, there is no guarantee that this code will always run on 2245 * the CPU being updated, so force the register update to run on the 2246 * right CPU. 2247 */ 2248 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL, 2249 pstate_funcs.get_val(cpu, pstate)); 2250 } 2251 2252 static void intel_pstate_set_min_pstate(struct cpudata *cpu) 2253 { 2254 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate); 2255 } 2256 2257 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu) 2258 { 2259 int perf_ctl_max_phys = pstate_funcs.get_max_physical(cpu->cpu); 2260 int perf_ctl_scaling = pstate_funcs.get_scaling(); 2261 2262 cpu->pstate.min_pstate = pstate_funcs.get_min(cpu->cpu); 2263 cpu->pstate.max_pstate_physical = perf_ctl_max_phys; 2264 cpu->pstate.perf_ctl_scaling = perf_ctl_scaling; 2265 2266 if (hwp_active && !hwp_mode_bdw) { 2267 __intel_pstate_get_hwp_cap(cpu); 2268 2269 if (pstate_funcs.get_cpu_scaling) { 2270 cpu->pstate.scaling = pstate_funcs.get_cpu_scaling(cpu->cpu); 2271 if (cpu->pstate.scaling != perf_ctl_scaling) { 2272 intel_pstate_hybrid_hwp_adjust(cpu); 2273 hwp_is_hybrid = true; 2274 } 2275 } else { 2276 cpu->pstate.scaling = perf_ctl_scaling; 2277 } 2278 /* 2279 * If the CPU is going online for the first time and it was 2280 * offline initially, asym capacity scaling needs to be updated. 2281 */ 2282 hybrid_update_capacity(cpu); 2283 } else { 2284 cpu->pstate.scaling = perf_ctl_scaling; 2285 cpu->pstate.max_pstate = pstate_funcs.get_max(cpu->cpu); 2286 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(cpu->cpu); 2287 } 2288 2289 if (cpu->pstate.scaling == perf_ctl_scaling) { 2290 cpu->pstate.min_freq = cpu->pstate.min_pstate * perf_ctl_scaling; 2291 cpu->pstate.max_freq = cpu->pstate.max_pstate * perf_ctl_scaling; 2292 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * perf_ctl_scaling; 2293 } 2294 2295 if (pstate_funcs.get_aperf_mperf_shift) 2296 cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift(); 2297 2298 if (pstate_funcs.get_vid) 2299 pstate_funcs.get_vid(cpu); 2300 2301 intel_pstate_set_min_pstate(cpu); 2302 } 2303 2304 /* 2305 * Long hold time will keep high perf limits for long time, 2306 * which negatively impacts perf/watt for some workloads, 2307 * like specpower. 3ms is based on experiements on some 2308 * workoads. 2309 */ 2310 static int hwp_boost_hold_time_ns = 3 * NSEC_PER_MSEC; 2311 2312 static inline void intel_pstate_hwp_boost_up(struct cpudata *cpu) 2313 { 2314 u64 hwp_req = READ_ONCE(cpu->hwp_req_cached); 2315 u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached); 2316 u32 max_limit = (hwp_req & 0xff00) >> 8; 2317 u32 min_limit = (hwp_req & 0xff); 2318 u32 boost_level1; 2319 2320 /* 2321 * Cases to consider (User changes via sysfs or boot time): 2322 * If, P0 (Turbo max) = P1 (Guaranteed max) = min: 2323 * No boost, return. 2324 * If, P0 (Turbo max) > P1 (Guaranteed max) = min: 2325 * Should result in one level boost only for P0. 2326 * If, P0 (Turbo max) = P1 (Guaranteed max) > min: 2327 * Should result in two level boost: 2328 * (min + p1)/2 and P1. 2329 * If, P0 (Turbo max) > P1 (Guaranteed max) > min: 2330 * Should result in three level boost: 2331 * (min + p1)/2, P1 and P0. 2332 */ 2333 2334 /* If max and min are equal or already at max, nothing to boost */ 2335 if (max_limit == min_limit || cpu->hwp_boost_min >= max_limit) 2336 return; 2337 2338 if (!cpu->hwp_boost_min) 2339 cpu->hwp_boost_min = min_limit; 2340 2341 /* level at half way mark between min and guranteed */ 2342 boost_level1 = (HWP_GUARANTEED_PERF(hwp_cap) + min_limit) >> 1; 2343 2344 if (cpu->hwp_boost_min < boost_level1) 2345 cpu->hwp_boost_min = boost_level1; 2346 else if (cpu->hwp_boost_min < HWP_GUARANTEED_PERF(hwp_cap)) 2347 cpu->hwp_boost_min = HWP_GUARANTEED_PERF(hwp_cap); 2348 else if (cpu->hwp_boost_min == HWP_GUARANTEED_PERF(hwp_cap) && 2349 max_limit != HWP_GUARANTEED_PERF(hwp_cap)) 2350 cpu->hwp_boost_min = max_limit; 2351 else 2352 return; 2353 2354 hwp_req = (hwp_req & ~GENMASK_ULL(7, 0)) | cpu->hwp_boost_min; 2355 wrmsrl(MSR_HWP_REQUEST, hwp_req); 2356 cpu->last_update = cpu->sample.time; 2357 } 2358 2359 static inline void intel_pstate_hwp_boost_down(struct cpudata *cpu) 2360 { 2361 if (cpu->hwp_boost_min) { 2362 bool expired; 2363 2364 /* Check if we are idle for hold time to boost down */ 2365 expired = time_after64(cpu->sample.time, cpu->last_update + 2366 hwp_boost_hold_time_ns); 2367 if (expired) { 2368 wrmsrl(MSR_HWP_REQUEST, cpu->hwp_req_cached); 2369 cpu->hwp_boost_min = 0; 2370 } 2371 } 2372 cpu->last_update = cpu->sample.time; 2373 } 2374 2375 static inline void intel_pstate_update_util_hwp_local(struct cpudata *cpu, 2376 u64 time) 2377 { 2378 cpu->sample.time = time; 2379 2380 if (cpu->sched_flags & SCHED_CPUFREQ_IOWAIT) { 2381 bool do_io = false; 2382 2383 cpu->sched_flags = 0; 2384 /* 2385 * Set iowait_boost flag and update time. Since IO WAIT flag 2386 * is set all the time, we can't just conclude that there is 2387 * some IO bound activity is scheduled on this CPU with just 2388 * one occurrence. If we receive at least two in two 2389 * consecutive ticks, then we treat as boost candidate. 2390 */ 2391 if (time_before64(time, cpu->last_io_update + 2 * TICK_NSEC)) 2392 do_io = true; 2393 2394 cpu->last_io_update = time; 2395 2396 if (do_io) 2397 intel_pstate_hwp_boost_up(cpu); 2398 2399 } else { 2400 intel_pstate_hwp_boost_down(cpu); 2401 } 2402 } 2403 2404 static inline void intel_pstate_update_util_hwp(struct update_util_data *data, 2405 u64 time, unsigned int flags) 2406 { 2407 struct cpudata *cpu = container_of(data, struct cpudata, update_util); 2408 2409 cpu->sched_flags |= flags; 2410 2411 if (smp_processor_id() == cpu->cpu) 2412 intel_pstate_update_util_hwp_local(cpu, time); 2413 } 2414 2415 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu) 2416 { 2417 struct sample *sample = &cpu->sample; 2418 2419 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf); 2420 } 2421 2422 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time) 2423 { 2424 u64 aperf, mperf; 2425 unsigned long flags; 2426 u64 tsc; 2427 2428 local_irq_save(flags); 2429 rdmsrl(MSR_IA32_APERF, aperf); 2430 rdmsrl(MSR_IA32_MPERF, mperf); 2431 tsc = rdtsc(); 2432 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) { 2433 local_irq_restore(flags); 2434 return false; 2435 } 2436 local_irq_restore(flags); 2437 2438 cpu->last_sample_time = cpu->sample.time; 2439 cpu->sample.time = time; 2440 cpu->sample.aperf = aperf; 2441 cpu->sample.mperf = mperf; 2442 cpu->sample.tsc = tsc; 2443 cpu->sample.aperf -= cpu->prev_aperf; 2444 cpu->sample.mperf -= cpu->prev_mperf; 2445 cpu->sample.tsc -= cpu->prev_tsc; 2446 2447 cpu->prev_aperf = aperf; 2448 cpu->prev_mperf = mperf; 2449 cpu->prev_tsc = tsc; 2450 /* 2451 * First time this function is invoked in a given cycle, all of the 2452 * previous sample data fields are equal to zero or stale and they must 2453 * be populated with meaningful numbers for things to work, so assume 2454 * that sample.time will always be reset before setting the utilization 2455 * update hook and make the caller skip the sample then. 2456 */ 2457 if (cpu->last_sample_time) { 2458 intel_pstate_calc_avg_perf(cpu); 2459 return true; 2460 } 2461 return false; 2462 } 2463 2464 static inline int32_t get_avg_frequency(struct cpudata *cpu) 2465 { 2466 return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz); 2467 } 2468 2469 static inline int32_t get_avg_pstate(struct cpudata *cpu) 2470 { 2471 return mul_ext_fp(cpu->pstate.max_pstate_physical, 2472 cpu->sample.core_avg_perf); 2473 } 2474 2475 static inline int32_t get_target_pstate(struct cpudata *cpu) 2476 { 2477 struct sample *sample = &cpu->sample; 2478 int32_t busy_frac; 2479 int target, avg_pstate; 2480 2481 busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift, 2482 sample->tsc); 2483 2484 if (busy_frac < cpu->iowait_boost) 2485 busy_frac = cpu->iowait_boost; 2486 2487 sample->busy_scaled = busy_frac * 100; 2488 2489 target = READ_ONCE(global.no_turbo) ? 2490 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate; 2491 target += target >> 2; 2492 target = mul_fp(target, busy_frac); 2493 if (target < cpu->pstate.min_pstate) 2494 target = cpu->pstate.min_pstate; 2495 2496 /* 2497 * If the average P-state during the previous cycle was higher than the 2498 * current target, add 50% of the difference to the target to reduce 2499 * possible performance oscillations and offset possible performance 2500 * loss related to moving the workload from one CPU to another within 2501 * a package/module. 2502 */ 2503 avg_pstate = get_avg_pstate(cpu); 2504 if (avg_pstate > target) 2505 target += (avg_pstate - target) >> 1; 2506 2507 return target; 2508 } 2509 2510 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate) 2511 { 2512 int min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio); 2513 int max_pstate = max(min_pstate, cpu->max_perf_ratio); 2514 2515 return clamp_t(int, pstate, min_pstate, max_pstate); 2516 } 2517 2518 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate) 2519 { 2520 if (pstate == cpu->pstate.current_pstate) 2521 return; 2522 2523 cpu->pstate.current_pstate = pstate; 2524 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate)); 2525 } 2526 2527 static void intel_pstate_adjust_pstate(struct cpudata *cpu) 2528 { 2529 int from = cpu->pstate.current_pstate; 2530 struct sample *sample; 2531 int target_pstate; 2532 2533 target_pstate = get_target_pstate(cpu); 2534 target_pstate = intel_pstate_prepare_request(cpu, target_pstate); 2535 trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu); 2536 intel_pstate_update_pstate(cpu, target_pstate); 2537 2538 sample = &cpu->sample; 2539 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf), 2540 fp_toint(sample->busy_scaled), 2541 from, 2542 cpu->pstate.current_pstate, 2543 sample->mperf, 2544 sample->aperf, 2545 sample->tsc, 2546 get_avg_frequency(cpu), 2547 fp_toint(cpu->iowait_boost * 100)); 2548 } 2549 2550 static void intel_pstate_update_util(struct update_util_data *data, u64 time, 2551 unsigned int flags) 2552 { 2553 struct cpudata *cpu = container_of(data, struct cpudata, update_util); 2554 u64 delta_ns; 2555 2556 /* Don't allow remote callbacks */ 2557 if (smp_processor_id() != cpu->cpu) 2558 return; 2559 2560 delta_ns = time - cpu->last_update; 2561 if (flags & SCHED_CPUFREQ_IOWAIT) { 2562 /* Start over if the CPU may have been idle. */ 2563 if (delta_ns > TICK_NSEC) { 2564 cpu->iowait_boost = ONE_EIGHTH_FP; 2565 } else if (cpu->iowait_boost >= ONE_EIGHTH_FP) { 2566 cpu->iowait_boost <<= 1; 2567 if (cpu->iowait_boost > int_tofp(1)) 2568 cpu->iowait_boost = int_tofp(1); 2569 } else { 2570 cpu->iowait_boost = ONE_EIGHTH_FP; 2571 } 2572 } else if (cpu->iowait_boost) { 2573 /* Clear iowait_boost if the CPU may have been idle. */ 2574 if (delta_ns > TICK_NSEC) 2575 cpu->iowait_boost = 0; 2576 else 2577 cpu->iowait_boost >>= 1; 2578 } 2579 cpu->last_update = time; 2580 delta_ns = time - cpu->sample.time; 2581 if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL) 2582 return; 2583 2584 if (intel_pstate_sample(cpu, time)) 2585 intel_pstate_adjust_pstate(cpu); 2586 } 2587 2588 static struct pstate_funcs core_funcs = { 2589 .get_max = core_get_max_pstate, 2590 .get_max_physical = core_get_max_pstate_physical, 2591 .get_min = core_get_min_pstate, 2592 .get_turbo = core_get_turbo_pstate, 2593 .get_scaling = core_get_scaling, 2594 .get_val = core_get_val, 2595 }; 2596 2597 static const struct pstate_funcs silvermont_funcs = { 2598 .get_max = atom_get_max_pstate, 2599 .get_max_physical = atom_get_max_pstate, 2600 .get_min = atom_get_min_pstate, 2601 .get_turbo = atom_get_turbo_pstate, 2602 .get_val = atom_get_val, 2603 .get_scaling = silvermont_get_scaling, 2604 .get_vid = atom_get_vid, 2605 }; 2606 2607 static const struct pstate_funcs airmont_funcs = { 2608 .get_max = atom_get_max_pstate, 2609 .get_max_physical = atom_get_max_pstate, 2610 .get_min = atom_get_min_pstate, 2611 .get_turbo = atom_get_turbo_pstate, 2612 .get_val = atom_get_val, 2613 .get_scaling = airmont_get_scaling, 2614 .get_vid = atom_get_vid, 2615 }; 2616 2617 static const struct pstate_funcs knl_funcs = { 2618 .get_max = core_get_max_pstate, 2619 .get_max_physical = core_get_max_pstate_physical, 2620 .get_min = core_get_min_pstate, 2621 .get_turbo = knl_get_turbo_pstate, 2622 .get_aperf_mperf_shift = knl_get_aperf_mperf_shift, 2623 .get_scaling = core_get_scaling, 2624 .get_val = core_get_val, 2625 }; 2626 2627 #define X86_MATCH(vfm, policy) \ 2628 X86_MATCH_VFM_FEATURE(vfm, X86_FEATURE_APERFMPERF, &policy) 2629 2630 static const struct x86_cpu_id intel_pstate_cpu_ids[] = { 2631 X86_MATCH(INTEL_SANDYBRIDGE, core_funcs), 2632 X86_MATCH(INTEL_SANDYBRIDGE_X, core_funcs), 2633 X86_MATCH(INTEL_ATOM_SILVERMONT, silvermont_funcs), 2634 X86_MATCH(INTEL_IVYBRIDGE, core_funcs), 2635 X86_MATCH(INTEL_HASWELL, core_funcs), 2636 X86_MATCH(INTEL_BROADWELL, core_funcs), 2637 X86_MATCH(INTEL_IVYBRIDGE_X, core_funcs), 2638 X86_MATCH(INTEL_HASWELL_X, core_funcs), 2639 X86_MATCH(INTEL_HASWELL_L, core_funcs), 2640 X86_MATCH(INTEL_HASWELL_G, core_funcs), 2641 X86_MATCH(INTEL_BROADWELL_G, core_funcs), 2642 X86_MATCH(INTEL_ATOM_AIRMONT, airmont_funcs), 2643 X86_MATCH(INTEL_SKYLAKE_L, core_funcs), 2644 X86_MATCH(INTEL_BROADWELL_X, core_funcs), 2645 X86_MATCH(INTEL_SKYLAKE, core_funcs), 2646 X86_MATCH(INTEL_BROADWELL_D, core_funcs), 2647 X86_MATCH(INTEL_XEON_PHI_KNL, knl_funcs), 2648 X86_MATCH(INTEL_XEON_PHI_KNM, knl_funcs), 2649 X86_MATCH(INTEL_ATOM_GOLDMONT, core_funcs), 2650 X86_MATCH(INTEL_ATOM_GOLDMONT_PLUS, core_funcs), 2651 X86_MATCH(INTEL_SKYLAKE_X, core_funcs), 2652 X86_MATCH(INTEL_COMETLAKE, core_funcs), 2653 X86_MATCH(INTEL_ICELAKE_X, core_funcs), 2654 X86_MATCH(INTEL_TIGERLAKE, core_funcs), 2655 X86_MATCH(INTEL_SAPPHIRERAPIDS_X, core_funcs), 2656 X86_MATCH(INTEL_EMERALDRAPIDS_X, core_funcs), 2657 {} 2658 }; 2659 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids); 2660 2661 #ifdef CONFIG_ACPI 2662 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = { 2663 X86_MATCH(INTEL_BROADWELL_D, core_funcs), 2664 X86_MATCH(INTEL_BROADWELL_X, core_funcs), 2665 X86_MATCH(INTEL_SKYLAKE_X, core_funcs), 2666 X86_MATCH(INTEL_ICELAKE_X, core_funcs), 2667 X86_MATCH(INTEL_SAPPHIRERAPIDS_X, core_funcs), 2668 X86_MATCH(INTEL_EMERALDRAPIDS_X, core_funcs), 2669 X86_MATCH(INTEL_GRANITERAPIDS_D, core_funcs), 2670 X86_MATCH(INTEL_GRANITERAPIDS_X, core_funcs), 2671 X86_MATCH(INTEL_ATOM_CRESTMONT, core_funcs), 2672 X86_MATCH(INTEL_ATOM_CRESTMONT_X, core_funcs), 2673 {} 2674 }; 2675 #endif 2676 2677 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = { 2678 X86_MATCH(INTEL_KABYLAKE, core_funcs), 2679 {} 2680 }; 2681 2682 static int intel_pstate_init_cpu(unsigned int cpunum) 2683 { 2684 struct cpudata *cpu; 2685 2686 cpu = all_cpu_data[cpunum]; 2687 2688 if (!cpu) { 2689 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL); 2690 if (!cpu) 2691 return -ENOMEM; 2692 2693 WRITE_ONCE(all_cpu_data[cpunum], cpu); 2694 2695 cpu->cpu = cpunum; 2696 2697 cpu->epp_default = -EINVAL; 2698 2699 if (hwp_active) { 2700 intel_pstate_hwp_enable(cpu); 2701 2702 if (intel_pstate_acpi_pm_profile_server()) 2703 hwp_boost = true; 2704 } 2705 } else if (hwp_active) { 2706 /* 2707 * Re-enable HWP in case this happens after a resume from ACPI 2708 * S3 if the CPU was offline during the whole system/resume 2709 * cycle. 2710 */ 2711 intel_pstate_hwp_reenable(cpu); 2712 } 2713 2714 cpu->epp_powersave = -EINVAL; 2715 cpu->epp_policy = 0; 2716 2717 intel_pstate_get_cpu_pstates(cpu); 2718 2719 pr_debug("controlling: cpu %d\n", cpunum); 2720 2721 return 0; 2722 } 2723 2724 static void intel_pstate_set_update_util_hook(unsigned int cpu_num) 2725 { 2726 struct cpudata *cpu = all_cpu_data[cpu_num]; 2727 2728 if (hwp_active && !hwp_boost) 2729 return; 2730 2731 if (cpu->update_util_set) 2732 return; 2733 2734 /* Prevent intel_pstate_update_util() from using stale data. */ 2735 cpu->sample.time = 0; 2736 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util, 2737 (hwp_active ? 2738 intel_pstate_update_util_hwp : 2739 intel_pstate_update_util)); 2740 cpu->update_util_set = true; 2741 } 2742 2743 static void intel_pstate_clear_update_util_hook(unsigned int cpu) 2744 { 2745 struct cpudata *cpu_data = all_cpu_data[cpu]; 2746 2747 if (!cpu_data->update_util_set) 2748 return; 2749 2750 cpufreq_remove_update_util_hook(cpu); 2751 cpu_data->update_util_set = false; 2752 synchronize_rcu(); 2753 } 2754 2755 static int intel_pstate_get_max_freq(struct cpudata *cpu) 2756 { 2757 return READ_ONCE(global.no_turbo) ? 2758 cpu->pstate.max_freq : cpu->pstate.turbo_freq; 2759 } 2760 2761 static void intel_pstate_update_perf_limits(struct cpudata *cpu, 2762 unsigned int policy_min, 2763 unsigned int policy_max) 2764 { 2765 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling; 2766 int32_t max_policy_perf, min_policy_perf; 2767 2768 max_policy_perf = policy_max / perf_ctl_scaling; 2769 if (policy_max == policy_min) { 2770 min_policy_perf = max_policy_perf; 2771 } else { 2772 min_policy_perf = policy_min / perf_ctl_scaling; 2773 min_policy_perf = clamp_t(int32_t, min_policy_perf, 2774 0, max_policy_perf); 2775 } 2776 2777 /* 2778 * HWP needs some special consideration, because HWP_REQUEST uses 2779 * abstract values to represent performance rather than pure ratios. 2780 */ 2781 if (hwp_active && cpu->pstate.scaling != perf_ctl_scaling) { 2782 int freq; 2783 2784 freq = max_policy_perf * perf_ctl_scaling; 2785 max_policy_perf = intel_pstate_freq_to_hwp(cpu, freq); 2786 freq = min_policy_perf * perf_ctl_scaling; 2787 min_policy_perf = intel_pstate_freq_to_hwp(cpu, freq); 2788 } 2789 2790 pr_debug("cpu:%d min_policy_perf:%d max_policy_perf:%d\n", 2791 cpu->cpu, min_policy_perf, max_policy_perf); 2792 2793 /* Normalize user input to [min_perf, max_perf] */ 2794 if (per_cpu_limits) { 2795 cpu->min_perf_ratio = min_policy_perf; 2796 cpu->max_perf_ratio = max_policy_perf; 2797 } else { 2798 int turbo_max = cpu->pstate.turbo_pstate; 2799 int32_t global_min, global_max; 2800 2801 /* Global limits are in percent of the maximum turbo P-state. */ 2802 global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100); 2803 global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100); 2804 global_min = clamp_t(int32_t, global_min, 0, global_max); 2805 2806 pr_debug("cpu:%d global_min:%d global_max:%d\n", cpu->cpu, 2807 global_min, global_max); 2808 2809 cpu->min_perf_ratio = max(min_policy_perf, global_min); 2810 cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf); 2811 cpu->max_perf_ratio = min(max_policy_perf, global_max); 2812 cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio); 2813 2814 /* Make sure min_perf <= max_perf */ 2815 cpu->min_perf_ratio = min(cpu->min_perf_ratio, 2816 cpu->max_perf_ratio); 2817 2818 } 2819 pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", cpu->cpu, 2820 cpu->max_perf_ratio, 2821 cpu->min_perf_ratio); 2822 } 2823 2824 static int intel_pstate_set_policy(struct cpufreq_policy *policy) 2825 { 2826 struct cpudata *cpu; 2827 2828 if (!policy->cpuinfo.max_freq) 2829 return -ENODEV; 2830 2831 pr_debug("set_policy cpuinfo.max %u policy->max %u\n", 2832 policy->cpuinfo.max_freq, policy->max); 2833 2834 cpu = all_cpu_data[policy->cpu]; 2835 cpu->policy = policy->policy; 2836 2837 mutex_lock(&intel_pstate_limits_lock); 2838 2839 intel_pstate_update_perf_limits(cpu, policy->min, policy->max); 2840 2841 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) { 2842 int pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio); 2843 2844 /* 2845 * NOHZ_FULL CPUs need this as the governor callback may not 2846 * be invoked on them. 2847 */ 2848 intel_pstate_clear_update_util_hook(policy->cpu); 2849 intel_pstate_set_pstate(cpu, pstate); 2850 } else { 2851 intel_pstate_set_update_util_hook(policy->cpu); 2852 } 2853 2854 if (hwp_active) { 2855 /* 2856 * When hwp_boost was active before and dynamically it 2857 * was turned off, in that case we need to clear the 2858 * update util hook. 2859 */ 2860 if (!hwp_boost) 2861 intel_pstate_clear_update_util_hook(policy->cpu); 2862 intel_pstate_hwp_set(policy->cpu); 2863 } 2864 /* 2865 * policy->cur is never updated with the intel_pstate driver, but it 2866 * is used as a stale frequency value. So, keep it within limits. 2867 */ 2868 policy->cur = policy->min; 2869 2870 mutex_unlock(&intel_pstate_limits_lock); 2871 2872 return 0; 2873 } 2874 2875 static void intel_pstate_adjust_policy_max(struct cpudata *cpu, 2876 struct cpufreq_policy_data *policy) 2877 { 2878 if (!hwp_active && 2879 cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate && 2880 policy->max < policy->cpuinfo.max_freq && 2881 policy->max > cpu->pstate.max_freq) { 2882 pr_debug("policy->max > max non turbo frequency\n"); 2883 policy->max = policy->cpuinfo.max_freq; 2884 } 2885 } 2886 2887 static void intel_pstate_verify_cpu_policy(struct cpudata *cpu, 2888 struct cpufreq_policy_data *policy) 2889 { 2890 int max_freq; 2891 2892 if (hwp_active) { 2893 intel_pstate_get_hwp_cap(cpu); 2894 max_freq = READ_ONCE(global.no_turbo) ? 2895 cpu->pstate.max_freq : cpu->pstate.turbo_freq; 2896 } else { 2897 max_freq = intel_pstate_get_max_freq(cpu); 2898 } 2899 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, max_freq); 2900 2901 intel_pstate_adjust_policy_max(cpu, policy); 2902 } 2903 2904 static int intel_pstate_verify_policy(struct cpufreq_policy_data *policy) 2905 { 2906 intel_pstate_verify_cpu_policy(all_cpu_data[policy->cpu], policy); 2907 2908 return 0; 2909 } 2910 2911 static int intel_cpufreq_cpu_offline(struct cpufreq_policy *policy) 2912 { 2913 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2914 2915 pr_debug("CPU %d going offline\n", cpu->cpu); 2916 2917 if (cpu->suspended) 2918 return 0; 2919 2920 /* 2921 * If the CPU is an SMT thread and it goes offline with the performance 2922 * settings different from the minimum, it will prevent its sibling 2923 * from getting to lower performance levels, so force the minimum 2924 * performance on CPU offline to prevent that from happening. 2925 */ 2926 if (hwp_active) 2927 intel_pstate_hwp_offline(cpu); 2928 else 2929 intel_pstate_set_min_pstate(cpu); 2930 2931 intel_pstate_exit_perf_limits(policy); 2932 2933 return 0; 2934 } 2935 2936 static int intel_pstate_cpu_online(struct cpufreq_policy *policy) 2937 { 2938 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2939 2940 pr_debug("CPU %d going online\n", cpu->cpu); 2941 2942 intel_pstate_init_acpi_perf_limits(policy); 2943 2944 if (hwp_active) { 2945 /* 2946 * Re-enable HWP and clear the "suspended" flag to let "resume" 2947 * know that it need not do that. 2948 */ 2949 intel_pstate_hwp_reenable(cpu); 2950 cpu->suspended = false; 2951 2952 hybrid_update_capacity(cpu); 2953 } 2954 2955 return 0; 2956 } 2957 2958 static int intel_pstate_cpu_offline(struct cpufreq_policy *policy) 2959 { 2960 intel_pstate_clear_update_util_hook(policy->cpu); 2961 2962 return intel_cpufreq_cpu_offline(policy); 2963 } 2964 2965 static void intel_pstate_cpu_exit(struct cpufreq_policy *policy) 2966 { 2967 pr_debug("CPU %d exiting\n", policy->cpu); 2968 2969 policy->fast_switch_possible = false; 2970 } 2971 2972 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy) 2973 { 2974 struct cpudata *cpu; 2975 int rc; 2976 2977 rc = intel_pstate_init_cpu(policy->cpu); 2978 if (rc) 2979 return rc; 2980 2981 cpu = all_cpu_data[policy->cpu]; 2982 2983 cpu->max_perf_ratio = 0xFF; 2984 cpu->min_perf_ratio = 0; 2985 2986 /* cpuinfo and default policy values */ 2987 policy->cpuinfo.min_freq = cpu->pstate.min_freq; 2988 policy->cpuinfo.max_freq = READ_ONCE(global.no_turbo) ? 2989 cpu->pstate.max_freq : cpu->pstate.turbo_freq; 2990 2991 policy->min = policy->cpuinfo.min_freq; 2992 policy->max = policy->cpuinfo.max_freq; 2993 2994 intel_pstate_init_acpi_perf_limits(policy); 2995 2996 policy->fast_switch_possible = true; 2997 2998 return 0; 2999 } 3000 3001 static int intel_pstate_cpu_init(struct cpufreq_policy *policy) 3002 { 3003 int ret = __intel_pstate_cpu_init(policy); 3004 3005 if (ret) 3006 return ret; 3007 3008 /* 3009 * Set the policy to powersave to provide a valid fallback value in case 3010 * the default cpufreq governor is neither powersave nor performance. 3011 */ 3012 policy->policy = CPUFREQ_POLICY_POWERSAVE; 3013 3014 if (hwp_active) { 3015 struct cpudata *cpu = all_cpu_data[policy->cpu]; 3016 3017 cpu->epp_cached = intel_pstate_get_epp(cpu, 0); 3018 } 3019 3020 return 0; 3021 } 3022 3023 static struct cpufreq_driver intel_pstate = { 3024 .flags = CPUFREQ_CONST_LOOPS, 3025 .verify = intel_pstate_verify_policy, 3026 .setpolicy = intel_pstate_set_policy, 3027 .suspend = intel_pstate_suspend, 3028 .resume = intel_pstate_resume, 3029 .init = intel_pstate_cpu_init, 3030 .exit = intel_pstate_cpu_exit, 3031 .offline = intel_pstate_cpu_offline, 3032 .online = intel_pstate_cpu_online, 3033 .update_limits = intel_pstate_update_limits, 3034 .name = "intel_pstate", 3035 }; 3036 3037 static int intel_cpufreq_verify_policy(struct cpufreq_policy_data *policy) 3038 { 3039 struct cpudata *cpu = all_cpu_data[policy->cpu]; 3040 3041 intel_pstate_verify_cpu_policy(cpu, policy); 3042 intel_pstate_update_perf_limits(cpu, policy->min, policy->max); 3043 3044 return 0; 3045 } 3046 3047 /* Use of trace in passive mode: 3048 * 3049 * In passive mode the trace core_busy field (also known as the 3050 * performance field, and lablelled as such on the graphs; also known as 3051 * core_avg_perf) is not needed and so is re-assigned to indicate if the 3052 * driver call was via the normal or fast switch path. Various graphs 3053 * output from the intel_pstate_tracer.py utility that include core_busy 3054 * (or performance or core_avg_perf) have a fixed y-axis from 0 to 100%, 3055 * so we use 10 to indicate the normal path through the driver, and 3056 * 90 to indicate the fast switch path through the driver. 3057 * The scaled_busy field is not used, and is set to 0. 3058 */ 3059 3060 #define INTEL_PSTATE_TRACE_TARGET 10 3061 #define INTEL_PSTATE_TRACE_FAST_SWITCH 90 3062 3063 static void intel_cpufreq_trace(struct cpudata *cpu, unsigned int trace_type, int old_pstate) 3064 { 3065 struct sample *sample; 3066 3067 if (!trace_pstate_sample_enabled()) 3068 return; 3069 3070 if (!intel_pstate_sample(cpu, ktime_get())) 3071 return; 3072 3073 sample = &cpu->sample; 3074 trace_pstate_sample(trace_type, 3075 0, 3076 old_pstate, 3077 cpu->pstate.current_pstate, 3078 sample->mperf, 3079 sample->aperf, 3080 sample->tsc, 3081 get_avg_frequency(cpu), 3082 fp_toint(cpu->iowait_boost * 100)); 3083 } 3084 3085 static void intel_cpufreq_hwp_update(struct cpudata *cpu, u32 min, u32 max, 3086 u32 desired, bool fast_switch) 3087 { 3088 u64 prev = READ_ONCE(cpu->hwp_req_cached), value = prev; 3089 3090 value &= ~HWP_MIN_PERF(~0L); 3091 value |= HWP_MIN_PERF(min); 3092 3093 value &= ~HWP_MAX_PERF(~0L); 3094 value |= HWP_MAX_PERF(max); 3095 3096 value &= ~HWP_DESIRED_PERF(~0L); 3097 value |= HWP_DESIRED_PERF(desired); 3098 3099 if (value == prev) 3100 return; 3101 3102 WRITE_ONCE(cpu->hwp_req_cached, value); 3103 if (fast_switch) 3104 wrmsrl(MSR_HWP_REQUEST, value); 3105 else 3106 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 3107 } 3108 3109 static void intel_cpufreq_perf_ctl_update(struct cpudata *cpu, 3110 u32 target_pstate, bool fast_switch) 3111 { 3112 if (fast_switch) 3113 wrmsrl(MSR_IA32_PERF_CTL, 3114 pstate_funcs.get_val(cpu, target_pstate)); 3115 else 3116 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL, 3117 pstate_funcs.get_val(cpu, target_pstate)); 3118 } 3119 3120 static int intel_cpufreq_update_pstate(struct cpufreq_policy *policy, 3121 int target_pstate, bool fast_switch) 3122 { 3123 struct cpudata *cpu = all_cpu_data[policy->cpu]; 3124 int old_pstate = cpu->pstate.current_pstate; 3125 3126 target_pstate = intel_pstate_prepare_request(cpu, target_pstate); 3127 if (hwp_active) { 3128 int max_pstate = policy->strict_target ? 3129 target_pstate : cpu->max_perf_ratio; 3130 3131 intel_cpufreq_hwp_update(cpu, target_pstate, max_pstate, 0, 3132 fast_switch); 3133 } else if (target_pstate != old_pstate) { 3134 intel_cpufreq_perf_ctl_update(cpu, target_pstate, fast_switch); 3135 } 3136 3137 cpu->pstate.current_pstate = target_pstate; 3138 3139 intel_cpufreq_trace(cpu, fast_switch ? INTEL_PSTATE_TRACE_FAST_SWITCH : 3140 INTEL_PSTATE_TRACE_TARGET, old_pstate); 3141 3142 return target_pstate; 3143 } 3144 3145 static int intel_cpufreq_target(struct cpufreq_policy *policy, 3146 unsigned int target_freq, 3147 unsigned int relation) 3148 { 3149 struct cpudata *cpu = all_cpu_data[policy->cpu]; 3150 struct cpufreq_freqs freqs; 3151 int target_pstate; 3152 3153 freqs.old = policy->cur; 3154 freqs.new = target_freq; 3155 3156 cpufreq_freq_transition_begin(policy, &freqs); 3157 3158 target_pstate = intel_pstate_freq_to_hwp_rel(cpu, freqs.new, relation); 3159 target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, false); 3160 3161 freqs.new = target_pstate * cpu->pstate.scaling; 3162 3163 cpufreq_freq_transition_end(policy, &freqs, false); 3164 3165 return 0; 3166 } 3167 3168 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy, 3169 unsigned int target_freq) 3170 { 3171 struct cpudata *cpu = all_cpu_data[policy->cpu]; 3172 int target_pstate; 3173 3174 target_pstate = intel_pstate_freq_to_hwp(cpu, target_freq); 3175 3176 target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, true); 3177 3178 return target_pstate * cpu->pstate.scaling; 3179 } 3180 3181 static void intel_cpufreq_adjust_perf(unsigned int cpunum, 3182 unsigned long min_perf, 3183 unsigned long target_perf, 3184 unsigned long capacity) 3185 { 3186 struct cpudata *cpu = all_cpu_data[cpunum]; 3187 u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached); 3188 int old_pstate = cpu->pstate.current_pstate; 3189 int cap_pstate, min_pstate, max_pstate, target_pstate; 3190 3191 cap_pstate = READ_ONCE(global.no_turbo) ? 3192 HWP_GUARANTEED_PERF(hwp_cap) : 3193 HWP_HIGHEST_PERF(hwp_cap); 3194 3195 /* Optimization: Avoid unnecessary divisions. */ 3196 3197 target_pstate = cap_pstate; 3198 if (target_perf < capacity) 3199 target_pstate = DIV_ROUND_UP(cap_pstate * target_perf, capacity); 3200 3201 min_pstate = cap_pstate; 3202 if (min_perf < capacity) 3203 min_pstate = DIV_ROUND_UP(cap_pstate * min_perf, capacity); 3204 3205 if (min_pstate < cpu->pstate.min_pstate) 3206 min_pstate = cpu->pstate.min_pstate; 3207 3208 if (min_pstate < cpu->min_perf_ratio) 3209 min_pstate = cpu->min_perf_ratio; 3210 3211 if (min_pstate > cpu->max_perf_ratio) 3212 min_pstate = cpu->max_perf_ratio; 3213 3214 max_pstate = min(cap_pstate, cpu->max_perf_ratio); 3215 if (max_pstate < min_pstate) 3216 max_pstate = min_pstate; 3217 3218 target_pstate = clamp_t(int, target_pstate, min_pstate, max_pstate); 3219 3220 intel_cpufreq_hwp_update(cpu, min_pstate, max_pstate, target_pstate, true); 3221 3222 cpu->pstate.current_pstate = target_pstate; 3223 intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_FAST_SWITCH, old_pstate); 3224 } 3225 3226 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy) 3227 { 3228 struct freq_qos_request *req; 3229 struct cpudata *cpu; 3230 struct device *dev; 3231 int ret, freq; 3232 3233 dev = get_cpu_device(policy->cpu); 3234 if (!dev) 3235 return -ENODEV; 3236 3237 ret = __intel_pstate_cpu_init(policy); 3238 if (ret) 3239 return ret; 3240 3241 policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY; 3242 /* This reflects the intel_pstate_get_cpu_pstates() setting. */ 3243 policy->cur = policy->cpuinfo.min_freq; 3244 3245 req = kcalloc(2, sizeof(*req), GFP_KERNEL); 3246 if (!req) { 3247 ret = -ENOMEM; 3248 goto pstate_exit; 3249 } 3250 3251 cpu = all_cpu_data[policy->cpu]; 3252 3253 if (hwp_active) { 3254 u64 value; 3255 3256 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY_HWP; 3257 3258 intel_pstate_get_hwp_cap(cpu); 3259 3260 rdmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, &value); 3261 WRITE_ONCE(cpu->hwp_req_cached, value); 3262 3263 cpu->epp_cached = intel_pstate_get_epp(cpu, value); 3264 } else { 3265 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY; 3266 } 3267 3268 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.min_perf_pct, 100); 3269 3270 ret = freq_qos_add_request(&policy->constraints, req, FREQ_QOS_MIN, 3271 freq); 3272 if (ret < 0) { 3273 dev_err(dev, "Failed to add min-freq constraint (%d)\n", ret); 3274 goto free_req; 3275 } 3276 3277 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.max_perf_pct, 100); 3278 3279 ret = freq_qos_add_request(&policy->constraints, req + 1, FREQ_QOS_MAX, 3280 freq); 3281 if (ret < 0) { 3282 dev_err(dev, "Failed to add max-freq constraint (%d)\n", ret); 3283 goto remove_min_req; 3284 } 3285 3286 policy->driver_data = req; 3287 3288 return 0; 3289 3290 remove_min_req: 3291 freq_qos_remove_request(req); 3292 free_req: 3293 kfree(req); 3294 pstate_exit: 3295 intel_pstate_exit_perf_limits(policy); 3296 3297 return ret; 3298 } 3299 3300 static void intel_cpufreq_cpu_exit(struct cpufreq_policy *policy) 3301 { 3302 struct freq_qos_request *req; 3303 3304 req = policy->driver_data; 3305 3306 freq_qos_remove_request(req + 1); 3307 freq_qos_remove_request(req); 3308 kfree(req); 3309 3310 intel_pstate_cpu_exit(policy); 3311 } 3312 3313 static int intel_cpufreq_suspend(struct cpufreq_policy *policy) 3314 { 3315 intel_pstate_suspend(policy); 3316 3317 if (hwp_active) { 3318 struct cpudata *cpu = all_cpu_data[policy->cpu]; 3319 u64 value = READ_ONCE(cpu->hwp_req_cached); 3320 3321 /* 3322 * Clear the desired perf field in MSR_HWP_REQUEST in case 3323 * intel_cpufreq_adjust_perf() is in use and the last value 3324 * written by it may not be suitable. 3325 */ 3326 value &= ~HWP_DESIRED_PERF(~0L); 3327 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 3328 WRITE_ONCE(cpu->hwp_req_cached, value); 3329 } 3330 3331 return 0; 3332 } 3333 3334 static struct cpufreq_driver intel_cpufreq = { 3335 .flags = CPUFREQ_CONST_LOOPS, 3336 .verify = intel_cpufreq_verify_policy, 3337 .target = intel_cpufreq_target, 3338 .fast_switch = intel_cpufreq_fast_switch, 3339 .init = intel_cpufreq_cpu_init, 3340 .exit = intel_cpufreq_cpu_exit, 3341 .offline = intel_cpufreq_cpu_offline, 3342 .online = intel_pstate_cpu_online, 3343 .suspend = intel_cpufreq_suspend, 3344 .resume = intel_pstate_resume, 3345 .update_limits = intel_pstate_update_limits, 3346 .name = "intel_cpufreq", 3347 }; 3348 3349 static struct cpufreq_driver *default_driver; 3350 3351 static void intel_pstate_driver_cleanup(void) 3352 { 3353 unsigned int cpu; 3354 3355 cpus_read_lock(); 3356 for_each_online_cpu(cpu) { 3357 if (all_cpu_data[cpu]) { 3358 if (intel_pstate_driver == &intel_pstate) 3359 intel_pstate_clear_update_util_hook(cpu); 3360 3361 kfree(all_cpu_data[cpu]); 3362 WRITE_ONCE(all_cpu_data[cpu], NULL); 3363 } 3364 } 3365 cpus_read_unlock(); 3366 3367 intel_pstate_driver = NULL; 3368 } 3369 3370 static int intel_pstate_register_driver(struct cpufreq_driver *driver) 3371 { 3372 bool refresh_cpu_cap_scaling; 3373 int ret; 3374 3375 if (driver == &intel_pstate) 3376 intel_pstate_sysfs_expose_hwp_dynamic_boost(); 3377 3378 memset(&global, 0, sizeof(global)); 3379 global.max_perf_pct = 100; 3380 global.turbo_disabled = turbo_is_disabled(); 3381 global.no_turbo = global.turbo_disabled; 3382 3383 arch_set_max_freq_ratio(global.turbo_disabled); 3384 3385 refresh_cpu_cap_scaling = hybrid_clear_max_perf_cpu(); 3386 3387 intel_pstate_driver = driver; 3388 ret = cpufreq_register_driver(intel_pstate_driver); 3389 if (ret) { 3390 intel_pstate_driver_cleanup(); 3391 return ret; 3392 } 3393 3394 global.min_perf_pct = min_perf_pct_min(); 3395 3396 hybrid_init_cpu_capacity_scaling(refresh_cpu_cap_scaling); 3397 3398 return 0; 3399 } 3400 3401 static ssize_t intel_pstate_show_status(char *buf) 3402 { 3403 if (!intel_pstate_driver) 3404 return sprintf(buf, "off\n"); 3405 3406 return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ? 3407 "active" : "passive"); 3408 } 3409 3410 static int intel_pstate_update_status(const char *buf, size_t size) 3411 { 3412 if (size == 3 && !strncmp(buf, "off", size)) { 3413 if (!intel_pstate_driver) 3414 return -EINVAL; 3415 3416 if (hwp_active) 3417 return -EBUSY; 3418 3419 cpufreq_unregister_driver(intel_pstate_driver); 3420 intel_pstate_driver_cleanup(); 3421 return 0; 3422 } 3423 3424 if (size == 6 && !strncmp(buf, "active", size)) { 3425 if (intel_pstate_driver) { 3426 if (intel_pstate_driver == &intel_pstate) 3427 return 0; 3428 3429 cpufreq_unregister_driver(intel_pstate_driver); 3430 } 3431 3432 return intel_pstate_register_driver(&intel_pstate); 3433 } 3434 3435 if (size == 7 && !strncmp(buf, "passive", size)) { 3436 if (intel_pstate_driver) { 3437 if (intel_pstate_driver == &intel_cpufreq) 3438 return 0; 3439 3440 cpufreq_unregister_driver(intel_pstate_driver); 3441 intel_pstate_sysfs_hide_hwp_dynamic_boost(); 3442 } 3443 3444 return intel_pstate_register_driver(&intel_cpufreq); 3445 } 3446 3447 return -EINVAL; 3448 } 3449 3450 static int no_load __initdata; 3451 static int no_hwp __initdata; 3452 static int hwp_only __initdata; 3453 static unsigned int force_load __initdata; 3454 3455 static int __init intel_pstate_msrs_not_valid(void) 3456 { 3457 if (!pstate_funcs.get_max(0) || 3458 !pstate_funcs.get_min(0) || 3459 !pstate_funcs.get_turbo(0)) 3460 return -ENODEV; 3461 3462 return 0; 3463 } 3464 3465 static void __init copy_cpu_funcs(struct pstate_funcs *funcs) 3466 { 3467 pstate_funcs.get_max = funcs->get_max; 3468 pstate_funcs.get_max_physical = funcs->get_max_physical; 3469 pstate_funcs.get_min = funcs->get_min; 3470 pstate_funcs.get_turbo = funcs->get_turbo; 3471 pstate_funcs.get_scaling = funcs->get_scaling; 3472 pstate_funcs.get_val = funcs->get_val; 3473 pstate_funcs.get_vid = funcs->get_vid; 3474 pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift; 3475 } 3476 3477 #ifdef CONFIG_ACPI 3478 3479 static bool __init intel_pstate_no_acpi_pss(void) 3480 { 3481 int i; 3482 3483 for_each_possible_cpu(i) { 3484 acpi_status status; 3485 union acpi_object *pss; 3486 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; 3487 struct acpi_processor *pr = per_cpu(processors, i); 3488 3489 if (!pr) 3490 continue; 3491 3492 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer); 3493 if (ACPI_FAILURE(status)) 3494 continue; 3495 3496 pss = buffer.pointer; 3497 if (pss && pss->type == ACPI_TYPE_PACKAGE) { 3498 kfree(pss); 3499 return false; 3500 } 3501 3502 kfree(pss); 3503 } 3504 3505 pr_debug("ACPI _PSS not found\n"); 3506 return true; 3507 } 3508 3509 static bool __init intel_pstate_no_acpi_pcch(void) 3510 { 3511 acpi_status status; 3512 acpi_handle handle; 3513 3514 status = acpi_get_handle(NULL, "\\_SB", &handle); 3515 if (ACPI_FAILURE(status)) 3516 goto not_found; 3517 3518 if (acpi_has_method(handle, "PCCH")) 3519 return false; 3520 3521 not_found: 3522 pr_debug("ACPI PCCH not found\n"); 3523 return true; 3524 } 3525 3526 static bool __init intel_pstate_has_acpi_ppc(void) 3527 { 3528 int i; 3529 3530 for_each_possible_cpu(i) { 3531 struct acpi_processor *pr = per_cpu(processors, i); 3532 3533 if (!pr) 3534 continue; 3535 if (acpi_has_method(pr->handle, "_PPC")) 3536 return true; 3537 } 3538 pr_debug("ACPI _PPC not found\n"); 3539 return false; 3540 } 3541 3542 enum { 3543 PSS, 3544 PPC, 3545 }; 3546 3547 /* Hardware vendor-specific info that has its own power management modes */ 3548 static struct acpi_platform_list plat_info[] __initdata = { 3549 {"HP ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, NULL, PSS}, 3550 {"ORACLE", "X4-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3551 {"ORACLE", "X4-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3552 {"ORACLE", "X4-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3553 {"ORACLE", "X3-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3554 {"ORACLE", "X3-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3555 {"ORACLE", "X3-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3556 {"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3557 {"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3558 {"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3559 {"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3560 {"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3561 {"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3562 {"ORACLE", "X6-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3563 {"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3564 { } /* End */ 3565 }; 3566 3567 #define BITMASK_OOB (BIT(8) | BIT(18)) 3568 3569 static bool __init intel_pstate_platform_pwr_mgmt_exists(void) 3570 { 3571 const struct x86_cpu_id *id; 3572 u64 misc_pwr; 3573 int idx; 3574 3575 id = x86_match_cpu(intel_pstate_cpu_oob_ids); 3576 if (id) { 3577 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr); 3578 if (misc_pwr & BITMASK_OOB) { 3579 pr_debug("Bit 8 or 18 in the MISC_PWR_MGMT MSR set\n"); 3580 pr_debug("P states are controlled in Out of Band mode by the firmware/hardware\n"); 3581 return true; 3582 } 3583 } 3584 3585 idx = acpi_match_platform_list(plat_info); 3586 if (idx < 0) 3587 return false; 3588 3589 switch (plat_info[idx].data) { 3590 case PSS: 3591 if (!intel_pstate_no_acpi_pss()) 3592 return false; 3593 3594 return intel_pstate_no_acpi_pcch(); 3595 case PPC: 3596 return intel_pstate_has_acpi_ppc() && !force_load; 3597 } 3598 3599 return false; 3600 } 3601 3602 static void intel_pstate_request_control_from_smm(void) 3603 { 3604 /* 3605 * It may be unsafe to request P-states control from SMM if _PPC support 3606 * has not been enabled. 3607 */ 3608 if (acpi_ppc) 3609 acpi_processor_pstate_control(); 3610 } 3611 #else /* CONFIG_ACPI not enabled */ 3612 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; } 3613 static inline bool intel_pstate_has_acpi_ppc(void) { return false; } 3614 static inline void intel_pstate_request_control_from_smm(void) {} 3615 #endif /* CONFIG_ACPI */ 3616 3617 #define INTEL_PSTATE_HWP_BROADWELL 0x01 3618 3619 #define X86_MATCH_HWP(vfm, hwp_mode) \ 3620 X86_MATCH_VFM_FEATURE(vfm, X86_FEATURE_HWP, hwp_mode) 3621 3622 static const struct x86_cpu_id hwp_support_ids[] __initconst = { 3623 X86_MATCH_HWP(INTEL_BROADWELL_X, INTEL_PSTATE_HWP_BROADWELL), 3624 X86_MATCH_HWP(INTEL_BROADWELL_D, INTEL_PSTATE_HWP_BROADWELL), 3625 X86_MATCH_HWP(INTEL_ANY, 0), 3626 {} 3627 }; 3628 3629 static bool intel_pstate_hwp_is_enabled(void) 3630 { 3631 u64 value; 3632 3633 rdmsrl(MSR_PM_ENABLE, value); 3634 return !!(value & 0x1); 3635 } 3636 3637 #define POWERSAVE_MASK GENMASK(7, 0) 3638 #define BALANCE_POWER_MASK GENMASK(15, 8) 3639 #define BALANCE_PERFORMANCE_MASK GENMASK(23, 16) 3640 #define PERFORMANCE_MASK GENMASK(31, 24) 3641 3642 #define HWP_SET_EPP_VALUES(powersave, balance_power, balance_perf, performance) \ 3643 (FIELD_PREP_CONST(POWERSAVE_MASK, powersave) |\ 3644 FIELD_PREP_CONST(BALANCE_POWER_MASK, balance_power) |\ 3645 FIELD_PREP_CONST(BALANCE_PERFORMANCE_MASK, balance_perf) |\ 3646 FIELD_PREP_CONST(PERFORMANCE_MASK, performance)) 3647 3648 #define HWP_SET_DEF_BALANCE_PERF_EPP(balance_perf) \ 3649 (HWP_SET_EPP_VALUES(HWP_EPP_POWERSAVE, HWP_EPP_BALANCE_POWERSAVE,\ 3650 balance_perf, HWP_EPP_PERFORMANCE)) 3651 3652 static const struct x86_cpu_id intel_epp_default[] = { 3653 /* 3654 * Set EPP value as 102, this is the max suggested EPP 3655 * which can result in one core turbo frequency for 3656 * AlderLake Mobile CPUs. 3657 */ 3658 X86_MATCH_VFM(INTEL_ALDERLAKE_L, HWP_SET_DEF_BALANCE_PERF_EPP(102)), 3659 X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, HWP_SET_DEF_BALANCE_PERF_EPP(32)), 3660 X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, HWP_SET_DEF_BALANCE_PERF_EPP(32)), 3661 X86_MATCH_VFM(INTEL_METEORLAKE_L, HWP_SET_EPP_VALUES(HWP_EPP_POWERSAVE, 3662 179, 64, 16)), 3663 X86_MATCH_VFM(INTEL_ARROWLAKE, HWP_SET_EPP_VALUES(HWP_EPP_POWERSAVE, 3664 179, 64, 16)), 3665 {} 3666 }; 3667 3668 static const struct x86_cpu_id intel_hybrid_scaling_factor[] = { 3669 X86_MATCH_VFM(INTEL_METEORLAKE_L, HYBRID_SCALING_FACTOR_MTL), 3670 X86_MATCH_VFM(INTEL_ARROWLAKE, HYBRID_SCALING_FACTOR_MTL), 3671 X86_MATCH_VFM(INTEL_LUNARLAKE_M, HYBRID_SCALING_FACTOR_LNL), 3672 {} 3673 }; 3674 3675 static int __init intel_pstate_init(void) 3676 { 3677 static struct cpudata **_all_cpu_data; 3678 const struct x86_cpu_id *id; 3679 int rc; 3680 3681 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) 3682 return -ENODEV; 3683 3684 id = x86_match_cpu(hwp_support_ids); 3685 if (id) { 3686 hwp_forced = intel_pstate_hwp_is_enabled(); 3687 3688 if (hwp_forced) 3689 pr_info("HWP enabled by BIOS\n"); 3690 else if (no_load) 3691 return -ENODEV; 3692 3693 copy_cpu_funcs(&core_funcs); 3694 /* 3695 * Avoid enabling HWP for processors without EPP support, 3696 * because that means incomplete HWP implementation which is a 3697 * corner case and supporting it is generally problematic. 3698 * 3699 * If HWP is enabled already, though, there is no choice but to 3700 * deal with it. 3701 */ 3702 if ((!no_hwp && boot_cpu_has(X86_FEATURE_HWP_EPP)) || hwp_forced) { 3703 hwp_active = true; 3704 hwp_mode_bdw = id->driver_data; 3705 intel_pstate.attr = hwp_cpufreq_attrs; 3706 intel_cpufreq.attr = hwp_cpufreq_attrs; 3707 intel_cpufreq.flags |= CPUFREQ_NEED_UPDATE_LIMITS; 3708 intel_cpufreq.adjust_perf = intel_cpufreq_adjust_perf; 3709 if (!default_driver) 3710 default_driver = &intel_pstate; 3711 3712 pstate_funcs.get_cpu_scaling = hwp_get_cpu_scaling; 3713 3714 goto hwp_cpu_matched; 3715 } 3716 pr_info("HWP not enabled\n"); 3717 } else { 3718 if (no_load) 3719 return -ENODEV; 3720 3721 id = x86_match_cpu(intel_pstate_cpu_ids); 3722 if (!id) { 3723 pr_info("CPU model not supported\n"); 3724 return -ENODEV; 3725 } 3726 3727 copy_cpu_funcs((struct pstate_funcs *)id->driver_data); 3728 } 3729 3730 if (intel_pstate_msrs_not_valid()) { 3731 pr_info("Invalid MSRs\n"); 3732 return -ENODEV; 3733 } 3734 /* Without HWP start in the passive mode. */ 3735 if (!default_driver) 3736 default_driver = &intel_cpufreq; 3737 3738 hwp_cpu_matched: 3739 /* 3740 * The Intel pstate driver will be ignored if the platform 3741 * firmware has its own power management modes. 3742 */ 3743 if (intel_pstate_platform_pwr_mgmt_exists()) { 3744 pr_info("P-states controlled by the platform\n"); 3745 return -ENODEV; 3746 } 3747 3748 if (!hwp_active && hwp_only) 3749 return -ENOTSUPP; 3750 3751 pr_info("Intel P-state driver initializing\n"); 3752 3753 _all_cpu_data = vzalloc(array_size(sizeof(void *), num_possible_cpus())); 3754 if (!_all_cpu_data) 3755 return -ENOMEM; 3756 3757 WRITE_ONCE(all_cpu_data, _all_cpu_data); 3758 3759 intel_pstate_request_control_from_smm(); 3760 3761 intel_pstate_sysfs_expose_params(); 3762 3763 if (hwp_active) { 3764 const struct x86_cpu_id *id = x86_match_cpu(intel_epp_default); 3765 const struct x86_cpu_id *hybrid_id = x86_match_cpu(intel_hybrid_scaling_factor); 3766 3767 if (id) { 3768 epp_values[EPP_INDEX_POWERSAVE] = 3769 FIELD_GET(POWERSAVE_MASK, id->driver_data); 3770 epp_values[EPP_INDEX_BALANCE_POWERSAVE] = 3771 FIELD_GET(BALANCE_POWER_MASK, id->driver_data); 3772 epp_values[EPP_INDEX_BALANCE_PERFORMANCE] = 3773 FIELD_GET(BALANCE_PERFORMANCE_MASK, id->driver_data); 3774 epp_values[EPP_INDEX_PERFORMANCE] = 3775 FIELD_GET(PERFORMANCE_MASK, id->driver_data); 3776 pr_debug("Updated EPPs powersave:%x balanced power:%x balanced perf:%x performance:%x\n", 3777 epp_values[EPP_INDEX_POWERSAVE], 3778 epp_values[EPP_INDEX_BALANCE_POWERSAVE], 3779 epp_values[EPP_INDEX_BALANCE_PERFORMANCE], 3780 epp_values[EPP_INDEX_PERFORMANCE]); 3781 } 3782 3783 if (hybrid_id) { 3784 hybrid_scaling_factor = hybrid_id->driver_data; 3785 pr_debug("hybrid scaling factor: %d\n", hybrid_scaling_factor); 3786 } 3787 3788 } 3789 3790 mutex_lock(&intel_pstate_driver_lock); 3791 rc = intel_pstate_register_driver(default_driver); 3792 mutex_unlock(&intel_pstate_driver_lock); 3793 if (rc) { 3794 intel_pstate_sysfs_remove(); 3795 return rc; 3796 } 3797 3798 if (hwp_active) { 3799 const struct x86_cpu_id *id; 3800 3801 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids); 3802 if (id) { 3803 set_power_ctl_ee_state(false); 3804 pr_info("Disabling energy efficiency optimization\n"); 3805 } 3806 3807 pr_info("HWP enabled\n"); 3808 } else if (boot_cpu_has(X86_FEATURE_HYBRID_CPU)) { 3809 pr_warn("Problematic setup: Hybrid processor with disabled HWP\n"); 3810 } 3811 3812 return 0; 3813 } 3814 device_initcall(intel_pstate_init); 3815 3816 static int __init intel_pstate_setup(char *str) 3817 { 3818 if (!str) 3819 return -EINVAL; 3820 3821 if (!strcmp(str, "disable")) 3822 no_load = 1; 3823 else if (!strcmp(str, "active")) 3824 default_driver = &intel_pstate; 3825 else if (!strcmp(str, "passive")) 3826 default_driver = &intel_cpufreq; 3827 3828 if (!strcmp(str, "no_hwp")) 3829 no_hwp = 1; 3830 3831 if (!strcmp(str, "force")) 3832 force_load = 1; 3833 if (!strcmp(str, "hwp_only")) 3834 hwp_only = 1; 3835 if (!strcmp(str, "per_cpu_perf_limits")) 3836 per_cpu_limits = true; 3837 3838 #ifdef CONFIG_ACPI 3839 if (!strcmp(str, "support_acpi_ppc")) 3840 acpi_ppc = true; 3841 #endif 3842 3843 return 0; 3844 } 3845 early_param("intel_pstate", intel_pstate_setup); 3846 3847 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>"); 3848 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors"); 3849