1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * intel_pstate.c: Native P state management for Intel processors 4 * 5 * (C) Copyright 2012 Intel Corporation 6 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com> 7 */ 8 9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10 11 #include <linux/kernel.h> 12 #include <linux/kernel_stat.h> 13 #include <linux/module.h> 14 #include <linux/ktime.h> 15 #include <linux/hrtimer.h> 16 #include <linux/tick.h> 17 #include <linux/slab.h> 18 #include <linux/sched/cpufreq.h> 19 #include <linux/sched/smt.h> 20 #include <linux/list.h> 21 #include <linux/cpu.h> 22 #include <linux/cpufreq.h> 23 #include <linux/sysfs.h> 24 #include <linux/types.h> 25 #include <linux/fs.h> 26 #include <linux/acpi.h> 27 #include <linux/vmalloc.h> 28 #include <linux/pm_qos.h> 29 #include <linux/bitfield.h> 30 #include <trace/events/power.h> 31 #include <linux/units.h> 32 33 #include <asm/cpu.h> 34 #include <asm/div64.h> 35 #include <asm/msr.h> 36 #include <asm/cpu_device_id.h> 37 #include <asm/cpufeature.h> 38 #include <asm/intel-family.h> 39 #include "../drivers/thermal/intel/thermal_interrupt.h" 40 41 #define INTEL_PSTATE_SAMPLING_INTERVAL (10 * NSEC_PER_MSEC) 42 43 #define INTEL_CPUFREQ_TRANSITION_LATENCY 20000 44 #define INTEL_CPUFREQ_TRANSITION_DELAY_HWP 5000 45 #define INTEL_CPUFREQ_TRANSITION_DELAY 500 46 47 #ifdef CONFIG_ACPI 48 #include <acpi/processor.h> 49 #include <acpi/cppc_acpi.h> 50 #endif 51 52 #define FRAC_BITS 8 53 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS) 54 #define fp_toint(X) ((X) >> FRAC_BITS) 55 56 #define ONE_EIGHTH_FP ((int64_t)1 << (FRAC_BITS - 3)) 57 58 #define EXT_BITS 6 59 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS) 60 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS) 61 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS) 62 63 static inline int32_t mul_fp(int32_t x, int32_t y) 64 { 65 return ((int64_t)x * (int64_t)y) >> FRAC_BITS; 66 } 67 68 static inline int32_t div_fp(s64 x, s64 y) 69 { 70 return div64_s64((int64_t)x << FRAC_BITS, y); 71 } 72 73 static inline int ceiling_fp(int32_t x) 74 { 75 int mask, ret; 76 77 ret = fp_toint(x); 78 mask = (1 << FRAC_BITS) - 1; 79 if (x & mask) 80 ret += 1; 81 return ret; 82 } 83 84 static inline u64 mul_ext_fp(u64 x, u64 y) 85 { 86 return (x * y) >> EXT_FRAC_BITS; 87 } 88 89 static inline u64 div_ext_fp(u64 x, u64 y) 90 { 91 return div64_u64(x << EXT_FRAC_BITS, y); 92 } 93 94 /** 95 * struct sample - Store performance sample 96 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average 97 * performance during last sample period 98 * @busy_scaled: Scaled busy value which is used to calculate next 99 * P state. This can be different than core_avg_perf 100 * to account for cpu idle period 101 * @aperf: Difference of actual performance frequency clock count 102 * read from APERF MSR between last and current sample 103 * @mperf: Difference of maximum performance frequency clock count 104 * read from MPERF MSR between last and current sample 105 * @tsc: Difference of time stamp counter between last and 106 * current sample 107 * @time: Current time from scheduler 108 * 109 * This structure is used in the cpudata structure to store performance sample 110 * data for choosing next P State. 111 */ 112 struct sample { 113 int32_t core_avg_perf; 114 int32_t busy_scaled; 115 u64 aperf; 116 u64 mperf; 117 u64 tsc; 118 u64 time; 119 }; 120 121 /** 122 * struct pstate_data - Store P state data 123 * @current_pstate: Current requested P state 124 * @min_pstate: Min P state possible for this platform 125 * @max_pstate: Max P state possible for this platform 126 * @max_pstate_physical:This is physical Max P state for a processor 127 * This can be higher than the max_pstate which can 128 * be limited by platform thermal design power limits 129 * @perf_ctl_scaling: PERF_CTL P-state to frequency scaling factor 130 * @scaling: Scaling factor between performance and frequency 131 * @turbo_pstate: Max Turbo P state possible for this platform 132 * @min_freq: @min_pstate frequency in cpufreq units 133 * @max_freq: @max_pstate frequency in cpufreq units 134 * @turbo_freq: @turbo_pstate frequency in cpufreq units 135 * 136 * Stores the per cpu model P state limits and current P state. 137 */ 138 struct pstate_data { 139 int current_pstate; 140 int min_pstate; 141 int max_pstate; 142 int max_pstate_physical; 143 int perf_ctl_scaling; 144 int scaling; 145 int turbo_pstate; 146 unsigned int min_freq; 147 unsigned int max_freq; 148 unsigned int turbo_freq; 149 }; 150 151 /** 152 * struct vid_data - Stores voltage information data 153 * @min: VID data for this platform corresponding to 154 * the lowest P state 155 * @max: VID data corresponding to the highest P State. 156 * @turbo: VID data for turbo P state 157 * @ratio: Ratio of (vid max - vid min) / 158 * (max P state - Min P State) 159 * 160 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling) 161 * This data is used in Atom platforms, where in addition to target P state, 162 * the voltage data needs to be specified to select next P State. 163 */ 164 struct vid_data { 165 int min; 166 int max; 167 int turbo; 168 int32_t ratio; 169 }; 170 171 /** 172 * struct global_params - Global parameters, mostly tunable via sysfs. 173 * @no_turbo: Whether or not to use turbo P-states. 174 * @turbo_disabled: Whether or not turbo P-states are available at all, 175 * based on the MSR_IA32_MISC_ENABLE value and whether or 176 * not the maximum reported turbo P-state is different from 177 * the maximum reported non-turbo one. 178 * @min_perf_pct: Minimum capacity limit in percent of the maximum turbo 179 * P-state capacity. 180 * @max_perf_pct: Maximum capacity limit in percent of the maximum turbo 181 * P-state capacity. 182 */ 183 struct global_params { 184 bool no_turbo; 185 bool turbo_disabled; 186 int max_perf_pct; 187 int min_perf_pct; 188 }; 189 190 /** 191 * struct cpudata - Per CPU instance data storage 192 * @cpu: CPU number for this instance data 193 * @policy: CPUFreq policy value 194 * @update_util: CPUFreq utility callback information 195 * @update_util_set: CPUFreq utility callback is set 196 * @iowait_boost: iowait-related boost fraction 197 * @last_update: Time of the last update. 198 * @pstate: Stores P state limits for this CPU 199 * @vid: Stores VID limits for this CPU 200 * @last_sample_time: Last Sample time 201 * @aperf_mperf_shift: APERF vs MPERF counting frequency difference 202 * @prev_aperf: Last APERF value read from APERF MSR 203 * @prev_mperf: Last MPERF value read from MPERF MSR 204 * @prev_tsc: Last timestamp counter (TSC) value 205 * @sample: Storage for storing last Sample data 206 * @min_perf_ratio: Minimum capacity in terms of PERF or HWP ratios 207 * @max_perf_ratio: Maximum capacity in terms of PERF or HWP ratios 208 * @acpi_perf_data: Stores ACPI perf information read from _PSS 209 * @valid_pss_table: Set to true for valid ACPI _PSS entries found 210 * @epp_powersave: Last saved HWP energy performance preference 211 * (EPP) or energy performance bias (EPB), 212 * when policy switched to performance 213 * @epp_policy: Last saved policy used to set EPP/EPB 214 * @epp_default: Power on default HWP energy performance 215 * preference/bias 216 * @epp_cached: Cached HWP energy-performance preference value 217 * @hwp_req_cached: Cached value of the last HWP Request MSR 218 * @hwp_cap_cached: Cached value of the last HWP Capabilities MSR 219 * @last_io_update: Last time when IO wake flag was set 220 * @capacity_perf: Highest perf used for scale invariance 221 * @sched_flags: Store scheduler flags for possible cross CPU update 222 * @hwp_boost_min: Last HWP boosted min performance 223 * @suspended: Whether or not the driver has been suspended. 224 * @hwp_notify_work: workqueue for HWP notifications. 225 * 226 * This structure stores per CPU instance data for all CPUs. 227 */ 228 struct cpudata { 229 int cpu; 230 231 unsigned int policy; 232 struct update_util_data update_util; 233 bool update_util_set; 234 235 struct pstate_data pstate; 236 struct vid_data vid; 237 238 u64 last_update; 239 u64 last_sample_time; 240 u64 aperf_mperf_shift; 241 u64 prev_aperf; 242 u64 prev_mperf; 243 u64 prev_tsc; 244 struct sample sample; 245 int32_t min_perf_ratio; 246 int32_t max_perf_ratio; 247 #ifdef CONFIG_ACPI 248 struct acpi_processor_performance acpi_perf_data; 249 bool valid_pss_table; 250 #endif 251 unsigned int iowait_boost; 252 s16 epp_powersave; 253 s16 epp_policy; 254 s16 epp_default; 255 s16 epp_cached; 256 u64 hwp_req_cached; 257 u64 hwp_cap_cached; 258 u64 last_io_update; 259 unsigned int capacity_perf; 260 unsigned int sched_flags; 261 u32 hwp_boost_min; 262 bool suspended; 263 struct delayed_work hwp_notify_work; 264 }; 265 266 static struct cpudata **all_cpu_data; 267 268 /** 269 * struct pstate_funcs - Per CPU model specific callbacks 270 * @get_max: Callback to get maximum non turbo effective P state 271 * @get_max_physical: Callback to get maximum non turbo physical P state 272 * @get_min: Callback to get minimum P state 273 * @get_turbo: Callback to get turbo P state 274 * @get_scaling: Callback to get frequency scaling factor 275 * @get_cpu_scaling: Get frequency scaling factor for a given cpu 276 * @get_aperf_mperf_shift: Callback to get the APERF vs MPERF frequency difference 277 * @get_val: Callback to convert P state to actual MSR write value 278 * @get_vid: Callback to get VID data for Atom platforms 279 * 280 * Core and Atom CPU models have different way to get P State limits. This 281 * structure is used to store those callbacks. 282 */ 283 struct pstate_funcs { 284 int (*get_max)(int cpu); 285 int (*get_max_physical)(int cpu); 286 int (*get_min)(int cpu); 287 int (*get_turbo)(int cpu); 288 int (*get_scaling)(void); 289 int (*get_cpu_scaling)(int cpu); 290 int (*get_aperf_mperf_shift)(void); 291 u64 (*get_val)(struct cpudata*, int pstate); 292 void (*get_vid)(struct cpudata *); 293 }; 294 295 static struct pstate_funcs pstate_funcs __read_mostly; 296 297 static bool hwp_active __ro_after_init; 298 static int hwp_mode_bdw __ro_after_init; 299 static bool per_cpu_limits __ro_after_init; 300 static bool hwp_forced __ro_after_init; 301 static bool hwp_boost __read_mostly; 302 static bool hwp_is_hybrid; 303 304 static struct cpufreq_driver *intel_pstate_driver __read_mostly; 305 306 #define HYBRID_SCALING_FACTOR_ADL 78741 307 #define HYBRID_SCALING_FACTOR_MTL 80000 308 #define HYBRID_SCALING_FACTOR_LNL 86957 309 310 static int hybrid_scaling_factor; 311 312 static inline int core_get_scaling(void) 313 { 314 return 100000; 315 } 316 317 #ifdef CONFIG_ACPI 318 static bool acpi_ppc; 319 #endif 320 321 static struct global_params global; 322 323 static DEFINE_MUTEX(intel_pstate_driver_lock); 324 static DEFINE_MUTEX(intel_pstate_limits_lock); 325 326 #ifdef CONFIG_ACPI 327 328 static bool intel_pstate_acpi_pm_profile_server(void) 329 { 330 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER || 331 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER) 332 return true; 333 334 return false; 335 } 336 337 static bool intel_pstate_get_ppc_enable_status(void) 338 { 339 if (intel_pstate_acpi_pm_profile_server()) 340 return true; 341 342 return acpi_ppc; 343 } 344 345 #ifdef CONFIG_ACPI_CPPC_LIB 346 347 /* The work item is needed to avoid CPU hotplug locking issues */ 348 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work) 349 { 350 sched_set_itmt_support(); 351 } 352 353 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn); 354 355 #define CPPC_MAX_PERF U8_MAX 356 357 static void intel_pstate_set_itmt_prio(int cpu) 358 { 359 struct cppc_perf_caps cppc_perf; 360 static u32 max_highest_perf = 0, min_highest_perf = U32_MAX; 361 int ret; 362 363 ret = cppc_get_perf_caps(cpu, &cppc_perf); 364 /* 365 * If CPPC is not available, fall back to MSR_HWP_CAPABILITIES bits [8:0]. 366 * 367 * Also, on some systems with overclocking enabled, CPPC.highest_perf is 368 * hardcoded to 0xff, so CPPC.highest_perf cannot be used to enable ITMT. 369 * Fall back to MSR_HWP_CAPABILITIES then too. 370 */ 371 if (ret || cppc_perf.highest_perf == CPPC_MAX_PERF) 372 cppc_perf.highest_perf = HWP_HIGHEST_PERF(READ_ONCE(all_cpu_data[cpu]->hwp_cap_cached)); 373 374 /* 375 * The priorities can be set regardless of whether or not 376 * sched_set_itmt_support(true) has been called and it is valid to 377 * update them at any time after it has been called. 378 */ 379 sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu); 380 381 if (max_highest_perf <= min_highest_perf) { 382 if (cppc_perf.highest_perf > max_highest_perf) 383 max_highest_perf = cppc_perf.highest_perf; 384 385 if (cppc_perf.highest_perf < min_highest_perf) 386 min_highest_perf = cppc_perf.highest_perf; 387 388 if (max_highest_perf > min_highest_perf) { 389 /* 390 * This code can be run during CPU online under the 391 * CPU hotplug locks, so sched_set_itmt_support() 392 * cannot be called from here. Queue up a work item 393 * to invoke it. 394 */ 395 schedule_work(&sched_itmt_work); 396 } 397 } 398 } 399 400 static int intel_pstate_get_cppc_guaranteed(int cpu) 401 { 402 struct cppc_perf_caps cppc_perf; 403 int ret; 404 405 ret = cppc_get_perf_caps(cpu, &cppc_perf); 406 if (ret) 407 return ret; 408 409 if (cppc_perf.guaranteed_perf) 410 return cppc_perf.guaranteed_perf; 411 412 return cppc_perf.nominal_perf; 413 } 414 415 static int intel_pstate_cppc_get_scaling(int cpu) 416 { 417 struct cppc_perf_caps cppc_perf; 418 419 /* 420 * Compute the perf-to-frequency scaling factor for the given CPU if 421 * possible, unless it would be 0. 422 */ 423 if (!cppc_get_perf_caps(cpu, &cppc_perf) && 424 cppc_perf.nominal_perf && cppc_perf.nominal_freq) 425 return div_u64(cppc_perf.nominal_freq * KHZ_PER_MHZ, 426 cppc_perf.nominal_perf); 427 428 return core_get_scaling(); 429 } 430 431 #else /* CONFIG_ACPI_CPPC_LIB */ 432 static inline void intel_pstate_set_itmt_prio(int cpu) 433 { 434 } 435 #endif /* CONFIG_ACPI_CPPC_LIB */ 436 437 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) 438 { 439 struct cpudata *cpu; 440 int ret; 441 int i; 442 443 if (hwp_active) { 444 intel_pstate_set_itmt_prio(policy->cpu); 445 return; 446 } 447 448 if (!intel_pstate_get_ppc_enable_status()) 449 return; 450 451 cpu = all_cpu_data[policy->cpu]; 452 453 ret = acpi_processor_register_performance(&cpu->acpi_perf_data, 454 policy->cpu); 455 if (ret) 456 return; 457 458 /* 459 * Check if the control value in _PSS is for PERF_CTL MSR, which should 460 * guarantee that the states returned by it map to the states in our 461 * list directly. 462 */ 463 if (cpu->acpi_perf_data.control_register.space_id != 464 ACPI_ADR_SPACE_FIXED_HARDWARE) 465 goto err; 466 467 /* 468 * If there is only one entry _PSS, simply ignore _PSS and continue as 469 * usual without taking _PSS into account 470 */ 471 if (cpu->acpi_perf_data.state_count < 2) 472 goto err; 473 474 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu); 475 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) { 476 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n", 477 (i == cpu->acpi_perf_data.state ? '*' : ' '), i, 478 (u32) cpu->acpi_perf_data.states[i].core_frequency, 479 (u32) cpu->acpi_perf_data.states[i].power, 480 (u32) cpu->acpi_perf_data.states[i].control); 481 } 482 483 cpu->valid_pss_table = true; 484 pr_debug("_PPC limits will be enforced\n"); 485 486 return; 487 488 err: 489 cpu->valid_pss_table = false; 490 acpi_processor_unregister_performance(policy->cpu); 491 } 492 493 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) 494 { 495 struct cpudata *cpu; 496 497 cpu = all_cpu_data[policy->cpu]; 498 if (!cpu->valid_pss_table) 499 return; 500 501 acpi_processor_unregister_performance(policy->cpu); 502 } 503 #else /* CONFIG_ACPI */ 504 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) 505 { 506 } 507 508 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) 509 { 510 } 511 512 static inline bool intel_pstate_acpi_pm_profile_server(void) 513 { 514 return false; 515 } 516 #endif /* CONFIG_ACPI */ 517 518 #ifndef CONFIG_ACPI_CPPC_LIB 519 static inline int intel_pstate_get_cppc_guaranteed(int cpu) 520 { 521 return -ENOTSUPP; 522 } 523 524 static int intel_pstate_cppc_get_scaling(int cpu) 525 { 526 return core_get_scaling(); 527 } 528 #endif /* CONFIG_ACPI_CPPC_LIB */ 529 530 static int intel_pstate_freq_to_hwp_rel(struct cpudata *cpu, int freq, 531 unsigned int relation) 532 { 533 if (freq == cpu->pstate.turbo_freq) 534 return cpu->pstate.turbo_pstate; 535 536 if (freq == cpu->pstate.max_freq) 537 return cpu->pstate.max_pstate; 538 539 switch (relation) { 540 case CPUFREQ_RELATION_H: 541 return freq / cpu->pstate.scaling; 542 case CPUFREQ_RELATION_C: 543 return DIV_ROUND_CLOSEST(freq, cpu->pstate.scaling); 544 } 545 546 return DIV_ROUND_UP(freq, cpu->pstate.scaling); 547 } 548 549 static int intel_pstate_freq_to_hwp(struct cpudata *cpu, int freq) 550 { 551 return intel_pstate_freq_to_hwp_rel(cpu, freq, CPUFREQ_RELATION_L); 552 } 553 554 /** 555 * intel_pstate_hybrid_hwp_adjust - Calibrate HWP performance levels. 556 * @cpu: Target CPU. 557 * 558 * On hybrid processors, HWP may expose more performance levels than there are 559 * P-states accessible through the PERF_CTL interface. If that happens, the 560 * scaling factor between HWP performance levels and CPU frequency will be less 561 * than the scaling factor between P-state values and CPU frequency. 562 * 563 * In that case, adjust the CPU parameters used in computations accordingly. 564 */ 565 static void intel_pstate_hybrid_hwp_adjust(struct cpudata *cpu) 566 { 567 int perf_ctl_max_phys = cpu->pstate.max_pstate_physical; 568 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling; 569 int perf_ctl_turbo = pstate_funcs.get_turbo(cpu->cpu); 570 int scaling = cpu->pstate.scaling; 571 int freq; 572 573 pr_debug("CPU%d: perf_ctl_max_phys = %d\n", cpu->cpu, perf_ctl_max_phys); 574 pr_debug("CPU%d: perf_ctl_turbo = %d\n", cpu->cpu, perf_ctl_turbo); 575 pr_debug("CPU%d: perf_ctl_scaling = %d\n", cpu->cpu, perf_ctl_scaling); 576 pr_debug("CPU%d: HWP_CAP guaranteed = %d\n", cpu->cpu, cpu->pstate.max_pstate); 577 pr_debug("CPU%d: HWP_CAP highest = %d\n", cpu->cpu, cpu->pstate.turbo_pstate); 578 pr_debug("CPU%d: HWP-to-frequency scaling factor: %d\n", cpu->cpu, scaling); 579 580 cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_pstate * scaling, 581 perf_ctl_scaling); 582 cpu->pstate.max_freq = rounddown(cpu->pstate.max_pstate * scaling, 583 perf_ctl_scaling); 584 585 freq = perf_ctl_max_phys * perf_ctl_scaling; 586 cpu->pstate.max_pstate_physical = intel_pstate_freq_to_hwp(cpu, freq); 587 588 freq = cpu->pstate.min_pstate * perf_ctl_scaling; 589 cpu->pstate.min_freq = freq; 590 /* 591 * Cast the min P-state value retrieved via pstate_funcs.get_min() to 592 * the effective range of HWP performance levels. 593 */ 594 cpu->pstate.min_pstate = intel_pstate_freq_to_hwp(cpu, freq); 595 } 596 597 static bool turbo_is_disabled(void) 598 { 599 u64 misc_en; 600 601 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en); 602 603 return !!(misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE); 604 } 605 606 static int min_perf_pct_min(void) 607 { 608 struct cpudata *cpu = all_cpu_data[0]; 609 int turbo_pstate = cpu->pstate.turbo_pstate; 610 611 return turbo_pstate ? 612 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0; 613 } 614 615 static s16 intel_pstate_get_epb(struct cpudata *cpu_data) 616 { 617 u64 epb; 618 int ret; 619 620 if (!boot_cpu_has(X86_FEATURE_EPB)) 621 return -ENXIO; 622 623 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb); 624 if (ret) 625 return (s16)ret; 626 627 return (s16)(epb & 0x0f); 628 } 629 630 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data) 631 { 632 s16 epp; 633 634 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 635 /* 636 * When hwp_req_data is 0, means that caller didn't read 637 * MSR_HWP_REQUEST, so need to read and get EPP. 638 */ 639 if (!hwp_req_data) { 640 epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, 641 &hwp_req_data); 642 if (epp) 643 return epp; 644 } 645 epp = (hwp_req_data >> 24) & 0xff; 646 } else { 647 /* When there is no EPP present, HWP uses EPB settings */ 648 epp = intel_pstate_get_epb(cpu_data); 649 } 650 651 return epp; 652 } 653 654 static int intel_pstate_set_epb(int cpu, s16 pref) 655 { 656 u64 epb; 657 int ret; 658 659 if (!boot_cpu_has(X86_FEATURE_EPB)) 660 return -ENXIO; 661 662 ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb); 663 if (ret) 664 return ret; 665 666 epb = (epb & ~0x0f) | pref; 667 wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb); 668 669 return 0; 670 } 671 672 /* 673 * EPP/EPB display strings corresponding to EPP index in the 674 * energy_perf_strings[] 675 * index String 676 *------------------------------------- 677 * 0 default 678 * 1 performance 679 * 2 balance_performance 680 * 3 balance_power 681 * 4 power 682 */ 683 684 enum energy_perf_value_index { 685 EPP_INDEX_DEFAULT = 0, 686 EPP_INDEX_PERFORMANCE, 687 EPP_INDEX_BALANCE_PERFORMANCE, 688 EPP_INDEX_BALANCE_POWERSAVE, 689 EPP_INDEX_POWERSAVE, 690 }; 691 692 static const char * const energy_perf_strings[] = { 693 [EPP_INDEX_DEFAULT] = "default", 694 [EPP_INDEX_PERFORMANCE] = "performance", 695 [EPP_INDEX_BALANCE_PERFORMANCE] = "balance_performance", 696 [EPP_INDEX_BALANCE_POWERSAVE] = "balance_power", 697 [EPP_INDEX_POWERSAVE] = "power", 698 NULL 699 }; 700 static unsigned int epp_values[] = { 701 [EPP_INDEX_DEFAULT] = 0, /* Unused index */ 702 [EPP_INDEX_PERFORMANCE] = HWP_EPP_PERFORMANCE, 703 [EPP_INDEX_BALANCE_PERFORMANCE] = HWP_EPP_BALANCE_PERFORMANCE, 704 [EPP_INDEX_BALANCE_POWERSAVE] = HWP_EPP_BALANCE_POWERSAVE, 705 [EPP_INDEX_POWERSAVE] = HWP_EPP_POWERSAVE, 706 }; 707 708 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data, int *raw_epp) 709 { 710 s16 epp; 711 int index = -EINVAL; 712 713 *raw_epp = 0; 714 epp = intel_pstate_get_epp(cpu_data, 0); 715 if (epp < 0) 716 return epp; 717 718 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 719 if (epp == epp_values[EPP_INDEX_PERFORMANCE]) 720 return EPP_INDEX_PERFORMANCE; 721 if (epp == epp_values[EPP_INDEX_BALANCE_PERFORMANCE]) 722 return EPP_INDEX_BALANCE_PERFORMANCE; 723 if (epp == epp_values[EPP_INDEX_BALANCE_POWERSAVE]) 724 return EPP_INDEX_BALANCE_POWERSAVE; 725 if (epp == epp_values[EPP_INDEX_POWERSAVE]) 726 return EPP_INDEX_POWERSAVE; 727 *raw_epp = epp; 728 return 0; 729 } else if (boot_cpu_has(X86_FEATURE_EPB)) { 730 /* 731 * Range: 732 * 0x00-0x03 : Performance 733 * 0x04-0x07 : Balance performance 734 * 0x08-0x0B : Balance power 735 * 0x0C-0x0F : Power 736 * The EPB is a 4 bit value, but our ranges restrict the 737 * value which can be set. Here only using top two bits 738 * effectively. 739 */ 740 index = (epp >> 2) + 1; 741 } 742 743 return index; 744 } 745 746 static int intel_pstate_set_epp(struct cpudata *cpu, u32 epp) 747 { 748 int ret; 749 750 /* 751 * Use the cached HWP Request MSR value, because in the active mode the 752 * register itself may be updated by intel_pstate_hwp_boost_up() or 753 * intel_pstate_hwp_boost_down() at any time. 754 */ 755 u64 value = READ_ONCE(cpu->hwp_req_cached); 756 757 value &= ~GENMASK_ULL(31, 24); 758 value |= (u64)epp << 24; 759 /* 760 * The only other updater of hwp_req_cached in the active mode, 761 * intel_pstate_hwp_set(), is called under the same lock as this 762 * function, so it cannot run in parallel with the update below. 763 */ 764 WRITE_ONCE(cpu->hwp_req_cached, value); 765 ret = wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 766 if (!ret) 767 cpu->epp_cached = epp; 768 769 return ret; 770 } 771 772 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data, 773 int pref_index, bool use_raw, 774 u32 raw_epp) 775 { 776 int epp = -EINVAL; 777 int ret; 778 779 if (!pref_index) 780 epp = cpu_data->epp_default; 781 782 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 783 if (use_raw) 784 epp = raw_epp; 785 else if (epp == -EINVAL) 786 epp = epp_values[pref_index]; 787 788 /* 789 * To avoid confusion, refuse to set EPP to any values different 790 * from 0 (performance) if the current policy is "performance", 791 * because those values would be overridden. 792 */ 793 if (epp > 0 && cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) 794 return -EBUSY; 795 796 ret = intel_pstate_set_epp(cpu_data, epp); 797 } else { 798 if (epp == -EINVAL) 799 epp = (pref_index - 1) << 2; 800 ret = intel_pstate_set_epb(cpu_data->cpu, epp); 801 } 802 803 return ret; 804 } 805 806 static ssize_t show_energy_performance_available_preferences( 807 struct cpufreq_policy *policy, char *buf) 808 { 809 int i = 0; 810 int ret = 0; 811 812 while (energy_perf_strings[i] != NULL) 813 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]); 814 815 ret += sprintf(&buf[ret], "\n"); 816 817 return ret; 818 } 819 820 cpufreq_freq_attr_ro(energy_performance_available_preferences); 821 822 static struct cpufreq_driver intel_pstate; 823 824 static ssize_t store_energy_performance_preference( 825 struct cpufreq_policy *policy, const char *buf, size_t count) 826 { 827 struct cpudata *cpu = all_cpu_data[policy->cpu]; 828 char str_preference[21]; 829 bool raw = false; 830 ssize_t ret; 831 u32 epp = 0; 832 833 ret = sscanf(buf, "%20s", str_preference); 834 if (ret != 1) 835 return -EINVAL; 836 837 ret = match_string(energy_perf_strings, -1, str_preference); 838 if (ret < 0) { 839 if (!boot_cpu_has(X86_FEATURE_HWP_EPP)) 840 return ret; 841 842 ret = kstrtouint(buf, 10, &epp); 843 if (ret) 844 return ret; 845 846 if (epp > 255) 847 return -EINVAL; 848 849 raw = true; 850 } 851 852 /* 853 * This function runs with the policy R/W semaphore held, which 854 * guarantees that the driver pointer will not change while it is 855 * running. 856 */ 857 if (!intel_pstate_driver) 858 return -EAGAIN; 859 860 mutex_lock(&intel_pstate_limits_lock); 861 862 if (intel_pstate_driver == &intel_pstate) { 863 ret = intel_pstate_set_energy_pref_index(cpu, ret, raw, epp); 864 } else { 865 /* 866 * In the passive mode the governor needs to be stopped on the 867 * target CPU before the EPP update and restarted after it, 868 * which is super-heavy-weight, so make sure it is worth doing 869 * upfront. 870 */ 871 if (!raw) 872 epp = ret ? epp_values[ret] : cpu->epp_default; 873 874 if (cpu->epp_cached != epp) { 875 int err; 876 877 cpufreq_stop_governor(policy); 878 ret = intel_pstate_set_epp(cpu, epp); 879 err = cpufreq_start_governor(policy); 880 if (!ret) 881 ret = err; 882 } else { 883 ret = 0; 884 } 885 } 886 887 mutex_unlock(&intel_pstate_limits_lock); 888 889 return ret ?: count; 890 } 891 892 static ssize_t show_energy_performance_preference( 893 struct cpufreq_policy *policy, char *buf) 894 { 895 struct cpudata *cpu_data = all_cpu_data[policy->cpu]; 896 int preference, raw_epp; 897 898 preference = intel_pstate_get_energy_pref_index(cpu_data, &raw_epp); 899 if (preference < 0) 900 return preference; 901 902 if (raw_epp) 903 return sprintf(buf, "%d\n", raw_epp); 904 else 905 return sprintf(buf, "%s\n", energy_perf_strings[preference]); 906 } 907 908 cpufreq_freq_attr_rw(energy_performance_preference); 909 910 static ssize_t show_base_frequency(struct cpufreq_policy *policy, char *buf) 911 { 912 struct cpudata *cpu = all_cpu_data[policy->cpu]; 913 int ratio, freq; 914 915 ratio = intel_pstate_get_cppc_guaranteed(policy->cpu); 916 if (ratio <= 0) { 917 u64 cap; 918 919 rdmsrl_on_cpu(policy->cpu, MSR_HWP_CAPABILITIES, &cap); 920 ratio = HWP_GUARANTEED_PERF(cap); 921 } 922 923 freq = ratio * cpu->pstate.scaling; 924 if (cpu->pstate.scaling != cpu->pstate.perf_ctl_scaling) 925 freq = rounddown(freq, cpu->pstate.perf_ctl_scaling); 926 927 return sprintf(buf, "%d\n", freq); 928 } 929 930 cpufreq_freq_attr_ro(base_frequency); 931 932 static struct freq_attr *hwp_cpufreq_attrs[] = { 933 &energy_performance_preference, 934 &energy_performance_available_preferences, 935 &base_frequency, 936 NULL, 937 }; 938 939 static struct cpudata *hybrid_max_perf_cpu __read_mostly; 940 /* 941 * Protects hybrid_max_perf_cpu, the capacity_perf fields in struct cpudata, 942 * and the x86 arch scale-invariance information from concurrent updates. 943 */ 944 static DEFINE_MUTEX(hybrid_capacity_lock); 945 946 static void hybrid_set_cpu_capacity(struct cpudata *cpu) 947 { 948 arch_set_cpu_capacity(cpu->cpu, cpu->capacity_perf, 949 hybrid_max_perf_cpu->capacity_perf, 950 cpu->capacity_perf, 951 cpu->pstate.max_pstate_physical); 952 953 pr_debug("CPU%d: perf = %u, max. perf = %u, base perf = %d\n", cpu->cpu, 954 cpu->capacity_perf, hybrid_max_perf_cpu->capacity_perf, 955 cpu->pstate.max_pstate_physical); 956 } 957 958 static void hybrid_clear_cpu_capacity(unsigned int cpunum) 959 { 960 arch_set_cpu_capacity(cpunum, 1, 1, 1, 1); 961 } 962 963 static void hybrid_get_capacity_perf(struct cpudata *cpu) 964 { 965 if (READ_ONCE(global.no_turbo)) { 966 cpu->capacity_perf = cpu->pstate.max_pstate_physical; 967 return; 968 } 969 970 cpu->capacity_perf = HWP_HIGHEST_PERF(READ_ONCE(cpu->hwp_cap_cached)); 971 } 972 973 static void hybrid_set_capacity_of_cpus(void) 974 { 975 int cpunum; 976 977 for_each_online_cpu(cpunum) { 978 struct cpudata *cpu = all_cpu_data[cpunum]; 979 980 if (cpu) 981 hybrid_set_cpu_capacity(cpu); 982 } 983 } 984 985 static void hybrid_update_cpu_capacity_scaling(void) 986 { 987 struct cpudata *max_perf_cpu = NULL; 988 unsigned int max_cap_perf = 0; 989 int cpunum; 990 991 for_each_online_cpu(cpunum) { 992 struct cpudata *cpu = all_cpu_data[cpunum]; 993 994 if (!cpu) 995 continue; 996 997 /* 998 * During initialization, CPU performance at full capacity needs 999 * to be determined. 1000 */ 1001 if (!hybrid_max_perf_cpu) 1002 hybrid_get_capacity_perf(cpu); 1003 1004 /* 1005 * If hybrid_max_perf_cpu is not NULL at this point, it is 1006 * being replaced, so don't take it into account when looking 1007 * for the new one. 1008 */ 1009 if (cpu == hybrid_max_perf_cpu) 1010 continue; 1011 1012 if (cpu->capacity_perf > max_cap_perf) { 1013 max_cap_perf = cpu->capacity_perf; 1014 max_perf_cpu = cpu; 1015 } 1016 } 1017 1018 if (max_perf_cpu) { 1019 hybrid_max_perf_cpu = max_perf_cpu; 1020 hybrid_set_capacity_of_cpus(); 1021 } else { 1022 pr_info("Found no CPUs with nonzero maximum performance\n"); 1023 /* Revert to the flat CPU capacity structure. */ 1024 for_each_online_cpu(cpunum) 1025 hybrid_clear_cpu_capacity(cpunum); 1026 } 1027 } 1028 1029 static void __hybrid_refresh_cpu_capacity_scaling(void) 1030 { 1031 hybrid_max_perf_cpu = NULL; 1032 hybrid_update_cpu_capacity_scaling(); 1033 } 1034 1035 static void hybrid_refresh_cpu_capacity_scaling(void) 1036 { 1037 guard(mutex)(&hybrid_capacity_lock); 1038 1039 __hybrid_refresh_cpu_capacity_scaling(); 1040 } 1041 1042 static void hybrid_init_cpu_capacity_scaling(bool refresh) 1043 { 1044 /* 1045 * If hybrid_max_perf_cpu is set at this point, the hybrid CPU capacity 1046 * scaling has been enabled already and the driver is just changing the 1047 * operation mode. 1048 */ 1049 if (refresh) { 1050 hybrid_refresh_cpu_capacity_scaling(); 1051 return; 1052 } 1053 1054 /* 1055 * On hybrid systems, use asym capacity instead of ITMT, but because 1056 * the capacity of SMT threads is not deterministic even approximately, 1057 * do not do that when SMT is in use. 1058 */ 1059 if (hwp_is_hybrid && !sched_smt_active() && arch_enable_hybrid_capacity_scale()) { 1060 hybrid_refresh_cpu_capacity_scaling(); 1061 /* 1062 * Disabling ITMT causes sched domains to be rebuilt to disable asym 1063 * packing and enable asym capacity. 1064 */ 1065 sched_clear_itmt_support(); 1066 } 1067 } 1068 1069 static bool hybrid_clear_max_perf_cpu(void) 1070 { 1071 bool ret; 1072 1073 guard(mutex)(&hybrid_capacity_lock); 1074 1075 ret = !!hybrid_max_perf_cpu; 1076 hybrid_max_perf_cpu = NULL; 1077 1078 return ret; 1079 } 1080 1081 static void __intel_pstate_get_hwp_cap(struct cpudata *cpu) 1082 { 1083 u64 cap; 1084 1085 rdmsrl_on_cpu(cpu->cpu, MSR_HWP_CAPABILITIES, &cap); 1086 WRITE_ONCE(cpu->hwp_cap_cached, cap); 1087 cpu->pstate.max_pstate = HWP_GUARANTEED_PERF(cap); 1088 cpu->pstate.turbo_pstate = HWP_HIGHEST_PERF(cap); 1089 } 1090 1091 static void intel_pstate_get_hwp_cap(struct cpudata *cpu) 1092 { 1093 int scaling = cpu->pstate.scaling; 1094 1095 __intel_pstate_get_hwp_cap(cpu); 1096 1097 cpu->pstate.max_freq = cpu->pstate.max_pstate * scaling; 1098 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * scaling; 1099 if (scaling != cpu->pstate.perf_ctl_scaling) { 1100 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling; 1101 1102 cpu->pstate.max_freq = rounddown(cpu->pstate.max_freq, 1103 perf_ctl_scaling); 1104 cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_freq, 1105 perf_ctl_scaling); 1106 } 1107 } 1108 1109 static void hybrid_update_capacity(struct cpudata *cpu) 1110 { 1111 unsigned int max_cap_perf; 1112 1113 mutex_lock(&hybrid_capacity_lock); 1114 1115 if (!hybrid_max_perf_cpu) 1116 goto unlock; 1117 1118 /* 1119 * The maximum performance of the CPU may have changed, but assume 1120 * that the performance of the other CPUs has not changed. 1121 */ 1122 max_cap_perf = hybrid_max_perf_cpu->capacity_perf; 1123 1124 intel_pstate_get_hwp_cap(cpu); 1125 1126 hybrid_get_capacity_perf(cpu); 1127 /* Should hybrid_max_perf_cpu be replaced by this CPU? */ 1128 if (cpu->capacity_perf > max_cap_perf) { 1129 hybrid_max_perf_cpu = cpu; 1130 hybrid_set_capacity_of_cpus(); 1131 goto unlock; 1132 } 1133 1134 /* If this CPU is hybrid_max_perf_cpu, should it be replaced? */ 1135 if (cpu == hybrid_max_perf_cpu && cpu->capacity_perf < max_cap_perf) { 1136 hybrid_update_cpu_capacity_scaling(); 1137 goto unlock; 1138 } 1139 1140 hybrid_set_cpu_capacity(cpu); 1141 1142 unlock: 1143 mutex_unlock(&hybrid_capacity_lock); 1144 } 1145 1146 static void intel_pstate_hwp_set(unsigned int cpu) 1147 { 1148 struct cpudata *cpu_data = all_cpu_data[cpu]; 1149 int max, min; 1150 u64 value; 1151 s16 epp; 1152 1153 max = cpu_data->max_perf_ratio; 1154 min = cpu_data->min_perf_ratio; 1155 1156 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) 1157 min = max; 1158 1159 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value); 1160 1161 value &= ~HWP_MIN_PERF(~0L); 1162 value |= HWP_MIN_PERF(min); 1163 1164 value &= ~HWP_MAX_PERF(~0L); 1165 value |= HWP_MAX_PERF(max); 1166 1167 if (cpu_data->epp_policy == cpu_data->policy) 1168 goto skip_epp; 1169 1170 cpu_data->epp_policy = cpu_data->policy; 1171 1172 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) { 1173 epp = intel_pstate_get_epp(cpu_data, value); 1174 cpu_data->epp_powersave = epp; 1175 /* If EPP read was failed, then don't try to write */ 1176 if (epp < 0) 1177 goto skip_epp; 1178 1179 epp = 0; 1180 } else { 1181 /* skip setting EPP, when saved value is invalid */ 1182 if (cpu_data->epp_powersave < 0) 1183 goto skip_epp; 1184 1185 /* 1186 * No need to restore EPP when it is not zero. This 1187 * means: 1188 * - Policy is not changed 1189 * - user has manually changed 1190 * - Error reading EPB 1191 */ 1192 epp = intel_pstate_get_epp(cpu_data, value); 1193 if (epp) 1194 goto skip_epp; 1195 1196 epp = cpu_data->epp_powersave; 1197 } 1198 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 1199 value &= ~GENMASK_ULL(31, 24); 1200 value |= (u64)epp << 24; 1201 } else { 1202 intel_pstate_set_epb(cpu, epp); 1203 } 1204 skip_epp: 1205 WRITE_ONCE(cpu_data->hwp_req_cached, value); 1206 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value); 1207 } 1208 1209 static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata); 1210 1211 static void intel_pstate_hwp_offline(struct cpudata *cpu) 1212 { 1213 u64 value = READ_ONCE(cpu->hwp_req_cached); 1214 int min_perf; 1215 1216 intel_pstate_disable_hwp_interrupt(cpu); 1217 1218 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 1219 /* 1220 * In case the EPP has been set to "performance" by the 1221 * active mode "performance" scaling algorithm, replace that 1222 * temporary value with the cached EPP one. 1223 */ 1224 value &= ~GENMASK_ULL(31, 24); 1225 value |= HWP_ENERGY_PERF_PREFERENCE(cpu->epp_cached); 1226 /* 1227 * However, make sure that EPP will be set to "performance" when 1228 * the CPU is brought back online again and the "performance" 1229 * scaling algorithm is still in effect. 1230 */ 1231 cpu->epp_policy = CPUFREQ_POLICY_UNKNOWN; 1232 } 1233 1234 /* 1235 * Clear the desired perf field in the cached HWP request value to 1236 * prevent nonzero desired values from being leaked into the active 1237 * mode. 1238 */ 1239 value &= ~HWP_DESIRED_PERF(~0L); 1240 WRITE_ONCE(cpu->hwp_req_cached, value); 1241 1242 value &= ~GENMASK_ULL(31, 0); 1243 min_perf = HWP_LOWEST_PERF(READ_ONCE(cpu->hwp_cap_cached)); 1244 1245 /* Set hwp_max = hwp_min */ 1246 value |= HWP_MAX_PERF(min_perf); 1247 value |= HWP_MIN_PERF(min_perf); 1248 1249 /* Set EPP to min */ 1250 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) 1251 value |= HWP_ENERGY_PERF_PREFERENCE(HWP_EPP_POWERSAVE); 1252 1253 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 1254 1255 mutex_lock(&hybrid_capacity_lock); 1256 1257 if (!hybrid_max_perf_cpu) { 1258 mutex_unlock(&hybrid_capacity_lock); 1259 1260 return; 1261 } 1262 1263 if (hybrid_max_perf_cpu == cpu) 1264 hybrid_update_cpu_capacity_scaling(); 1265 1266 mutex_unlock(&hybrid_capacity_lock); 1267 1268 /* Reset the capacity of the CPU going offline to the initial value. */ 1269 hybrid_clear_cpu_capacity(cpu->cpu); 1270 } 1271 1272 #define POWER_CTL_EE_ENABLE 1 1273 #define POWER_CTL_EE_DISABLE 2 1274 1275 static int power_ctl_ee_state; 1276 1277 static void set_power_ctl_ee_state(bool input) 1278 { 1279 u64 power_ctl; 1280 1281 mutex_lock(&intel_pstate_driver_lock); 1282 rdmsrl(MSR_IA32_POWER_CTL, power_ctl); 1283 if (input) { 1284 power_ctl &= ~BIT(MSR_IA32_POWER_CTL_BIT_EE); 1285 power_ctl_ee_state = POWER_CTL_EE_ENABLE; 1286 } else { 1287 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE); 1288 power_ctl_ee_state = POWER_CTL_EE_DISABLE; 1289 } 1290 wrmsrl(MSR_IA32_POWER_CTL, power_ctl); 1291 mutex_unlock(&intel_pstate_driver_lock); 1292 } 1293 1294 static void intel_pstate_hwp_enable(struct cpudata *cpudata); 1295 1296 static void intel_pstate_hwp_reenable(struct cpudata *cpu) 1297 { 1298 intel_pstate_hwp_enable(cpu); 1299 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, READ_ONCE(cpu->hwp_req_cached)); 1300 } 1301 1302 static int intel_pstate_suspend(struct cpufreq_policy *policy) 1303 { 1304 struct cpudata *cpu = all_cpu_data[policy->cpu]; 1305 1306 pr_debug("CPU %d suspending\n", cpu->cpu); 1307 1308 cpu->suspended = true; 1309 1310 /* disable HWP interrupt and cancel any pending work */ 1311 intel_pstate_disable_hwp_interrupt(cpu); 1312 1313 return 0; 1314 } 1315 1316 static int intel_pstate_resume(struct cpufreq_policy *policy) 1317 { 1318 struct cpudata *cpu = all_cpu_data[policy->cpu]; 1319 1320 pr_debug("CPU %d resuming\n", cpu->cpu); 1321 1322 /* Only restore if the system default is changed */ 1323 if (power_ctl_ee_state == POWER_CTL_EE_ENABLE) 1324 set_power_ctl_ee_state(true); 1325 else if (power_ctl_ee_state == POWER_CTL_EE_DISABLE) 1326 set_power_ctl_ee_state(false); 1327 1328 if (cpu->suspended && hwp_active) { 1329 mutex_lock(&intel_pstate_limits_lock); 1330 1331 /* Re-enable HWP, because "online" has not done that. */ 1332 intel_pstate_hwp_reenable(cpu); 1333 1334 mutex_unlock(&intel_pstate_limits_lock); 1335 } 1336 1337 cpu->suspended = false; 1338 1339 return 0; 1340 } 1341 1342 static void intel_pstate_update_policies(void) 1343 { 1344 int cpu; 1345 1346 for_each_possible_cpu(cpu) 1347 cpufreq_update_policy(cpu); 1348 } 1349 1350 static void __intel_pstate_update_max_freq(struct cpudata *cpudata, 1351 struct cpufreq_policy *policy) 1352 { 1353 if (hwp_active) 1354 intel_pstate_get_hwp_cap(cpudata); 1355 1356 policy->cpuinfo.max_freq = READ_ONCE(global.no_turbo) ? 1357 cpudata->pstate.max_freq : cpudata->pstate.turbo_freq; 1358 1359 refresh_frequency_limits(policy); 1360 } 1361 1362 static void intel_pstate_update_limits(unsigned int cpu) 1363 { 1364 struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpu); 1365 struct cpudata *cpudata; 1366 1367 if (!policy) 1368 return; 1369 1370 cpudata = all_cpu_data[cpu]; 1371 1372 __intel_pstate_update_max_freq(cpudata, policy); 1373 1374 /* Prevent the driver from being unregistered now. */ 1375 mutex_lock(&intel_pstate_driver_lock); 1376 1377 cpufreq_cpu_release(policy); 1378 1379 hybrid_update_capacity(cpudata); 1380 1381 mutex_unlock(&intel_pstate_driver_lock); 1382 } 1383 1384 static void intel_pstate_update_limits_for_all(void) 1385 { 1386 int cpu; 1387 1388 for_each_possible_cpu(cpu) { 1389 struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpu); 1390 1391 if (!policy) 1392 continue; 1393 1394 __intel_pstate_update_max_freq(all_cpu_data[cpu], policy); 1395 1396 cpufreq_cpu_release(policy); 1397 } 1398 1399 mutex_lock(&hybrid_capacity_lock); 1400 1401 if (hybrid_max_perf_cpu) 1402 __hybrid_refresh_cpu_capacity_scaling(); 1403 1404 mutex_unlock(&hybrid_capacity_lock); 1405 } 1406 1407 /************************** sysfs begin ************************/ 1408 #define show_one(file_name, object) \ 1409 static ssize_t show_##file_name \ 1410 (struct kobject *kobj, struct kobj_attribute *attr, char *buf) \ 1411 { \ 1412 return sprintf(buf, "%u\n", global.object); \ 1413 } 1414 1415 static ssize_t intel_pstate_show_status(char *buf); 1416 static int intel_pstate_update_status(const char *buf, size_t size); 1417 1418 static ssize_t show_status(struct kobject *kobj, 1419 struct kobj_attribute *attr, char *buf) 1420 { 1421 ssize_t ret; 1422 1423 mutex_lock(&intel_pstate_driver_lock); 1424 ret = intel_pstate_show_status(buf); 1425 mutex_unlock(&intel_pstate_driver_lock); 1426 1427 return ret; 1428 } 1429 1430 static ssize_t store_status(struct kobject *a, struct kobj_attribute *b, 1431 const char *buf, size_t count) 1432 { 1433 char *p = memchr(buf, '\n', count); 1434 int ret; 1435 1436 mutex_lock(&intel_pstate_driver_lock); 1437 ret = intel_pstate_update_status(buf, p ? p - buf : count); 1438 mutex_unlock(&intel_pstate_driver_lock); 1439 1440 return ret < 0 ? ret : count; 1441 } 1442 1443 static ssize_t show_turbo_pct(struct kobject *kobj, 1444 struct kobj_attribute *attr, char *buf) 1445 { 1446 struct cpudata *cpu; 1447 int total, no_turbo, turbo_pct; 1448 uint32_t turbo_fp; 1449 1450 mutex_lock(&intel_pstate_driver_lock); 1451 1452 if (!intel_pstate_driver) { 1453 mutex_unlock(&intel_pstate_driver_lock); 1454 return -EAGAIN; 1455 } 1456 1457 cpu = all_cpu_data[0]; 1458 1459 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; 1460 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1; 1461 turbo_fp = div_fp(no_turbo, total); 1462 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100))); 1463 1464 mutex_unlock(&intel_pstate_driver_lock); 1465 1466 return sprintf(buf, "%u\n", turbo_pct); 1467 } 1468 1469 static ssize_t show_num_pstates(struct kobject *kobj, 1470 struct kobj_attribute *attr, char *buf) 1471 { 1472 struct cpudata *cpu; 1473 int total; 1474 1475 mutex_lock(&intel_pstate_driver_lock); 1476 1477 if (!intel_pstate_driver) { 1478 mutex_unlock(&intel_pstate_driver_lock); 1479 return -EAGAIN; 1480 } 1481 1482 cpu = all_cpu_data[0]; 1483 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; 1484 1485 mutex_unlock(&intel_pstate_driver_lock); 1486 1487 return sprintf(buf, "%u\n", total); 1488 } 1489 1490 static ssize_t show_no_turbo(struct kobject *kobj, 1491 struct kobj_attribute *attr, char *buf) 1492 { 1493 ssize_t ret; 1494 1495 mutex_lock(&intel_pstate_driver_lock); 1496 1497 if (!intel_pstate_driver) { 1498 mutex_unlock(&intel_pstate_driver_lock); 1499 return -EAGAIN; 1500 } 1501 1502 ret = sprintf(buf, "%u\n", global.no_turbo); 1503 1504 mutex_unlock(&intel_pstate_driver_lock); 1505 1506 return ret; 1507 } 1508 1509 static ssize_t store_no_turbo(struct kobject *a, struct kobj_attribute *b, 1510 const char *buf, size_t count) 1511 { 1512 unsigned int input; 1513 bool no_turbo; 1514 1515 if (sscanf(buf, "%u", &input) != 1) 1516 return -EINVAL; 1517 1518 mutex_lock(&intel_pstate_driver_lock); 1519 1520 if (!intel_pstate_driver) { 1521 count = -EAGAIN; 1522 goto unlock_driver; 1523 } 1524 1525 no_turbo = !!clamp_t(int, input, 0, 1); 1526 1527 WRITE_ONCE(global.turbo_disabled, turbo_is_disabled()); 1528 if (global.turbo_disabled && !no_turbo) { 1529 pr_notice("Turbo disabled by BIOS or unavailable on processor\n"); 1530 count = -EPERM; 1531 if (global.no_turbo) 1532 goto unlock_driver; 1533 else 1534 no_turbo = 1; 1535 } 1536 1537 if (no_turbo == global.no_turbo) { 1538 goto unlock_driver; 1539 } 1540 1541 WRITE_ONCE(global.no_turbo, no_turbo); 1542 1543 mutex_lock(&intel_pstate_limits_lock); 1544 1545 if (no_turbo) { 1546 struct cpudata *cpu = all_cpu_data[0]; 1547 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate; 1548 1549 /* Squash the global minimum into the permitted range. */ 1550 if (global.min_perf_pct > pct) 1551 global.min_perf_pct = pct; 1552 } 1553 1554 mutex_unlock(&intel_pstate_limits_lock); 1555 1556 intel_pstate_update_limits_for_all(); 1557 arch_set_max_freq_ratio(no_turbo); 1558 1559 unlock_driver: 1560 mutex_unlock(&intel_pstate_driver_lock); 1561 1562 return count; 1563 } 1564 1565 static void update_qos_request(enum freq_qos_req_type type) 1566 { 1567 struct freq_qos_request *req; 1568 struct cpufreq_policy *policy; 1569 int i; 1570 1571 for_each_possible_cpu(i) { 1572 struct cpudata *cpu = all_cpu_data[i]; 1573 unsigned int freq, perf_pct; 1574 1575 policy = cpufreq_cpu_get(i); 1576 if (!policy) 1577 continue; 1578 1579 req = policy->driver_data; 1580 cpufreq_cpu_put(policy); 1581 1582 if (!req) 1583 continue; 1584 1585 if (hwp_active) 1586 intel_pstate_get_hwp_cap(cpu); 1587 1588 if (type == FREQ_QOS_MIN) { 1589 perf_pct = global.min_perf_pct; 1590 } else { 1591 req++; 1592 perf_pct = global.max_perf_pct; 1593 } 1594 1595 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * perf_pct, 100); 1596 1597 if (freq_qos_update_request(req, freq) < 0) 1598 pr_warn("Failed to update freq constraint: CPU%d\n", i); 1599 } 1600 } 1601 1602 static ssize_t store_max_perf_pct(struct kobject *a, struct kobj_attribute *b, 1603 const char *buf, size_t count) 1604 { 1605 unsigned int input; 1606 int ret; 1607 1608 ret = sscanf(buf, "%u", &input); 1609 if (ret != 1) 1610 return -EINVAL; 1611 1612 mutex_lock(&intel_pstate_driver_lock); 1613 1614 if (!intel_pstate_driver) { 1615 mutex_unlock(&intel_pstate_driver_lock); 1616 return -EAGAIN; 1617 } 1618 1619 mutex_lock(&intel_pstate_limits_lock); 1620 1621 global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100); 1622 1623 mutex_unlock(&intel_pstate_limits_lock); 1624 1625 if (intel_pstate_driver == &intel_pstate) 1626 intel_pstate_update_policies(); 1627 else 1628 update_qos_request(FREQ_QOS_MAX); 1629 1630 mutex_unlock(&intel_pstate_driver_lock); 1631 1632 return count; 1633 } 1634 1635 static ssize_t store_min_perf_pct(struct kobject *a, struct kobj_attribute *b, 1636 const char *buf, size_t count) 1637 { 1638 unsigned int input; 1639 int ret; 1640 1641 ret = sscanf(buf, "%u", &input); 1642 if (ret != 1) 1643 return -EINVAL; 1644 1645 mutex_lock(&intel_pstate_driver_lock); 1646 1647 if (!intel_pstate_driver) { 1648 mutex_unlock(&intel_pstate_driver_lock); 1649 return -EAGAIN; 1650 } 1651 1652 mutex_lock(&intel_pstate_limits_lock); 1653 1654 global.min_perf_pct = clamp_t(int, input, 1655 min_perf_pct_min(), global.max_perf_pct); 1656 1657 mutex_unlock(&intel_pstate_limits_lock); 1658 1659 if (intel_pstate_driver == &intel_pstate) 1660 intel_pstate_update_policies(); 1661 else 1662 update_qos_request(FREQ_QOS_MIN); 1663 1664 mutex_unlock(&intel_pstate_driver_lock); 1665 1666 return count; 1667 } 1668 1669 static ssize_t show_hwp_dynamic_boost(struct kobject *kobj, 1670 struct kobj_attribute *attr, char *buf) 1671 { 1672 return sprintf(buf, "%u\n", hwp_boost); 1673 } 1674 1675 static ssize_t store_hwp_dynamic_boost(struct kobject *a, 1676 struct kobj_attribute *b, 1677 const char *buf, size_t count) 1678 { 1679 unsigned int input; 1680 int ret; 1681 1682 ret = kstrtouint(buf, 10, &input); 1683 if (ret) 1684 return ret; 1685 1686 mutex_lock(&intel_pstate_driver_lock); 1687 hwp_boost = !!input; 1688 intel_pstate_update_policies(); 1689 mutex_unlock(&intel_pstate_driver_lock); 1690 1691 return count; 1692 } 1693 1694 static ssize_t show_energy_efficiency(struct kobject *kobj, struct kobj_attribute *attr, 1695 char *buf) 1696 { 1697 u64 power_ctl; 1698 int enable; 1699 1700 rdmsrl(MSR_IA32_POWER_CTL, power_ctl); 1701 enable = !!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE)); 1702 return sprintf(buf, "%d\n", !enable); 1703 } 1704 1705 static ssize_t store_energy_efficiency(struct kobject *a, struct kobj_attribute *b, 1706 const char *buf, size_t count) 1707 { 1708 bool input; 1709 int ret; 1710 1711 ret = kstrtobool(buf, &input); 1712 if (ret) 1713 return ret; 1714 1715 set_power_ctl_ee_state(input); 1716 1717 return count; 1718 } 1719 1720 show_one(max_perf_pct, max_perf_pct); 1721 show_one(min_perf_pct, min_perf_pct); 1722 1723 define_one_global_rw(status); 1724 define_one_global_rw(no_turbo); 1725 define_one_global_rw(max_perf_pct); 1726 define_one_global_rw(min_perf_pct); 1727 define_one_global_ro(turbo_pct); 1728 define_one_global_ro(num_pstates); 1729 define_one_global_rw(hwp_dynamic_boost); 1730 define_one_global_rw(energy_efficiency); 1731 1732 static struct attribute *intel_pstate_attributes[] = { 1733 &status.attr, 1734 &no_turbo.attr, 1735 NULL 1736 }; 1737 1738 static const struct attribute_group intel_pstate_attr_group = { 1739 .attrs = intel_pstate_attributes, 1740 }; 1741 1742 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[]; 1743 1744 static struct kobject *intel_pstate_kobject; 1745 1746 static void __init intel_pstate_sysfs_expose_params(void) 1747 { 1748 struct device *dev_root = bus_get_dev_root(&cpu_subsys); 1749 int rc; 1750 1751 if (dev_root) { 1752 intel_pstate_kobject = kobject_create_and_add("intel_pstate", &dev_root->kobj); 1753 put_device(dev_root); 1754 } 1755 if (WARN_ON(!intel_pstate_kobject)) 1756 return; 1757 1758 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group); 1759 if (WARN_ON(rc)) 1760 return; 1761 1762 if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) { 1763 rc = sysfs_create_file(intel_pstate_kobject, &turbo_pct.attr); 1764 WARN_ON(rc); 1765 1766 rc = sysfs_create_file(intel_pstate_kobject, &num_pstates.attr); 1767 WARN_ON(rc); 1768 } 1769 1770 /* 1771 * If per cpu limits are enforced there are no global limits, so 1772 * return without creating max/min_perf_pct attributes 1773 */ 1774 if (per_cpu_limits) 1775 return; 1776 1777 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr); 1778 WARN_ON(rc); 1779 1780 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr); 1781 WARN_ON(rc); 1782 1783 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids)) { 1784 rc = sysfs_create_file(intel_pstate_kobject, &energy_efficiency.attr); 1785 WARN_ON(rc); 1786 } 1787 } 1788 1789 static void __init intel_pstate_sysfs_remove(void) 1790 { 1791 if (!intel_pstate_kobject) 1792 return; 1793 1794 sysfs_remove_group(intel_pstate_kobject, &intel_pstate_attr_group); 1795 1796 if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) { 1797 sysfs_remove_file(intel_pstate_kobject, &num_pstates.attr); 1798 sysfs_remove_file(intel_pstate_kobject, &turbo_pct.attr); 1799 } 1800 1801 if (!per_cpu_limits) { 1802 sysfs_remove_file(intel_pstate_kobject, &max_perf_pct.attr); 1803 sysfs_remove_file(intel_pstate_kobject, &min_perf_pct.attr); 1804 1805 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids)) 1806 sysfs_remove_file(intel_pstate_kobject, &energy_efficiency.attr); 1807 } 1808 1809 kobject_put(intel_pstate_kobject); 1810 } 1811 1812 static void intel_pstate_sysfs_expose_hwp_dynamic_boost(void) 1813 { 1814 int rc; 1815 1816 if (!hwp_active) 1817 return; 1818 1819 rc = sysfs_create_file(intel_pstate_kobject, &hwp_dynamic_boost.attr); 1820 WARN_ON_ONCE(rc); 1821 } 1822 1823 static void intel_pstate_sysfs_hide_hwp_dynamic_boost(void) 1824 { 1825 if (!hwp_active) 1826 return; 1827 1828 sysfs_remove_file(intel_pstate_kobject, &hwp_dynamic_boost.attr); 1829 } 1830 1831 /************************** sysfs end ************************/ 1832 1833 static void intel_pstate_notify_work(struct work_struct *work) 1834 { 1835 struct cpudata *cpudata = 1836 container_of(to_delayed_work(work), struct cpudata, hwp_notify_work); 1837 struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpudata->cpu); 1838 1839 if (policy) { 1840 __intel_pstate_update_max_freq(cpudata, policy); 1841 1842 cpufreq_cpu_release(policy); 1843 1844 /* 1845 * The driver will not be unregistered while this function is 1846 * running, so update the capacity without acquiring the driver 1847 * lock. 1848 */ 1849 hybrid_update_capacity(cpudata); 1850 } 1851 1852 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0); 1853 } 1854 1855 static DEFINE_RAW_SPINLOCK(hwp_notify_lock); 1856 static cpumask_t hwp_intr_enable_mask; 1857 1858 #define HWP_GUARANTEED_PERF_CHANGE_STATUS BIT(0) 1859 #define HWP_HIGHEST_PERF_CHANGE_STATUS BIT(3) 1860 1861 void notify_hwp_interrupt(void) 1862 { 1863 unsigned int this_cpu = smp_processor_id(); 1864 u64 value, status_mask; 1865 unsigned long flags; 1866 1867 if (!hwp_active || !cpu_feature_enabled(X86_FEATURE_HWP_NOTIFY)) 1868 return; 1869 1870 status_mask = HWP_GUARANTEED_PERF_CHANGE_STATUS; 1871 if (cpu_feature_enabled(X86_FEATURE_HWP_HIGHEST_PERF_CHANGE)) 1872 status_mask |= HWP_HIGHEST_PERF_CHANGE_STATUS; 1873 1874 rdmsrl_safe(MSR_HWP_STATUS, &value); 1875 if (!(value & status_mask)) 1876 return; 1877 1878 raw_spin_lock_irqsave(&hwp_notify_lock, flags); 1879 1880 if (!cpumask_test_cpu(this_cpu, &hwp_intr_enable_mask)) 1881 goto ack_intr; 1882 1883 schedule_delayed_work(&all_cpu_data[this_cpu]->hwp_notify_work, 1884 msecs_to_jiffies(10)); 1885 1886 raw_spin_unlock_irqrestore(&hwp_notify_lock, flags); 1887 1888 return; 1889 1890 ack_intr: 1891 wrmsrl_safe(MSR_HWP_STATUS, 0); 1892 raw_spin_unlock_irqrestore(&hwp_notify_lock, flags); 1893 } 1894 1895 static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata) 1896 { 1897 bool cancel_work; 1898 1899 if (!cpu_feature_enabled(X86_FEATURE_HWP_NOTIFY)) 1900 return; 1901 1902 /* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */ 1903 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00); 1904 1905 raw_spin_lock_irq(&hwp_notify_lock); 1906 cancel_work = cpumask_test_and_clear_cpu(cpudata->cpu, &hwp_intr_enable_mask); 1907 raw_spin_unlock_irq(&hwp_notify_lock); 1908 1909 if (cancel_work) 1910 cancel_delayed_work_sync(&cpudata->hwp_notify_work); 1911 } 1912 1913 #define HWP_GUARANTEED_PERF_CHANGE_REQ BIT(0) 1914 #define HWP_HIGHEST_PERF_CHANGE_REQ BIT(2) 1915 1916 static void intel_pstate_enable_hwp_interrupt(struct cpudata *cpudata) 1917 { 1918 /* Enable HWP notification interrupt for performance change */ 1919 if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) { 1920 u64 interrupt_mask = HWP_GUARANTEED_PERF_CHANGE_REQ; 1921 1922 raw_spin_lock_irq(&hwp_notify_lock); 1923 INIT_DELAYED_WORK(&cpudata->hwp_notify_work, intel_pstate_notify_work); 1924 cpumask_set_cpu(cpudata->cpu, &hwp_intr_enable_mask); 1925 raw_spin_unlock_irq(&hwp_notify_lock); 1926 1927 if (cpu_feature_enabled(X86_FEATURE_HWP_HIGHEST_PERF_CHANGE)) 1928 interrupt_mask |= HWP_HIGHEST_PERF_CHANGE_REQ; 1929 1930 /* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */ 1931 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, interrupt_mask); 1932 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0); 1933 } 1934 } 1935 1936 static void intel_pstate_update_epp_defaults(struct cpudata *cpudata) 1937 { 1938 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0); 1939 1940 /* 1941 * If the EPP is set by firmware, which means that firmware enabled HWP 1942 * - Is equal or less than 0x80 (default balance_perf EPP) 1943 * - But less performance oriented than performance EPP 1944 * then use this as new balance_perf EPP. 1945 */ 1946 if (hwp_forced && cpudata->epp_default <= HWP_EPP_BALANCE_PERFORMANCE && 1947 cpudata->epp_default > HWP_EPP_PERFORMANCE) { 1948 epp_values[EPP_INDEX_BALANCE_PERFORMANCE] = cpudata->epp_default; 1949 return; 1950 } 1951 1952 /* 1953 * If this CPU gen doesn't call for change in balance_perf 1954 * EPP return. 1955 */ 1956 if (epp_values[EPP_INDEX_BALANCE_PERFORMANCE] == HWP_EPP_BALANCE_PERFORMANCE) 1957 return; 1958 1959 /* 1960 * Use hard coded value per gen to update the balance_perf 1961 * and default EPP. 1962 */ 1963 cpudata->epp_default = epp_values[EPP_INDEX_BALANCE_PERFORMANCE]; 1964 intel_pstate_set_epp(cpudata, cpudata->epp_default); 1965 } 1966 1967 static void intel_pstate_hwp_enable(struct cpudata *cpudata) 1968 { 1969 /* First disable HWP notification interrupt till we activate again */ 1970 if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) 1971 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00); 1972 1973 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1); 1974 1975 intel_pstate_enable_hwp_interrupt(cpudata); 1976 1977 if (cpudata->epp_default >= 0) 1978 return; 1979 1980 intel_pstate_update_epp_defaults(cpudata); 1981 } 1982 1983 static int atom_get_min_pstate(int not_used) 1984 { 1985 u64 value; 1986 1987 rdmsrl(MSR_ATOM_CORE_RATIOS, value); 1988 return (value >> 8) & 0x7F; 1989 } 1990 1991 static int atom_get_max_pstate(int not_used) 1992 { 1993 u64 value; 1994 1995 rdmsrl(MSR_ATOM_CORE_RATIOS, value); 1996 return (value >> 16) & 0x7F; 1997 } 1998 1999 static int atom_get_turbo_pstate(int not_used) 2000 { 2001 u64 value; 2002 2003 rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value); 2004 return value & 0x7F; 2005 } 2006 2007 static u64 atom_get_val(struct cpudata *cpudata, int pstate) 2008 { 2009 u64 val; 2010 int32_t vid_fp; 2011 u32 vid; 2012 2013 val = (u64)pstate << 8; 2014 if (READ_ONCE(global.no_turbo) && !READ_ONCE(global.turbo_disabled)) 2015 val |= (u64)1 << 32; 2016 2017 vid_fp = cpudata->vid.min + mul_fp( 2018 int_tofp(pstate - cpudata->pstate.min_pstate), 2019 cpudata->vid.ratio); 2020 2021 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max); 2022 vid = ceiling_fp(vid_fp); 2023 2024 if (pstate > cpudata->pstate.max_pstate) 2025 vid = cpudata->vid.turbo; 2026 2027 return val | vid; 2028 } 2029 2030 static int silvermont_get_scaling(void) 2031 { 2032 u64 value; 2033 int i; 2034 /* Defined in Table 35-6 from SDM (Sept 2015) */ 2035 static int silvermont_freq_table[] = { 2036 83300, 100000, 133300, 116700, 80000}; 2037 2038 rdmsrl(MSR_FSB_FREQ, value); 2039 i = value & 0x7; 2040 WARN_ON(i > 4); 2041 2042 return silvermont_freq_table[i]; 2043 } 2044 2045 static int airmont_get_scaling(void) 2046 { 2047 u64 value; 2048 int i; 2049 /* Defined in Table 35-10 from SDM (Sept 2015) */ 2050 static int airmont_freq_table[] = { 2051 83300, 100000, 133300, 116700, 80000, 2052 93300, 90000, 88900, 87500}; 2053 2054 rdmsrl(MSR_FSB_FREQ, value); 2055 i = value & 0xF; 2056 WARN_ON(i > 8); 2057 2058 return airmont_freq_table[i]; 2059 } 2060 2061 static void atom_get_vid(struct cpudata *cpudata) 2062 { 2063 u64 value; 2064 2065 rdmsrl(MSR_ATOM_CORE_VIDS, value); 2066 cpudata->vid.min = int_tofp((value >> 8) & 0x7f); 2067 cpudata->vid.max = int_tofp((value >> 16) & 0x7f); 2068 cpudata->vid.ratio = div_fp( 2069 cpudata->vid.max - cpudata->vid.min, 2070 int_tofp(cpudata->pstate.max_pstate - 2071 cpudata->pstate.min_pstate)); 2072 2073 rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value); 2074 cpudata->vid.turbo = value & 0x7f; 2075 } 2076 2077 static int core_get_min_pstate(int cpu) 2078 { 2079 u64 value; 2080 2081 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &value); 2082 return (value >> 40) & 0xFF; 2083 } 2084 2085 static int core_get_max_pstate_physical(int cpu) 2086 { 2087 u64 value; 2088 2089 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &value); 2090 return (value >> 8) & 0xFF; 2091 } 2092 2093 static int core_get_tdp_ratio(int cpu, u64 plat_info) 2094 { 2095 /* Check how many TDP levels present */ 2096 if (plat_info & 0x600000000) { 2097 u64 tdp_ctrl; 2098 u64 tdp_ratio; 2099 int tdp_msr; 2100 int err; 2101 2102 /* Get the TDP level (0, 1, 2) to get ratios */ 2103 err = rdmsrl_safe_on_cpu(cpu, MSR_CONFIG_TDP_CONTROL, &tdp_ctrl); 2104 if (err) 2105 return err; 2106 2107 /* TDP MSR are continuous starting at 0x648 */ 2108 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03); 2109 err = rdmsrl_safe_on_cpu(cpu, tdp_msr, &tdp_ratio); 2110 if (err) 2111 return err; 2112 2113 /* For level 1 and 2, bits[23:16] contain the ratio */ 2114 if (tdp_ctrl & 0x03) 2115 tdp_ratio >>= 16; 2116 2117 tdp_ratio &= 0xff; /* ratios are only 8 bits long */ 2118 pr_debug("tdp_ratio %x\n", (int)tdp_ratio); 2119 2120 return (int)tdp_ratio; 2121 } 2122 2123 return -ENXIO; 2124 } 2125 2126 static int core_get_max_pstate(int cpu) 2127 { 2128 u64 tar; 2129 u64 plat_info; 2130 int max_pstate; 2131 int tdp_ratio; 2132 int err; 2133 2134 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &plat_info); 2135 max_pstate = (plat_info >> 8) & 0xFF; 2136 2137 tdp_ratio = core_get_tdp_ratio(cpu, plat_info); 2138 if (tdp_ratio <= 0) 2139 return max_pstate; 2140 2141 if (hwp_active) { 2142 /* Turbo activation ratio is not used on HWP platforms */ 2143 return tdp_ratio; 2144 } 2145 2146 err = rdmsrl_safe_on_cpu(cpu, MSR_TURBO_ACTIVATION_RATIO, &tar); 2147 if (!err) { 2148 int tar_levels; 2149 2150 /* Do some sanity checking for safety */ 2151 tar_levels = tar & 0xff; 2152 if (tdp_ratio - 1 == tar_levels) { 2153 max_pstate = tar_levels; 2154 pr_debug("max_pstate=TAC %x\n", max_pstate); 2155 } 2156 } 2157 2158 return max_pstate; 2159 } 2160 2161 static int core_get_turbo_pstate(int cpu) 2162 { 2163 u64 value; 2164 int nont, ret; 2165 2166 rdmsrl_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value); 2167 nont = core_get_max_pstate(cpu); 2168 ret = (value) & 255; 2169 if (ret <= nont) 2170 ret = nont; 2171 return ret; 2172 } 2173 2174 static u64 core_get_val(struct cpudata *cpudata, int pstate) 2175 { 2176 u64 val; 2177 2178 val = (u64)pstate << 8; 2179 if (READ_ONCE(global.no_turbo) && !READ_ONCE(global.turbo_disabled)) 2180 val |= (u64)1 << 32; 2181 2182 return val; 2183 } 2184 2185 static int knl_get_aperf_mperf_shift(void) 2186 { 2187 return 10; 2188 } 2189 2190 static int knl_get_turbo_pstate(int cpu) 2191 { 2192 u64 value; 2193 int nont, ret; 2194 2195 rdmsrl_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value); 2196 nont = core_get_max_pstate(cpu); 2197 ret = (((value) >> 8) & 0xFF); 2198 if (ret <= nont) 2199 ret = nont; 2200 return ret; 2201 } 2202 2203 static int hwp_get_cpu_scaling(int cpu) 2204 { 2205 if (hybrid_scaling_factor) { 2206 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id()); 2207 u8 cpu_type = c->topo.intel_type; 2208 2209 /* 2210 * Return the hybrid scaling factor for P-cores and use the 2211 * default core scaling for E-cores. 2212 */ 2213 if (cpu_type == INTEL_CPU_TYPE_CORE) 2214 return hybrid_scaling_factor; 2215 2216 if (cpu_type == INTEL_CPU_TYPE_ATOM) 2217 return core_get_scaling(); 2218 } 2219 2220 /* Use core scaling on non-hybrid systems. */ 2221 if (!cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) 2222 return core_get_scaling(); 2223 2224 /* 2225 * The system is hybrid, but the hybrid scaling factor is not known or 2226 * the CPU type is not one of the above, so use CPPC to compute the 2227 * scaling factor for this CPU. 2228 */ 2229 return intel_pstate_cppc_get_scaling(cpu); 2230 } 2231 2232 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate) 2233 { 2234 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu); 2235 cpu->pstate.current_pstate = pstate; 2236 /* 2237 * Generally, there is no guarantee that this code will always run on 2238 * the CPU being updated, so force the register update to run on the 2239 * right CPU. 2240 */ 2241 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL, 2242 pstate_funcs.get_val(cpu, pstate)); 2243 } 2244 2245 static void intel_pstate_set_min_pstate(struct cpudata *cpu) 2246 { 2247 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate); 2248 } 2249 2250 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu) 2251 { 2252 int perf_ctl_max_phys = pstate_funcs.get_max_physical(cpu->cpu); 2253 int perf_ctl_scaling = pstate_funcs.get_scaling(); 2254 2255 cpu->pstate.min_pstate = pstate_funcs.get_min(cpu->cpu); 2256 cpu->pstate.max_pstate_physical = perf_ctl_max_phys; 2257 cpu->pstate.perf_ctl_scaling = perf_ctl_scaling; 2258 2259 if (hwp_active && !hwp_mode_bdw) { 2260 __intel_pstate_get_hwp_cap(cpu); 2261 2262 if (pstate_funcs.get_cpu_scaling) { 2263 cpu->pstate.scaling = pstate_funcs.get_cpu_scaling(cpu->cpu); 2264 if (cpu->pstate.scaling != perf_ctl_scaling) { 2265 intel_pstate_hybrid_hwp_adjust(cpu); 2266 hwp_is_hybrid = true; 2267 } 2268 } else { 2269 cpu->pstate.scaling = perf_ctl_scaling; 2270 } 2271 /* 2272 * If the CPU is going online for the first time and it was 2273 * offline initially, asym capacity scaling needs to be updated. 2274 */ 2275 hybrid_update_capacity(cpu); 2276 } else { 2277 cpu->pstate.scaling = perf_ctl_scaling; 2278 cpu->pstate.max_pstate = pstate_funcs.get_max(cpu->cpu); 2279 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(cpu->cpu); 2280 } 2281 2282 if (cpu->pstate.scaling == perf_ctl_scaling) { 2283 cpu->pstate.min_freq = cpu->pstate.min_pstate * perf_ctl_scaling; 2284 cpu->pstate.max_freq = cpu->pstate.max_pstate * perf_ctl_scaling; 2285 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * perf_ctl_scaling; 2286 } 2287 2288 if (pstate_funcs.get_aperf_mperf_shift) 2289 cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift(); 2290 2291 if (pstate_funcs.get_vid) 2292 pstate_funcs.get_vid(cpu); 2293 2294 intel_pstate_set_min_pstate(cpu); 2295 } 2296 2297 /* 2298 * Long hold time will keep high perf limits for long time, 2299 * which negatively impacts perf/watt for some workloads, 2300 * like specpower. 3ms is based on experiements on some 2301 * workoads. 2302 */ 2303 static int hwp_boost_hold_time_ns = 3 * NSEC_PER_MSEC; 2304 2305 static inline void intel_pstate_hwp_boost_up(struct cpudata *cpu) 2306 { 2307 u64 hwp_req = READ_ONCE(cpu->hwp_req_cached); 2308 u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached); 2309 u32 max_limit = (hwp_req & 0xff00) >> 8; 2310 u32 min_limit = (hwp_req & 0xff); 2311 u32 boost_level1; 2312 2313 /* 2314 * Cases to consider (User changes via sysfs or boot time): 2315 * If, P0 (Turbo max) = P1 (Guaranteed max) = min: 2316 * No boost, return. 2317 * If, P0 (Turbo max) > P1 (Guaranteed max) = min: 2318 * Should result in one level boost only for P0. 2319 * If, P0 (Turbo max) = P1 (Guaranteed max) > min: 2320 * Should result in two level boost: 2321 * (min + p1)/2 and P1. 2322 * If, P0 (Turbo max) > P1 (Guaranteed max) > min: 2323 * Should result in three level boost: 2324 * (min + p1)/2, P1 and P0. 2325 */ 2326 2327 /* If max and min are equal or already at max, nothing to boost */ 2328 if (max_limit == min_limit || cpu->hwp_boost_min >= max_limit) 2329 return; 2330 2331 if (!cpu->hwp_boost_min) 2332 cpu->hwp_boost_min = min_limit; 2333 2334 /* level at half way mark between min and guranteed */ 2335 boost_level1 = (HWP_GUARANTEED_PERF(hwp_cap) + min_limit) >> 1; 2336 2337 if (cpu->hwp_boost_min < boost_level1) 2338 cpu->hwp_boost_min = boost_level1; 2339 else if (cpu->hwp_boost_min < HWP_GUARANTEED_PERF(hwp_cap)) 2340 cpu->hwp_boost_min = HWP_GUARANTEED_PERF(hwp_cap); 2341 else if (cpu->hwp_boost_min == HWP_GUARANTEED_PERF(hwp_cap) && 2342 max_limit != HWP_GUARANTEED_PERF(hwp_cap)) 2343 cpu->hwp_boost_min = max_limit; 2344 else 2345 return; 2346 2347 hwp_req = (hwp_req & ~GENMASK_ULL(7, 0)) | cpu->hwp_boost_min; 2348 wrmsrl(MSR_HWP_REQUEST, hwp_req); 2349 cpu->last_update = cpu->sample.time; 2350 } 2351 2352 static inline void intel_pstate_hwp_boost_down(struct cpudata *cpu) 2353 { 2354 if (cpu->hwp_boost_min) { 2355 bool expired; 2356 2357 /* Check if we are idle for hold time to boost down */ 2358 expired = time_after64(cpu->sample.time, cpu->last_update + 2359 hwp_boost_hold_time_ns); 2360 if (expired) { 2361 wrmsrl(MSR_HWP_REQUEST, cpu->hwp_req_cached); 2362 cpu->hwp_boost_min = 0; 2363 } 2364 } 2365 cpu->last_update = cpu->sample.time; 2366 } 2367 2368 static inline void intel_pstate_update_util_hwp_local(struct cpudata *cpu, 2369 u64 time) 2370 { 2371 cpu->sample.time = time; 2372 2373 if (cpu->sched_flags & SCHED_CPUFREQ_IOWAIT) { 2374 bool do_io = false; 2375 2376 cpu->sched_flags = 0; 2377 /* 2378 * Set iowait_boost flag and update time. Since IO WAIT flag 2379 * is set all the time, we can't just conclude that there is 2380 * some IO bound activity is scheduled on this CPU with just 2381 * one occurrence. If we receive at least two in two 2382 * consecutive ticks, then we treat as boost candidate. 2383 */ 2384 if (time_before64(time, cpu->last_io_update + 2 * TICK_NSEC)) 2385 do_io = true; 2386 2387 cpu->last_io_update = time; 2388 2389 if (do_io) 2390 intel_pstate_hwp_boost_up(cpu); 2391 2392 } else { 2393 intel_pstate_hwp_boost_down(cpu); 2394 } 2395 } 2396 2397 static inline void intel_pstate_update_util_hwp(struct update_util_data *data, 2398 u64 time, unsigned int flags) 2399 { 2400 struct cpudata *cpu = container_of(data, struct cpudata, update_util); 2401 2402 cpu->sched_flags |= flags; 2403 2404 if (smp_processor_id() == cpu->cpu) 2405 intel_pstate_update_util_hwp_local(cpu, time); 2406 } 2407 2408 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu) 2409 { 2410 struct sample *sample = &cpu->sample; 2411 2412 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf); 2413 } 2414 2415 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time) 2416 { 2417 u64 aperf, mperf; 2418 unsigned long flags; 2419 u64 tsc; 2420 2421 local_irq_save(flags); 2422 rdmsrl(MSR_IA32_APERF, aperf); 2423 rdmsrl(MSR_IA32_MPERF, mperf); 2424 tsc = rdtsc(); 2425 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) { 2426 local_irq_restore(flags); 2427 return false; 2428 } 2429 local_irq_restore(flags); 2430 2431 cpu->last_sample_time = cpu->sample.time; 2432 cpu->sample.time = time; 2433 cpu->sample.aperf = aperf; 2434 cpu->sample.mperf = mperf; 2435 cpu->sample.tsc = tsc; 2436 cpu->sample.aperf -= cpu->prev_aperf; 2437 cpu->sample.mperf -= cpu->prev_mperf; 2438 cpu->sample.tsc -= cpu->prev_tsc; 2439 2440 cpu->prev_aperf = aperf; 2441 cpu->prev_mperf = mperf; 2442 cpu->prev_tsc = tsc; 2443 /* 2444 * First time this function is invoked in a given cycle, all of the 2445 * previous sample data fields are equal to zero or stale and they must 2446 * be populated with meaningful numbers for things to work, so assume 2447 * that sample.time will always be reset before setting the utilization 2448 * update hook and make the caller skip the sample then. 2449 */ 2450 if (cpu->last_sample_time) { 2451 intel_pstate_calc_avg_perf(cpu); 2452 return true; 2453 } 2454 return false; 2455 } 2456 2457 static inline int32_t get_avg_frequency(struct cpudata *cpu) 2458 { 2459 return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz); 2460 } 2461 2462 static inline int32_t get_avg_pstate(struct cpudata *cpu) 2463 { 2464 return mul_ext_fp(cpu->pstate.max_pstate_physical, 2465 cpu->sample.core_avg_perf); 2466 } 2467 2468 static inline int32_t get_target_pstate(struct cpudata *cpu) 2469 { 2470 struct sample *sample = &cpu->sample; 2471 int32_t busy_frac; 2472 int target, avg_pstate; 2473 2474 busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift, 2475 sample->tsc); 2476 2477 if (busy_frac < cpu->iowait_boost) 2478 busy_frac = cpu->iowait_boost; 2479 2480 sample->busy_scaled = busy_frac * 100; 2481 2482 target = READ_ONCE(global.no_turbo) ? 2483 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate; 2484 target += target >> 2; 2485 target = mul_fp(target, busy_frac); 2486 if (target < cpu->pstate.min_pstate) 2487 target = cpu->pstate.min_pstate; 2488 2489 /* 2490 * If the average P-state during the previous cycle was higher than the 2491 * current target, add 50% of the difference to the target to reduce 2492 * possible performance oscillations and offset possible performance 2493 * loss related to moving the workload from one CPU to another within 2494 * a package/module. 2495 */ 2496 avg_pstate = get_avg_pstate(cpu); 2497 if (avg_pstate > target) 2498 target += (avg_pstate - target) >> 1; 2499 2500 return target; 2501 } 2502 2503 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate) 2504 { 2505 int min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio); 2506 int max_pstate = max(min_pstate, cpu->max_perf_ratio); 2507 2508 return clamp_t(int, pstate, min_pstate, max_pstate); 2509 } 2510 2511 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate) 2512 { 2513 if (pstate == cpu->pstate.current_pstate) 2514 return; 2515 2516 cpu->pstate.current_pstate = pstate; 2517 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate)); 2518 } 2519 2520 static void intel_pstate_adjust_pstate(struct cpudata *cpu) 2521 { 2522 int from = cpu->pstate.current_pstate; 2523 struct sample *sample; 2524 int target_pstate; 2525 2526 target_pstate = get_target_pstate(cpu); 2527 target_pstate = intel_pstate_prepare_request(cpu, target_pstate); 2528 trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu); 2529 intel_pstate_update_pstate(cpu, target_pstate); 2530 2531 sample = &cpu->sample; 2532 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf), 2533 fp_toint(sample->busy_scaled), 2534 from, 2535 cpu->pstate.current_pstate, 2536 sample->mperf, 2537 sample->aperf, 2538 sample->tsc, 2539 get_avg_frequency(cpu), 2540 fp_toint(cpu->iowait_boost * 100)); 2541 } 2542 2543 static void intel_pstate_update_util(struct update_util_data *data, u64 time, 2544 unsigned int flags) 2545 { 2546 struct cpudata *cpu = container_of(data, struct cpudata, update_util); 2547 u64 delta_ns; 2548 2549 /* Don't allow remote callbacks */ 2550 if (smp_processor_id() != cpu->cpu) 2551 return; 2552 2553 delta_ns = time - cpu->last_update; 2554 if (flags & SCHED_CPUFREQ_IOWAIT) { 2555 /* Start over if the CPU may have been idle. */ 2556 if (delta_ns > TICK_NSEC) { 2557 cpu->iowait_boost = ONE_EIGHTH_FP; 2558 } else if (cpu->iowait_boost >= ONE_EIGHTH_FP) { 2559 cpu->iowait_boost <<= 1; 2560 if (cpu->iowait_boost > int_tofp(1)) 2561 cpu->iowait_boost = int_tofp(1); 2562 } else { 2563 cpu->iowait_boost = ONE_EIGHTH_FP; 2564 } 2565 } else if (cpu->iowait_boost) { 2566 /* Clear iowait_boost if the CPU may have been idle. */ 2567 if (delta_ns > TICK_NSEC) 2568 cpu->iowait_boost = 0; 2569 else 2570 cpu->iowait_boost >>= 1; 2571 } 2572 cpu->last_update = time; 2573 delta_ns = time - cpu->sample.time; 2574 if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL) 2575 return; 2576 2577 if (intel_pstate_sample(cpu, time)) 2578 intel_pstate_adjust_pstate(cpu); 2579 } 2580 2581 static struct pstate_funcs core_funcs = { 2582 .get_max = core_get_max_pstate, 2583 .get_max_physical = core_get_max_pstate_physical, 2584 .get_min = core_get_min_pstate, 2585 .get_turbo = core_get_turbo_pstate, 2586 .get_scaling = core_get_scaling, 2587 .get_val = core_get_val, 2588 }; 2589 2590 static const struct pstate_funcs silvermont_funcs = { 2591 .get_max = atom_get_max_pstate, 2592 .get_max_physical = atom_get_max_pstate, 2593 .get_min = atom_get_min_pstate, 2594 .get_turbo = atom_get_turbo_pstate, 2595 .get_val = atom_get_val, 2596 .get_scaling = silvermont_get_scaling, 2597 .get_vid = atom_get_vid, 2598 }; 2599 2600 static const struct pstate_funcs airmont_funcs = { 2601 .get_max = atom_get_max_pstate, 2602 .get_max_physical = atom_get_max_pstate, 2603 .get_min = atom_get_min_pstate, 2604 .get_turbo = atom_get_turbo_pstate, 2605 .get_val = atom_get_val, 2606 .get_scaling = airmont_get_scaling, 2607 .get_vid = atom_get_vid, 2608 }; 2609 2610 static const struct pstate_funcs knl_funcs = { 2611 .get_max = core_get_max_pstate, 2612 .get_max_physical = core_get_max_pstate_physical, 2613 .get_min = core_get_min_pstate, 2614 .get_turbo = knl_get_turbo_pstate, 2615 .get_aperf_mperf_shift = knl_get_aperf_mperf_shift, 2616 .get_scaling = core_get_scaling, 2617 .get_val = core_get_val, 2618 }; 2619 2620 #define X86_MATCH(vfm, policy) \ 2621 X86_MATCH_VFM_FEATURE(vfm, X86_FEATURE_APERFMPERF, &policy) 2622 2623 static const struct x86_cpu_id intel_pstate_cpu_ids[] = { 2624 X86_MATCH(INTEL_SANDYBRIDGE, core_funcs), 2625 X86_MATCH(INTEL_SANDYBRIDGE_X, core_funcs), 2626 X86_MATCH(INTEL_ATOM_SILVERMONT, silvermont_funcs), 2627 X86_MATCH(INTEL_IVYBRIDGE, core_funcs), 2628 X86_MATCH(INTEL_HASWELL, core_funcs), 2629 X86_MATCH(INTEL_BROADWELL, core_funcs), 2630 X86_MATCH(INTEL_IVYBRIDGE_X, core_funcs), 2631 X86_MATCH(INTEL_HASWELL_X, core_funcs), 2632 X86_MATCH(INTEL_HASWELL_L, core_funcs), 2633 X86_MATCH(INTEL_HASWELL_G, core_funcs), 2634 X86_MATCH(INTEL_BROADWELL_G, core_funcs), 2635 X86_MATCH(INTEL_ATOM_AIRMONT, airmont_funcs), 2636 X86_MATCH(INTEL_SKYLAKE_L, core_funcs), 2637 X86_MATCH(INTEL_BROADWELL_X, core_funcs), 2638 X86_MATCH(INTEL_SKYLAKE, core_funcs), 2639 X86_MATCH(INTEL_BROADWELL_D, core_funcs), 2640 X86_MATCH(INTEL_XEON_PHI_KNL, knl_funcs), 2641 X86_MATCH(INTEL_XEON_PHI_KNM, knl_funcs), 2642 X86_MATCH(INTEL_ATOM_GOLDMONT, core_funcs), 2643 X86_MATCH(INTEL_ATOM_GOLDMONT_PLUS, core_funcs), 2644 X86_MATCH(INTEL_SKYLAKE_X, core_funcs), 2645 X86_MATCH(INTEL_COMETLAKE, core_funcs), 2646 X86_MATCH(INTEL_ICELAKE_X, core_funcs), 2647 X86_MATCH(INTEL_TIGERLAKE, core_funcs), 2648 X86_MATCH(INTEL_SAPPHIRERAPIDS_X, core_funcs), 2649 X86_MATCH(INTEL_EMERALDRAPIDS_X, core_funcs), 2650 {} 2651 }; 2652 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids); 2653 2654 #ifdef CONFIG_ACPI 2655 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = { 2656 X86_MATCH(INTEL_BROADWELL_D, core_funcs), 2657 X86_MATCH(INTEL_BROADWELL_X, core_funcs), 2658 X86_MATCH(INTEL_SKYLAKE_X, core_funcs), 2659 X86_MATCH(INTEL_ICELAKE_X, core_funcs), 2660 X86_MATCH(INTEL_SAPPHIRERAPIDS_X, core_funcs), 2661 X86_MATCH(INTEL_EMERALDRAPIDS_X, core_funcs), 2662 X86_MATCH(INTEL_GRANITERAPIDS_D, core_funcs), 2663 X86_MATCH(INTEL_GRANITERAPIDS_X, core_funcs), 2664 X86_MATCH(INTEL_ATOM_CRESTMONT, core_funcs), 2665 X86_MATCH(INTEL_ATOM_CRESTMONT_X, core_funcs), 2666 {} 2667 }; 2668 #endif 2669 2670 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = { 2671 X86_MATCH(INTEL_KABYLAKE, core_funcs), 2672 {} 2673 }; 2674 2675 static int intel_pstate_init_cpu(unsigned int cpunum) 2676 { 2677 struct cpudata *cpu; 2678 2679 cpu = all_cpu_data[cpunum]; 2680 2681 if (!cpu) { 2682 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL); 2683 if (!cpu) 2684 return -ENOMEM; 2685 2686 WRITE_ONCE(all_cpu_data[cpunum], cpu); 2687 2688 cpu->cpu = cpunum; 2689 2690 cpu->epp_default = -EINVAL; 2691 2692 if (hwp_active) { 2693 intel_pstate_hwp_enable(cpu); 2694 2695 if (intel_pstate_acpi_pm_profile_server()) 2696 hwp_boost = true; 2697 } 2698 } else if (hwp_active) { 2699 /* 2700 * Re-enable HWP in case this happens after a resume from ACPI 2701 * S3 if the CPU was offline during the whole system/resume 2702 * cycle. 2703 */ 2704 intel_pstate_hwp_reenable(cpu); 2705 } 2706 2707 cpu->epp_powersave = -EINVAL; 2708 cpu->epp_policy = CPUFREQ_POLICY_UNKNOWN; 2709 2710 intel_pstate_get_cpu_pstates(cpu); 2711 2712 pr_debug("controlling: cpu %d\n", cpunum); 2713 2714 return 0; 2715 } 2716 2717 static void intel_pstate_set_update_util_hook(unsigned int cpu_num) 2718 { 2719 struct cpudata *cpu = all_cpu_data[cpu_num]; 2720 2721 if (hwp_active && !hwp_boost) 2722 return; 2723 2724 if (cpu->update_util_set) 2725 return; 2726 2727 /* Prevent intel_pstate_update_util() from using stale data. */ 2728 cpu->sample.time = 0; 2729 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util, 2730 (hwp_active ? 2731 intel_pstate_update_util_hwp : 2732 intel_pstate_update_util)); 2733 cpu->update_util_set = true; 2734 } 2735 2736 static void intel_pstate_clear_update_util_hook(unsigned int cpu) 2737 { 2738 struct cpudata *cpu_data = all_cpu_data[cpu]; 2739 2740 if (!cpu_data->update_util_set) 2741 return; 2742 2743 cpufreq_remove_update_util_hook(cpu); 2744 cpu_data->update_util_set = false; 2745 synchronize_rcu(); 2746 } 2747 2748 static int intel_pstate_get_max_freq(struct cpudata *cpu) 2749 { 2750 return READ_ONCE(global.no_turbo) ? 2751 cpu->pstate.max_freq : cpu->pstate.turbo_freq; 2752 } 2753 2754 static void intel_pstate_update_perf_limits(struct cpudata *cpu, 2755 unsigned int policy_min, 2756 unsigned int policy_max) 2757 { 2758 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling; 2759 int32_t max_policy_perf, min_policy_perf; 2760 2761 max_policy_perf = policy_max / perf_ctl_scaling; 2762 if (policy_max == policy_min) { 2763 min_policy_perf = max_policy_perf; 2764 } else { 2765 min_policy_perf = policy_min / perf_ctl_scaling; 2766 min_policy_perf = clamp_t(int32_t, min_policy_perf, 2767 0, max_policy_perf); 2768 } 2769 2770 /* 2771 * HWP needs some special consideration, because HWP_REQUEST uses 2772 * abstract values to represent performance rather than pure ratios. 2773 */ 2774 if (hwp_active && cpu->pstate.scaling != perf_ctl_scaling) { 2775 int freq; 2776 2777 freq = max_policy_perf * perf_ctl_scaling; 2778 max_policy_perf = intel_pstate_freq_to_hwp(cpu, freq); 2779 freq = min_policy_perf * perf_ctl_scaling; 2780 min_policy_perf = intel_pstate_freq_to_hwp(cpu, freq); 2781 } 2782 2783 pr_debug("cpu:%d min_policy_perf:%d max_policy_perf:%d\n", 2784 cpu->cpu, min_policy_perf, max_policy_perf); 2785 2786 /* Normalize user input to [min_perf, max_perf] */ 2787 if (per_cpu_limits) { 2788 cpu->min_perf_ratio = min_policy_perf; 2789 cpu->max_perf_ratio = max_policy_perf; 2790 } else { 2791 int turbo_max = cpu->pstate.turbo_pstate; 2792 int32_t global_min, global_max; 2793 2794 /* Global limits are in percent of the maximum turbo P-state. */ 2795 global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100); 2796 global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100); 2797 global_min = clamp_t(int32_t, global_min, 0, global_max); 2798 2799 pr_debug("cpu:%d global_min:%d global_max:%d\n", cpu->cpu, 2800 global_min, global_max); 2801 2802 cpu->min_perf_ratio = max(min_policy_perf, global_min); 2803 cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf); 2804 cpu->max_perf_ratio = min(max_policy_perf, global_max); 2805 cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio); 2806 2807 /* Make sure min_perf <= max_perf */ 2808 cpu->min_perf_ratio = min(cpu->min_perf_ratio, 2809 cpu->max_perf_ratio); 2810 2811 } 2812 pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", cpu->cpu, 2813 cpu->max_perf_ratio, 2814 cpu->min_perf_ratio); 2815 } 2816 2817 static int intel_pstate_set_policy(struct cpufreq_policy *policy) 2818 { 2819 struct cpudata *cpu; 2820 2821 if (!policy->cpuinfo.max_freq) 2822 return -ENODEV; 2823 2824 pr_debug("set_policy cpuinfo.max %u policy->max %u\n", 2825 policy->cpuinfo.max_freq, policy->max); 2826 2827 cpu = all_cpu_data[policy->cpu]; 2828 cpu->policy = policy->policy; 2829 2830 mutex_lock(&intel_pstate_limits_lock); 2831 2832 intel_pstate_update_perf_limits(cpu, policy->min, policy->max); 2833 2834 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) { 2835 int pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio); 2836 2837 /* 2838 * NOHZ_FULL CPUs need this as the governor callback may not 2839 * be invoked on them. 2840 */ 2841 intel_pstate_clear_update_util_hook(policy->cpu); 2842 intel_pstate_set_pstate(cpu, pstate); 2843 } else { 2844 intel_pstate_set_update_util_hook(policy->cpu); 2845 } 2846 2847 if (hwp_active) { 2848 /* 2849 * When hwp_boost was active before and dynamically it 2850 * was turned off, in that case we need to clear the 2851 * update util hook. 2852 */ 2853 if (!hwp_boost) 2854 intel_pstate_clear_update_util_hook(policy->cpu); 2855 intel_pstate_hwp_set(policy->cpu); 2856 } 2857 /* 2858 * policy->cur is never updated with the intel_pstate driver, but it 2859 * is used as a stale frequency value. So, keep it within limits. 2860 */ 2861 policy->cur = policy->min; 2862 2863 mutex_unlock(&intel_pstate_limits_lock); 2864 2865 return 0; 2866 } 2867 2868 static void intel_pstate_adjust_policy_max(struct cpudata *cpu, 2869 struct cpufreq_policy_data *policy) 2870 { 2871 if (!hwp_active && 2872 cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate && 2873 policy->max < policy->cpuinfo.max_freq && 2874 policy->max > cpu->pstate.max_freq) { 2875 pr_debug("policy->max > max non turbo frequency\n"); 2876 policy->max = policy->cpuinfo.max_freq; 2877 } 2878 } 2879 2880 static void intel_pstate_verify_cpu_policy(struct cpudata *cpu, 2881 struct cpufreq_policy_data *policy) 2882 { 2883 int max_freq; 2884 2885 if (hwp_active) { 2886 intel_pstate_get_hwp_cap(cpu); 2887 max_freq = READ_ONCE(global.no_turbo) ? 2888 cpu->pstate.max_freq : cpu->pstate.turbo_freq; 2889 } else { 2890 max_freq = intel_pstate_get_max_freq(cpu); 2891 } 2892 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, max_freq); 2893 2894 intel_pstate_adjust_policy_max(cpu, policy); 2895 } 2896 2897 static int intel_pstate_verify_policy(struct cpufreq_policy_data *policy) 2898 { 2899 intel_pstate_verify_cpu_policy(all_cpu_data[policy->cpu], policy); 2900 2901 return 0; 2902 } 2903 2904 static int intel_cpufreq_cpu_offline(struct cpufreq_policy *policy) 2905 { 2906 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2907 2908 pr_debug("CPU %d going offline\n", cpu->cpu); 2909 2910 if (cpu->suspended) 2911 return 0; 2912 2913 /* 2914 * If the CPU is an SMT thread and it goes offline with the performance 2915 * settings different from the minimum, it will prevent its sibling 2916 * from getting to lower performance levels, so force the minimum 2917 * performance on CPU offline to prevent that from happening. 2918 */ 2919 if (hwp_active) 2920 intel_pstate_hwp_offline(cpu); 2921 else 2922 intel_pstate_set_min_pstate(cpu); 2923 2924 intel_pstate_exit_perf_limits(policy); 2925 2926 return 0; 2927 } 2928 2929 static int intel_pstate_cpu_online(struct cpufreq_policy *policy) 2930 { 2931 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2932 2933 pr_debug("CPU %d going online\n", cpu->cpu); 2934 2935 intel_pstate_init_acpi_perf_limits(policy); 2936 2937 if (hwp_active) { 2938 /* 2939 * Re-enable HWP and clear the "suspended" flag to let "resume" 2940 * know that it need not do that. 2941 */ 2942 intel_pstate_hwp_reenable(cpu); 2943 cpu->suspended = false; 2944 2945 hybrid_update_capacity(cpu); 2946 } 2947 2948 return 0; 2949 } 2950 2951 static int intel_pstate_cpu_offline(struct cpufreq_policy *policy) 2952 { 2953 intel_pstate_clear_update_util_hook(policy->cpu); 2954 2955 return intel_cpufreq_cpu_offline(policy); 2956 } 2957 2958 static void intel_pstate_cpu_exit(struct cpufreq_policy *policy) 2959 { 2960 pr_debug("CPU %d exiting\n", policy->cpu); 2961 2962 policy->fast_switch_possible = false; 2963 } 2964 2965 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy) 2966 { 2967 struct cpudata *cpu; 2968 int rc; 2969 2970 rc = intel_pstate_init_cpu(policy->cpu); 2971 if (rc) 2972 return rc; 2973 2974 cpu = all_cpu_data[policy->cpu]; 2975 2976 cpu->max_perf_ratio = 0xFF; 2977 cpu->min_perf_ratio = 0; 2978 2979 /* cpuinfo and default policy values */ 2980 policy->cpuinfo.min_freq = cpu->pstate.min_freq; 2981 policy->cpuinfo.max_freq = READ_ONCE(global.no_turbo) ? 2982 cpu->pstate.max_freq : cpu->pstate.turbo_freq; 2983 2984 policy->min = policy->cpuinfo.min_freq; 2985 policy->max = policy->cpuinfo.max_freq; 2986 2987 intel_pstate_init_acpi_perf_limits(policy); 2988 2989 policy->fast_switch_possible = true; 2990 2991 return 0; 2992 } 2993 2994 static int intel_pstate_cpu_init(struct cpufreq_policy *policy) 2995 { 2996 int ret = __intel_pstate_cpu_init(policy); 2997 2998 if (ret) 2999 return ret; 3000 3001 /* 3002 * Set the policy to powersave to provide a valid fallback value in case 3003 * the default cpufreq governor is neither powersave nor performance. 3004 */ 3005 policy->policy = CPUFREQ_POLICY_POWERSAVE; 3006 3007 if (hwp_active) { 3008 struct cpudata *cpu = all_cpu_data[policy->cpu]; 3009 3010 cpu->epp_cached = intel_pstate_get_epp(cpu, 0); 3011 } 3012 3013 return 0; 3014 } 3015 3016 static struct cpufreq_driver intel_pstate = { 3017 .flags = CPUFREQ_CONST_LOOPS, 3018 .verify = intel_pstate_verify_policy, 3019 .setpolicy = intel_pstate_set_policy, 3020 .suspend = intel_pstate_suspend, 3021 .resume = intel_pstate_resume, 3022 .init = intel_pstate_cpu_init, 3023 .exit = intel_pstate_cpu_exit, 3024 .offline = intel_pstate_cpu_offline, 3025 .online = intel_pstate_cpu_online, 3026 .update_limits = intel_pstate_update_limits, 3027 .name = "intel_pstate", 3028 }; 3029 3030 static int intel_cpufreq_verify_policy(struct cpufreq_policy_data *policy) 3031 { 3032 struct cpudata *cpu = all_cpu_data[policy->cpu]; 3033 3034 intel_pstate_verify_cpu_policy(cpu, policy); 3035 intel_pstate_update_perf_limits(cpu, policy->min, policy->max); 3036 3037 return 0; 3038 } 3039 3040 /* Use of trace in passive mode: 3041 * 3042 * In passive mode the trace core_busy field (also known as the 3043 * performance field, and lablelled as such on the graphs; also known as 3044 * core_avg_perf) is not needed and so is re-assigned to indicate if the 3045 * driver call was via the normal or fast switch path. Various graphs 3046 * output from the intel_pstate_tracer.py utility that include core_busy 3047 * (or performance or core_avg_perf) have a fixed y-axis from 0 to 100%, 3048 * so we use 10 to indicate the normal path through the driver, and 3049 * 90 to indicate the fast switch path through the driver. 3050 * The scaled_busy field is not used, and is set to 0. 3051 */ 3052 3053 #define INTEL_PSTATE_TRACE_TARGET 10 3054 #define INTEL_PSTATE_TRACE_FAST_SWITCH 90 3055 3056 static void intel_cpufreq_trace(struct cpudata *cpu, unsigned int trace_type, int old_pstate) 3057 { 3058 struct sample *sample; 3059 3060 if (!trace_pstate_sample_enabled()) 3061 return; 3062 3063 if (!intel_pstate_sample(cpu, ktime_get())) 3064 return; 3065 3066 sample = &cpu->sample; 3067 trace_pstate_sample(trace_type, 3068 0, 3069 old_pstate, 3070 cpu->pstate.current_pstate, 3071 sample->mperf, 3072 sample->aperf, 3073 sample->tsc, 3074 get_avg_frequency(cpu), 3075 fp_toint(cpu->iowait_boost * 100)); 3076 } 3077 3078 static void intel_cpufreq_hwp_update(struct cpudata *cpu, u32 min, u32 max, 3079 u32 desired, bool fast_switch) 3080 { 3081 u64 prev = READ_ONCE(cpu->hwp_req_cached), value = prev; 3082 3083 value &= ~HWP_MIN_PERF(~0L); 3084 value |= HWP_MIN_PERF(min); 3085 3086 value &= ~HWP_MAX_PERF(~0L); 3087 value |= HWP_MAX_PERF(max); 3088 3089 value &= ~HWP_DESIRED_PERF(~0L); 3090 value |= HWP_DESIRED_PERF(desired); 3091 3092 if (value == prev) 3093 return; 3094 3095 WRITE_ONCE(cpu->hwp_req_cached, value); 3096 if (fast_switch) 3097 wrmsrl(MSR_HWP_REQUEST, value); 3098 else 3099 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 3100 } 3101 3102 static void intel_cpufreq_perf_ctl_update(struct cpudata *cpu, 3103 u32 target_pstate, bool fast_switch) 3104 { 3105 if (fast_switch) 3106 wrmsrl(MSR_IA32_PERF_CTL, 3107 pstate_funcs.get_val(cpu, target_pstate)); 3108 else 3109 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL, 3110 pstate_funcs.get_val(cpu, target_pstate)); 3111 } 3112 3113 static int intel_cpufreq_update_pstate(struct cpufreq_policy *policy, 3114 int target_pstate, bool fast_switch) 3115 { 3116 struct cpudata *cpu = all_cpu_data[policy->cpu]; 3117 int old_pstate = cpu->pstate.current_pstate; 3118 3119 target_pstate = intel_pstate_prepare_request(cpu, target_pstate); 3120 if (hwp_active) { 3121 int max_pstate = policy->strict_target ? 3122 target_pstate : cpu->max_perf_ratio; 3123 3124 intel_cpufreq_hwp_update(cpu, target_pstate, max_pstate, 0, 3125 fast_switch); 3126 } else if (target_pstate != old_pstate) { 3127 intel_cpufreq_perf_ctl_update(cpu, target_pstate, fast_switch); 3128 } 3129 3130 cpu->pstate.current_pstate = target_pstate; 3131 3132 intel_cpufreq_trace(cpu, fast_switch ? INTEL_PSTATE_TRACE_FAST_SWITCH : 3133 INTEL_PSTATE_TRACE_TARGET, old_pstate); 3134 3135 return target_pstate; 3136 } 3137 3138 static int intel_cpufreq_target(struct cpufreq_policy *policy, 3139 unsigned int target_freq, 3140 unsigned int relation) 3141 { 3142 struct cpudata *cpu = all_cpu_data[policy->cpu]; 3143 struct cpufreq_freqs freqs; 3144 int target_pstate; 3145 3146 freqs.old = policy->cur; 3147 freqs.new = target_freq; 3148 3149 cpufreq_freq_transition_begin(policy, &freqs); 3150 3151 target_pstate = intel_pstate_freq_to_hwp_rel(cpu, freqs.new, relation); 3152 target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, false); 3153 3154 freqs.new = target_pstate * cpu->pstate.scaling; 3155 3156 cpufreq_freq_transition_end(policy, &freqs, false); 3157 3158 return 0; 3159 } 3160 3161 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy, 3162 unsigned int target_freq) 3163 { 3164 struct cpudata *cpu = all_cpu_data[policy->cpu]; 3165 int target_pstate; 3166 3167 target_pstate = intel_pstate_freq_to_hwp(cpu, target_freq); 3168 3169 target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, true); 3170 3171 return target_pstate * cpu->pstate.scaling; 3172 } 3173 3174 static void intel_cpufreq_adjust_perf(unsigned int cpunum, 3175 unsigned long min_perf, 3176 unsigned long target_perf, 3177 unsigned long capacity) 3178 { 3179 struct cpudata *cpu = all_cpu_data[cpunum]; 3180 u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached); 3181 int old_pstate = cpu->pstate.current_pstate; 3182 int cap_pstate, min_pstate, max_pstate, target_pstate; 3183 3184 cap_pstate = READ_ONCE(global.no_turbo) ? 3185 HWP_GUARANTEED_PERF(hwp_cap) : 3186 HWP_HIGHEST_PERF(hwp_cap); 3187 3188 /* Optimization: Avoid unnecessary divisions. */ 3189 3190 target_pstate = cap_pstate; 3191 if (target_perf < capacity) 3192 target_pstate = DIV_ROUND_UP(cap_pstate * target_perf, capacity); 3193 3194 min_pstate = cap_pstate; 3195 if (min_perf < capacity) 3196 min_pstate = DIV_ROUND_UP(cap_pstate * min_perf, capacity); 3197 3198 if (min_pstate < cpu->pstate.min_pstate) 3199 min_pstate = cpu->pstate.min_pstate; 3200 3201 if (min_pstate < cpu->min_perf_ratio) 3202 min_pstate = cpu->min_perf_ratio; 3203 3204 if (min_pstate > cpu->max_perf_ratio) 3205 min_pstate = cpu->max_perf_ratio; 3206 3207 max_pstate = min(cap_pstate, cpu->max_perf_ratio); 3208 if (max_pstate < min_pstate) 3209 max_pstate = min_pstate; 3210 3211 target_pstate = clamp_t(int, target_pstate, min_pstate, max_pstate); 3212 3213 intel_cpufreq_hwp_update(cpu, min_pstate, max_pstate, target_pstate, true); 3214 3215 cpu->pstate.current_pstate = target_pstate; 3216 intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_FAST_SWITCH, old_pstate); 3217 } 3218 3219 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy) 3220 { 3221 struct freq_qos_request *req; 3222 struct cpudata *cpu; 3223 struct device *dev; 3224 int ret, freq; 3225 3226 dev = get_cpu_device(policy->cpu); 3227 if (!dev) 3228 return -ENODEV; 3229 3230 ret = __intel_pstate_cpu_init(policy); 3231 if (ret) 3232 return ret; 3233 3234 policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY; 3235 /* This reflects the intel_pstate_get_cpu_pstates() setting. */ 3236 policy->cur = policy->cpuinfo.min_freq; 3237 3238 req = kcalloc(2, sizeof(*req), GFP_KERNEL); 3239 if (!req) { 3240 ret = -ENOMEM; 3241 goto pstate_exit; 3242 } 3243 3244 cpu = all_cpu_data[policy->cpu]; 3245 3246 if (hwp_active) { 3247 u64 value; 3248 3249 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY_HWP; 3250 3251 intel_pstate_get_hwp_cap(cpu); 3252 3253 rdmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, &value); 3254 WRITE_ONCE(cpu->hwp_req_cached, value); 3255 3256 cpu->epp_cached = intel_pstate_get_epp(cpu, value); 3257 } else { 3258 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY; 3259 } 3260 3261 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.min_perf_pct, 100); 3262 3263 ret = freq_qos_add_request(&policy->constraints, req, FREQ_QOS_MIN, 3264 freq); 3265 if (ret < 0) { 3266 dev_err(dev, "Failed to add min-freq constraint (%d)\n", ret); 3267 goto free_req; 3268 } 3269 3270 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.max_perf_pct, 100); 3271 3272 ret = freq_qos_add_request(&policy->constraints, req + 1, FREQ_QOS_MAX, 3273 freq); 3274 if (ret < 0) { 3275 dev_err(dev, "Failed to add max-freq constraint (%d)\n", ret); 3276 goto remove_min_req; 3277 } 3278 3279 policy->driver_data = req; 3280 3281 return 0; 3282 3283 remove_min_req: 3284 freq_qos_remove_request(req); 3285 free_req: 3286 kfree(req); 3287 pstate_exit: 3288 intel_pstate_exit_perf_limits(policy); 3289 3290 return ret; 3291 } 3292 3293 static void intel_cpufreq_cpu_exit(struct cpufreq_policy *policy) 3294 { 3295 struct freq_qos_request *req; 3296 3297 req = policy->driver_data; 3298 3299 freq_qos_remove_request(req + 1); 3300 freq_qos_remove_request(req); 3301 kfree(req); 3302 3303 intel_pstate_cpu_exit(policy); 3304 } 3305 3306 static int intel_cpufreq_suspend(struct cpufreq_policy *policy) 3307 { 3308 intel_pstate_suspend(policy); 3309 3310 if (hwp_active) { 3311 struct cpudata *cpu = all_cpu_data[policy->cpu]; 3312 u64 value = READ_ONCE(cpu->hwp_req_cached); 3313 3314 /* 3315 * Clear the desired perf field in MSR_HWP_REQUEST in case 3316 * intel_cpufreq_adjust_perf() is in use and the last value 3317 * written by it may not be suitable. 3318 */ 3319 value &= ~HWP_DESIRED_PERF(~0L); 3320 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 3321 WRITE_ONCE(cpu->hwp_req_cached, value); 3322 } 3323 3324 return 0; 3325 } 3326 3327 static struct cpufreq_driver intel_cpufreq = { 3328 .flags = CPUFREQ_CONST_LOOPS, 3329 .verify = intel_cpufreq_verify_policy, 3330 .target = intel_cpufreq_target, 3331 .fast_switch = intel_cpufreq_fast_switch, 3332 .init = intel_cpufreq_cpu_init, 3333 .exit = intel_cpufreq_cpu_exit, 3334 .offline = intel_cpufreq_cpu_offline, 3335 .online = intel_pstate_cpu_online, 3336 .suspend = intel_cpufreq_suspend, 3337 .resume = intel_pstate_resume, 3338 .update_limits = intel_pstate_update_limits, 3339 .name = "intel_cpufreq", 3340 }; 3341 3342 static struct cpufreq_driver *default_driver; 3343 3344 static void intel_pstate_driver_cleanup(void) 3345 { 3346 unsigned int cpu; 3347 3348 cpus_read_lock(); 3349 for_each_online_cpu(cpu) { 3350 if (all_cpu_data[cpu]) { 3351 if (intel_pstate_driver == &intel_pstate) 3352 intel_pstate_clear_update_util_hook(cpu); 3353 3354 kfree(all_cpu_data[cpu]); 3355 WRITE_ONCE(all_cpu_data[cpu], NULL); 3356 } 3357 } 3358 cpus_read_unlock(); 3359 3360 intel_pstate_driver = NULL; 3361 } 3362 3363 static int intel_pstate_register_driver(struct cpufreq_driver *driver) 3364 { 3365 bool refresh_cpu_cap_scaling; 3366 int ret; 3367 3368 if (driver == &intel_pstate) 3369 intel_pstate_sysfs_expose_hwp_dynamic_boost(); 3370 3371 memset(&global, 0, sizeof(global)); 3372 global.max_perf_pct = 100; 3373 global.turbo_disabled = turbo_is_disabled(); 3374 global.no_turbo = global.turbo_disabled; 3375 3376 arch_set_max_freq_ratio(global.turbo_disabled); 3377 3378 refresh_cpu_cap_scaling = hybrid_clear_max_perf_cpu(); 3379 3380 intel_pstate_driver = driver; 3381 ret = cpufreq_register_driver(intel_pstate_driver); 3382 if (ret) { 3383 intel_pstate_driver_cleanup(); 3384 return ret; 3385 } 3386 3387 global.min_perf_pct = min_perf_pct_min(); 3388 3389 hybrid_init_cpu_capacity_scaling(refresh_cpu_cap_scaling); 3390 3391 return 0; 3392 } 3393 3394 static ssize_t intel_pstate_show_status(char *buf) 3395 { 3396 if (!intel_pstate_driver) 3397 return sprintf(buf, "off\n"); 3398 3399 return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ? 3400 "active" : "passive"); 3401 } 3402 3403 static int intel_pstate_update_status(const char *buf, size_t size) 3404 { 3405 if (size == 3 && !strncmp(buf, "off", size)) { 3406 if (!intel_pstate_driver) 3407 return -EINVAL; 3408 3409 if (hwp_active) 3410 return -EBUSY; 3411 3412 cpufreq_unregister_driver(intel_pstate_driver); 3413 intel_pstate_driver_cleanup(); 3414 return 0; 3415 } 3416 3417 if (size == 6 && !strncmp(buf, "active", size)) { 3418 if (intel_pstate_driver) { 3419 if (intel_pstate_driver == &intel_pstate) 3420 return 0; 3421 3422 cpufreq_unregister_driver(intel_pstate_driver); 3423 } 3424 3425 return intel_pstate_register_driver(&intel_pstate); 3426 } 3427 3428 if (size == 7 && !strncmp(buf, "passive", size)) { 3429 if (intel_pstate_driver) { 3430 if (intel_pstate_driver == &intel_cpufreq) 3431 return 0; 3432 3433 cpufreq_unregister_driver(intel_pstate_driver); 3434 intel_pstate_sysfs_hide_hwp_dynamic_boost(); 3435 } 3436 3437 return intel_pstate_register_driver(&intel_cpufreq); 3438 } 3439 3440 return -EINVAL; 3441 } 3442 3443 static int no_load __initdata; 3444 static int no_hwp __initdata; 3445 static int hwp_only __initdata; 3446 static unsigned int force_load __initdata; 3447 3448 static int __init intel_pstate_msrs_not_valid(void) 3449 { 3450 if (!pstate_funcs.get_max(0) || 3451 !pstate_funcs.get_min(0) || 3452 !pstate_funcs.get_turbo(0)) 3453 return -ENODEV; 3454 3455 return 0; 3456 } 3457 3458 static void __init copy_cpu_funcs(struct pstate_funcs *funcs) 3459 { 3460 pstate_funcs.get_max = funcs->get_max; 3461 pstate_funcs.get_max_physical = funcs->get_max_physical; 3462 pstate_funcs.get_min = funcs->get_min; 3463 pstate_funcs.get_turbo = funcs->get_turbo; 3464 pstate_funcs.get_scaling = funcs->get_scaling; 3465 pstate_funcs.get_val = funcs->get_val; 3466 pstate_funcs.get_vid = funcs->get_vid; 3467 pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift; 3468 } 3469 3470 #ifdef CONFIG_ACPI 3471 3472 static bool __init intel_pstate_no_acpi_pss(void) 3473 { 3474 int i; 3475 3476 for_each_possible_cpu(i) { 3477 acpi_status status; 3478 union acpi_object *pss; 3479 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; 3480 struct acpi_processor *pr = per_cpu(processors, i); 3481 3482 if (!pr) 3483 continue; 3484 3485 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer); 3486 if (ACPI_FAILURE(status)) 3487 continue; 3488 3489 pss = buffer.pointer; 3490 if (pss && pss->type == ACPI_TYPE_PACKAGE) { 3491 kfree(pss); 3492 return false; 3493 } 3494 3495 kfree(pss); 3496 } 3497 3498 pr_debug("ACPI _PSS not found\n"); 3499 return true; 3500 } 3501 3502 static bool __init intel_pstate_no_acpi_pcch(void) 3503 { 3504 acpi_status status; 3505 acpi_handle handle; 3506 3507 status = acpi_get_handle(NULL, "\\_SB", &handle); 3508 if (ACPI_FAILURE(status)) 3509 goto not_found; 3510 3511 if (acpi_has_method(handle, "PCCH")) 3512 return false; 3513 3514 not_found: 3515 pr_debug("ACPI PCCH not found\n"); 3516 return true; 3517 } 3518 3519 static bool __init intel_pstate_has_acpi_ppc(void) 3520 { 3521 int i; 3522 3523 for_each_possible_cpu(i) { 3524 struct acpi_processor *pr = per_cpu(processors, i); 3525 3526 if (!pr) 3527 continue; 3528 if (acpi_has_method(pr->handle, "_PPC")) 3529 return true; 3530 } 3531 pr_debug("ACPI _PPC not found\n"); 3532 return false; 3533 } 3534 3535 enum { 3536 PSS, 3537 PPC, 3538 }; 3539 3540 /* Hardware vendor-specific info that has its own power management modes */ 3541 static struct acpi_platform_list plat_info[] __initdata = { 3542 {"HP ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, NULL, PSS}, 3543 {"ORACLE", "X4-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3544 {"ORACLE", "X4-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3545 {"ORACLE", "X4-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3546 {"ORACLE", "X3-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3547 {"ORACLE", "X3-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3548 {"ORACLE", "X3-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3549 {"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3550 {"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3551 {"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3552 {"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3553 {"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3554 {"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3555 {"ORACLE", "X6-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3556 {"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3557 { } /* End */ 3558 }; 3559 3560 #define BITMASK_OOB (BIT(8) | BIT(18)) 3561 3562 static bool __init intel_pstate_platform_pwr_mgmt_exists(void) 3563 { 3564 const struct x86_cpu_id *id; 3565 u64 misc_pwr; 3566 int idx; 3567 3568 id = x86_match_cpu(intel_pstate_cpu_oob_ids); 3569 if (id) { 3570 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr); 3571 if (misc_pwr & BITMASK_OOB) { 3572 pr_debug("Bit 8 or 18 in the MISC_PWR_MGMT MSR set\n"); 3573 pr_debug("P states are controlled in Out of Band mode by the firmware/hardware\n"); 3574 return true; 3575 } 3576 } 3577 3578 idx = acpi_match_platform_list(plat_info); 3579 if (idx < 0) 3580 return false; 3581 3582 switch (plat_info[idx].data) { 3583 case PSS: 3584 if (!intel_pstate_no_acpi_pss()) 3585 return false; 3586 3587 return intel_pstate_no_acpi_pcch(); 3588 case PPC: 3589 return intel_pstate_has_acpi_ppc() && !force_load; 3590 } 3591 3592 return false; 3593 } 3594 3595 static void intel_pstate_request_control_from_smm(void) 3596 { 3597 /* 3598 * It may be unsafe to request P-states control from SMM if _PPC support 3599 * has not been enabled. 3600 */ 3601 if (acpi_ppc) 3602 acpi_processor_pstate_control(); 3603 } 3604 #else /* CONFIG_ACPI not enabled */ 3605 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; } 3606 static inline bool intel_pstate_has_acpi_ppc(void) { return false; } 3607 static inline void intel_pstate_request_control_from_smm(void) {} 3608 #endif /* CONFIG_ACPI */ 3609 3610 #define INTEL_PSTATE_HWP_BROADWELL 0x01 3611 3612 #define X86_MATCH_HWP(vfm, hwp_mode) \ 3613 X86_MATCH_VFM_FEATURE(vfm, X86_FEATURE_HWP, hwp_mode) 3614 3615 static const struct x86_cpu_id hwp_support_ids[] __initconst = { 3616 X86_MATCH_HWP(INTEL_BROADWELL_X, INTEL_PSTATE_HWP_BROADWELL), 3617 X86_MATCH_HWP(INTEL_BROADWELL_D, INTEL_PSTATE_HWP_BROADWELL), 3618 X86_MATCH_HWP(INTEL_ANY, 0), 3619 {} 3620 }; 3621 3622 static bool intel_pstate_hwp_is_enabled(void) 3623 { 3624 u64 value; 3625 3626 rdmsrl(MSR_PM_ENABLE, value); 3627 return !!(value & 0x1); 3628 } 3629 3630 #define POWERSAVE_MASK GENMASK(7, 0) 3631 #define BALANCE_POWER_MASK GENMASK(15, 8) 3632 #define BALANCE_PERFORMANCE_MASK GENMASK(23, 16) 3633 #define PERFORMANCE_MASK GENMASK(31, 24) 3634 3635 #define HWP_SET_EPP_VALUES(powersave, balance_power, balance_perf, performance) \ 3636 (FIELD_PREP_CONST(POWERSAVE_MASK, powersave) |\ 3637 FIELD_PREP_CONST(BALANCE_POWER_MASK, balance_power) |\ 3638 FIELD_PREP_CONST(BALANCE_PERFORMANCE_MASK, balance_perf) |\ 3639 FIELD_PREP_CONST(PERFORMANCE_MASK, performance)) 3640 3641 #define HWP_SET_DEF_BALANCE_PERF_EPP(balance_perf) \ 3642 (HWP_SET_EPP_VALUES(HWP_EPP_POWERSAVE, HWP_EPP_BALANCE_POWERSAVE,\ 3643 balance_perf, HWP_EPP_PERFORMANCE)) 3644 3645 static const struct x86_cpu_id intel_epp_default[] = { 3646 /* 3647 * Set EPP value as 102, this is the max suggested EPP 3648 * which can result in one core turbo frequency for 3649 * AlderLake Mobile CPUs. 3650 */ 3651 X86_MATCH_VFM(INTEL_ALDERLAKE_L, HWP_SET_DEF_BALANCE_PERF_EPP(102)), 3652 X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, HWP_SET_DEF_BALANCE_PERF_EPP(32)), 3653 X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, HWP_SET_DEF_BALANCE_PERF_EPP(32)), 3654 X86_MATCH_VFM(INTEL_GRANITERAPIDS_X, HWP_SET_DEF_BALANCE_PERF_EPP(32)), 3655 X86_MATCH_VFM(INTEL_GRANITERAPIDS_D, HWP_SET_DEF_BALANCE_PERF_EPP(32)), 3656 X86_MATCH_VFM(INTEL_METEORLAKE_L, HWP_SET_EPP_VALUES(HWP_EPP_POWERSAVE, 3657 179, 64, 16)), 3658 X86_MATCH_VFM(INTEL_ARROWLAKE, HWP_SET_EPP_VALUES(HWP_EPP_POWERSAVE, 3659 179, 64, 16)), 3660 {} 3661 }; 3662 3663 static const struct x86_cpu_id intel_hybrid_scaling_factor[] = { 3664 X86_MATCH_VFM(INTEL_ALDERLAKE, HYBRID_SCALING_FACTOR_ADL), 3665 X86_MATCH_VFM(INTEL_ALDERLAKE_L, HYBRID_SCALING_FACTOR_ADL), 3666 X86_MATCH_VFM(INTEL_RAPTORLAKE, HYBRID_SCALING_FACTOR_ADL), 3667 X86_MATCH_VFM(INTEL_RAPTORLAKE_P, HYBRID_SCALING_FACTOR_ADL), 3668 X86_MATCH_VFM(INTEL_RAPTORLAKE_S, HYBRID_SCALING_FACTOR_ADL), 3669 X86_MATCH_VFM(INTEL_METEORLAKE_L, HYBRID_SCALING_FACTOR_MTL), 3670 X86_MATCH_VFM(INTEL_LUNARLAKE_M, HYBRID_SCALING_FACTOR_LNL), 3671 {} 3672 }; 3673 3674 static int __init intel_pstate_init(void) 3675 { 3676 static struct cpudata **_all_cpu_data; 3677 const struct x86_cpu_id *id; 3678 int rc; 3679 3680 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) 3681 return -ENODEV; 3682 3683 id = x86_match_cpu(hwp_support_ids); 3684 if (id) { 3685 hwp_forced = intel_pstate_hwp_is_enabled(); 3686 3687 if (hwp_forced) 3688 pr_info("HWP enabled by BIOS\n"); 3689 else if (no_load) 3690 return -ENODEV; 3691 3692 copy_cpu_funcs(&core_funcs); 3693 /* 3694 * Avoid enabling HWP for processors without EPP support, 3695 * because that means incomplete HWP implementation which is a 3696 * corner case and supporting it is generally problematic. 3697 * 3698 * If HWP is enabled already, though, there is no choice but to 3699 * deal with it. 3700 */ 3701 if ((!no_hwp && boot_cpu_has(X86_FEATURE_HWP_EPP)) || hwp_forced) { 3702 hwp_active = true; 3703 hwp_mode_bdw = id->driver_data; 3704 intel_pstate.attr = hwp_cpufreq_attrs; 3705 intel_cpufreq.attr = hwp_cpufreq_attrs; 3706 intel_cpufreq.flags |= CPUFREQ_NEED_UPDATE_LIMITS; 3707 intel_cpufreq.adjust_perf = intel_cpufreq_adjust_perf; 3708 if (!default_driver) 3709 default_driver = &intel_pstate; 3710 3711 pstate_funcs.get_cpu_scaling = hwp_get_cpu_scaling; 3712 3713 goto hwp_cpu_matched; 3714 } 3715 pr_info("HWP not enabled\n"); 3716 } else { 3717 if (no_load) 3718 return -ENODEV; 3719 3720 id = x86_match_cpu(intel_pstate_cpu_ids); 3721 if (!id) { 3722 pr_info("CPU model not supported\n"); 3723 return -ENODEV; 3724 } 3725 3726 copy_cpu_funcs((struct pstate_funcs *)id->driver_data); 3727 } 3728 3729 if (intel_pstate_msrs_not_valid()) { 3730 pr_info("Invalid MSRs\n"); 3731 return -ENODEV; 3732 } 3733 /* Without HWP start in the passive mode. */ 3734 if (!default_driver) 3735 default_driver = &intel_cpufreq; 3736 3737 hwp_cpu_matched: 3738 /* 3739 * The Intel pstate driver will be ignored if the platform 3740 * firmware has its own power management modes. 3741 */ 3742 if (intel_pstate_platform_pwr_mgmt_exists()) { 3743 pr_info("P-states controlled by the platform\n"); 3744 return -ENODEV; 3745 } 3746 3747 if (!hwp_active && hwp_only) 3748 return -ENOTSUPP; 3749 3750 pr_info("Intel P-state driver initializing\n"); 3751 3752 _all_cpu_data = vzalloc(array_size(sizeof(void *), num_possible_cpus())); 3753 if (!_all_cpu_data) 3754 return -ENOMEM; 3755 3756 WRITE_ONCE(all_cpu_data, _all_cpu_data); 3757 3758 intel_pstate_request_control_from_smm(); 3759 3760 intel_pstate_sysfs_expose_params(); 3761 3762 if (hwp_active) { 3763 const struct x86_cpu_id *id = x86_match_cpu(intel_epp_default); 3764 const struct x86_cpu_id *hybrid_id = x86_match_cpu(intel_hybrid_scaling_factor); 3765 3766 if (id) { 3767 epp_values[EPP_INDEX_POWERSAVE] = 3768 FIELD_GET(POWERSAVE_MASK, id->driver_data); 3769 epp_values[EPP_INDEX_BALANCE_POWERSAVE] = 3770 FIELD_GET(BALANCE_POWER_MASK, id->driver_data); 3771 epp_values[EPP_INDEX_BALANCE_PERFORMANCE] = 3772 FIELD_GET(BALANCE_PERFORMANCE_MASK, id->driver_data); 3773 epp_values[EPP_INDEX_PERFORMANCE] = 3774 FIELD_GET(PERFORMANCE_MASK, id->driver_data); 3775 pr_debug("Updated EPPs powersave:%x balanced power:%x balanced perf:%x performance:%x\n", 3776 epp_values[EPP_INDEX_POWERSAVE], 3777 epp_values[EPP_INDEX_BALANCE_POWERSAVE], 3778 epp_values[EPP_INDEX_BALANCE_PERFORMANCE], 3779 epp_values[EPP_INDEX_PERFORMANCE]); 3780 } 3781 3782 if (hybrid_id) { 3783 hybrid_scaling_factor = hybrid_id->driver_data; 3784 pr_debug("hybrid scaling factor: %d\n", hybrid_scaling_factor); 3785 } 3786 3787 } 3788 3789 mutex_lock(&intel_pstate_driver_lock); 3790 rc = intel_pstate_register_driver(default_driver); 3791 mutex_unlock(&intel_pstate_driver_lock); 3792 if (rc) { 3793 intel_pstate_sysfs_remove(); 3794 return rc; 3795 } 3796 3797 if (hwp_active) { 3798 const struct x86_cpu_id *id; 3799 3800 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids); 3801 if (id) { 3802 set_power_ctl_ee_state(false); 3803 pr_info("Disabling energy efficiency optimization\n"); 3804 } 3805 3806 pr_info("HWP enabled\n"); 3807 } else if (boot_cpu_has(X86_FEATURE_HYBRID_CPU)) { 3808 pr_warn("Problematic setup: Hybrid processor with disabled HWP\n"); 3809 } 3810 3811 return 0; 3812 } 3813 device_initcall(intel_pstate_init); 3814 3815 static int __init intel_pstate_setup(char *str) 3816 { 3817 if (!str) 3818 return -EINVAL; 3819 3820 if (!strcmp(str, "disable")) 3821 no_load = 1; 3822 else if (!strcmp(str, "active")) 3823 default_driver = &intel_pstate; 3824 else if (!strcmp(str, "passive")) 3825 default_driver = &intel_cpufreq; 3826 3827 if (!strcmp(str, "no_hwp")) 3828 no_hwp = 1; 3829 3830 if (!strcmp(str, "force")) 3831 force_load = 1; 3832 if (!strcmp(str, "hwp_only")) 3833 hwp_only = 1; 3834 if (!strcmp(str, "per_cpu_perf_limits")) 3835 per_cpu_limits = true; 3836 3837 #ifdef CONFIG_ACPI 3838 if (!strcmp(str, "support_acpi_ppc")) 3839 acpi_ppc = true; 3840 #endif 3841 3842 return 0; 3843 } 3844 early_param("intel_pstate", intel_pstate_setup); 3845 3846 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>"); 3847 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors"); 3848