1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * intel_pstate.c: Native P state management for Intel processors 4 * 5 * (C) Copyright 2012 Intel Corporation 6 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com> 7 */ 8 9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10 11 #include <linux/kernel.h> 12 #include <linux/kernel_stat.h> 13 #include <linux/module.h> 14 #include <linux/ktime.h> 15 #include <linux/hrtimer.h> 16 #include <linux/tick.h> 17 #include <linux/slab.h> 18 #include <linux/sched/cpufreq.h> 19 #include <linux/list.h> 20 #include <linux/cpu.h> 21 #include <linux/cpufreq.h> 22 #include <linux/sysfs.h> 23 #include <linux/types.h> 24 #include <linux/fs.h> 25 #include <linux/acpi.h> 26 #include <linux/vmalloc.h> 27 #include <linux/pm_qos.h> 28 #include <linux/bitfield.h> 29 #include <trace/events/power.h> 30 31 #include <asm/cpu.h> 32 #include <asm/div64.h> 33 #include <asm/msr.h> 34 #include <asm/cpu_device_id.h> 35 #include <asm/cpufeature.h> 36 #include <asm/intel-family.h> 37 #include "../drivers/thermal/intel/thermal_interrupt.h" 38 39 #define INTEL_PSTATE_SAMPLING_INTERVAL (10 * NSEC_PER_MSEC) 40 41 #define INTEL_CPUFREQ_TRANSITION_LATENCY 20000 42 #define INTEL_CPUFREQ_TRANSITION_DELAY_HWP 5000 43 #define INTEL_CPUFREQ_TRANSITION_DELAY 500 44 45 #ifdef CONFIG_ACPI 46 #include <acpi/processor.h> 47 #include <acpi/cppc_acpi.h> 48 #endif 49 50 #define FRAC_BITS 8 51 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS) 52 #define fp_toint(X) ((X) >> FRAC_BITS) 53 54 #define ONE_EIGHTH_FP ((int64_t)1 << (FRAC_BITS - 3)) 55 56 #define EXT_BITS 6 57 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS) 58 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS) 59 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS) 60 61 static inline int32_t mul_fp(int32_t x, int32_t y) 62 { 63 return ((int64_t)x * (int64_t)y) >> FRAC_BITS; 64 } 65 66 static inline int32_t div_fp(s64 x, s64 y) 67 { 68 return div64_s64((int64_t)x << FRAC_BITS, y); 69 } 70 71 static inline int ceiling_fp(int32_t x) 72 { 73 int mask, ret; 74 75 ret = fp_toint(x); 76 mask = (1 << FRAC_BITS) - 1; 77 if (x & mask) 78 ret += 1; 79 return ret; 80 } 81 82 static inline u64 mul_ext_fp(u64 x, u64 y) 83 { 84 return (x * y) >> EXT_FRAC_BITS; 85 } 86 87 static inline u64 div_ext_fp(u64 x, u64 y) 88 { 89 return div64_u64(x << EXT_FRAC_BITS, y); 90 } 91 92 /** 93 * struct sample - Store performance sample 94 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average 95 * performance during last sample period 96 * @busy_scaled: Scaled busy value which is used to calculate next 97 * P state. This can be different than core_avg_perf 98 * to account for cpu idle period 99 * @aperf: Difference of actual performance frequency clock count 100 * read from APERF MSR between last and current sample 101 * @mperf: Difference of maximum performance frequency clock count 102 * read from MPERF MSR between last and current sample 103 * @tsc: Difference of time stamp counter between last and 104 * current sample 105 * @time: Current time from scheduler 106 * 107 * This structure is used in the cpudata structure to store performance sample 108 * data for choosing next P State. 109 */ 110 struct sample { 111 int32_t core_avg_perf; 112 int32_t busy_scaled; 113 u64 aperf; 114 u64 mperf; 115 u64 tsc; 116 u64 time; 117 }; 118 119 /** 120 * struct pstate_data - Store P state data 121 * @current_pstate: Current requested P state 122 * @min_pstate: Min P state possible for this platform 123 * @max_pstate: Max P state possible for this platform 124 * @max_pstate_physical:This is physical Max P state for a processor 125 * This can be higher than the max_pstate which can 126 * be limited by platform thermal design power limits 127 * @perf_ctl_scaling: PERF_CTL P-state to frequency scaling factor 128 * @scaling: Scaling factor between performance and frequency 129 * @turbo_pstate: Max Turbo P state possible for this platform 130 * @min_freq: @min_pstate frequency in cpufreq units 131 * @max_freq: @max_pstate frequency in cpufreq units 132 * @turbo_freq: @turbo_pstate frequency in cpufreq units 133 * 134 * Stores the per cpu model P state limits and current P state. 135 */ 136 struct pstate_data { 137 int current_pstate; 138 int min_pstate; 139 int max_pstate; 140 int max_pstate_physical; 141 int perf_ctl_scaling; 142 int scaling; 143 int turbo_pstate; 144 unsigned int min_freq; 145 unsigned int max_freq; 146 unsigned int turbo_freq; 147 }; 148 149 /** 150 * struct vid_data - Stores voltage information data 151 * @min: VID data for this platform corresponding to 152 * the lowest P state 153 * @max: VID data corresponding to the highest P State. 154 * @turbo: VID data for turbo P state 155 * @ratio: Ratio of (vid max - vid min) / 156 * (max P state - Min P State) 157 * 158 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling) 159 * This data is used in Atom platforms, where in addition to target P state, 160 * the voltage data needs to be specified to select next P State. 161 */ 162 struct vid_data { 163 int min; 164 int max; 165 int turbo; 166 int32_t ratio; 167 }; 168 169 /** 170 * struct global_params - Global parameters, mostly tunable via sysfs. 171 * @no_turbo: Whether or not to use turbo P-states. 172 * @turbo_disabled: Whether or not turbo P-states are available at all, 173 * based on the MSR_IA32_MISC_ENABLE value and whether or 174 * not the maximum reported turbo P-state is different from 175 * the maximum reported non-turbo one. 176 * @min_perf_pct: Minimum capacity limit in percent of the maximum turbo 177 * P-state capacity. 178 * @max_perf_pct: Maximum capacity limit in percent of the maximum turbo 179 * P-state capacity. 180 */ 181 struct global_params { 182 bool no_turbo; 183 bool turbo_disabled; 184 int max_perf_pct; 185 int min_perf_pct; 186 }; 187 188 /** 189 * struct cpudata - Per CPU instance data storage 190 * @cpu: CPU number for this instance data 191 * @policy: CPUFreq policy value 192 * @update_util: CPUFreq utility callback information 193 * @update_util_set: CPUFreq utility callback is set 194 * @iowait_boost: iowait-related boost fraction 195 * @last_update: Time of the last update. 196 * @pstate: Stores P state limits for this CPU 197 * @vid: Stores VID limits for this CPU 198 * @last_sample_time: Last Sample time 199 * @aperf_mperf_shift: APERF vs MPERF counting frequency difference 200 * @prev_aperf: Last APERF value read from APERF MSR 201 * @prev_mperf: Last MPERF value read from MPERF MSR 202 * @prev_tsc: Last timestamp counter (TSC) value 203 * @sample: Storage for storing last Sample data 204 * @min_perf_ratio: Minimum capacity in terms of PERF or HWP ratios 205 * @max_perf_ratio: Maximum capacity in terms of PERF or HWP ratios 206 * @acpi_perf_data: Stores ACPI perf information read from _PSS 207 * @valid_pss_table: Set to true for valid ACPI _PSS entries found 208 * @epp_powersave: Last saved HWP energy performance preference 209 * (EPP) or energy performance bias (EPB), 210 * when policy switched to performance 211 * @epp_policy: Last saved policy used to set EPP/EPB 212 * @epp_default: Power on default HWP energy performance 213 * preference/bias 214 * @epp_cached: Cached HWP energy-performance preference value 215 * @hwp_req_cached: Cached value of the last HWP Request MSR 216 * @hwp_cap_cached: Cached value of the last HWP Capabilities MSR 217 * @last_io_update: Last time when IO wake flag was set 218 * @sched_flags: Store scheduler flags for possible cross CPU update 219 * @hwp_boost_min: Last HWP boosted min performance 220 * @suspended: Whether or not the driver has been suspended. 221 * @hwp_notify_work: workqueue for HWP notifications. 222 * 223 * This structure stores per CPU instance data for all CPUs. 224 */ 225 struct cpudata { 226 int cpu; 227 228 unsigned int policy; 229 struct update_util_data update_util; 230 bool update_util_set; 231 232 struct pstate_data pstate; 233 struct vid_data vid; 234 235 u64 last_update; 236 u64 last_sample_time; 237 u64 aperf_mperf_shift; 238 u64 prev_aperf; 239 u64 prev_mperf; 240 u64 prev_tsc; 241 struct sample sample; 242 int32_t min_perf_ratio; 243 int32_t max_perf_ratio; 244 #ifdef CONFIG_ACPI 245 struct acpi_processor_performance acpi_perf_data; 246 bool valid_pss_table; 247 #endif 248 unsigned int iowait_boost; 249 s16 epp_powersave; 250 s16 epp_policy; 251 s16 epp_default; 252 s16 epp_cached; 253 u64 hwp_req_cached; 254 u64 hwp_cap_cached; 255 u64 last_io_update; 256 unsigned int sched_flags; 257 u32 hwp_boost_min; 258 bool suspended; 259 struct delayed_work hwp_notify_work; 260 }; 261 262 static struct cpudata **all_cpu_data; 263 264 /** 265 * struct pstate_funcs - Per CPU model specific callbacks 266 * @get_max: Callback to get maximum non turbo effective P state 267 * @get_max_physical: Callback to get maximum non turbo physical P state 268 * @get_min: Callback to get minimum P state 269 * @get_turbo: Callback to get turbo P state 270 * @get_scaling: Callback to get frequency scaling factor 271 * @get_cpu_scaling: Get frequency scaling factor for a given cpu 272 * @get_aperf_mperf_shift: Callback to get the APERF vs MPERF frequency difference 273 * @get_val: Callback to convert P state to actual MSR write value 274 * @get_vid: Callback to get VID data for Atom platforms 275 * 276 * Core and Atom CPU models have different way to get P State limits. This 277 * structure is used to store those callbacks. 278 */ 279 struct pstate_funcs { 280 int (*get_max)(int cpu); 281 int (*get_max_physical)(int cpu); 282 int (*get_min)(int cpu); 283 int (*get_turbo)(int cpu); 284 int (*get_scaling)(void); 285 int (*get_cpu_scaling)(int cpu); 286 int (*get_aperf_mperf_shift)(void); 287 u64 (*get_val)(struct cpudata*, int pstate); 288 void (*get_vid)(struct cpudata *); 289 }; 290 291 static struct pstate_funcs pstate_funcs __read_mostly; 292 293 static bool hwp_active __ro_after_init; 294 static int hwp_mode_bdw __ro_after_init; 295 static bool per_cpu_limits __ro_after_init; 296 static bool hwp_forced __ro_after_init; 297 static bool hwp_boost __read_mostly; 298 299 static struct cpufreq_driver *intel_pstate_driver __read_mostly; 300 301 #define HYBRID_SCALING_FACTOR 78741 302 #define HYBRID_SCALING_FACTOR_MTL 80000 303 304 static int hybrid_scaling_factor = HYBRID_SCALING_FACTOR; 305 306 static inline int core_get_scaling(void) 307 { 308 return 100000; 309 } 310 311 #ifdef CONFIG_ACPI 312 static bool acpi_ppc; 313 #endif 314 315 static struct global_params global; 316 317 static DEFINE_MUTEX(intel_pstate_driver_lock); 318 static DEFINE_MUTEX(intel_pstate_limits_lock); 319 320 #ifdef CONFIG_ACPI 321 322 static bool intel_pstate_acpi_pm_profile_server(void) 323 { 324 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER || 325 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER) 326 return true; 327 328 return false; 329 } 330 331 static bool intel_pstate_get_ppc_enable_status(void) 332 { 333 if (intel_pstate_acpi_pm_profile_server()) 334 return true; 335 336 return acpi_ppc; 337 } 338 339 #ifdef CONFIG_ACPI_CPPC_LIB 340 341 /* The work item is needed to avoid CPU hotplug locking issues */ 342 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work) 343 { 344 sched_set_itmt_support(); 345 } 346 347 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn); 348 349 #define CPPC_MAX_PERF U8_MAX 350 351 static void intel_pstate_set_itmt_prio(int cpu) 352 { 353 struct cppc_perf_caps cppc_perf; 354 static u32 max_highest_perf = 0, min_highest_perf = U32_MAX; 355 int ret; 356 357 ret = cppc_get_perf_caps(cpu, &cppc_perf); 358 /* 359 * If CPPC is not available, fall back to MSR_HWP_CAPABILITIES bits [8:0]. 360 * 361 * Also, on some systems with overclocking enabled, CPPC.highest_perf is 362 * hardcoded to 0xff, so CPPC.highest_perf cannot be used to enable ITMT. 363 * Fall back to MSR_HWP_CAPABILITIES then too. 364 */ 365 if (ret || cppc_perf.highest_perf == CPPC_MAX_PERF) 366 cppc_perf.highest_perf = HWP_HIGHEST_PERF(READ_ONCE(all_cpu_data[cpu]->hwp_cap_cached)); 367 368 /* 369 * The priorities can be set regardless of whether or not 370 * sched_set_itmt_support(true) has been called and it is valid to 371 * update them at any time after it has been called. 372 */ 373 sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu); 374 375 if (max_highest_perf <= min_highest_perf) { 376 if (cppc_perf.highest_perf > max_highest_perf) 377 max_highest_perf = cppc_perf.highest_perf; 378 379 if (cppc_perf.highest_perf < min_highest_perf) 380 min_highest_perf = cppc_perf.highest_perf; 381 382 if (max_highest_perf > min_highest_perf) { 383 /* 384 * This code can be run during CPU online under the 385 * CPU hotplug locks, so sched_set_itmt_support() 386 * cannot be called from here. Queue up a work item 387 * to invoke it. 388 */ 389 schedule_work(&sched_itmt_work); 390 } 391 } 392 } 393 394 static int intel_pstate_get_cppc_guaranteed(int cpu) 395 { 396 struct cppc_perf_caps cppc_perf; 397 int ret; 398 399 ret = cppc_get_perf_caps(cpu, &cppc_perf); 400 if (ret) 401 return ret; 402 403 if (cppc_perf.guaranteed_perf) 404 return cppc_perf.guaranteed_perf; 405 406 return cppc_perf.nominal_perf; 407 } 408 409 static int intel_pstate_cppc_get_scaling(int cpu) 410 { 411 struct cppc_perf_caps cppc_perf; 412 int ret; 413 414 ret = cppc_get_perf_caps(cpu, &cppc_perf); 415 416 /* 417 * If the nominal frequency and the nominal performance are not 418 * zero and the ratio between them is not 100, return the hybrid 419 * scaling factor. 420 */ 421 if (!ret && cppc_perf.nominal_perf && cppc_perf.nominal_freq && 422 cppc_perf.nominal_perf * 100 != cppc_perf.nominal_freq) 423 return hybrid_scaling_factor; 424 425 return core_get_scaling(); 426 } 427 428 #else /* CONFIG_ACPI_CPPC_LIB */ 429 static inline void intel_pstate_set_itmt_prio(int cpu) 430 { 431 } 432 #endif /* CONFIG_ACPI_CPPC_LIB */ 433 434 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) 435 { 436 struct cpudata *cpu; 437 int ret; 438 int i; 439 440 if (hwp_active) { 441 intel_pstate_set_itmt_prio(policy->cpu); 442 return; 443 } 444 445 if (!intel_pstate_get_ppc_enable_status()) 446 return; 447 448 cpu = all_cpu_data[policy->cpu]; 449 450 ret = acpi_processor_register_performance(&cpu->acpi_perf_data, 451 policy->cpu); 452 if (ret) 453 return; 454 455 /* 456 * Check if the control value in _PSS is for PERF_CTL MSR, which should 457 * guarantee that the states returned by it map to the states in our 458 * list directly. 459 */ 460 if (cpu->acpi_perf_data.control_register.space_id != 461 ACPI_ADR_SPACE_FIXED_HARDWARE) 462 goto err; 463 464 /* 465 * If there is only one entry _PSS, simply ignore _PSS and continue as 466 * usual without taking _PSS into account 467 */ 468 if (cpu->acpi_perf_data.state_count < 2) 469 goto err; 470 471 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu); 472 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) { 473 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n", 474 (i == cpu->acpi_perf_data.state ? '*' : ' '), i, 475 (u32) cpu->acpi_perf_data.states[i].core_frequency, 476 (u32) cpu->acpi_perf_data.states[i].power, 477 (u32) cpu->acpi_perf_data.states[i].control); 478 } 479 480 cpu->valid_pss_table = true; 481 pr_debug("_PPC limits will be enforced\n"); 482 483 return; 484 485 err: 486 cpu->valid_pss_table = false; 487 acpi_processor_unregister_performance(policy->cpu); 488 } 489 490 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) 491 { 492 struct cpudata *cpu; 493 494 cpu = all_cpu_data[policy->cpu]; 495 if (!cpu->valid_pss_table) 496 return; 497 498 acpi_processor_unregister_performance(policy->cpu); 499 } 500 #else /* CONFIG_ACPI */ 501 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) 502 { 503 } 504 505 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) 506 { 507 } 508 509 static inline bool intel_pstate_acpi_pm_profile_server(void) 510 { 511 return false; 512 } 513 #endif /* CONFIG_ACPI */ 514 515 #ifndef CONFIG_ACPI_CPPC_LIB 516 static inline int intel_pstate_get_cppc_guaranteed(int cpu) 517 { 518 return -ENOTSUPP; 519 } 520 521 static int intel_pstate_cppc_get_scaling(int cpu) 522 { 523 return core_get_scaling(); 524 } 525 #endif /* CONFIG_ACPI_CPPC_LIB */ 526 527 static int intel_pstate_freq_to_hwp_rel(struct cpudata *cpu, int freq, 528 unsigned int relation) 529 { 530 if (freq == cpu->pstate.turbo_freq) 531 return cpu->pstate.turbo_pstate; 532 533 if (freq == cpu->pstate.max_freq) 534 return cpu->pstate.max_pstate; 535 536 switch (relation) { 537 case CPUFREQ_RELATION_H: 538 return freq / cpu->pstate.scaling; 539 case CPUFREQ_RELATION_C: 540 return DIV_ROUND_CLOSEST(freq, cpu->pstate.scaling); 541 } 542 543 return DIV_ROUND_UP(freq, cpu->pstate.scaling); 544 } 545 546 static int intel_pstate_freq_to_hwp(struct cpudata *cpu, int freq) 547 { 548 return intel_pstate_freq_to_hwp_rel(cpu, freq, CPUFREQ_RELATION_L); 549 } 550 551 /** 552 * intel_pstate_hybrid_hwp_adjust - Calibrate HWP performance levels. 553 * @cpu: Target CPU. 554 * 555 * On hybrid processors, HWP may expose more performance levels than there are 556 * P-states accessible through the PERF_CTL interface. If that happens, the 557 * scaling factor between HWP performance levels and CPU frequency will be less 558 * than the scaling factor between P-state values and CPU frequency. 559 * 560 * In that case, adjust the CPU parameters used in computations accordingly. 561 */ 562 static void intel_pstate_hybrid_hwp_adjust(struct cpudata *cpu) 563 { 564 int perf_ctl_max_phys = cpu->pstate.max_pstate_physical; 565 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling; 566 int perf_ctl_turbo = pstate_funcs.get_turbo(cpu->cpu); 567 int scaling = cpu->pstate.scaling; 568 int freq; 569 570 pr_debug("CPU%d: perf_ctl_max_phys = %d\n", cpu->cpu, perf_ctl_max_phys); 571 pr_debug("CPU%d: perf_ctl_turbo = %d\n", cpu->cpu, perf_ctl_turbo); 572 pr_debug("CPU%d: perf_ctl_scaling = %d\n", cpu->cpu, perf_ctl_scaling); 573 pr_debug("CPU%d: HWP_CAP guaranteed = %d\n", cpu->cpu, cpu->pstate.max_pstate); 574 pr_debug("CPU%d: HWP_CAP highest = %d\n", cpu->cpu, cpu->pstate.turbo_pstate); 575 pr_debug("CPU%d: HWP-to-frequency scaling factor: %d\n", cpu->cpu, scaling); 576 577 cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_pstate * scaling, 578 perf_ctl_scaling); 579 cpu->pstate.max_freq = rounddown(cpu->pstate.max_pstate * scaling, 580 perf_ctl_scaling); 581 582 freq = perf_ctl_max_phys * perf_ctl_scaling; 583 cpu->pstate.max_pstate_physical = intel_pstate_freq_to_hwp(cpu, freq); 584 585 freq = cpu->pstate.min_pstate * perf_ctl_scaling; 586 cpu->pstate.min_freq = freq; 587 /* 588 * Cast the min P-state value retrieved via pstate_funcs.get_min() to 589 * the effective range of HWP performance levels. 590 */ 591 cpu->pstate.min_pstate = intel_pstate_freq_to_hwp(cpu, freq); 592 } 593 594 static bool turbo_is_disabled(void) 595 { 596 u64 misc_en; 597 598 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en); 599 600 return !!(misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE); 601 } 602 603 static int min_perf_pct_min(void) 604 { 605 struct cpudata *cpu = all_cpu_data[0]; 606 int turbo_pstate = cpu->pstate.turbo_pstate; 607 608 return turbo_pstate ? 609 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0; 610 } 611 612 static s16 intel_pstate_get_epb(struct cpudata *cpu_data) 613 { 614 u64 epb; 615 int ret; 616 617 if (!boot_cpu_has(X86_FEATURE_EPB)) 618 return -ENXIO; 619 620 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb); 621 if (ret) 622 return (s16)ret; 623 624 return (s16)(epb & 0x0f); 625 } 626 627 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data) 628 { 629 s16 epp; 630 631 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 632 /* 633 * When hwp_req_data is 0, means that caller didn't read 634 * MSR_HWP_REQUEST, so need to read and get EPP. 635 */ 636 if (!hwp_req_data) { 637 epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, 638 &hwp_req_data); 639 if (epp) 640 return epp; 641 } 642 epp = (hwp_req_data >> 24) & 0xff; 643 } else { 644 /* When there is no EPP present, HWP uses EPB settings */ 645 epp = intel_pstate_get_epb(cpu_data); 646 } 647 648 return epp; 649 } 650 651 static int intel_pstate_set_epb(int cpu, s16 pref) 652 { 653 u64 epb; 654 int ret; 655 656 if (!boot_cpu_has(X86_FEATURE_EPB)) 657 return -ENXIO; 658 659 ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb); 660 if (ret) 661 return ret; 662 663 epb = (epb & ~0x0f) | pref; 664 wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb); 665 666 return 0; 667 } 668 669 /* 670 * EPP/EPB display strings corresponding to EPP index in the 671 * energy_perf_strings[] 672 * index String 673 *------------------------------------- 674 * 0 default 675 * 1 performance 676 * 2 balance_performance 677 * 3 balance_power 678 * 4 power 679 */ 680 681 enum energy_perf_value_index { 682 EPP_INDEX_DEFAULT = 0, 683 EPP_INDEX_PERFORMANCE, 684 EPP_INDEX_BALANCE_PERFORMANCE, 685 EPP_INDEX_BALANCE_POWERSAVE, 686 EPP_INDEX_POWERSAVE, 687 }; 688 689 static const char * const energy_perf_strings[] = { 690 [EPP_INDEX_DEFAULT] = "default", 691 [EPP_INDEX_PERFORMANCE] = "performance", 692 [EPP_INDEX_BALANCE_PERFORMANCE] = "balance_performance", 693 [EPP_INDEX_BALANCE_POWERSAVE] = "balance_power", 694 [EPP_INDEX_POWERSAVE] = "power", 695 NULL 696 }; 697 static unsigned int epp_values[] = { 698 [EPP_INDEX_DEFAULT] = 0, /* Unused index */ 699 [EPP_INDEX_PERFORMANCE] = HWP_EPP_PERFORMANCE, 700 [EPP_INDEX_BALANCE_PERFORMANCE] = HWP_EPP_BALANCE_PERFORMANCE, 701 [EPP_INDEX_BALANCE_POWERSAVE] = HWP_EPP_BALANCE_POWERSAVE, 702 [EPP_INDEX_POWERSAVE] = HWP_EPP_POWERSAVE, 703 }; 704 705 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data, int *raw_epp) 706 { 707 s16 epp; 708 int index = -EINVAL; 709 710 *raw_epp = 0; 711 epp = intel_pstate_get_epp(cpu_data, 0); 712 if (epp < 0) 713 return epp; 714 715 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 716 if (epp == epp_values[EPP_INDEX_PERFORMANCE]) 717 return EPP_INDEX_PERFORMANCE; 718 if (epp == epp_values[EPP_INDEX_BALANCE_PERFORMANCE]) 719 return EPP_INDEX_BALANCE_PERFORMANCE; 720 if (epp == epp_values[EPP_INDEX_BALANCE_POWERSAVE]) 721 return EPP_INDEX_BALANCE_POWERSAVE; 722 if (epp == epp_values[EPP_INDEX_POWERSAVE]) 723 return EPP_INDEX_POWERSAVE; 724 *raw_epp = epp; 725 return 0; 726 } else if (boot_cpu_has(X86_FEATURE_EPB)) { 727 /* 728 * Range: 729 * 0x00-0x03 : Performance 730 * 0x04-0x07 : Balance performance 731 * 0x08-0x0B : Balance power 732 * 0x0C-0x0F : Power 733 * The EPB is a 4 bit value, but our ranges restrict the 734 * value which can be set. Here only using top two bits 735 * effectively. 736 */ 737 index = (epp >> 2) + 1; 738 } 739 740 return index; 741 } 742 743 static int intel_pstate_set_epp(struct cpudata *cpu, u32 epp) 744 { 745 int ret; 746 747 /* 748 * Use the cached HWP Request MSR value, because in the active mode the 749 * register itself may be updated by intel_pstate_hwp_boost_up() or 750 * intel_pstate_hwp_boost_down() at any time. 751 */ 752 u64 value = READ_ONCE(cpu->hwp_req_cached); 753 754 value &= ~GENMASK_ULL(31, 24); 755 value |= (u64)epp << 24; 756 /* 757 * The only other updater of hwp_req_cached in the active mode, 758 * intel_pstate_hwp_set(), is called under the same lock as this 759 * function, so it cannot run in parallel with the update below. 760 */ 761 WRITE_ONCE(cpu->hwp_req_cached, value); 762 ret = wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 763 if (!ret) 764 cpu->epp_cached = epp; 765 766 return ret; 767 } 768 769 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data, 770 int pref_index, bool use_raw, 771 u32 raw_epp) 772 { 773 int epp = -EINVAL; 774 int ret; 775 776 if (!pref_index) 777 epp = cpu_data->epp_default; 778 779 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 780 if (use_raw) 781 epp = raw_epp; 782 else if (epp == -EINVAL) 783 epp = epp_values[pref_index]; 784 785 /* 786 * To avoid confusion, refuse to set EPP to any values different 787 * from 0 (performance) if the current policy is "performance", 788 * because those values would be overridden. 789 */ 790 if (epp > 0 && cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) 791 return -EBUSY; 792 793 ret = intel_pstate_set_epp(cpu_data, epp); 794 } else { 795 if (epp == -EINVAL) 796 epp = (pref_index - 1) << 2; 797 ret = intel_pstate_set_epb(cpu_data->cpu, epp); 798 } 799 800 return ret; 801 } 802 803 static ssize_t show_energy_performance_available_preferences( 804 struct cpufreq_policy *policy, char *buf) 805 { 806 int i = 0; 807 int ret = 0; 808 809 while (energy_perf_strings[i] != NULL) 810 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]); 811 812 ret += sprintf(&buf[ret], "\n"); 813 814 return ret; 815 } 816 817 cpufreq_freq_attr_ro(energy_performance_available_preferences); 818 819 static struct cpufreq_driver intel_pstate; 820 821 static ssize_t store_energy_performance_preference( 822 struct cpufreq_policy *policy, const char *buf, size_t count) 823 { 824 struct cpudata *cpu = all_cpu_data[policy->cpu]; 825 char str_preference[21]; 826 bool raw = false; 827 ssize_t ret; 828 u32 epp = 0; 829 830 ret = sscanf(buf, "%20s", str_preference); 831 if (ret != 1) 832 return -EINVAL; 833 834 ret = match_string(energy_perf_strings, -1, str_preference); 835 if (ret < 0) { 836 if (!boot_cpu_has(X86_FEATURE_HWP_EPP)) 837 return ret; 838 839 ret = kstrtouint(buf, 10, &epp); 840 if (ret) 841 return ret; 842 843 if (epp > 255) 844 return -EINVAL; 845 846 raw = true; 847 } 848 849 /* 850 * This function runs with the policy R/W semaphore held, which 851 * guarantees that the driver pointer will not change while it is 852 * running. 853 */ 854 if (!intel_pstate_driver) 855 return -EAGAIN; 856 857 mutex_lock(&intel_pstate_limits_lock); 858 859 if (intel_pstate_driver == &intel_pstate) { 860 ret = intel_pstate_set_energy_pref_index(cpu, ret, raw, epp); 861 } else { 862 /* 863 * In the passive mode the governor needs to be stopped on the 864 * target CPU before the EPP update and restarted after it, 865 * which is super-heavy-weight, so make sure it is worth doing 866 * upfront. 867 */ 868 if (!raw) 869 epp = ret ? epp_values[ret] : cpu->epp_default; 870 871 if (cpu->epp_cached != epp) { 872 int err; 873 874 cpufreq_stop_governor(policy); 875 ret = intel_pstate_set_epp(cpu, epp); 876 err = cpufreq_start_governor(policy); 877 if (!ret) 878 ret = err; 879 } else { 880 ret = 0; 881 } 882 } 883 884 mutex_unlock(&intel_pstate_limits_lock); 885 886 return ret ?: count; 887 } 888 889 static ssize_t show_energy_performance_preference( 890 struct cpufreq_policy *policy, char *buf) 891 { 892 struct cpudata *cpu_data = all_cpu_data[policy->cpu]; 893 int preference, raw_epp; 894 895 preference = intel_pstate_get_energy_pref_index(cpu_data, &raw_epp); 896 if (preference < 0) 897 return preference; 898 899 if (raw_epp) 900 return sprintf(buf, "%d\n", raw_epp); 901 else 902 return sprintf(buf, "%s\n", energy_perf_strings[preference]); 903 } 904 905 cpufreq_freq_attr_rw(energy_performance_preference); 906 907 static ssize_t show_base_frequency(struct cpufreq_policy *policy, char *buf) 908 { 909 struct cpudata *cpu = all_cpu_data[policy->cpu]; 910 int ratio, freq; 911 912 ratio = intel_pstate_get_cppc_guaranteed(policy->cpu); 913 if (ratio <= 0) { 914 u64 cap; 915 916 rdmsrl_on_cpu(policy->cpu, MSR_HWP_CAPABILITIES, &cap); 917 ratio = HWP_GUARANTEED_PERF(cap); 918 } 919 920 freq = ratio * cpu->pstate.scaling; 921 if (cpu->pstate.scaling != cpu->pstate.perf_ctl_scaling) 922 freq = rounddown(freq, cpu->pstate.perf_ctl_scaling); 923 924 return sprintf(buf, "%d\n", freq); 925 } 926 927 cpufreq_freq_attr_ro(base_frequency); 928 929 static struct freq_attr *hwp_cpufreq_attrs[] = { 930 &energy_performance_preference, 931 &energy_performance_available_preferences, 932 &base_frequency, 933 NULL, 934 }; 935 936 static void __intel_pstate_get_hwp_cap(struct cpudata *cpu) 937 { 938 u64 cap; 939 940 rdmsrl_on_cpu(cpu->cpu, MSR_HWP_CAPABILITIES, &cap); 941 WRITE_ONCE(cpu->hwp_cap_cached, cap); 942 cpu->pstate.max_pstate = HWP_GUARANTEED_PERF(cap); 943 cpu->pstate.turbo_pstate = HWP_HIGHEST_PERF(cap); 944 } 945 946 static void intel_pstate_get_hwp_cap(struct cpudata *cpu) 947 { 948 int scaling = cpu->pstate.scaling; 949 950 __intel_pstate_get_hwp_cap(cpu); 951 952 cpu->pstate.max_freq = cpu->pstate.max_pstate * scaling; 953 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * scaling; 954 if (scaling != cpu->pstate.perf_ctl_scaling) { 955 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling; 956 957 cpu->pstate.max_freq = rounddown(cpu->pstate.max_freq, 958 perf_ctl_scaling); 959 cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_freq, 960 perf_ctl_scaling); 961 } 962 } 963 964 static void intel_pstate_hwp_set(unsigned int cpu) 965 { 966 struct cpudata *cpu_data = all_cpu_data[cpu]; 967 int max, min; 968 u64 value; 969 s16 epp; 970 971 max = cpu_data->max_perf_ratio; 972 min = cpu_data->min_perf_ratio; 973 974 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) 975 min = max; 976 977 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value); 978 979 value &= ~HWP_MIN_PERF(~0L); 980 value |= HWP_MIN_PERF(min); 981 982 value &= ~HWP_MAX_PERF(~0L); 983 value |= HWP_MAX_PERF(max); 984 985 if (cpu_data->epp_policy == cpu_data->policy) 986 goto skip_epp; 987 988 cpu_data->epp_policy = cpu_data->policy; 989 990 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) { 991 epp = intel_pstate_get_epp(cpu_data, value); 992 cpu_data->epp_powersave = epp; 993 /* If EPP read was failed, then don't try to write */ 994 if (epp < 0) 995 goto skip_epp; 996 997 epp = 0; 998 } else { 999 /* skip setting EPP, when saved value is invalid */ 1000 if (cpu_data->epp_powersave < 0) 1001 goto skip_epp; 1002 1003 /* 1004 * No need to restore EPP when it is not zero. This 1005 * means: 1006 * - Policy is not changed 1007 * - user has manually changed 1008 * - Error reading EPB 1009 */ 1010 epp = intel_pstate_get_epp(cpu_data, value); 1011 if (epp) 1012 goto skip_epp; 1013 1014 epp = cpu_data->epp_powersave; 1015 } 1016 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 1017 value &= ~GENMASK_ULL(31, 24); 1018 value |= (u64)epp << 24; 1019 } else { 1020 intel_pstate_set_epb(cpu, epp); 1021 } 1022 skip_epp: 1023 WRITE_ONCE(cpu_data->hwp_req_cached, value); 1024 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value); 1025 } 1026 1027 static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata); 1028 1029 static void intel_pstate_hwp_offline(struct cpudata *cpu) 1030 { 1031 u64 value = READ_ONCE(cpu->hwp_req_cached); 1032 int min_perf; 1033 1034 intel_pstate_disable_hwp_interrupt(cpu); 1035 1036 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 1037 /* 1038 * In case the EPP has been set to "performance" by the 1039 * active mode "performance" scaling algorithm, replace that 1040 * temporary value with the cached EPP one. 1041 */ 1042 value &= ~GENMASK_ULL(31, 24); 1043 value |= HWP_ENERGY_PERF_PREFERENCE(cpu->epp_cached); 1044 /* 1045 * However, make sure that EPP will be set to "performance" when 1046 * the CPU is brought back online again and the "performance" 1047 * scaling algorithm is still in effect. 1048 */ 1049 cpu->epp_policy = CPUFREQ_POLICY_UNKNOWN; 1050 } 1051 1052 /* 1053 * Clear the desired perf field in the cached HWP request value to 1054 * prevent nonzero desired values from being leaked into the active 1055 * mode. 1056 */ 1057 value &= ~HWP_DESIRED_PERF(~0L); 1058 WRITE_ONCE(cpu->hwp_req_cached, value); 1059 1060 value &= ~GENMASK_ULL(31, 0); 1061 min_perf = HWP_LOWEST_PERF(READ_ONCE(cpu->hwp_cap_cached)); 1062 1063 /* Set hwp_max = hwp_min */ 1064 value |= HWP_MAX_PERF(min_perf); 1065 value |= HWP_MIN_PERF(min_perf); 1066 1067 /* Set EPP to min */ 1068 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) 1069 value |= HWP_ENERGY_PERF_PREFERENCE(HWP_EPP_POWERSAVE); 1070 1071 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 1072 } 1073 1074 #define POWER_CTL_EE_ENABLE 1 1075 #define POWER_CTL_EE_DISABLE 2 1076 1077 static int power_ctl_ee_state; 1078 1079 static void set_power_ctl_ee_state(bool input) 1080 { 1081 u64 power_ctl; 1082 1083 mutex_lock(&intel_pstate_driver_lock); 1084 rdmsrl(MSR_IA32_POWER_CTL, power_ctl); 1085 if (input) { 1086 power_ctl &= ~BIT(MSR_IA32_POWER_CTL_BIT_EE); 1087 power_ctl_ee_state = POWER_CTL_EE_ENABLE; 1088 } else { 1089 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE); 1090 power_ctl_ee_state = POWER_CTL_EE_DISABLE; 1091 } 1092 wrmsrl(MSR_IA32_POWER_CTL, power_ctl); 1093 mutex_unlock(&intel_pstate_driver_lock); 1094 } 1095 1096 static void intel_pstate_hwp_enable(struct cpudata *cpudata); 1097 1098 static void intel_pstate_hwp_reenable(struct cpudata *cpu) 1099 { 1100 intel_pstate_hwp_enable(cpu); 1101 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, READ_ONCE(cpu->hwp_req_cached)); 1102 } 1103 1104 static int intel_pstate_suspend(struct cpufreq_policy *policy) 1105 { 1106 struct cpudata *cpu = all_cpu_data[policy->cpu]; 1107 1108 pr_debug("CPU %d suspending\n", cpu->cpu); 1109 1110 cpu->suspended = true; 1111 1112 /* disable HWP interrupt and cancel any pending work */ 1113 intel_pstate_disable_hwp_interrupt(cpu); 1114 1115 return 0; 1116 } 1117 1118 static int intel_pstate_resume(struct cpufreq_policy *policy) 1119 { 1120 struct cpudata *cpu = all_cpu_data[policy->cpu]; 1121 1122 pr_debug("CPU %d resuming\n", cpu->cpu); 1123 1124 /* Only restore if the system default is changed */ 1125 if (power_ctl_ee_state == POWER_CTL_EE_ENABLE) 1126 set_power_ctl_ee_state(true); 1127 else if (power_ctl_ee_state == POWER_CTL_EE_DISABLE) 1128 set_power_ctl_ee_state(false); 1129 1130 if (cpu->suspended && hwp_active) { 1131 mutex_lock(&intel_pstate_limits_lock); 1132 1133 /* Re-enable HWP, because "online" has not done that. */ 1134 intel_pstate_hwp_reenable(cpu); 1135 1136 mutex_unlock(&intel_pstate_limits_lock); 1137 } 1138 1139 cpu->suspended = false; 1140 1141 return 0; 1142 } 1143 1144 static void intel_pstate_update_policies(void) 1145 { 1146 int cpu; 1147 1148 for_each_possible_cpu(cpu) 1149 cpufreq_update_policy(cpu); 1150 } 1151 1152 static void __intel_pstate_update_max_freq(struct cpudata *cpudata, 1153 struct cpufreq_policy *policy) 1154 { 1155 if (hwp_active) 1156 intel_pstate_get_hwp_cap(cpudata); 1157 1158 policy->cpuinfo.max_freq = READ_ONCE(global.no_turbo) ? 1159 cpudata->pstate.max_freq : cpudata->pstate.turbo_freq; 1160 1161 refresh_frequency_limits(policy); 1162 } 1163 1164 static void intel_pstate_update_limits(unsigned int cpu) 1165 { 1166 struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpu); 1167 1168 if (!policy) 1169 return; 1170 1171 __intel_pstate_update_max_freq(all_cpu_data[cpu], policy); 1172 1173 cpufreq_cpu_release(policy); 1174 } 1175 1176 static void intel_pstate_update_limits_for_all(void) 1177 { 1178 int cpu; 1179 1180 for_each_possible_cpu(cpu) 1181 intel_pstate_update_limits(cpu); 1182 } 1183 1184 /************************** sysfs begin ************************/ 1185 #define show_one(file_name, object) \ 1186 static ssize_t show_##file_name \ 1187 (struct kobject *kobj, struct kobj_attribute *attr, char *buf) \ 1188 { \ 1189 return sprintf(buf, "%u\n", global.object); \ 1190 } 1191 1192 static ssize_t intel_pstate_show_status(char *buf); 1193 static int intel_pstate_update_status(const char *buf, size_t size); 1194 1195 static ssize_t show_status(struct kobject *kobj, 1196 struct kobj_attribute *attr, char *buf) 1197 { 1198 ssize_t ret; 1199 1200 mutex_lock(&intel_pstate_driver_lock); 1201 ret = intel_pstate_show_status(buf); 1202 mutex_unlock(&intel_pstate_driver_lock); 1203 1204 return ret; 1205 } 1206 1207 static ssize_t store_status(struct kobject *a, struct kobj_attribute *b, 1208 const char *buf, size_t count) 1209 { 1210 char *p = memchr(buf, '\n', count); 1211 int ret; 1212 1213 mutex_lock(&intel_pstate_driver_lock); 1214 ret = intel_pstate_update_status(buf, p ? p - buf : count); 1215 mutex_unlock(&intel_pstate_driver_lock); 1216 1217 return ret < 0 ? ret : count; 1218 } 1219 1220 static ssize_t show_turbo_pct(struct kobject *kobj, 1221 struct kobj_attribute *attr, char *buf) 1222 { 1223 struct cpudata *cpu; 1224 int total, no_turbo, turbo_pct; 1225 uint32_t turbo_fp; 1226 1227 mutex_lock(&intel_pstate_driver_lock); 1228 1229 if (!intel_pstate_driver) { 1230 mutex_unlock(&intel_pstate_driver_lock); 1231 return -EAGAIN; 1232 } 1233 1234 cpu = all_cpu_data[0]; 1235 1236 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; 1237 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1; 1238 turbo_fp = div_fp(no_turbo, total); 1239 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100))); 1240 1241 mutex_unlock(&intel_pstate_driver_lock); 1242 1243 return sprintf(buf, "%u\n", turbo_pct); 1244 } 1245 1246 static ssize_t show_num_pstates(struct kobject *kobj, 1247 struct kobj_attribute *attr, char *buf) 1248 { 1249 struct cpudata *cpu; 1250 int total; 1251 1252 mutex_lock(&intel_pstate_driver_lock); 1253 1254 if (!intel_pstate_driver) { 1255 mutex_unlock(&intel_pstate_driver_lock); 1256 return -EAGAIN; 1257 } 1258 1259 cpu = all_cpu_data[0]; 1260 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; 1261 1262 mutex_unlock(&intel_pstate_driver_lock); 1263 1264 return sprintf(buf, "%u\n", total); 1265 } 1266 1267 static ssize_t show_no_turbo(struct kobject *kobj, 1268 struct kobj_attribute *attr, char *buf) 1269 { 1270 ssize_t ret; 1271 1272 mutex_lock(&intel_pstate_driver_lock); 1273 1274 if (!intel_pstate_driver) { 1275 mutex_unlock(&intel_pstate_driver_lock); 1276 return -EAGAIN; 1277 } 1278 1279 ret = sprintf(buf, "%u\n", global.no_turbo); 1280 1281 mutex_unlock(&intel_pstate_driver_lock); 1282 1283 return ret; 1284 } 1285 1286 static ssize_t store_no_turbo(struct kobject *a, struct kobj_attribute *b, 1287 const char *buf, size_t count) 1288 { 1289 unsigned int input; 1290 bool no_turbo; 1291 1292 if (sscanf(buf, "%u", &input) != 1) 1293 return -EINVAL; 1294 1295 mutex_lock(&intel_pstate_driver_lock); 1296 1297 if (!intel_pstate_driver) { 1298 count = -EAGAIN; 1299 goto unlock_driver; 1300 } 1301 1302 no_turbo = !!clamp_t(int, input, 0, 1); 1303 1304 WRITE_ONCE(global.turbo_disabled, turbo_is_disabled()); 1305 if (global.turbo_disabled && !no_turbo) { 1306 pr_notice("Turbo disabled by BIOS or unavailable on processor\n"); 1307 count = -EPERM; 1308 if (global.no_turbo) 1309 goto unlock_driver; 1310 else 1311 no_turbo = 1; 1312 } 1313 1314 if (no_turbo == global.no_turbo) { 1315 goto unlock_driver; 1316 } 1317 1318 WRITE_ONCE(global.no_turbo, no_turbo); 1319 1320 mutex_lock(&intel_pstate_limits_lock); 1321 1322 if (no_turbo) { 1323 struct cpudata *cpu = all_cpu_data[0]; 1324 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate; 1325 1326 /* Squash the global minimum into the permitted range. */ 1327 if (global.min_perf_pct > pct) 1328 global.min_perf_pct = pct; 1329 } 1330 1331 mutex_unlock(&intel_pstate_limits_lock); 1332 1333 intel_pstate_update_limits_for_all(); 1334 arch_set_max_freq_ratio(no_turbo); 1335 1336 unlock_driver: 1337 mutex_unlock(&intel_pstate_driver_lock); 1338 1339 return count; 1340 } 1341 1342 static void update_qos_request(enum freq_qos_req_type type) 1343 { 1344 struct freq_qos_request *req; 1345 struct cpufreq_policy *policy; 1346 int i; 1347 1348 for_each_possible_cpu(i) { 1349 struct cpudata *cpu = all_cpu_data[i]; 1350 unsigned int freq, perf_pct; 1351 1352 policy = cpufreq_cpu_get(i); 1353 if (!policy) 1354 continue; 1355 1356 req = policy->driver_data; 1357 cpufreq_cpu_put(policy); 1358 1359 if (!req) 1360 continue; 1361 1362 if (hwp_active) 1363 intel_pstate_get_hwp_cap(cpu); 1364 1365 if (type == FREQ_QOS_MIN) { 1366 perf_pct = global.min_perf_pct; 1367 } else { 1368 req++; 1369 perf_pct = global.max_perf_pct; 1370 } 1371 1372 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * perf_pct, 100); 1373 1374 if (freq_qos_update_request(req, freq) < 0) 1375 pr_warn("Failed to update freq constraint: CPU%d\n", i); 1376 } 1377 } 1378 1379 static ssize_t store_max_perf_pct(struct kobject *a, struct kobj_attribute *b, 1380 const char *buf, size_t count) 1381 { 1382 unsigned int input; 1383 int ret; 1384 1385 ret = sscanf(buf, "%u", &input); 1386 if (ret != 1) 1387 return -EINVAL; 1388 1389 mutex_lock(&intel_pstate_driver_lock); 1390 1391 if (!intel_pstate_driver) { 1392 mutex_unlock(&intel_pstate_driver_lock); 1393 return -EAGAIN; 1394 } 1395 1396 mutex_lock(&intel_pstate_limits_lock); 1397 1398 global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100); 1399 1400 mutex_unlock(&intel_pstate_limits_lock); 1401 1402 if (intel_pstate_driver == &intel_pstate) 1403 intel_pstate_update_policies(); 1404 else 1405 update_qos_request(FREQ_QOS_MAX); 1406 1407 mutex_unlock(&intel_pstate_driver_lock); 1408 1409 return count; 1410 } 1411 1412 static ssize_t store_min_perf_pct(struct kobject *a, struct kobj_attribute *b, 1413 const char *buf, size_t count) 1414 { 1415 unsigned int input; 1416 int ret; 1417 1418 ret = sscanf(buf, "%u", &input); 1419 if (ret != 1) 1420 return -EINVAL; 1421 1422 mutex_lock(&intel_pstate_driver_lock); 1423 1424 if (!intel_pstate_driver) { 1425 mutex_unlock(&intel_pstate_driver_lock); 1426 return -EAGAIN; 1427 } 1428 1429 mutex_lock(&intel_pstate_limits_lock); 1430 1431 global.min_perf_pct = clamp_t(int, input, 1432 min_perf_pct_min(), global.max_perf_pct); 1433 1434 mutex_unlock(&intel_pstate_limits_lock); 1435 1436 if (intel_pstate_driver == &intel_pstate) 1437 intel_pstate_update_policies(); 1438 else 1439 update_qos_request(FREQ_QOS_MIN); 1440 1441 mutex_unlock(&intel_pstate_driver_lock); 1442 1443 return count; 1444 } 1445 1446 static ssize_t show_hwp_dynamic_boost(struct kobject *kobj, 1447 struct kobj_attribute *attr, char *buf) 1448 { 1449 return sprintf(buf, "%u\n", hwp_boost); 1450 } 1451 1452 static ssize_t store_hwp_dynamic_boost(struct kobject *a, 1453 struct kobj_attribute *b, 1454 const char *buf, size_t count) 1455 { 1456 unsigned int input; 1457 int ret; 1458 1459 ret = kstrtouint(buf, 10, &input); 1460 if (ret) 1461 return ret; 1462 1463 mutex_lock(&intel_pstate_driver_lock); 1464 hwp_boost = !!input; 1465 intel_pstate_update_policies(); 1466 mutex_unlock(&intel_pstate_driver_lock); 1467 1468 return count; 1469 } 1470 1471 static ssize_t show_energy_efficiency(struct kobject *kobj, struct kobj_attribute *attr, 1472 char *buf) 1473 { 1474 u64 power_ctl; 1475 int enable; 1476 1477 rdmsrl(MSR_IA32_POWER_CTL, power_ctl); 1478 enable = !!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE)); 1479 return sprintf(buf, "%d\n", !enable); 1480 } 1481 1482 static ssize_t store_energy_efficiency(struct kobject *a, struct kobj_attribute *b, 1483 const char *buf, size_t count) 1484 { 1485 bool input; 1486 int ret; 1487 1488 ret = kstrtobool(buf, &input); 1489 if (ret) 1490 return ret; 1491 1492 set_power_ctl_ee_state(input); 1493 1494 return count; 1495 } 1496 1497 show_one(max_perf_pct, max_perf_pct); 1498 show_one(min_perf_pct, min_perf_pct); 1499 1500 define_one_global_rw(status); 1501 define_one_global_rw(no_turbo); 1502 define_one_global_rw(max_perf_pct); 1503 define_one_global_rw(min_perf_pct); 1504 define_one_global_ro(turbo_pct); 1505 define_one_global_ro(num_pstates); 1506 define_one_global_rw(hwp_dynamic_boost); 1507 define_one_global_rw(energy_efficiency); 1508 1509 static struct attribute *intel_pstate_attributes[] = { 1510 &status.attr, 1511 &no_turbo.attr, 1512 NULL 1513 }; 1514 1515 static const struct attribute_group intel_pstate_attr_group = { 1516 .attrs = intel_pstate_attributes, 1517 }; 1518 1519 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[]; 1520 1521 static struct kobject *intel_pstate_kobject; 1522 1523 static void __init intel_pstate_sysfs_expose_params(void) 1524 { 1525 struct device *dev_root = bus_get_dev_root(&cpu_subsys); 1526 int rc; 1527 1528 if (dev_root) { 1529 intel_pstate_kobject = kobject_create_and_add("intel_pstate", &dev_root->kobj); 1530 put_device(dev_root); 1531 } 1532 if (WARN_ON(!intel_pstate_kobject)) 1533 return; 1534 1535 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group); 1536 if (WARN_ON(rc)) 1537 return; 1538 1539 if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) { 1540 rc = sysfs_create_file(intel_pstate_kobject, &turbo_pct.attr); 1541 WARN_ON(rc); 1542 1543 rc = sysfs_create_file(intel_pstate_kobject, &num_pstates.attr); 1544 WARN_ON(rc); 1545 } 1546 1547 /* 1548 * If per cpu limits are enforced there are no global limits, so 1549 * return without creating max/min_perf_pct attributes 1550 */ 1551 if (per_cpu_limits) 1552 return; 1553 1554 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr); 1555 WARN_ON(rc); 1556 1557 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr); 1558 WARN_ON(rc); 1559 1560 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids)) { 1561 rc = sysfs_create_file(intel_pstate_kobject, &energy_efficiency.attr); 1562 WARN_ON(rc); 1563 } 1564 } 1565 1566 static void __init intel_pstate_sysfs_remove(void) 1567 { 1568 if (!intel_pstate_kobject) 1569 return; 1570 1571 sysfs_remove_group(intel_pstate_kobject, &intel_pstate_attr_group); 1572 1573 if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) { 1574 sysfs_remove_file(intel_pstate_kobject, &num_pstates.attr); 1575 sysfs_remove_file(intel_pstate_kobject, &turbo_pct.attr); 1576 } 1577 1578 if (!per_cpu_limits) { 1579 sysfs_remove_file(intel_pstate_kobject, &max_perf_pct.attr); 1580 sysfs_remove_file(intel_pstate_kobject, &min_perf_pct.attr); 1581 1582 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids)) 1583 sysfs_remove_file(intel_pstate_kobject, &energy_efficiency.attr); 1584 } 1585 1586 kobject_put(intel_pstate_kobject); 1587 } 1588 1589 static void intel_pstate_sysfs_expose_hwp_dynamic_boost(void) 1590 { 1591 int rc; 1592 1593 if (!hwp_active) 1594 return; 1595 1596 rc = sysfs_create_file(intel_pstate_kobject, &hwp_dynamic_boost.attr); 1597 WARN_ON_ONCE(rc); 1598 } 1599 1600 static void intel_pstate_sysfs_hide_hwp_dynamic_boost(void) 1601 { 1602 if (!hwp_active) 1603 return; 1604 1605 sysfs_remove_file(intel_pstate_kobject, &hwp_dynamic_boost.attr); 1606 } 1607 1608 /************************** sysfs end ************************/ 1609 1610 static void intel_pstate_notify_work(struct work_struct *work) 1611 { 1612 struct cpudata *cpudata = 1613 container_of(to_delayed_work(work), struct cpudata, hwp_notify_work); 1614 struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpudata->cpu); 1615 1616 if (policy) { 1617 __intel_pstate_update_max_freq(cpudata, policy); 1618 1619 cpufreq_cpu_release(policy); 1620 } 1621 1622 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0); 1623 } 1624 1625 static DEFINE_SPINLOCK(hwp_notify_lock); 1626 static cpumask_t hwp_intr_enable_mask; 1627 1628 void notify_hwp_interrupt(void) 1629 { 1630 unsigned int this_cpu = smp_processor_id(); 1631 unsigned long flags; 1632 u64 value; 1633 1634 if (!hwp_active || !boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) 1635 return; 1636 1637 rdmsrl_safe(MSR_HWP_STATUS, &value); 1638 if (!(value & 0x01)) 1639 return; 1640 1641 spin_lock_irqsave(&hwp_notify_lock, flags); 1642 1643 if (!cpumask_test_cpu(this_cpu, &hwp_intr_enable_mask)) 1644 goto ack_intr; 1645 1646 schedule_delayed_work(&all_cpu_data[this_cpu]->hwp_notify_work, 1647 msecs_to_jiffies(10)); 1648 1649 spin_unlock_irqrestore(&hwp_notify_lock, flags); 1650 1651 return; 1652 1653 ack_intr: 1654 wrmsrl_safe(MSR_HWP_STATUS, 0); 1655 spin_unlock_irqrestore(&hwp_notify_lock, flags); 1656 } 1657 1658 static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata) 1659 { 1660 bool cancel_work; 1661 1662 if (!boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) 1663 return; 1664 1665 /* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */ 1666 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00); 1667 1668 spin_lock_irq(&hwp_notify_lock); 1669 cancel_work = cpumask_test_and_clear_cpu(cpudata->cpu, &hwp_intr_enable_mask); 1670 spin_unlock_irq(&hwp_notify_lock); 1671 1672 if (cancel_work) 1673 cancel_delayed_work_sync(&cpudata->hwp_notify_work); 1674 } 1675 1676 static void intel_pstate_enable_hwp_interrupt(struct cpudata *cpudata) 1677 { 1678 /* Enable HWP notification interrupt for guaranteed performance change */ 1679 if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) { 1680 spin_lock_irq(&hwp_notify_lock); 1681 INIT_DELAYED_WORK(&cpudata->hwp_notify_work, intel_pstate_notify_work); 1682 cpumask_set_cpu(cpudata->cpu, &hwp_intr_enable_mask); 1683 spin_unlock_irq(&hwp_notify_lock); 1684 1685 /* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */ 1686 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x01); 1687 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0); 1688 } 1689 } 1690 1691 static void intel_pstate_update_epp_defaults(struct cpudata *cpudata) 1692 { 1693 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0); 1694 1695 /* 1696 * If the EPP is set by firmware, which means that firmware enabled HWP 1697 * - Is equal or less than 0x80 (default balance_perf EPP) 1698 * - But less performance oriented than performance EPP 1699 * then use this as new balance_perf EPP. 1700 */ 1701 if (hwp_forced && cpudata->epp_default <= HWP_EPP_BALANCE_PERFORMANCE && 1702 cpudata->epp_default > HWP_EPP_PERFORMANCE) { 1703 epp_values[EPP_INDEX_BALANCE_PERFORMANCE] = cpudata->epp_default; 1704 return; 1705 } 1706 1707 /* 1708 * If this CPU gen doesn't call for change in balance_perf 1709 * EPP return. 1710 */ 1711 if (epp_values[EPP_INDEX_BALANCE_PERFORMANCE] == HWP_EPP_BALANCE_PERFORMANCE) 1712 return; 1713 1714 /* 1715 * Use hard coded value per gen to update the balance_perf 1716 * and default EPP. 1717 */ 1718 cpudata->epp_default = epp_values[EPP_INDEX_BALANCE_PERFORMANCE]; 1719 intel_pstate_set_epp(cpudata, cpudata->epp_default); 1720 } 1721 1722 static void intel_pstate_hwp_enable(struct cpudata *cpudata) 1723 { 1724 /* First disable HWP notification interrupt till we activate again */ 1725 if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) 1726 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00); 1727 1728 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1); 1729 1730 intel_pstate_enable_hwp_interrupt(cpudata); 1731 1732 if (cpudata->epp_default >= 0) 1733 return; 1734 1735 intel_pstate_update_epp_defaults(cpudata); 1736 } 1737 1738 static int atom_get_min_pstate(int not_used) 1739 { 1740 u64 value; 1741 1742 rdmsrl(MSR_ATOM_CORE_RATIOS, value); 1743 return (value >> 8) & 0x7F; 1744 } 1745 1746 static int atom_get_max_pstate(int not_used) 1747 { 1748 u64 value; 1749 1750 rdmsrl(MSR_ATOM_CORE_RATIOS, value); 1751 return (value >> 16) & 0x7F; 1752 } 1753 1754 static int atom_get_turbo_pstate(int not_used) 1755 { 1756 u64 value; 1757 1758 rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value); 1759 return value & 0x7F; 1760 } 1761 1762 static u64 atom_get_val(struct cpudata *cpudata, int pstate) 1763 { 1764 u64 val; 1765 int32_t vid_fp; 1766 u32 vid; 1767 1768 val = (u64)pstate << 8; 1769 if (READ_ONCE(global.no_turbo) && !READ_ONCE(global.turbo_disabled)) 1770 val |= (u64)1 << 32; 1771 1772 vid_fp = cpudata->vid.min + mul_fp( 1773 int_tofp(pstate - cpudata->pstate.min_pstate), 1774 cpudata->vid.ratio); 1775 1776 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max); 1777 vid = ceiling_fp(vid_fp); 1778 1779 if (pstate > cpudata->pstate.max_pstate) 1780 vid = cpudata->vid.turbo; 1781 1782 return val | vid; 1783 } 1784 1785 static int silvermont_get_scaling(void) 1786 { 1787 u64 value; 1788 int i; 1789 /* Defined in Table 35-6 from SDM (Sept 2015) */ 1790 static int silvermont_freq_table[] = { 1791 83300, 100000, 133300, 116700, 80000}; 1792 1793 rdmsrl(MSR_FSB_FREQ, value); 1794 i = value & 0x7; 1795 WARN_ON(i > 4); 1796 1797 return silvermont_freq_table[i]; 1798 } 1799 1800 static int airmont_get_scaling(void) 1801 { 1802 u64 value; 1803 int i; 1804 /* Defined in Table 35-10 from SDM (Sept 2015) */ 1805 static int airmont_freq_table[] = { 1806 83300, 100000, 133300, 116700, 80000, 1807 93300, 90000, 88900, 87500}; 1808 1809 rdmsrl(MSR_FSB_FREQ, value); 1810 i = value & 0xF; 1811 WARN_ON(i > 8); 1812 1813 return airmont_freq_table[i]; 1814 } 1815 1816 static void atom_get_vid(struct cpudata *cpudata) 1817 { 1818 u64 value; 1819 1820 rdmsrl(MSR_ATOM_CORE_VIDS, value); 1821 cpudata->vid.min = int_tofp((value >> 8) & 0x7f); 1822 cpudata->vid.max = int_tofp((value >> 16) & 0x7f); 1823 cpudata->vid.ratio = div_fp( 1824 cpudata->vid.max - cpudata->vid.min, 1825 int_tofp(cpudata->pstate.max_pstate - 1826 cpudata->pstate.min_pstate)); 1827 1828 rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value); 1829 cpudata->vid.turbo = value & 0x7f; 1830 } 1831 1832 static int core_get_min_pstate(int cpu) 1833 { 1834 u64 value; 1835 1836 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &value); 1837 return (value >> 40) & 0xFF; 1838 } 1839 1840 static int core_get_max_pstate_physical(int cpu) 1841 { 1842 u64 value; 1843 1844 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &value); 1845 return (value >> 8) & 0xFF; 1846 } 1847 1848 static int core_get_tdp_ratio(int cpu, u64 plat_info) 1849 { 1850 /* Check how many TDP levels present */ 1851 if (plat_info & 0x600000000) { 1852 u64 tdp_ctrl; 1853 u64 tdp_ratio; 1854 int tdp_msr; 1855 int err; 1856 1857 /* Get the TDP level (0, 1, 2) to get ratios */ 1858 err = rdmsrl_safe_on_cpu(cpu, MSR_CONFIG_TDP_CONTROL, &tdp_ctrl); 1859 if (err) 1860 return err; 1861 1862 /* TDP MSR are continuous starting at 0x648 */ 1863 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03); 1864 err = rdmsrl_safe_on_cpu(cpu, tdp_msr, &tdp_ratio); 1865 if (err) 1866 return err; 1867 1868 /* For level 1 and 2, bits[23:16] contain the ratio */ 1869 if (tdp_ctrl & 0x03) 1870 tdp_ratio >>= 16; 1871 1872 tdp_ratio &= 0xff; /* ratios are only 8 bits long */ 1873 pr_debug("tdp_ratio %x\n", (int)tdp_ratio); 1874 1875 return (int)tdp_ratio; 1876 } 1877 1878 return -ENXIO; 1879 } 1880 1881 static int core_get_max_pstate(int cpu) 1882 { 1883 u64 tar; 1884 u64 plat_info; 1885 int max_pstate; 1886 int tdp_ratio; 1887 int err; 1888 1889 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &plat_info); 1890 max_pstate = (plat_info >> 8) & 0xFF; 1891 1892 tdp_ratio = core_get_tdp_ratio(cpu, plat_info); 1893 if (tdp_ratio <= 0) 1894 return max_pstate; 1895 1896 if (hwp_active) { 1897 /* Turbo activation ratio is not used on HWP platforms */ 1898 return tdp_ratio; 1899 } 1900 1901 err = rdmsrl_safe_on_cpu(cpu, MSR_TURBO_ACTIVATION_RATIO, &tar); 1902 if (!err) { 1903 int tar_levels; 1904 1905 /* Do some sanity checking for safety */ 1906 tar_levels = tar & 0xff; 1907 if (tdp_ratio - 1 == tar_levels) { 1908 max_pstate = tar_levels; 1909 pr_debug("max_pstate=TAC %x\n", max_pstate); 1910 } 1911 } 1912 1913 return max_pstate; 1914 } 1915 1916 static int core_get_turbo_pstate(int cpu) 1917 { 1918 u64 value; 1919 int nont, ret; 1920 1921 rdmsrl_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value); 1922 nont = core_get_max_pstate(cpu); 1923 ret = (value) & 255; 1924 if (ret <= nont) 1925 ret = nont; 1926 return ret; 1927 } 1928 1929 static u64 core_get_val(struct cpudata *cpudata, int pstate) 1930 { 1931 u64 val; 1932 1933 val = (u64)pstate << 8; 1934 if (READ_ONCE(global.no_turbo) && !READ_ONCE(global.turbo_disabled)) 1935 val |= (u64)1 << 32; 1936 1937 return val; 1938 } 1939 1940 static int knl_get_aperf_mperf_shift(void) 1941 { 1942 return 10; 1943 } 1944 1945 static int knl_get_turbo_pstate(int cpu) 1946 { 1947 u64 value; 1948 int nont, ret; 1949 1950 rdmsrl_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value); 1951 nont = core_get_max_pstate(cpu); 1952 ret = (((value) >> 8) & 0xFF); 1953 if (ret <= nont) 1954 ret = nont; 1955 return ret; 1956 } 1957 1958 static void hybrid_get_type(void *data) 1959 { 1960 u8 *cpu_type = data; 1961 1962 *cpu_type = get_this_hybrid_cpu_type(); 1963 } 1964 1965 static int hwp_get_cpu_scaling(int cpu) 1966 { 1967 u8 cpu_type = 0; 1968 1969 smp_call_function_single(cpu, hybrid_get_type, &cpu_type, 1); 1970 /* P-cores have a smaller perf level-to-freqency scaling factor. */ 1971 if (cpu_type == 0x40) 1972 return hybrid_scaling_factor; 1973 1974 /* Use default core scaling for E-cores */ 1975 if (cpu_type == 0x20) 1976 return core_get_scaling(); 1977 1978 /* 1979 * If reached here, this system is either non-hybrid (like Tiger 1980 * Lake) or hybrid-capable (like Alder Lake or Raptor Lake) with 1981 * no E cores (in which case CPUID for hybrid support is 0). 1982 * 1983 * The CPPC nominal_frequency field is 0 for non-hybrid systems, 1984 * so the default core scaling will be used for them. 1985 */ 1986 return intel_pstate_cppc_get_scaling(cpu); 1987 } 1988 1989 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate) 1990 { 1991 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu); 1992 cpu->pstate.current_pstate = pstate; 1993 /* 1994 * Generally, there is no guarantee that this code will always run on 1995 * the CPU being updated, so force the register update to run on the 1996 * right CPU. 1997 */ 1998 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL, 1999 pstate_funcs.get_val(cpu, pstate)); 2000 } 2001 2002 static void intel_pstate_set_min_pstate(struct cpudata *cpu) 2003 { 2004 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate); 2005 } 2006 2007 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu) 2008 { 2009 int perf_ctl_max_phys = pstate_funcs.get_max_physical(cpu->cpu); 2010 int perf_ctl_scaling = pstate_funcs.get_scaling(); 2011 2012 cpu->pstate.min_pstate = pstate_funcs.get_min(cpu->cpu); 2013 cpu->pstate.max_pstate_physical = perf_ctl_max_phys; 2014 cpu->pstate.perf_ctl_scaling = perf_ctl_scaling; 2015 2016 if (hwp_active && !hwp_mode_bdw) { 2017 __intel_pstate_get_hwp_cap(cpu); 2018 2019 if (pstate_funcs.get_cpu_scaling) { 2020 cpu->pstate.scaling = pstate_funcs.get_cpu_scaling(cpu->cpu); 2021 if (cpu->pstate.scaling != perf_ctl_scaling) 2022 intel_pstate_hybrid_hwp_adjust(cpu); 2023 } else { 2024 cpu->pstate.scaling = perf_ctl_scaling; 2025 } 2026 } else { 2027 cpu->pstate.scaling = perf_ctl_scaling; 2028 cpu->pstate.max_pstate = pstate_funcs.get_max(cpu->cpu); 2029 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(cpu->cpu); 2030 } 2031 2032 if (cpu->pstate.scaling == perf_ctl_scaling) { 2033 cpu->pstate.min_freq = cpu->pstate.min_pstate * perf_ctl_scaling; 2034 cpu->pstate.max_freq = cpu->pstate.max_pstate * perf_ctl_scaling; 2035 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * perf_ctl_scaling; 2036 } 2037 2038 if (pstate_funcs.get_aperf_mperf_shift) 2039 cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift(); 2040 2041 if (pstate_funcs.get_vid) 2042 pstate_funcs.get_vid(cpu); 2043 2044 intel_pstate_set_min_pstate(cpu); 2045 } 2046 2047 /* 2048 * Long hold time will keep high perf limits for long time, 2049 * which negatively impacts perf/watt for some workloads, 2050 * like specpower. 3ms is based on experiements on some 2051 * workoads. 2052 */ 2053 static int hwp_boost_hold_time_ns = 3 * NSEC_PER_MSEC; 2054 2055 static inline void intel_pstate_hwp_boost_up(struct cpudata *cpu) 2056 { 2057 u64 hwp_req = READ_ONCE(cpu->hwp_req_cached); 2058 u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached); 2059 u32 max_limit = (hwp_req & 0xff00) >> 8; 2060 u32 min_limit = (hwp_req & 0xff); 2061 u32 boost_level1; 2062 2063 /* 2064 * Cases to consider (User changes via sysfs or boot time): 2065 * If, P0 (Turbo max) = P1 (Guaranteed max) = min: 2066 * No boost, return. 2067 * If, P0 (Turbo max) > P1 (Guaranteed max) = min: 2068 * Should result in one level boost only for P0. 2069 * If, P0 (Turbo max) = P1 (Guaranteed max) > min: 2070 * Should result in two level boost: 2071 * (min + p1)/2 and P1. 2072 * If, P0 (Turbo max) > P1 (Guaranteed max) > min: 2073 * Should result in three level boost: 2074 * (min + p1)/2, P1 and P0. 2075 */ 2076 2077 /* If max and min are equal or already at max, nothing to boost */ 2078 if (max_limit == min_limit || cpu->hwp_boost_min >= max_limit) 2079 return; 2080 2081 if (!cpu->hwp_boost_min) 2082 cpu->hwp_boost_min = min_limit; 2083 2084 /* level at half way mark between min and guranteed */ 2085 boost_level1 = (HWP_GUARANTEED_PERF(hwp_cap) + min_limit) >> 1; 2086 2087 if (cpu->hwp_boost_min < boost_level1) 2088 cpu->hwp_boost_min = boost_level1; 2089 else if (cpu->hwp_boost_min < HWP_GUARANTEED_PERF(hwp_cap)) 2090 cpu->hwp_boost_min = HWP_GUARANTEED_PERF(hwp_cap); 2091 else if (cpu->hwp_boost_min == HWP_GUARANTEED_PERF(hwp_cap) && 2092 max_limit != HWP_GUARANTEED_PERF(hwp_cap)) 2093 cpu->hwp_boost_min = max_limit; 2094 else 2095 return; 2096 2097 hwp_req = (hwp_req & ~GENMASK_ULL(7, 0)) | cpu->hwp_boost_min; 2098 wrmsrl(MSR_HWP_REQUEST, hwp_req); 2099 cpu->last_update = cpu->sample.time; 2100 } 2101 2102 static inline void intel_pstate_hwp_boost_down(struct cpudata *cpu) 2103 { 2104 if (cpu->hwp_boost_min) { 2105 bool expired; 2106 2107 /* Check if we are idle for hold time to boost down */ 2108 expired = time_after64(cpu->sample.time, cpu->last_update + 2109 hwp_boost_hold_time_ns); 2110 if (expired) { 2111 wrmsrl(MSR_HWP_REQUEST, cpu->hwp_req_cached); 2112 cpu->hwp_boost_min = 0; 2113 } 2114 } 2115 cpu->last_update = cpu->sample.time; 2116 } 2117 2118 static inline void intel_pstate_update_util_hwp_local(struct cpudata *cpu, 2119 u64 time) 2120 { 2121 cpu->sample.time = time; 2122 2123 if (cpu->sched_flags & SCHED_CPUFREQ_IOWAIT) { 2124 bool do_io = false; 2125 2126 cpu->sched_flags = 0; 2127 /* 2128 * Set iowait_boost flag and update time. Since IO WAIT flag 2129 * is set all the time, we can't just conclude that there is 2130 * some IO bound activity is scheduled on this CPU with just 2131 * one occurrence. If we receive at least two in two 2132 * consecutive ticks, then we treat as boost candidate. 2133 */ 2134 if (time_before64(time, cpu->last_io_update + 2 * TICK_NSEC)) 2135 do_io = true; 2136 2137 cpu->last_io_update = time; 2138 2139 if (do_io) 2140 intel_pstate_hwp_boost_up(cpu); 2141 2142 } else { 2143 intel_pstate_hwp_boost_down(cpu); 2144 } 2145 } 2146 2147 static inline void intel_pstate_update_util_hwp(struct update_util_data *data, 2148 u64 time, unsigned int flags) 2149 { 2150 struct cpudata *cpu = container_of(data, struct cpudata, update_util); 2151 2152 cpu->sched_flags |= flags; 2153 2154 if (smp_processor_id() == cpu->cpu) 2155 intel_pstate_update_util_hwp_local(cpu, time); 2156 } 2157 2158 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu) 2159 { 2160 struct sample *sample = &cpu->sample; 2161 2162 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf); 2163 } 2164 2165 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time) 2166 { 2167 u64 aperf, mperf; 2168 unsigned long flags; 2169 u64 tsc; 2170 2171 local_irq_save(flags); 2172 rdmsrl(MSR_IA32_APERF, aperf); 2173 rdmsrl(MSR_IA32_MPERF, mperf); 2174 tsc = rdtsc(); 2175 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) { 2176 local_irq_restore(flags); 2177 return false; 2178 } 2179 local_irq_restore(flags); 2180 2181 cpu->last_sample_time = cpu->sample.time; 2182 cpu->sample.time = time; 2183 cpu->sample.aperf = aperf; 2184 cpu->sample.mperf = mperf; 2185 cpu->sample.tsc = tsc; 2186 cpu->sample.aperf -= cpu->prev_aperf; 2187 cpu->sample.mperf -= cpu->prev_mperf; 2188 cpu->sample.tsc -= cpu->prev_tsc; 2189 2190 cpu->prev_aperf = aperf; 2191 cpu->prev_mperf = mperf; 2192 cpu->prev_tsc = tsc; 2193 /* 2194 * First time this function is invoked in a given cycle, all of the 2195 * previous sample data fields are equal to zero or stale and they must 2196 * be populated with meaningful numbers for things to work, so assume 2197 * that sample.time will always be reset before setting the utilization 2198 * update hook and make the caller skip the sample then. 2199 */ 2200 if (cpu->last_sample_time) { 2201 intel_pstate_calc_avg_perf(cpu); 2202 return true; 2203 } 2204 return false; 2205 } 2206 2207 static inline int32_t get_avg_frequency(struct cpudata *cpu) 2208 { 2209 return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz); 2210 } 2211 2212 static inline int32_t get_avg_pstate(struct cpudata *cpu) 2213 { 2214 return mul_ext_fp(cpu->pstate.max_pstate_physical, 2215 cpu->sample.core_avg_perf); 2216 } 2217 2218 static inline int32_t get_target_pstate(struct cpudata *cpu) 2219 { 2220 struct sample *sample = &cpu->sample; 2221 int32_t busy_frac; 2222 int target, avg_pstate; 2223 2224 busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift, 2225 sample->tsc); 2226 2227 if (busy_frac < cpu->iowait_boost) 2228 busy_frac = cpu->iowait_boost; 2229 2230 sample->busy_scaled = busy_frac * 100; 2231 2232 target = READ_ONCE(global.no_turbo) ? 2233 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate; 2234 target += target >> 2; 2235 target = mul_fp(target, busy_frac); 2236 if (target < cpu->pstate.min_pstate) 2237 target = cpu->pstate.min_pstate; 2238 2239 /* 2240 * If the average P-state during the previous cycle was higher than the 2241 * current target, add 50% of the difference to the target to reduce 2242 * possible performance oscillations and offset possible performance 2243 * loss related to moving the workload from one CPU to another within 2244 * a package/module. 2245 */ 2246 avg_pstate = get_avg_pstate(cpu); 2247 if (avg_pstate > target) 2248 target += (avg_pstate - target) >> 1; 2249 2250 return target; 2251 } 2252 2253 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate) 2254 { 2255 int min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio); 2256 int max_pstate = max(min_pstate, cpu->max_perf_ratio); 2257 2258 return clamp_t(int, pstate, min_pstate, max_pstate); 2259 } 2260 2261 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate) 2262 { 2263 if (pstate == cpu->pstate.current_pstate) 2264 return; 2265 2266 cpu->pstate.current_pstate = pstate; 2267 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate)); 2268 } 2269 2270 static void intel_pstate_adjust_pstate(struct cpudata *cpu) 2271 { 2272 int from = cpu->pstate.current_pstate; 2273 struct sample *sample; 2274 int target_pstate; 2275 2276 target_pstate = get_target_pstate(cpu); 2277 target_pstate = intel_pstate_prepare_request(cpu, target_pstate); 2278 trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu); 2279 intel_pstate_update_pstate(cpu, target_pstate); 2280 2281 sample = &cpu->sample; 2282 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf), 2283 fp_toint(sample->busy_scaled), 2284 from, 2285 cpu->pstate.current_pstate, 2286 sample->mperf, 2287 sample->aperf, 2288 sample->tsc, 2289 get_avg_frequency(cpu), 2290 fp_toint(cpu->iowait_boost * 100)); 2291 } 2292 2293 static void intel_pstate_update_util(struct update_util_data *data, u64 time, 2294 unsigned int flags) 2295 { 2296 struct cpudata *cpu = container_of(data, struct cpudata, update_util); 2297 u64 delta_ns; 2298 2299 /* Don't allow remote callbacks */ 2300 if (smp_processor_id() != cpu->cpu) 2301 return; 2302 2303 delta_ns = time - cpu->last_update; 2304 if (flags & SCHED_CPUFREQ_IOWAIT) { 2305 /* Start over if the CPU may have been idle. */ 2306 if (delta_ns > TICK_NSEC) { 2307 cpu->iowait_boost = ONE_EIGHTH_FP; 2308 } else if (cpu->iowait_boost >= ONE_EIGHTH_FP) { 2309 cpu->iowait_boost <<= 1; 2310 if (cpu->iowait_boost > int_tofp(1)) 2311 cpu->iowait_boost = int_tofp(1); 2312 } else { 2313 cpu->iowait_boost = ONE_EIGHTH_FP; 2314 } 2315 } else if (cpu->iowait_boost) { 2316 /* Clear iowait_boost if the CPU may have been idle. */ 2317 if (delta_ns > TICK_NSEC) 2318 cpu->iowait_boost = 0; 2319 else 2320 cpu->iowait_boost >>= 1; 2321 } 2322 cpu->last_update = time; 2323 delta_ns = time - cpu->sample.time; 2324 if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL) 2325 return; 2326 2327 if (intel_pstate_sample(cpu, time)) 2328 intel_pstate_adjust_pstate(cpu); 2329 } 2330 2331 static struct pstate_funcs core_funcs = { 2332 .get_max = core_get_max_pstate, 2333 .get_max_physical = core_get_max_pstate_physical, 2334 .get_min = core_get_min_pstate, 2335 .get_turbo = core_get_turbo_pstate, 2336 .get_scaling = core_get_scaling, 2337 .get_val = core_get_val, 2338 }; 2339 2340 static const struct pstate_funcs silvermont_funcs = { 2341 .get_max = atom_get_max_pstate, 2342 .get_max_physical = atom_get_max_pstate, 2343 .get_min = atom_get_min_pstate, 2344 .get_turbo = atom_get_turbo_pstate, 2345 .get_val = atom_get_val, 2346 .get_scaling = silvermont_get_scaling, 2347 .get_vid = atom_get_vid, 2348 }; 2349 2350 static const struct pstate_funcs airmont_funcs = { 2351 .get_max = atom_get_max_pstate, 2352 .get_max_physical = atom_get_max_pstate, 2353 .get_min = atom_get_min_pstate, 2354 .get_turbo = atom_get_turbo_pstate, 2355 .get_val = atom_get_val, 2356 .get_scaling = airmont_get_scaling, 2357 .get_vid = atom_get_vid, 2358 }; 2359 2360 static const struct pstate_funcs knl_funcs = { 2361 .get_max = core_get_max_pstate, 2362 .get_max_physical = core_get_max_pstate_physical, 2363 .get_min = core_get_min_pstate, 2364 .get_turbo = knl_get_turbo_pstate, 2365 .get_aperf_mperf_shift = knl_get_aperf_mperf_shift, 2366 .get_scaling = core_get_scaling, 2367 .get_val = core_get_val, 2368 }; 2369 2370 #define X86_MATCH(model, policy) \ 2371 X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \ 2372 X86_FEATURE_APERFMPERF, &policy) 2373 2374 static const struct x86_cpu_id intel_pstate_cpu_ids[] = { 2375 X86_MATCH(SANDYBRIDGE, core_funcs), 2376 X86_MATCH(SANDYBRIDGE_X, core_funcs), 2377 X86_MATCH(ATOM_SILVERMONT, silvermont_funcs), 2378 X86_MATCH(IVYBRIDGE, core_funcs), 2379 X86_MATCH(HASWELL, core_funcs), 2380 X86_MATCH(BROADWELL, core_funcs), 2381 X86_MATCH(IVYBRIDGE_X, core_funcs), 2382 X86_MATCH(HASWELL_X, core_funcs), 2383 X86_MATCH(HASWELL_L, core_funcs), 2384 X86_MATCH(HASWELL_G, core_funcs), 2385 X86_MATCH(BROADWELL_G, core_funcs), 2386 X86_MATCH(ATOM_AIRMONT, airmont_funcs), 2387 X86_MATCH(SKYLAKE_L, core_funcs), 2388 X86_MATCH(BROADWELL_X, core_funcs), 2389 X86_MATCH(SKYLAKE, core_funcs), 2390 X86_MATCH(BROADWELL_D, core_funcs), 2391 X86_MATCH(XEON_PHI_KNL, knl_funcs), 2392 X86_MATCH(XEON_PHI_KNM, knl_funcs), 2393 X86_MATCH(ATOM_GOLDMONT, core_funcs), 2394 X86_MATCH(ATOM_GOLDMONT_PLUS, core_funcs), 2395 X86_MATCH(SKYLAKE_X, core_funcs), 2396 X86_MATCH(COMETLAKE, core_funcs), 2397 X86_MATCH(ICELAKE_X, core_funcs), 2398 X86_MATCH(TIGERLAKE, core_funcs), 2399 X86_MATCH(SAPPHIRERAPIDS_X, core_funcs), 2400 X86_MATCH(EMERALDRAPIDS_X, core_funcs), 2401 {} 2402 }; 2403 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids); 2404 2405 #ifdef CONFIG_ACPI 2406 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = { 2407 X86_MATCH(BROADWELL_D, core_funcs), 2408 X86_MATCH(BROADWELL_X, core_funcs), 2409 X86_MATCH(SKYLAKE_X, core_funcs), 2410 X86_MATCH(ICELAKE_X, core_funcs), 2411 X86_MATCH(SAPPHIRERAPIDS_X, core_funcs), 2412 {} 2413 }; 2414 #endif 2415 2416 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = { 2417 X86_MATCH(KABYLAKE, core_funcs), 2418 {} 2419 }; 2420 2421 static int intel_pstate_init_cpu(unsigned int cpunum) 2422 { 2423 struct cpudata *cpu; 2424 2425 cpu = all_cpu_data[cpunum]; 2426 2427 if (!cpu) { 2428 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL); 2429 if (!cpu) 2430 return -ENOMEM; 2431 2432 WRITE_ONCE(all_cpu_data[cpunum], cpu); 2433 2434 cpu->cpu = cpunum; 2435 2436 cpu->epp_default = -EINVAL; 2437 2438 if (hwp_active) { 2439 intel_pstate_hwp_enable(cpu); 2440 2441 if (intel_pstate_acpi_pm_profile_server()) 2442 hwp_boost = true; 2443 } 2444 } else if (hwp_active) { 2445 /* 2446 * Re-enable HWP in case this happens after a resume from ACPI 2447 * S3 if the CPU was offline during the whole system/resume 2448 * cycle. 2449 */ 2450 intel_pstate_hwp_reenable(cpu); 2451 } 2452 2453 cpu->epp_powersave = -EINVAL; 2454 cpu->epp_policy = 0; 2455 2456 intel_pstate_get_cpu_pstates(cpu); 2457 2458 pr_debug("controlling: cpu %d\n", cpunum); 2459 2460 return 0; 2461 } 2462 2463 static void intel_pstate_set_update_util_hook(unsigned int cpu_num) 2464 { 2465 struct cpudata *cpu = all_cpu_data[cpu_num]; 2466 2467 if (hwp_active && !hwp_boost) 2468 return; 2469 2470 if (cpu->update_util_set) 2471 return; 2472 2473 /* Prevent intel_pstate_update_util() from using stale data. */ 2474 cpu->sample.time = 0; 2475 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util, 2476 (hwp_active ? 2477 intel_pstate_update_util_hwp : 2478 intel_pstate_update_util)); 2479 cpu->update_util_set = true; 2480 } 2481 2482 static void intel_pstate_clear_update_util_hook(unsigned int cpu) 2483 { 2484 struct cpudata *cpu_data = all_cpu_data[cpu]; 2485 2486 if (!cpu_data->update_util_set) 2487 return; 2488 2489 cpufreq_remove_update_util_hook(cpu); 2490 cpu_data->update_util_set = false; 2491 synchronize_rcu(); 2492 } 2493 2494 static int intel_pstate_get_max_freq(struct cpudata *cpu) 2495 { 2496 return READ_ONCE(global.no_turbo) ? 2497 cpu->pstate.max_freq : cpu->pstate.turbo_freq; 2498 } 2499 2500 static void intel_pstate_update_perf_limits(struct cpudata *cpu, 2501 unsigned int policy_min, 2502 unsigned int policy_max) 2503 { 2504 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling; 2505 int32_t max_policy_perf, min_policy_perf; 2506 2507 max_policy_perf = policy_max / perf_ctl_scaling; 2508 if (policy_max == policy_min) { 2509 min_policy_perf = max_policy_perf; 2510 } else { 2511 min_policy_perf = policy_min / perf_ctl_scaling; 2512 min_policy_perf = clamp_t(int32_t, min_policy_perf, 2513 0, max_policy_perf); 2514 } 2515 2516 /* 2517 * HWP needs some special consideration, because HWP_REQUEST uses 2518 * abstract values to represent performance rather than pure ratios. 2519 */ 2520 if (hwp_active && cpu->pstate.scaling != perf_ctl_scaling) { 2521 int freq; 2522 2523 freq = max_policy_perf * perf_ctl_scaling; 2524 max_policy_perf = intel_pstate_freq_to_hwp(cpu, freq); 2525 freq = min_policy_perf * perf_ctl_scaling; 2526 min_policy_perf = intel_pstate_freq_to_hwp(cpu, freq); 2527 } 2528 2529 pr_debug("cpu:%d min_policy_perf:%d max_policy_perf:%d\n", 2530 cpu->cpu, min_policy_perf, max_policy_perf); 2531 2532 /* Normalize user input to [min_perf, max_perf] */ 2533 if (per_cpu_limits) { 2534 cpu->min_perf_ratio = min_policy_perf; 2535 cpu->max_perf_ratio = max_policy_perf; 2536 } else { 2537 int turbo_max = cpu->pstate.turbo_pstate; 2538 int32_t global_min, global_max; 2539 2540 /* Global limits are in percent of the maximum turbo P-state. */ 2541 global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100); 2542 global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100); 2543 global_min = clamp_t(int32_t, global_min, 0, global_max); 2544 2545 pr_debug("cpu:%d global_min:%d global_max:%d\n", cpu->cpu, 2546 global_min, global_max); 2547 2548 cpu->min_perf_ratio = max(min_policy_perf, global_min); 2549 cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf); 2550 cpu->max_perf_ratio = min(max_policy_perf, global_max); 2551 cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio); 2552 2553 /* Make sure min_perf <= max_perf */ 2554 cpu->min_perf_ratio = min(cpu->min_perf_ratio, 2555 cpu->max_perf_ratio); 2556 2557 } 2558 pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", cpu->cpu, 2559 cpu->max_perf_ratio, 2560 cpu->min_perf_ratio); 2561 } 2562 2563 static int intel_pstate_set_policy(struct cpufreq_policy *policy) 2564 { 2565 struct cpudata *cpu; 2566 2567 if (!policy->cpuinfo.max_freq) 2568 return -ENODEV; 2569 2570 pr_debug("set_policy cpuinfo.max %u policy->max %u\n", 2571 policy->cpuinfo.max_freq, policy->max); 2572 2573 cpu = all_cpu_data[policy->cpu]; 2574 cpu->policy = policy->policy; 2575 2576 mutex_lock(&intel_pstate_limits_lock); 2577 2578 intel_pstate_update_perf_limits(cpu, policy->min, policy->max); 2579 2580 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) { 2581 int pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio); 2582 2583 /* 2584 * NOHZ_FULL CPUs need this as the governor callback may not 2585 * be invoked on them. 2586 */ 2587 intel_pstate_clear_update_util_hook(policy->cpu); 2588 intel_pstate_set_pstate(cpu, pstate); 2589 } else { 2590 intel_pstate_set_update_util_hook(policy->cpu); 2591 } 2592 2593 if (hwp_active) { 2594 /* 2595 * When hwp_boost was active before and dynamically it 2596 * was turned off, in that case we need to clear the 2597 * update util hook. 2598 */ 2599 if (!hwp_boost) 2600 intel_pstate_clear_update_util_hook(policy->cpu); 2601 intel_pstate_hwp_set(policy->cpu); 2602 } 2603 /* 2604 * policy->cur is never updated with the intel_pstate driver, but it 2605 * is used as a stale frequency value. So, keep it within limits. 2606 */ 2607 policy->cur = policy->min; 2608 2609 mutex_unlock(&intel_pstate_limits_lock); 2610 2611 return 0; 2612 } 2613 2614 static void intel_pstate_adjust_policy_max(struct cpudata *cpu, 2615 struct cpufreq_policy_data *policy) 2616 { 2617 if (!hwp_active && 2618 cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate && 2619 policy->max < policy->cpuinfo.max_freq && 2620 policy->max > cpu->pstate.max_freq) { 2621 pr_debug("policy->max > max non turbo frequency\n"); 2622 policy->max = policy->cpuinfo.max_freq; 2623 } 2624 } 2625 2626 static void intel_pstate_verify_cpu_policy(struct cpudata *cpu, 2627 struct cpufreq_policy_data *policy) 2628 { 2629 int max_freq; 2630 2631 if (hwp_active) { 2632 intel_pstate_get_hwp_cap(cpu); 2633 max_freq = READ_ONCE(global.no_turbo) ? 2634 cpu->pstate.max_freq : cpu->pstate.turbo_freq; 2635 } else { 2636 max_freq = intel_pstate_get_max_freq(cpu); 2637 } 2638 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, max_freq); 2639 2640 intel_pstate_adjust_policy_max(cpu, policy); 2641 } 2642 2643 static int intel_pstate_verify_policy(struct cpufreq_policy_data *policy) 2644 { 2645 intel_pstate_verify_cpu_policy(all_cpu_data[policy->cpu], policy); 2646 2647 return 0; 2648 } 2649 2650 static int intel_cpufreq_cpu_offline(struct cpufreq_policy *policy) 2651 { 2652 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2653 2654 pr_debug("CPU %d going offline\n", cpu->cpu); 2655 2656 if (cpu->suspended) 2657 return 0; 2658 2659 /* 2660 * If the CPU is an SMT thread and it goes offline with the performance 2661 * settings different from the minimum, it will prevent its sibling 2662 * from getting to lower performance levels, so force the minimum 2663 * performance on CPU offline to prevent that from happening. 2664 */ 2665 if (hwp_active) 2666 intel_pstate_hwp_offline(cpu); 2667 else 2668 intel_pstate_set_min_pstate(cpu); 2669 2670 intel_pstate_exit_perf_limits(policy); 2671 2672 return 0; 2673 } 2674 2675 static int intel_pstate_cpu_online(struct cpufreq_policy *policy) 2676 { 2677 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2678 2679 pr_debug("CPU %d going online\n", cpu->cpu); 2680 2681 intel_pstate_init_acpi_perf_limits(policy); 2682 2683 if (hwp_active) { 2684 /* 2685 * Re-enable HWP and clear the "suspended" flag to let "resume" 2686 * know that it need not do that. 2687 */ 2688 intel_pstate_hwp_reenable(cpu); 2689 cpu->suspended = false; 2690 } 2691 2692 return 0; 2693 } 2694 2695 static int intel_pstate_cpu_offline(struct cpufreq_policy *policy) 2696 { 2697 intel_pstate_clear_update_util_hook(policy->cpu); 2698 2699 return intel_cpufreq_cpu_offline(policy); 2700 } 2701 2702 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy) 2703 { 2704 pr_debug("CPU %d exiting\n", policy->cpu); 2705 2706 policy->fast_switch_possible = false; 2707 2708 return 0; 2709 } 2710 2711 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy) 2712 { 2713 struct cpudata *cpu; 2714 int rc; 2715 2716 rc = intel_pstate_init_cpu(policy->cpu); 2717 if (rc) 2718 return rc; 2719 2720 cpu = all_cpu_data[policy->cpu]; 2721 2722 cpu->max_perf_ratio = 0xFF; 2723 cpu->min_perf_ratio = 0; 2724 2725 /* cpuinfo and default policy values */ 2726 policy->cpuinfo.min_freq = cpu->pstate.min_freq; 2727 policy->cpuinfo.max_freq = READ_ONCE(global.no_turbo) ? 2728 cpu->pstate.max_freq : cpu->pstate.turbo_freq; 2729 2730 policy->min = policy->cpuinfo.min_freq; 2731 policy->max = policy->cpuinfo.max_freq; 2732 2733 intel_pstate_init_acpi_perf_limits(policy); 2734 2735 policy->fast_switch_possible = true; 2736 2737 return 0; 2738 } 2739 2740 static int intel_pstate_cpu_init(struct cpufreq_policy *policy) 2741 { 2742 int ret = __intel_pstate_cpu_init(policy); 2743 2744 if (ret) 2745 return ret; 2746 2747 /* 2748 * Set the policy to powersave to provide a valid fallback value in case 2749 * the default cpufreq governor is neither powersave nor performance. 2750 */ 2751 policy->policy = CPUFREQ_POLICY_POWERSAVE; 2752 2753 if (hwp_active) { 2754 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2755 2756 cpu->epp_cached = intel_pstate_get_epp(cpu, 0); 2757 } 2758 2759 return 0; 2760 } 2761 2762 static struct cpufreq_driver intel_pstate = { 2763 .flags = CPUFREQ_CONST_LOOPS, 2764 .verify = intel_pstate_verify_policy, 2765 .setpolicy = intel_pstate_set_policy, 2766 .suspend = intel_pstate_suspend, 2767 .resume = intel_pstate_resume, 2768 .init = intel_pstate_cpu_init, 2769 .exit = intel_pstate_cpu_exit, 2770 .offline = intel_pstate_cpu_offline, 2771 .online = intel_pstate_cpu_online, 2772 .update_limits = intel_pstate_update_limits, 2773 .name = "intel_pstate", 2774 }; 2775 2776 static int intel_cpufreq_verify_policy(struct cpufreq_policy_data *policy) 2777 { 2778 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2779 2780 intel_pstate_verify_cpu_policy(cpu, policy); 2781 intel_pstate_update_perf_limits(cpu, policy->min, policy->max); 2782 2783 return 0; 2784 } 2785 2786 /* Use of trace in passive mode: 2787 * 2788 * In passive mode the trace core_busy field (also known as the 2789 * performance field, and lablelled as such on the graphs; also known as 2790 * core_avg_perf) is not needed and so is re-assigned to indicate if the 2791 * driver call was via the normal or fast switch path. Various graphs 2792 * output from the intel_pstate_tracer.py utility that include core_busy 2793 * (or performance or core_avg_perf) have a fixed y-axis from 0 to 100%, 2794 * so we use 10 to indicate the normal path through the driver, and 2795 * 90 to indicate the fast switch path through the driver. 2796 * The scaled_busy field is not used, and is set to 0. 2797 */ 2798 2799 #define INTEL_PSTATE_TRACE_TARGET 10 2800 #define INTEL_PSTATE_TRACE_FAST_SWITCH 90 2801 2802 static void intel_cpufreq_trace(struct cpudata *cpu, unsigned int trace_type, int old_pstate) 2803 { 2804 struct sample *sample; 2805 2806 if (!trace_pstate_sample_enabled()) 2807 return; 2808 2809 if (!intel_pstate_sample(cpu, ktime_get())) 2810 return; 2811 2812 sample = &cpu->sample; 2813 trace_pstate_sample(trace_type, 2814 0, 2815 old_pstate, 2816 cpu->pstate.current_pstate, 2817 sample->mperf, 2818 sample->aperf, 2819 sample->tsc, 2820 get_avg_frequency(cpu), 2821 fp_toint(cpu->iowait_boost * 100)); 2822 } 2823 2824 static void intel_cpufreq_hwp_update(struct cpudata *cpu, u32 min, u32 max, 2825 u32 desired, bool fast_switch) 2826 { 2827 u64 prev = READ_ONCE(cpu->hwp_req_cached), value = prev; 2828 2829 value &= ~HWP_MIN_PERF(~0L); 2830 value |= HWP_MIN_PERF(min); 2831 2832 value &= ~HWP_MAX_PERF(~0L); 2833 value |= HWP_MAX_PERF(max); 2834 2835 value &= ~HWP_DESIRED_PERF(~0L); 2836 value |= HWP_DESIRED_PERF(desired); 2837 2838 if (value == prev) 2839 return; 2840 2841 WRITE_ONCE(cpu->hwp_req_cached, value); 2842 if (fast_switch) 2843 wrmsrl(MSR_HWP_REQUEST, value); 2844 else 2845 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 2846 } 2847 2848 static void intel_cpufreq_perf_ctl_update(struct cpudata *cpu, 2849 u32 target_pstate, bool fast_switch) 2850 { 2851 if (fast_switch) 2852 wrmsrl(MSR_IA32_PERF_CTL, 2853 pstate_funcs.get_val(cpu, target_pstate)); 2854 else 2855 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL, 2856 pstate_funcs.get_val(cpu, target_pstate)); 2857 } 2858 2859 static int intel_cpufreq_update_pstate(struct cpufreq_policy *policy, 2860 int target_pstate, bool fast_switch) 2861 { 2862 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2863 int old_pstate = cpu->pstate.current_pstate; 2864 2865 target_pstate = intel_pstate_prepare_request(cpu, target_pstate); 2866 if (hwp_active) { 2867 int max_pstate = policy->strict_target ? 2868 target_pstate : cpu->max_perf_ratio; 2869 2870 intel_cpufreq_hwp_update(cpu, target_pstate, max_pstate, 0, 2871 fast_switch); 2872 } else if (target_pstate != old_pstate) { 2873 intel_cpufreq_perf_ctl_update(cpu, target_pstate, fast_switch); 2874 } 2875 2876 cpu->pstate.current_pstate = target_pstate; 2877 2878 intel_cpufreq_trace(cpu, fast_switch ? INTEL_PSTATE_TRACE_FAST_SWITCH : 2879 INTEL_PSTATE_TRACE_TARGET, old_pstate); 2880 2881 return target_pstate; 2882 } 2883 2884 static int intel_cpufreq_target(struct cpufreq_policy *policy, 2885 unsigned int target_freq, 2886 unsigned int relation) 2887 { 2888 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2889 struct cpufreq_freqs freqs; 2890 int target_pstate; 2891 2892 freqs.old = policy->cur; 2893 freqs.new = target_freq; 2894 2895 cpufreq_freq_transition_begin(policy, &freqs); 2896 2897 target_pstate = intel_pstate_freq_to_hwp_rel(cpu, freqs.new, relation); 2898 target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, false); 2899 2900 freqs.new = target_pstate * cpu->pstate.scaling; 2901 2902 cpufreq_freq_transition_end(policy, &freqs, false); 2903 2904 return 0; 2905 } 2906 2907 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy, 2908 unsigned int target_freq) 2909 { 2910 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2911 int target_pstate; 2912 2913 target_pstate = intel_pstate_freq_to_hwp(cpu, target_freq); 2914 2915 target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, true); 2916 2917 return target_pstate * cpu->pstate.scaling; 2918 } 2919 2920 static void intel_cpufreq_adjust_perf(unsigned int cpunum, 2921 unsigned long min_perf, 2922 unsigned long target_perf, 2923 unsigned long capacity) 2924 { 2925 struct cpudata *cpu = all_cpu_data[cpunum]; 2926 u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached); 2927 int old_pstate = cpu->pstate.current_pstate; 2928 int cap_pstate, min_pstate, max_pstate, target_pstate; 2929 2930 cap_pstate = READ_ONCE(global.no_turbo) ? 2931 HWP_GUARANTEED_PERF(hwp_cap) : 2932 HWP_HIGHEST_PERF(hwp_cap); 2933 2934 /* Optimization: Avoid unnecessary divisions. */ 2935 2936 target_pstate = cap_pstate; 2937 if (target_perf < capacity) 2938 target_pstate = DIV_ROUND_UP(cap_pstate * target_perf, capacity); 2939 2940 min_pstate = cap_pstate; 2941 if (min_perf < capacity) 2942 min_pstate = DIV_ROUND_UP(cap_pstate * min_perf, capacity); 2943 2944 if (min_pstate < cpu->pstate.min_pstate) 2945 min_pstate = cpu->pstate.min_pstate; 2946 2947 if (min_pstate < cpu->min_perf_ratio) 2948 min_pstate = cpu->min_perf_ratio; 2949 2950 if (min_pstate > cpu->max_perf_ratio) 2951 min_pstate = cpu->max_perf_ratio; 2952 2953 max_pstate = min(cap_pstate, cpu->max_perf_ratio); 2954 if (max_pstate < min_pstate) 2955 max_pstate = min_pstate; 2956 2957 target_pstate = clamp_t(int, target_pstate, min_pstate, max_pstate); 2958 2959 intel_cpufreq_hwp_update(cpu, min_pstate, max_pstate, target_pstate, true); 2960 2961 cpu->pstate.current_pstate = target_pstate; 2962 intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_FAST_SWITCH, old_pstate); 2963 } 2964 2965 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy) 2966 { 2967 struct freq_qos_request *req; 2968 struct cpudata *cpu; 2969 struct device *dev; 2970 int ret, freq; 2971 2972 dev = get_cpu_device(policy->cpu); 2973 if (!dev) 2974 return -ENODEV; 2975 2976 ret = __intel_pstate_cpu_init(policy); 2977 if (ret) 2978 return ret; 2979 2980 policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY; 2981 /* This reflects the intel_pstate_get_cpu_pstates() setting. */ 2982 policy->cur = policy->cpuinfo.min_freq; 2983 2984 req = kcalloc(2, sizeof(*req), GFP_KERNEL); 2985 if (!req) { 2986 ret = -ENOMEM; 2987 goto pstate_exit; 2988 } 2989 2990 cpu = all_cpu_data[policy->cpu]; 2991 2992 if (hwp_active) { 2993 u64 value; 2994 2995 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY_HWP; 2996 2997 intel_pstate_get_hwp_cap(cpu); 2998 2999 rdmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, &value); 3000 WRITE_ONCE(cpu->hwp_req_cached, value); 3001 3002 cpu->epp_cached = intel_pstate_get_epp(cpu, value); 3003 } else { 3004 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY; 3005 } 3006 3007 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.min_perf_pct, 100); 3008 3009 ret = freq_qos_add_request(&policy->constraints, req, FREQ_QOS_MIN, 3010 freq); 3011 if (ret < 0) { 3012 dev_err(dev, "Failed to add min-freq constraint (%d)\n", ret); 3013 goto free_req; 3014 } 3015 3016 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.max_perf_pct, 100); 3017 3018 ret = freq_qos_add_request(&policy->constraints, req + 1, FREQ_QOS_MAX, 3019 freq); 3020 if (ret < 0) { 3021 dev_err(dev, "Failed to add max-freq constraint (%d)\n", ret); 3022 goto remove_min_req; 3023 } 3024 3025 policy->driver_data = req; 3026 3027 return 0; 3028 3029 remove_min_req: 3030 freq_qos_remove_request(req); 3031 free_req: 3032 kfree(req); 3033 pstate_exit: 3034 intel_pstate_exit_perf_limits(policy); 3035 3036 return ret; 3037 } 3038 3039 static int intel_cpufreq_cpu_exit(struct cpufreq_policy *policy) 3040 { 3041 struct freq_qos_request *req; 3042 3043 req = policy->driver_data; 3044 3045 freq_qos_remove_request(req + 1); 3046 freq_qos_remove_request(req); 3047 kfree(req); 3048 3049 return intel_pstate_cpu_exit(policy); 3050 } 3051 3052 static int intel_cpufreq_suspend(struct cpufreq_policy *policy) 3053 { 3054 intel_pstate_suspend(policy); 3055 3056 if (hwp_active) { 3057 struct cpudata *cpu = all_cpu_data[policy->cpu]; 3058 u64 value = READ_ONCE(cpu->hwp_req_cached); 3059 3060 /* 3061 * Clear the desired perf field in MSR_HWP_REQUEST in case 3062 * intel_cpufreq_adjust_perf() is in use and the last value 3063 * written by it may not be suitable. 3064 */ 3065 value &= ~HWP_DESIRED_PERF(~0L); 3066 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 3067 WRITE_ONCE(cpu->hwp_req_cached, value); 3068 } 3069 3070 return 0; 3071 } 3072 3073 static struct cpufreq_driver intel_cpufreq = { 3074 .flags = CPUFREQ_CONST_LOOPS, 3075 .verify = intel_cpufreq_verify_policy, 3076 .target = intel_cpufreq_target, 3077 .fast_switch = intel_cpufreq_fast_switch, 3078 .init = intel_cpufreq_cpu_init, 3079 .exit = intel_cpufreq_cpu_exit, 3080 .offline = intel_cpufreq_cpu_offline, 3081 .online = intel_pstate_cpu_online, 3082 .suspend = intel_cpufreq_suspend, 3083 .resume = intel_pstate_resume, 3084 .update_limits = intel_pstate_update_limits, 3085 .name = "intel_cpufreq", 3086 }; 3087 3088 static struct cpufreq_driver *default_driver; 3089 3090 static void intel_pstate_driver_cleanup(void) 3091 { 3092 unsigned int cpu; 3093 3094 cpus_read_lock(); 3095 for_each_online_cpu(cpu) { 3096 if (all_cpu_data[cpu]) { 3097 if (intel_pstate_driver == &intel_pstate) 3098 intel_pstate_clear_update_util_hook(cpu); 3099 3100 kfree(all_cpu_data[cpu]); 3101 WRITE_ONCE(all_cpu_data[cpu], NULL); 3102 } 3103 } 3104 cpus_read_unlock(); 3105 3106 intel_pstate_driver = NULL; 3107 } 3108 3109 static int intel_pstate_register_driver(struct cpufreq_driver *driver) 3110 { 3111 int ret; 3112 3113 if (driver == &intel_pstate) 3114 intel_pstate_sysfs_expose_hwp_dynamic_boost(); 3115 3116 memset(&global, 0, sizeof(global)); 3117 global.max_perf_pct = 100; 3118 global.turbo_disabled = turbo_is_disabled(); 3119 global.no_turbo = global.turbo_disabled; 3120 3121 arch_set_max_freq_ratio(global.turbo_disabled); 3122 3123 intel_pstate_driver = driver; 3124 ret = cpufreq_register_driver(intel_pstate_driver); 3125 if (ret) { 3126 intel_pstate_driver_cleanup(); 3127 return ret; 3128 } 3129 3130 global.min_perf_pct = min_perf_pct_min(); 3131 3132 return 0; 3133 } 3134 3135 static ssize_t intel_pstate_show_status(char *buf) 3136 { 3137 if (!intel_pstate_driver) 3138 return sprintf(buf, "off\n"); 3139 3140 return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ? 3141 "active" : "passive"); 3142 } 3143 3144 static int intel_pstate_update_status(const char *buf, size_t size) 3145 { 3146 if (size == 3 && !strncmp(buf, "off", size)) { 3147 if (!intel_pstate_driver) 3148 return -EINVAL; 3149 3150 if (hwp_active) 3151 return -EBUSY; 3152 3153 cpufreq_unregister_driver(intel_pstate_driver); 3154 intel_pstate_driver_cleanup(); 3155 return 0; 3156 } 3157 3158 if (size == 6 && !strncmp(buf, "active", size)) { 3159 if (intel_pstate_driver) { 3160 if (intel_pstate_driver == &intel_pstate) 3161 return 0; 3162 3163 cpufreq_unregister_driver(intel_pstate_driver); 3164 } 3165 3166 return intel_pstate_register_driver(&intel_pstate); 3167 } 3168 3169 if (size == 7 && !strncmp(buf, "passive", size)) { 3170 if (intel_pstate_driver) { 3171 if (intel_pstate_driver == &intel_cpufreq) 3172 return 0; 3173 3174 cpufreq_unregister_driver(intel_pstate_driver); 3175 intel_pstate_sysfs_hide_hwp_dynamic_boost(); 3176 } 3177 3178 return intel_pstate_register_driver(&intel_cpufreq); 3179 } 3180 3181 return -EINVAL; 3182 } 3183 3184 static int no_load __initdata; 3185 static int no_hwp __initdata; 3186 static int hwp_only __initdata; 3187 static unsigned int force_load __initdata; 3188 3189 static int __init intel_pstate_msrs_not_valid(void) 3190 { 3191 if (!pstate_funcs.get_max(0) || 3192 !pstate_funcs.get_min(0) || 3193 !pstate_funcs.get_turbo(0)) 3194 return -ENODEV; 3195 3196 return 0; 3197 } 3198 3199 static void __init copy_cpu_funcs(struct pstate_funcs *funcs) 3200 { 3201 pstate_funcs.get_max = funcs->get_max; 3202 pstate_funcs.get_max_physical = funcs->get_max_physical; 3203 pstate_funcs.get_min = funcs->get_min; 3204 pstate_funcs.get_turbo = funcs->get_turbo; 3205 pstate_funcs.get_scaling = funcs->get_scaling; 3206 pstate_funcs.get_val = funcs->get_val; 3207 pstate_funcs.get_vid = funcs->get_vid; 3208 pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift; 3209 } 3210 3211 #ifdef CONFIG_ACPI 3212 3213 static bool __init intel_pstate_no_acpi_pss(void) 3214 { 3215 int i; 3216 3217 for_each_possible_cpu(i) { 3218 acpi_status status; 3219 union acpi_object *pss; 3220 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; 3221 struct acpi_processor *pr = per_cpu(processors, i); 3222 3223 if (!pr) 3224 continue; 3225 3226 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer); 3227 if (ACPI_FAILURE(status)) 3228 continue; 3229 3230 pss = buffer.pointer; 3231 if (pss && pss->type == ACPI_TYPE_PACKAGE) { 3232 kfree(pss); 3233 return false; 3234 } 3235 3236 kfree(pss); 3237 } 3238 3239 pr_debug("ACPI _PSS not found\n"); 3240 return true; 3241 } 3242 3243 static bool __init intel_pstate_no_acpi_pcch(void) 3244 { 3245 acpi_status status; 3246 acpi_handle handle; 3247 3248 status = acpi_get_handle(NULL, "\\_SB", &handle); 3249 if (ACPI_FAILURE(status)) 3250 goto not_found; 3251 3252 if (acpi_has_method(handle, "PCCH")) 3253 return false; 3254 3255 not_found: 3256 pr_debug("ACPI PCCH not found\n"); 3257 return true; 3258 } 3259 3260 static bool __init intel_pstate_has_acpi_ppc(void) 3261 { 3262 int i; 3263 3264 for_each_possible_cpu(i) { 3265 struct acpi_processor *pr = per_cpu(processors, i); 3266 3267 if (!pr) 3268 continue; 3269 if (acpi_has_method(pr->handle, "_PPC")) 3270 return true; 3271 } 3272 pr_debug("ACPI _PPC not found\n"); 3273 return false; 3274 } 3275 3276 enum { 3277 PSS, 3278 PPC, 3279 }; 3280 3281 /* Hardware vendor-specific info that has its own power management modes */ 3282 static struct acpi_platform_list plat_info[] __initdata = { 3283 {"HP ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, NULL, PSS}, 3284 {"ORACLE", "X4-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3285 {"ORACLE", "X4-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3286 {"ORACLE", "X4-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3287 {"ORACLE", "X3-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3288 {"ORACLE", "X3-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3289 {"ORACLE", "X3-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3290 {"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3291 {"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3292 {"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3293 {"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3294 {"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3295 {"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3296 {"ORACLE", "X6-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3297 {"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3298 { } /* End */ 3299 }; 3300 3301 #define BITMASK_OOB (BIT(8) | BIT(18)) 3302 3303 static bool __init intel_pstate_platform_pwr_mgmt_exists(void) 3304 { 3305 const struct x86_cpu_id *id; 3306 u64 misc_pwr; 3307 int idx; 3308 3309 id = x86_match_cpu(intel_pstate_cpu_oob_ids); 3310 if (id) { 3311 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr); 3312 if (misc_pwr & BITMASK_OOB) { 3313 pr_debug("Bit 8 or 18 in the MISC_PWR_MGMT MSR set\n"); 3314 pr_debug("P states are controlled in Out of Band mode by the firmware/hardware\n"); 3315 return true; 3316 } 3317 } 3318 3319 idx = acpi_match_platform_list(plat_info); 3320 if (idx < 0) 3321 return false; 3322 3323 switch (plat_info[idx].data) { 3324 case PSS: 3325 if (!intel_pstate_no_acpi_pss()) 3326 return false; 3327 3328 return intel_pstate_no_acpi_pcch(); 3329 case PPC: 3330 return intel_pstate_has_acpi_ppc() && !force_load; 3331 } 3332 3333 return false; 3334 } 3335 3336 static void intel_pstate_request_control_from_smm(void) 3337 { 3338 /* 3339 * It may be unsafe to request P-states control from SMM if _PPC support 3340 * has not been enabled. 3341 */ 3342 if (acpi_ppc) 3343 acpi_processor_pstate_control(); 3344 } 3345 #else /* CONFIG_ACPI not enabled */ 3346 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; } 3347 static inline bool intel_pstate_has_acpi_ppc(void) { return false; } 3348 static inline void intel_pstate_request_control_from_smm(void) {} 3349 #endif /* CONFIG_ACPI */ 3350 3351 #define INTEL_PSTATE_HWP_BROADWELL 0x01 3352 3353 #define X86_MATCH_HWP(model, hwp_mode) \ 3354 X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \ 3355 X86_FEATURE_HWP, hwp_mode) 3356 3357 static const struct x86_cpu_id hwp_support_ids[] __initconst = { 3358 X86_MATCH_HWP(BROADWELL_X, INTEL_PSTATE_HWP_BROADWELL), 3359 X86_MATCH_HWP(BROADWELL_D, INTEL_PSTATE_HWP_BROADWELL), 3360 X86_MATCH_HWP(ANY, 0), 3361 {} 3362 }; 3363 3364 static bool intel_pstate_hwp_is_enabled(void) 3365 { 3366 u64 value; 3367 3368 rdmsrl(MSR_PM_ENABLE, value); 3369 return !!(value & 0x1); 3370 } 3371 3372 #define POWERSAVE_MASK GENMASK(7, 0) 3373 #define BALANCE_POWER_MASK GENMASK(15, 8) 3374 #define BALANCE_PERFORMANCE_MASK GENMASK(23, 16) 3375 #define PERFORMANCE_MASK GENMASK(31, 24) 3376 3377 #define HWP_SET_EPP_VALUES(powersave, balance_power, balance_perf, performance) \ 3378 (FIELD_PREP_CONST(POWERSAVE_MASK, powersave) |\ 3379 FIELD_PREP_CONST(BALANCE_POWER_MASK, balance_power) |\ 3380 FIELD_PREP_CONST(BALANCE_PERFORMANCE_MASK, balance_perf) |\ 3381 FIELD_PREP_CONST(PERFORMANCE_MASK, performance)) 3382 3383 #define HWP_SET_DEF_BALANCE_PERF_EPP(balance_perf) \ 3384 (HWP_SET_EPP_VALUES(HWP_EPP_POWERSAVE, HWP_EPP_BALANCE_POWERSAVE,\ 3385 balance_perf, HWP_EPP_PERFORMANCE)) 3386 3387 static const struct x86_cpu_id intel_epp_default[] = { 3388 /* 3389 * Set EPP value as 102, this is the max suggested EPP 3390 * which can result in one core turbo frequency for 3391 * AlderLake Mobile CPUs. 3392 */ 3393 X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, HWP_SET_DEF_BALANCE_PERF_EPP(102)), 3394 X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, HWP_SET_DEF_BALANCE_PERF_EPP(32)), 3395 X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE_L, HWP_SET_EPP_VALUES(HWP_EPP_POWERSAVE, 3396 HWP_EPP_BALANCE_POWERSAVE, 115, 16)), 3397 {} 3398 }; 3399 3400 static const struct x86_cpu_id intel_hybrid_scaling_factor[] = { 3401 X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE_L, HYBRID_SCALING_FACTOR_MTL), 3402 {} 3403 }; 3404 3405 static int __init intel_pstate_init(void) 3406 { 3407 static struct cpudata **_all_cpu_data; 3408 const struct x86_cpu_id *id; 3409 int rc; 3410 3411 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) 3412 return -ENODEV; 3413 3414 id = x86_match_cpu(hwp_support_ids); 3415 if (id) { 3416 hwp_forced = intel_pstate_hwp_is_enabled(); 3417 3418 if (hwp_forced) 3419 pr_info("HWP enabled by BIOS\n"); 3420 else if (no_load) 3421 return -ENODEV; 3422 3423 copy_cpu_funcs(&core_funcs); 3424 /* 3425 * Avoid enabling HWP for processors without EPP support, 3426 * because that means incomplete HWP implementation which is a 3427 * corner case and supporting it is generally problematic. 3428 * 3429 * If HWP is enabled already, though, there is no choice but to 3430 * deal with it. 3431 */ 3432 if ((!no_hwp && boot_cpu_has(X86_FEATURE_HWP_EPP)) || hwp_forced) { 3433 hwp_active = true; 3434 hwp_mode_bdw = id->driver_data; 3435 intel_pstate.attr = hwp_cpufreq_attrs; 3436 intel_cpufreq.attr = hwp_cpufreq_attrs; 3437 intel_cpufreq.flags |= CPUFREQ_NEED_UPDATE_LIMITS; 3438 intel_cpufreq.adjust_perf = intel_cpufreq_adjust_perf; 3439 if (!default_driver) 3440 default_driver = &intel_pstate; 3441 3442 pstate_funcs.get_cpu_scaling = hwp_get_cpu_scaling; 3443 3444 goto hwp_cpu_matched; 3445 } 3446 pr_info("HWP not enabled\n"); 3447 } else { 3448 if (no_load) 3449 return -ENODEV; 3450 3451 id = x86_match_cpu(intel_pstate_cpu_ids); 3452 if (!id) { 3453 pr_info("CPU model not supported\n"); 3454 return -ENODEV; 3455 } 3456 3457 copy_cpu_funcs((struct pstate_funcs *)id->driver_data); 3458 } 3459 3460 if (intel_pstate_msrs_not_valid()) { 3461 pr_info("Invalid MSRs\n"); 3462 return -ENODEV; 3463 } 3464 /* Without HWP start in the passive mode. */ 3465 if (!default_driver) 3466 default_driver = &intel_cpufreq; 3467 3468 hwp_cpu_matched: 3469 /* 3470 * The Intel pstate driver will be ignored if the platform 3471 * firmware has its own power management modes. 3472 */ 3473 if (intel_pstate_platform_pwr_mgmt_exists()) { 3474 pr_info("P-states controlled by the platform\n"); 3475 return -ENODEV; 3476 } 3477 3478 if (!hwp_active && hwp_only) 3479 return -ENOTSUPP; 3480 3481 pr_info("Intel P-state driver initializing\n"); 3482 3483 _all_cpu_data = vzalloc(array_size(sizeof(void *), num_possible_cpus())); 3484 if (!_all_cpu_data) 3485 return -ENOMEM; 3486 3487 WRITE_ONCE(all_cpu_data, _all_cpu_data); 3488 3489 intel_pstate_request_control_from_smm(); 3490 3491 intel_pstate_sysfs_expose_params(); 3492 3493 if (hwp_active) { 3494 const struct x86_cpu_id *id = x86_match_cpu(intel_epp_default); 3495 const struct x86_cpu_id *hybrid_id = x86_match_cpu(intel_hybrid_scaling_factor); 3496 3497 if (id) { 3498 epp_values[EPP_INDEX_POWERSAVE] = 3499 FIELD_GET(POWERSAVE_MASK, id->driver_data); 3500 epp_values[EPP_INDEX_BALANCE_POWERSAVE] = 3501 FIELD_GET(BALANCE_POWER_MASK, id->driver_data); 3502 epp_values[EPP_INDEX_BALANCE_PERFORMANCE] = 3503 FIELD_GET(BALANCE_PERFORMANCE_MASK, id->driver_data); 3504 epp_values[EPP_INDEX_PERFORMANCE] = 3505 FIELD_GET(PERFORMANCE_MASK, id->driver_data); 3506 pr_debug("Updated EPPs powersave:%x balanced power:%x balanced perf:%x performance:%x\n", 3507 epp_values[EPP_INDEX_POWERSAVE], 3508 epp_values[EPP_INDEX_BALANCE_POWERSAVE], 3509 epp_values[EPP_INDEX_BALANCE_PERFORMANCE], 3510 epp_values[EPP_INDEX_PERFORMANCE]); 3511 } 3512 3513 if (hybrid_id) { 3514 hybrid_scaling_factor = hybrid_id->driver_data; 3515 pr_debug("hybrid scaling factor: %d\n", hybrid_scaling_factor); 3516 } 3517 3518 } 3519 3520 mutex_lock(&intel_pstate_driver_lock); 3521 rc = intel_pstate_register_driver(default_driver); 3522 mutex_unlock(&intel_pstate_driver_lock); 3523 if (rc) { 3524 intel_pstate_sysfs_remove(); 3525 return rc; 3526 } 3527 3528 if (hwp_active) { 3529 const struct x86_cpu_id *id; 3530 3531 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids); 3532 if (id) { 3533 set_power_ctl_ee_state(false); 3534 pr_info("Disabling energy efficiency optimization\n"); 3535 } 3536 3537 pr_info("HWP enabled\n"); 3538 } else if (boot_cpu_has(X86_FEATURE_HYBRID_CPU)) { 3539 pr_warn("Problematic setup: Hybrid processor with disabled HWP\n"); 3540 } 3541 3542 return 0; 3543 } 3544 device_initcall(intel_pstate_init); 3545 3546 static int __init intel_pstate_setup(char *str) 3547 { 3548 if (!str) 3549 return -EINVAL; 3550 3551 if (!strcmp(str, "disable")) 3552 no_load = 1; 3553 else if (!strcmp(str, "active")) 3554 default_driver = &intel_pstate; 3555 else if (!strcmp(str, "passive")) 3556 default_driver = &intel_cpufreq; 3557 3558 if (!strcmp(str, "no_hwp")) 3559 no_hwp = 1; 3560 3561 if (!strcmp(str, "force")) 3562 force_load = 1; 3563 if (!strcmp(str, "hwp_only")) 3564 hwp_only = 1; 3565 if (!strcmp(str, "per_cpu_perf_limits")) 3566 per_cpu_limits = true; 3567 3568 #ifdef CONFIG_ACPI 3569 if (!strcmp(str, "support_acpi_ppc")) 3570 acpi_ppc = true; 3571 #endif 3572 3573 return 0; 3574 } 3575 early_param("intel_pstate", intel_pstate_setup); 3576 3577 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>"); 3578 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors"); 3579