1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * intel_pstate.c: Native P state management for Intel processors 4 * 5 * (C) Copyright 2012 Intel Corporation 6 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com> 7 */ 8 9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10 11 #include <linux/kernel.h> 12 #include <linux/kernel_stat.h> 13 #include <linux/module.h> 14 #include <linux/ktime.h> 15 #include <linux/hrtimer.h> 16 #include <linux/tick.h> 17 #include <linux/slab.h> 18 #include <linux/sched/cpufreq.h> 19 #include <linux/list.h> 20 #include <linux/cpu.h> 21 #include <linux/cpufreq.h> 22 #include <linux/sysfs.h> 23 #include <linux/types.h> 24 #include <linux/fs.h> 25 #include <linux/acpi.h> 26 #include <linux/vmalloc.h> 27 #include <linux/pm_qos.h> 28 #include <trace/events/power.h> 29 30 #include <asm/cpu.h> 31 #include <asm/div64.h> 32 #include <asm/msr.h> 33 #include <asm/cpu_device_id.h> 34 #include <asm/cpufeature.h> 35 #include <asm/intel-family.h> 36 #include "../drivers/thermal/intel/thermal_interrupt.h" 37 38 #define INTEL_PSTATE_SAMPLING_INTERVAL (10 * NSEC_PER_MSEC) 39 40 #define INTEL_CPUFREQ_TRANSITION_LATENCY 20000 41 #define INTEL_CPUFREQ_TRANSITION_DELAY_HWP 5000 42 #define INTEL_CPUFREQ_TRANSITION_DELAY 500 43 44 #ifdef CONFIG_ACPI 45 #include <acpi/processor.h> 46 #include <acpi/cppc_acpi.h> 47 #endif 48 49 #define FRAC_BITS 8 50 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS) 51 #define fp_toint(X) ((X) >> FRAC_BITS) 52 53 #define ONE_EIGHTH_FP ((int64_t)1 << (FRAC_BITS - 3)) 54 55 #define EXT_BITS 6 56 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS) 57 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS) 58 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS) 59 60 static inline int32_t mul_fp(int32_t x, int32_t y) 61 { 62 return ((int64_t)x * (int64_t)y) >> FRAC_BITS; 63 } 64 65 static inline int32_t div_fp(s64 x, s64 y) 66 { 67 return div64_s64((int64_t)x << FRAC_BITS, y); 68 } 69 70 static inline int ceiling_fp(int32_t x) 71 { 72 int mask, ret; 73 74 ret = fp_toint(x); 75 mask = (1 << FRAC_BITS) - 1; 76 if (x & mask) 77 ret += 1; 78 return ret; 79 } 80 81 static inline u64 mul_ext_fp(u64 x, u64 y) 82 { 83 return (x * y) >> EXT_FRAC_BITS; 84 } 85 86 static inline u64 div_ext_fp(u64 x, u64 y) 87 { 88 return div64_u64(x << EXT_FRAC_BITS, y); 89 } 90 91 /** 92 * struct sample - Store performance sample 93 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average 94 * performance during last sample period 95 * @busy_scaled: Scaled busy value which is used to calculate next 96 * P state. This can be different than core_avg_perf 97 * to account for cpu idle period 98 * @aperf: Difference of actual performance frequency clock count 99 * read from APERF MSR between last and current sample 100 * @mperf: Difference of maximum performance frequency clock count 101 * read from MPERF MSR between last and current sample 102 * @tsc: Difference of time stamp counter between last and 103 * current sample 104 * @time: Current time from scheduler 105 * 106 * This structure is used in the cpudata structure to store performance sample 107 * data for choosing next P State. 108 */ 109 struct sample { 110 int32_t core_avg_perf; 111 int32_t busy_scaled; 112 u64 aperf; 113 u64 mperf; 114 u64 tsc; 115 u64 time; 116 }; 117 118 /** 119 * struct pstate_data - Store P state data 120 * @current_pstate: Current requested P state 121 * @min_pstate: Min P state possible for this platform 122 * @max_pstate: Max P state possible for this platform 123 * @max_pstate_physical:This is physical Max P state for a processor 124 * This can be higher than the max_pstate which can 125 * be limited by platform thermal design power limits 126 * @perf_ctl_scaling: PERF_CTL P-state to frequency scaling factor 127 * @scaling: Scaling factor between performance and frequency 128 * @turbo_pstate: Max Turbo P state possible for this platform 129 * @min_freq: @min_pstate frequency in cpufreq units 130 * @max_freq: @max_pstate frequency in cpufreq units 131 * @turbo_freq: @turbo_pstate frequency in cpufreq units 132 * 133 * Stores the per cpu model P state limits and current P state. 134 */ 135 struct pstate_data { 136 int current_pstate; 137 int min_pstate; 138 int max_pstate; 139 int max_pstate_physical; 140 int perf_ctl_scaling; 141 int scaling; 142 int turbo_pstate; 143 unsigned int min_freq; 144 unsigned int max_freq; 145 unsigned int turbo_freq; 146 }; 147 148 /** 149 * struct vid_data - Stores voltage information data 150 * @min: VID data for this platform corresponding to 151 * the lowest P state 152 * @max: VID data corresponding to the highest P State. 153 * @turbo: VID data for turbo P state 154 * @ratio: Ratio of (vid max - vid min) / 155 * (max P state - Min P State) 156 * 157 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling) 158 * This data is used in Atom platforms, where in addition to target P state, 159 * the voltage data needs to be specified to select next P State. 160 */ 161 struct vid_data { 162 int min; 163 int max; 164 int turbo; 165 int32_t ratio; 166 }; 167 168 /** 169 * struct global_params - Global parameters, mostly tunable via sysfs. 170 * @no_turbo: Whether or not to use turbo P-states. 171 * @turbo_disabled: Whether or not turbo P-states are available at all, 172 * based on the MSR_IA32_MISC_ENABLE value and whether or 173 * not the maximum reported turbo P-state is different from 174 * the maximum reported non-turbo one. 175 * @turbo_disabled_mf: The @turbo_disabled value reflected by cpuinfo.max_freq. 176 * @min_perf_pct: Minimum capacity limit in percent of the maximum turbo 177 * P-state capacity. 178 * @max_perf_pct: Maximum capacity limit in percent of the maximum turbo 179 * P-state capacity. 180 */ 181 struct global_params { 182 bool no_turbo; 183 bool turbo_disabled; 184 bool turbo_disabled_mf; 185 int max_perf_pct; 186 int min_perf_pct; 187 }; 188 189 /** 190 * struct cpudata - Per CPU instance data storage 191 * @cpu: CPU number for this instance data 192 * @policy: CPUFreq policy value 193 * @update_util: CPUFreq utility callback information 194 * @update_util_set: CPUFreq utility callback is set 195 * @iowait_boost: iowait-related boost fraction 196 * @last_update: Time of the last update. 197 * @pstate: Stores P state limits for this CPU 198 * @vid: Stores VID limits for this CPU 199 * @last_sample_time: Last Sample time 200 * @aperf_mperf_shift: APERF vs MPERF counting frequency difference 201 * @prev_aperf: Last APERF value read from APERF MSR 202 * @prev_mperf: Last MPERF value read from MPERF MSR 203 * @prev_tsc: Last timestamp counter (TSC) value 204 * @prev_cummulative_iowait: IO Wait time difference from last and 205 * current sample 206 * @sample: Storage for storing last Sample data 207 * @min_perf_ratio: Minimum capacity in terms of PERF or HWP ratios 208 * @max_perf_ratio: Maximum capacity in terms of PERF or HWP ratios 209 * @acpi_perf_data: Stores ACPI perf information read from _PSS 210 * @valid_pss_table: Set to true for valid ACPI _PSS entries found 211 * @epp_powersave: Last saved HWP energy performance preference 212 * (EPP) or energy performance bias (EPB), 213 * when policy switched to performance 214 * @epp_policy: Last saved policy used to set EPP/EPB 215 * @epp_default: Power on default HWP energy performance 216 * preference/bias 217 * @epp_cached Cached HWP energy-performance preference value 218 * @hwp_req_cached: Cached value of the last HWP Request MSR 219 * @hwp_cap_cached: Cached value of the last HWP Capabilities MSR 220 * @last_io_update: Last time when IO wake flag was set 221 * @sched_flags: Store scheduler flags for possible cross CPU update 222 * @hwp_boost_min: Last HWP boosted min performance 223 * @suspended: Whether or not the driver has been suspended. 224 * @hwp_notify_work: workqueue for HWP notifications. 225 * 226 * This structure stores per CPU instance data for all CPUs. 227 */ 228 struct cpudata { 229 int cpu; 230 231 unsigned int policy; 232 struct update_util_data update_util; 233 bool update_util_set; 234 235 struct pstate_data pstate; 236 struct vid_data vid; 237 238 u64 last_update; 239 u64 last_sample_time; 240 u64 aperf_mperf_shift; 241 u64 prev_aperf; 242 u64 prev_mperf; 243 u64 prev_tsc; 244 u64 prev_cummulative_iowait; 245 struct sample sample; 246 int32_t min_perf_ratio; 247 int32_t max_perf_ratio; 248 #ifdef CONFIG_ACPI 249 struct acpi_processor_performance acpi_perf_data; 250 bool valid_pss_table; 251 #endif 252 unsigned int iowait_boost; 253 s16 epp_powersave; 254 s16 epp_policy; 255 s16 epp_default; 256 s16 epp_cached; 257 u64 hwp_req_cached; 258 u64 hwp_cap_cached; 259 u64 last_io_update; 260 unsigned int sched_flags; 261 u32 hwp_boost_min; 262 bool suspended; 263 struct delayed_work hwp_notify_work; 264 }; 265 266 static struct cpudata **all_cpu_data; 267 268 /** 269 * struct pstate_funcs - Per CPU model specific callbacks 270 * @get_max: Callback to get maximum non turbo effective P state 271 * @get_max_physical: Callback to get maximum non turbo physical P state 272 * @get_min: Callback to get minimum P state 273 * @get_turbo: Callback to get turbo P state 274 * @get_scaling: Callback to get frequency scaling factor 275 * @get_cpu_scaling: Get frequency scaling factor for a given cpu 276 * @get_aperf_mperf_shift: Callback to get the APERF vs MPERF frequency difference 277 * @get_val: Callback to convert P state to actual MSR write value 278 * @get_vid: Callback to get VID data for Atom platforms 279 * 280 * Core and Atom CPU models have different way to get P State limits. This 281 * structure is used to store those callbacks. 282 */ 283 struct pstate_funcs { 284 int (*get_max)(int cpu); 285 int (*get_max_physical)(int cpu); 286 int (*get_min)(int cpu); 287 int (*get_turbo)(int cpu); 288 int (*get_scaling)(void); 289 int (*get_cpu_scaling)(int cpu); 290 int (*get_aperf_mperf_shift)(void); 291 u64 (*get_val)(struct cpudata*, int pstate); 292 void (*get_vid)(struct cpudata *); 293 }; 294 295 static struct pstate_funcs pstate_funcs __read_mostly; 296 297 static int hwp_active __read_mostly; 298 static int hwp_mode_bdw __read_mostly; 299 static bool per_cpu_limits __read_mostly; 300 static bool hwp_boost __read_mostly; 301 static bool hwp_forced __read_mostly; 302 303 static struct cpufreq_driver *intel_pstate_driver __read_mostly; 304 305 #define HYBRID_SCALING_FACTOR 78741 306 #define HYBRID_SCALING_FACTOR_MTL 80000 307 308 static int hybrid_scaling_factor = HYBRID_SCALING_FACTOR; 309 310 static inline int core_get_scaling(void) 311 { 312 return 100000; 313 } 314 315 #ifdef CONFIG_ACPI 316 static bool acpi_ppc; 317 #endif 318 319 static struct global_params global; 320 321 static DEFINE_MUTEX(intel_pstate_driver_lock); 322 static DEFINE_MUTEX(intel_pstate_limits_lock); 323 324 #ifdef CONFIG_ACPI 325 326 static bool intel_pstate_acpi_pm_profile_server(void) 327 { 328 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER || 329 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER) 330 return true; 331 332 return false; 333 } 334 335 static bool intel_pstate_get_ppc_enable_status(void) 336 { 337 if (intel_pstate_acpi_pm_profile_server()) 338 return true; 339 340 return acpi_ppc; 341 } 342 343 #ifdef CONFIG_ACPI_CPPC_LIB 344 345 /* The work item is needed to avoid CPU hotplug locking issues */ 346 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work) 347 { 348 sched_set_itmt_support(); 349 } 350 351 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn); 352 353 #define CPPC_MAX_PERF U8_MAX 354 355 static void intel_pstate_set_itmt_prio(int cpu) 356 { 357 struct cppc_perf_caps cppc_perf; 358 static u32 max_highest_perf = 0, min_highest_perf = U32_MAX; 359 int ret; 360 361 ret = cppc_get_perf_caps(cpu, &cppc_perf); 362 if (ret) 363 return; 364 365 /* 366 * On some systems with overclocking enabled, CPPC.highest_perf is hardcoded to 0xff. 367 * In this case we can't use CPPC.highest_perf to enable ITMT. 368 * In this case we can look at MSR_HWP_CAPABILITIES bits [8:0] to decide. 369 */ 370 if (cppc_perf.highest_perf == CPPC_MAX_PERF) 371 cppc_perf.highest_perf = HWP_HIGHEST_PERF(READ_ONCE(all_cpu_data[cpu]->hwp_cap_cached)); 372 373 /* 374 * The priorities can be set regardless of whether or not 375 * sched_set_itmt_support(true) has been called and it is valid to 376 * update them at any time after it has been called. 377 */ 378 sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu); 379 380 if (max_highest_perf <= min_highest_perf) { 381 if (cppc_perf.highest_perf > max_highest_perf) 382 max_highest_perf = cppc_perf.highest_perf; 383 384 if (cppc_perf.highest_perf < min_highest_perf) 385 min_highest_perf = cppc_perf.highest_perf; 386 387 if (max_highest_perf > min_highest_perf) { 388 /* 389 * This code can be run during CPU online under the 390 * CPU hotplug locks, so sched_set_itmt_support() 391 * cannot be called from here. Queue up a work item 392 * to invoke it. 393 */ 394 schedule_work(&sched_itmt_work); 395 } 396 } 397 } 398 399 static int intel_pstate_get_cppc_guaranteed(int cpu) 400 { 401 struct cppc_perf_caps cppc_perf; 402 int ret; 403 404 ret = cppc_get_perf_caps(cpu, &cppc_perf); 405 if (ret) 406 return ret; 407 408 if (cppc_perf.guaranteed_perf) 409 return cppc_perf.guaranteed_perf; 410 411 return cppc_perf.nominal_perf; 412 } 413 414 static int intel_pstate_cppc_get_scaling(int cpu) 415 { 416 struct cppc_perf_caps cppc_perf; 417 int ret; 418 419 ret = cppc_get_perf_caps(cpu, &cppc_perf); 420 421 /* 422 * If the nominal frequency and the nominal performance are not 423 * zero and the ratio between them is not 100, return the hybrid 424 * scaling factor. 425 */ 426 if (!ret && cppc_perf.nominal_perf && cppc_perf.nominal_freq && 427 cppc_perf.nominal_perf * 100 != cppc_perf.nominal_freq) 428 return hybrid_scaling_factor; 429 430 return core_get_scaling(); 431 } 432 433 #else /* CONFIG_ACPI_CPPC_LIB */ 434 static inline void intel_pstate_set_itmt_prio(int cpu) 435 { 436 } 437 #endif /* CONFIG_ACPI_CPPC_LIB */ 438 439 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) 440 { 441 struct cpudata *cpu; 442 int ret; 443 int i; 444 445 if (hwp_active) { 446 intel_pstate_set_itmt_prio(policy->cpu); 447 return; 448 } 449 450 if (!intel_pstate_get_ppc_enable_status()) 451 return; 452 453 cpu = all_cpu_data[policy->cpu]; 454 455 ret = acpi_processor_register_performance(&cpu->acpi_perf_data, 456 policy->cpu); 457 if (ret) 458 return; 459 460 /* 461 * Check if the control value in _PSS is for PERF_CTL MSR, which should 462 * guarantee that the states returned by it map to the states in our 463 * list directly. 464 */ 465 if (cpu->acpi_perf_data.control_register.space_id != 466 ACPI_ADR_SPACE_FIXED_HARDWARE) 467 goto err; 468 469 /* 470 * If there is only one entry _PSS, simply ignore _PSS and continue as 471 * usual without taking _PSS into account 472 */ 473 if (cpu->acpi_perf_data.state_count < 2) 474 goto err; 475 476 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu); 477 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) { 478 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n", 479 (i == cpu->acpi_perf_data.state ? '*' : ' '), i, 480 (u32) cpu->acpi_perf_data.states[i].core_frequency, 481 (u32) cpu->acpi_perf_data.states[i].power, 482 (u32) cpu->acpi_perf_data.states[i].control); 483 } 484 485 cpu->valid_pss_table = true; 486 pr_debug("_PPC limits will be enforced\n"); 487 488 return; 489 490 err: 491 cpu->valid_pss_table = false; 492 acpi_processor_unregister_performance(policy->cpu); 493 } 494 495 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) 496 { 497 struct cpudata *cpu; 498 499 cpu = all_cpu_data[policy->cpu]; 500 if (!cpu->valid_pss_table) 501 return; 502 503 acpi_processor_unregister_performance(policy->cpu); 504 } 505 #else /* CONFIG_ACPI */ 506 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) 507 { 508 } 509 510 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) 511 { 512 } 513 514 static inline bool intel_pstate_acpi_pm_profile_server(void) 515 { 516 return false; 517 } 518 #endif /* CONFIG_ACPI */ 519 520 #ifndef CONFIG_ACPI_CPPC_LIB 521 static inline int intel_pstate_get_cppc_guaranteed(int cpu) 522 { 523 return -ENOTSUPP; 524 } 525 526 static int intel_pstate_cppc_get_scaling(int cpu) 527 { 528 return core_get_scaling(); 529 } 530 #endif /* CONFIG_ACPI_CPPC_LIB */ 531 532 /** 533 * intel_pstate_hybrid_hwp_adjust - Calibrate HWP performance levels. 534 * @cpu: Target CPU. 535 * 536 * On hybrid processors, HWP may expose more performance levels than there are 537 * P-states accessible through the PERF_CTL interface. If that happens, the 538 * scaling factor between HWP performance levels and CPU frequency will be less 539 * than the scaling factor between P-state values and CPU frequency. 540 * 541 * In that case, adjust the CPU parameters used in computations accordingly. 542 */ 543 static void intel_pstate_hybrid_hwp_adjust(struct cpudata *cpu) 544 { 545 int perf_ctl_max_phys = cpu->pstate.max_pstate_physical; 546 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling; 547 int perf_ctl_turbo = pstate_funcs.get_turbo(cpu->cpu); 548 int scaling = cpu->pstate.scaling; 549 550 pr_debug("CPU%d: perf_ctl_max_phys = %d\n", cpu->cpu, perf_ctl_max_phys); 551 pr_debug("CPU%d: perf_ctl_turbo = %d\n", cpu->cpu, perf_ctl_turbo); 552 pr_debug("CPU%d: perf_ctl_scaling = %d\n", cpu->cpu, perf_ctl_scaling); 553 pr_debug("CPU%d: HWP_CAP guaranteed = %d\n", cpu->cpu, cpu->pstate.max_pstate); 554 pr_debug("CPU%d: HWP_CAP highest = %d\n", cpu->cpu, cpu->pstate.turbo_pstate); 555 pr_debug("CPU%d: HWP-to-frequency scaling factor: %d\n", cpu->cpu, scaling); 556 557 cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_pstate * scaling, 558 perf_ctl_scaling); 559 cpu->pstate.max_freq = rounddown(cpu->pstate.max_pstate * scaling, 560 perf_ctl_scaling); 561 562 cpu->pstate.max_pstate_physical = 563 DIV_ROUND_UP(perf_ctl_max_phys * perf_ctl_scaling, 564 scaling); 565 566 cpu->pstate.min_freq = cpu->pstate.min_pstate * perf_ctl_scaling; 567 /* 568 * Cast the min P-state value retrieved via pstate_funcs.get_min() to 569 * the effective range of HWP performance levels. 570 */ 571 cpu->pstate.min_pstate = DIV_ROUND_UP(cpu->pstate.min_freq, scaling); 572 } 573 574 static inline void update_turbo_state(void) 575 { 576 u64 misc_en; 577 578 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en); 579 global.turbo_disabled = misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE; 580 } 581 582 static int min_perf_pct_min(void) 583 { 584 struct cpudata *cpu = all_cpu_data[0]; 585 int turbo_pstate = cpu->pstate.turbo_pstate; 586 587 return turbo_pstate ? 588 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0; 589 } 590 591 static s16 intel_pstate_get_epb(struct cpudata *cpu_data) 592 { 593 u64 epb; 594 int ret; 595 596 if (!boot_cpu_has(X86_FEATURE_EPB)) 597 return -ENXIO; 598 599 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb); 600 if (ret) 601 return (s16)ret; 602 603 return (s16)(epb & 0x0f); 604 } 605 606 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data) 607 { 608 s16 epp; 609 610 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 611 /* 612 * When hwp_req_data is 0, means that caller didn't read 613 * MSR_HWP_REQUEST, so need to read and get EPP. 614 */ 615 if (!hwp_req_data) { 616 epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, 617 &hwp_req_data); 618 if (epp) 619 return epp; 620 } 621 epp = (hwp_req_data >> 24) & 0xff; 622 } else { 623 /* When there is no EPP present, HWP uses EPB settings */ 624 epp = intel_pstate_get_epb(cpu_data); 625 } 626 627 return epp; 628 } 629 630 static int intel_pstate_set_epb(int cpu, s16 pref) 631 { 632 u64 epb; 633 int ret; 634 635 if (!boot_cpu_has(X86_FEATURE_EPB)) 636 return -ENXIO; 637 638 ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb); 639 if (ret) 640 return ret; 641 642 epb = (epb & ~0x0f) | pref; 643 wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb); 644 645 return 0; 646 } 647 648 /* 649 * EPP/EPB display strings corresponding to EPP index in the 650 * energy_perf_strings[] 651 * index String 652 *------------------------------------- 653 * 0 default 654 * 1 performance 655 * 2 balance_performance 656 * 3 balance_power 657 * 4 power 658 */ 659 660 enum energy_perf_value_index { 661 EPP_INDEX_DEFAULT = 0, 662 EPP_INDEX_PERFORMANCE, 663 EPP_INDEX_BALANCE_PERFORMANCE, 664 EPP_INDEX_BALANCE_POWERSAVE, 665 EPP_INDEX_POWERSAVE, 666 }; 667 668 static const char * const energy_perf_strings[] = { 669 [EPP_INDEX_DEFAULT] = "default", 670 [EPP_INDEX_PERFORMANCE] = "performance", 671 [EPP_INDEX_BALANCE_PERFORMANCE] = "balance_performance", 672 [EPP_INDEX_BALANCE_POWERSAVE] = "balance_power", 673 [EPP_INDEX_POWERSAVE] = "power", 674 NULL 675 }; 676 static unsigned int epp_values[] = { 677 [EPP_INDEX_DEFAULT] = 0, /* Unused index */ 678 [EPP_INDEX_PERFORMANCE] = HWP_EPP_PERFORMANCE, 679 [EPP_INDEX_BALANCE_PERFORMANCE] = HWP_EPP_BALANCE_PERFORMANCE, 680 [EPP_INDEX_BALANCE_POWERSAVE] = HWP_EPP_BALANCE_POWERSAVE, 681 [EPP_INDEX_POWERSAVE] = HWP_EPP_POWERSAVE, 682 }; 683 684 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data, int *raw_epp) 685 { 686 s16 epp; 687 int index = -EINVAL; 688 689 *raw_epp = 0; 690 epp = intel_pstate_get_epp(cpu_data, 0); 691 if (epp < 0) 692 return epp; 693 694 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 695 if (epp == epp_values[EPP_INDEX_PERFORMANCE]) 696 return EPP_INDEX_PERFORMANCE; 697 if (epp == epp_values[EPP_INDEX_BALANCE_PERFORMANCE]) 698 return EPP_INDEX_BALANCE_PERFORMANCE; 699 if (epp == epp_values[EPP_INDEX_BALANCE_POWERSAVE]) 700 return EPP_INDEX_BALANCE_POWERSAVE; 701 if (epp == epp_values[EPP_INDEX_POWERSAVE]) 702 return EPP_INDEX_POWERSAVE; 703 *raw_epp = epp; 704 return 0; 705 } else if (boot_cpu_has(X86_FEATURE_EPB)) { 706 /* 707 * Range: 708 * 0x00-0x03 : Performance 709 * 0x04-0x07 : Balance performance 710 * 0x08-0x0B : Balance power 711 * 0x0C-0x0F : Power 712 * The EPB is a 4 bit value, but our ranges restrict the 713 * value which can be set. Here only using top two bits 714 * effectively. 715 */ 716 index = (epp >> 2) + 1; 717 } 718 719 return index; 720 } 721 722 static int intel_pstate_set_epp(struct cpudata *cpu, u32 epp) 723 { 724 int ret; 725 726 /* 727 * Use the cached HWP Request MSR value, because in the active mode the 728 * register itself may be updated by intel_pstate_hwp_boost_up() or 729 * intel_pstate_hwp_boost_down() at any time. 730 */ 731 u64 value = READ_ONCE(cpu->hwp_req_cached); 732 733 value &= ~GENMASK_ULL(31, 24); 734 value |= (u64)epp << 24; 735 /* 736 * The only other updater of hwp_req_cached in the active mode, 737 * intel_pstate_hwp_set(), is called under the same lock as this 738 * function, so it cannot run in parallel with the update below. 739 */ 740 WRITE_ONCE(cpu->hwp_req_cached, value); 741 ret = wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 742 if (!ret) 743 cpu->epp_cached = epp; 744 745 return ret; 746 } 747 748 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data, 749 int pref_index, bool use_raw, 750 u32 raw_epp) 751 { 752 int epp = -EINVAL; 753 int ret; 754 755 if (!pref_index) 756 epp = cpu_data->epp_default; 757 758 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 759 if (use_raw) 760 epp = raw_epp; 761 else if (epp == -EINVAL) 762 epp = epp_values[pref_index]; 763 764 /* 765 * To avoid confusion, refuse to set EPP to any values different 766 * from 0 (performance) if the current policy is "performance", 767 * because those values would be overridden. 768 */ 769 if (epp > 0 && cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) 770 return -EBUSY; 771 772 ret = intel_pstate_set_epp(cpu_data, epp); 773 } else { 774 if (epp == -EINVAL) 775 epp = (pref_index - 1) << 2; 776 ret = intel_pstate_set_epb(cpu_data->cpu, epp); 777 } 778 779 return ret; 780 } 781 782 static ssize_t show_energy_performance_available_preferences( 783 struct cpufreq_policy *policy, char *buf) 784 { 785 int i = 0; 786 int ret = 0; 787 788 while (energy_perf_strings[i] != NULL) 789 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]); 790 791 ret += sprintf(&buf[ret], "\n"); 792 793 return ret; 794 } 795 796 cpufreq_freq_attr_ro(energy_performance_available_preferences); 797 798 static struct cpufreq_driver intel_pstate; 799 800 static ssize_t store_energy_performance_preference( 801 struct cpufreq_policy *policy, const char *buf, size_t count) 802 { 803 struct cpudata *cpu = all_cpu_data[policy->cpu]; 804 char str_preference[21]; 805 bool raw = false; 806 ssize_t ret; 807 u32 epp = 0; 808 809 ret = sscanf(buf, "%20s", str_preference); 810 if (ret != 1) 811 return -EINVAL; 812 813 ret = match_string(energy_perf_strings, -1, str_preference); 814 if (ret < 0) { 815 if (!boot_cpu_has(X86_FEATURE_HWP_EPP)) 816 return ret; 817 818 ret = kstrtouint(buf, 10, &epp); 819 if (ret) 820 return ret; 821 822 if (epp > 255) 823 return -EINVAL; 824 825 raw = true; 826 } 827 828 /* 829 * This function runs with the policy R/W semaphore held, which 830 * guarantees that the driver pointer will not change while it is 831 * running. 832 */ 833 if (!intel_pstate_driver) 834 return -EAGAIN; 835 836 mutex_lock(&intel_pstate_limits_lock); 837 838 if (intel_pstate_driver == &intel_pstate) { 839 ret = intel_pstate_set_energy_pref_index(cpu, ret, raw, epp); 840 } else { 841 /* 842 * In the passive mode the governor needs to be stopped on the 843 * target CPU before the EPP update and restarted after it, 844 * which is super-heavy-weight, so make sure it is worth doing 845 * upfront. 846 */ 847 if (!raw) 848 epp = ret ? epp_values[ret] : cpu->epp_default; 849 850 if (cpu->epp_cached != epp) { 851 int err; 852 853 cpufreq_stop_governor(policy); 854 ret = intel_pstate_set_epp(cpu, epp); 855 err = cpufreq_start_governor(policy); 856 if (!ret) 857 ret = err; 858 } else { 859 ret = 0; 860 } 861 } 862 863 mutex_unlock(&intel_pstate_limits_lock); 864 865 return ret ?: count; 866 } 867 868 static ssize_t show_energy_performance_preference( 869 struct cpufreq_policy *policy, char *buf) 870 { 871 struct cpudata *cpu_data = all_cpu_data[policy->cpu]; 872 int preference, raw_epp; 873 874 preference = intel_pstate_get_energy_pref_index(cpu_data, &raw_epp); 875 if (preference < 0) 876 return preference; 877 878 if (raw_epp) 879 return sprintf(buf, "%d\n", raw_epp); 880 else 881 return sprintf(buf, "%s\n", energy_perf_strings[preference]); 882 } 883 884 cpufreq_freq_attr_rw(energy_performance_preference); 885 886 static ssize_t show_base_frequency(struct cpufreq_policy *policy, char *buf) 887 { 888 struct cpudata *cpu = all_cpu_data[policy->cpu]; 889 int ratio, freq; 890 891 ratio = intel_pstate_get_cppc_guaranteed(policy->cpu); 892 if (ratio <= 0) { 893 u64 cap; 894 895 rdmsrl_on_cpu(policy->cpu, MSR_HWP_CAPABILITIES, &cap); 896 ratio = HWP_GUARANTEED_PERF(cap); 897 } 898 899 freq = ratio * cpu->pstate.scaling; 900 if (cpu->pstate.scaling != cpu->pstate.perf_ctl_scaling) 901 freq = rounddown(freq, cpu->pstate.perf_ctl_scaling); 902 903 return sprintf(buf, "%d\n", freq); 904 } 905 906 cpufreq_freq_attr_ro(base_frequency); 907 908 static struct freq_attr *hwp_cpufreq_attrs[] = { 909 &energy_performance_preference, 910 &energy_performance_available_preferences, 911 &base_frequency, 912 NULL, 913 }; 914 915 static void __intel_pstate_get_hwp_cap(struct cpudata *cpu) 916 { 917 u64 cap; 918 919 rdmsrl_on_cpu(cpu->cpu, MSR_HWP_CAPABILITIES, &cap); 920 WRITE_ONCE(cpu->hwp_cap_cached, cap); 921 cpu->pstate.max_pstate = HWP_GUARANTEED_PERF(cap); 922 cpu->pstate.turbo_pstate = HWP_HIGHEST_PERF(cap); 923 } 924 925 static void intel_pstate_get_hwp_cap(struct cpudata *cpu) 926 { 927 int scaling = cpu->pstate.scaling; 928 929 __intel_pstate_get_hwp_cap(cpu); 930 931 cpu->pstate.max_freq = cpu->pstate.max_pstate * scaling; 932 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * scaling; 933 if (scaling != cpu->pstate.perf_ctl_scaling) { 934 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling; 935 936 cpu->pstate.max_freq = rounddown(cpu->pstate.max_freq, 937 perf_ctl_scaling); 938 cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_freq, 939 perf_ctl_scaling); 940 } 941 } 942 943 static void intel_pstate_hwp_set(unsigned int cpu) 944 { 945 struct cpudata *cpu_data = all_cpu_data[cpu]; 946 int max, min; 947 u64 value; 948 s16 epp; 949 950 max = cpu_data->max_perf_ratio; 951 min = cpu_data->min_perf_ratio; 952 953 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) 954 min = max; 955 956 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value); 957 958 value &= ~HWP_MIN_PERF(~0L); 959 value |= HWP_MIN_PERF(min); 960 961 value &= ~HWP_MAX_PERF(~0L); 962 value |= HWP_MAX_PERF(max); 963 964 if (cpu_data->epp_policy == cpu_data->policy) 965 goto skip_epp; 966 967 cpu_data->epp_policy = cpu_data->policy; 968 969 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) { 970 epp = intel_pstate_get_epp(cpu_data, value); 971 cpu_data->epp_powersave = epp; 972 /* If EPP read was failed, then don't try to write */ 973 if (epp < 0) 974 goto skip_epp; 975 976 epp = 0; 977 } else { 978 /* skip setting EPP, when saved value is invalid */ 979 if (cpu_data->epp_powersave < 0) 980 goto skip_epp; 981 982 /* 983 * No need to restore EPP when it is not zero. This 984 * means: 985 * - Policy is not changed 986 * - user has manually changed 987 * - Error reading EPB 988 */ 989 epp = intel_pstate_get_epp(cpu_data, value); 990 if (epp) 991 goto skip_epp; 992 993 epp = cpu_data->epp_powersave; 994 } 995 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 996 value &= ~GENMASK_ULL(31, 24); 997 value |= (u64)epp << 24; 998 } else { 999 intel_pstate_set_epb(cpu, epp); 1000 } 1001 skip_epp: 1002 WRITE_ONCE(cpu_data->hwp_req_cached, value); 1003 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value); 1004 } 1005 1006 static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata); 1007 1008 static void intel_pstate_hwp_offline(struct cpudata *cpu) 1009 { 1010 u64 value = READ_ONCE(cpu->hwp_req_cached); 1011 int min_perf; 1012 1013 intel_pstate_disable_hwp_interrupt(cpu); 1014 1015 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 1016 /* 1017 * In case the EPP has been set to "performance" by the 1018 * active mode "performance" scaling algorithm, replace that 1019 * temporary value with the cached EPP one. 1020 */ 1021 value &= ~GENMASK_ULL(31, 24); 1022 value |= HWP_ENERGY_PERF_PREFERENCE(cpu->epp_cached); 1023 /* 1024 * However, make sure that EPP will be set to "performance" when 1025 * the CPU is brought back online again and the "performance" 1026 * scaling algorithm is still in effect. 1027 */ 1028 cpu->epp_policy = CPUFREQ_POLICY_UNKNOWN; 1029 } 1030 1031 /* 1032 * Clear the desired perf field in the cached HWP request value to 1033 * prevent nonzero desired values from being leaked into the active 1034 * mode. 1035 */ 1036 value &= ~HWP_DESIRED_PERF(~0L); 1037 WRITE_ONCE(cpu->hwp_req_cached, value); 1038 1039 value &= ~GENMASK_ULL(31, 0); 1040 min_perf = HWP_LOWEST_PERF(READ_ONCE(cpu->hwp_cap_cached)); 1041 1042 /* Set hwp_max = hwp_min */ 1043 value |= HWP_MAX_PERF(min_perf); 1044 value |= HWP_MIN_PERF(min_perf); 1045 1046 /* Set EPP to min */ 1047 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) 1048 value |= HWP_ENERGY_PERF_PREFERENCE(HWP_EPP_POWERSAVE); 1049 1050 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 1051 } 1052 1053 #define POWER_CTL_EE_ENABLE 1 1054 #define POWER_CTL_EE_DISABLE 2 1055 1056 static int power_ctl_ee_state; 1057 1058 static void set_power_ctl_ee_state(bool input) 1059 { 1060 u64 power_ctl; 1061 1062 mutex_lock(&intel_pstate_driver_lock); 1063 rdmsrl(MSR_IA32_POWER_CTL, power_ctl); 1064 if (input) { 1065 power_ctl &= ~BIT(MSR_IA32_POWER_CTL_BIT_EE); 1066 power_ctl_ee_state = POWER_CTL_EE_ENABLE; 1067 } else { 1068 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE); 1069 power_ctl_ee_state = POWER_CTL_EE_DISABLE; 1070 } 1071 wrmsrl(MSR_IA32_POWER_CTL, power_ctl); 1072 mutex_unlock(&intel_pstate_driver_lock); 1073 } 1074 1075 static void intel_pstate_hwp_enable(struct cpudata *cpudata); 1076 1077 static void intel_pstate_hwp_reenable(struct cpudata *cpu) 1078 { 1079 intel_pstate_hwp_enable(cpu); 1080 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, READ_ONCE(cpu->hwp_req_cached)); 1081 } 1082 1083 static int intel_pstate_suspend(struct cpufreq_policy *policy) 1084 { 1085 struct cpudata *cpu = all_cpu_data[policy->cpu]; 1086 1087 pr_debug("CPU %d suspending\n", cpu->cpu); 1088 1089 cpu->suspended = true; 1090 1091 /* disable HWP interrupt and cancel any pending work */ 1092 intel_pstate_disable_hwp_interrupt(cpu); 1093 1094 return 0; 1095 } 1096 1097 static int intel_pstate_resume(struct cpufreq_policy *policy) 1098 { 1099 struct cpudata *cpu = all_cpu_data[policy->cpu]; 1100 1101 pr_debug("CPU %d resuming\n", cpu->cpu); 1102 1103 /* Only restore if the system default is changed */ 1104 if (power_ctl_ee_state == POWER_CTL_EE_ENABLE) 1105 set_power_ctl_ee_state(true); 1106 else if (power_ctl_ee_state == POWER_CTL_EE_DISABLE) 1107 set_power_ctl_ee_state(false); 1108 1109 if (cpu->suspended && hwp_active) { 1110 mutex_lock(&intel_pstate_limits_lock); 1111 1112 /* Re-enable HWP, because "online" has not done that. */ 1113 intel_pstate_hwp_reenable(cpu); 1114 1115 mutex_unlock(&intel_pstate_limits_lock); 1116 } 1117 1118 cpu->suspended = false; 1119 1120 return 0; 1121 } 1122 1123 static void intel_pstate_update_policies(void) 1124 { 1125 int cpu; 1126 1127 for_each_possible_cpu(cpu) 1128 cpufreq_update_policy(cpu); 1129 } 1130 1131 static void __intel_pstate_update_max_freq(struct cpudata *cpudata, 1132 struct cpufreq_policy *policy) 1133 { 1134 policy->cpuinfo.max_freq = global.turbo_disabled_mf ? 1135 cpudata->pstate.max_freq : cpudata->pstate.turbo_freq; 1136 refresh_frequency_limits(policy); 1137 } 1138 1139 static void intel_pstate_update_max_freq(unsigned int cpu) 1140 { 1141 struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpu); 1142 1143 if (!policy) 1144 return; 1145 1146 __intel_pstate_update_max_freq(all_cpu_data[cpu], policy); 1147 1148 cpufreq_cpu_release(policy); 1149 } 1150 1151 static void intel_pstate_update_limits(unsigned int cpu) 1152 { 1153 mutex_lock(&intel_pstate_driver_lock); 1154 1155 update_turbo_state(); 1156 /* 1157 * If turbo has been turned on or off globally, policy limits for 1158 * all CPUs need to be updated to reflect that. 1159 */ 1160 if (global.turbo_disabled_mf != global.turbo_disabled) { 1161 global.turbo_disabled_mf = global.turbo_disabled; 1162 arch_set_max_freq_ratio(global.turbo_disabled); 1163 for_each_possible_cpu(cpu) 1164 intel_pstate_update_max_freq(cpu); 1165 } else { 1166 cpufreq_update_policy(cpu); 1167 } 1168 1169 mutex_unlock(&intel_pstate_driver_lock); 1170 } 1171 1172 /************************** sysfs begin ************************/ 1173 #define show_one(file_name, object) \ 1174 static ssize_t show_##file_name \ 1175 (struct kobject *kobj, struct kobj_attribute *attr, char *buf) \ 1176 { \ 1177 return sprintf(buf, "%u\n", global.object); \ 1178 } 1179 1180 static ssize_t intel_pstate_show_status(char *buf); 1181 static int intel_pstate_update_status(const char *buf, size_t size); 1182 1183 static ssize_t show_status(struct kobject *kobj, 1184 struct kobj_attribute *attr, char *buf) 1185 { 1186 ssize_t ret; 1187 1188 mutex_lock(&intel_pstate_driver_lock); 1189 ret = intel_pstate_show_status(buf); 1190 mutex_unlock(&intel_pstate_driver_lock); 1191 1192 return ret; 1193 } 1194 1195 static ssize_t store_status(struct kobject *a, struct kobj_attribute *b, 1196 const char *buf, size_t count) 1197 { 1198 char *p = memchr(buf, '\n', count); 1199 int ret; 1200 1201 mutex_lock(&intel_pstate_driver_lock); 1202 ret = intel_pstate_update_status(buf, p ? p - buf : count); 1203 mutex_unlock(&intel_pstate_driver_lock); 1204 1205 return ret < 0 ? ret : count; 1206 } 1207 1208 static ssize_t show_turbo_pct(struct kobject *kobj, 1209 struct kobj_attribute *attr, char *buf) 1210 { 1211 struct cpudata *cpu; 1212 int total, no_turbo, turbo_pct; 1213 uint32_t turbo_fp; 1214 1215 mutex_lock(&intel_pstate_driver_lock); 1216 1217 if (!intel_pstate_driver) { 1218 mutex_unlock(&intel_pstate_driver_lock); 1219 return -EAGAIN; 1220 } 1221 1222 cpu = all_cpu_data[0]; 1223 1224 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; 1225 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1; 1226 turbo_fp = div_fp(no_turbo, total); 1227 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100))); 1228 1229 mutex_unlock(&intel_pstate_driver_lock); 1230 1231 return sprintf(buf, "%u\n", turbo_pct); 1232 } 1233 1234 static ssize_t show_num_pstates(struct kobject *kobj, 1235 struct kobj_attribute *attr, char *buf) 1236 { 1237 struct cpudata *cpu; 1238 int total; 1239 1240 mutex_lock(&intel_pstate_driver_lock); 1241 1242 if (!intel_pstate_driver) { 1243 mutex_unlock(&intel_pstate_driver_lock); 1244 return -EAGAIN; 1245 } 1246 1247 cpu = all_cpu_data[0]; 1248 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; 1249 1250 mutex_unlock(&intel_pstate_driver_lock); 1251 1252 return sprintf(buf, "%u\n", total); 1253 } 1254 1255 static ssize_t show_no_turbo(struct kobject *kobj, 1256 struct kobj_attribute *attr, char *buf) 1257 { 1258 ssize_t ret; 1259 1260 mutex_lock(&intel_pstate_driver_lock); 1261 1262 if (!intel_pstate_driver) { 1263 mutex_unlock(&intel_pstate_driver_lock); 1264 return -EAGAIN; 1265 } 1266 1267 update_turbo_state(); 1268 if (global.turbo_disabled) 1269 ret = sprintf(buf, "%u\n", global.turbo_disabled); 1270 else 1271 ret = sprintf(buf, "%u\n", global.no_turbo); 1272 1273 mutex_unlock(&intel_pstate_driver_lock); 1274 1275 return ret; 1276 } 1277 1278 static ssize_t store_no_turbo(struct kobject *a, struct kobj_attribute *b, 1279 const char *buf, size_t count) 1280 { 1281 unsigned int input; 1282 int ret; 1283 1284 ret = sscanf(buf, "%u", &input); 1285 if (ret != 1) 1286 return -EINVAL; 1287 1288 mutex_lock(&intel_pstate_driver_lock); 1289 1290 if (!intel_pstate_driver) { 1291 mutex_unlock(&intel_pstate_driver_lock); 1292 return -EAGAIN; 1293 } 1294 1295 mutex_lock(&intel_pstate_limits_lock); 1296 1297 update_turbo_state(); 1298 if (global.turbo_disabled) { 1299 pr_notice_once("Turbo disabled by BIOS or unavailable on processor\n"); 1300 mutex_unlock(&intel_pstate_limits_lock); 1301 mutex_unlock(&intel_pstate_driver_lock); 1302 return -EPERM; 1303 } 1304 1305 global.no_turbo = clamp_t(int, input, 0, 1); 1306 1307 if (global.no_turbo) { 1308 struct cpudata *cpu = all_cpu_data[0]; 1309 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate; 1310 1311 /* Squash the global minimum into the permitted range. */ 1312 if (global.min_perf_pct > pct) 1313 global.min_perf_pct = pct; 1314 } 1315 1316 mutex_unlock(&intel_pstate_limits_lock); 1317 1318 intel_pstate_update_policies(); 1319 arch_set_max_freq_ratio(global.no_turbo); 1320 1321 mutex_unlock(&intel_pstate_driver_lock); 1322 1323 return count; 1324 } 1325 1326 static void update_qos_request(enum freq_qos_req_type type) 1327 { 1328 struct freq_qos_request *req; 1329 struct cpufreq_policy *policy; 1330 int i; 1331 1332 for_each_possible_cpu(i) { 1333 struct cpudata *cpu = all_cpu_data[i]; 1334 unsigned int freq, perf_pct; 1335 1336 policy = cpufreq_cpu_get(i); 1337 if (!policy) 1338 continue; 1339 1340 req = policy->driver_data; 1341 cpufreq_cpu_put(policy); 1342 1343 if (!req) 1344 continue; 1345 1346 if (hwp_active) 1347 intel_pstate_get_hwp_cap(cpu); 1348 1349 if (type == FREQ_QOS_MIN) { 1350 perf_pct = global.min_perf_pct; 1351 } else { 1352 req++; 1353 perf_pct = global.max_perf_pct; 1354 } 1355 1356 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * perf_pct, 100); 1357 1358 if (freq_qos_update_request(req, freq) < 0) 1359 pr_warn("Failed to update freq constraint: CPU%d\n", i); 1360 } 1361 } 1362 1363 static ssize_t store_max_perf_pct(struct kobject *a, struct kobj_attribute *b, 1364 const char *buf, size_t count) 1365 { 1366 unsigned int input; 1367 int ret; 1368 1369 ret = sscanf(buf, "%u", &input); 1370 if (ret != 1) 1371 return -EINVAL; 1372 1373 mutex_lock(&intel_pstate_driver_lock); 1374 1375 if (!intel_pstate_driver) { 1376 mutex_unlock(&intel_pstate_driver_lock); 1377 return -EAGAIN; 1378 } 1379 1380 mutex_lock(&intel_pstate_limits_lock); 1381 1382 global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100); 1383 1384 mutex_unlock(&intel_pstate_limits_lock); 1385 1386 if (intel_pstate_driver == &intel_pstate) 1387 intel_pstate_update_policies(); 1388 else 1389 update_qos_request(FREQ_QOS_MAX); 1390 1391 mutex_unlock(&intel_pstate_driver_lock); 1392 1393 return count; 1394 } 1395 1396 static ssize_t store_min_perf_pct(struct kobject *a, struct kobj_attribute *b, 1397 const char *buf, size_t count) 1398 { 1399 unsigned int input; 1400 int ret; 1401 1402 ret = sscanf(buf, "%u", &input); 1403 if (ret != 1) 1404 return -EINVAL; 1405 1406 mutex_lock(&intel_pstate_driver_lock); 1407 1408 if (!intel_pstate_driver) { 1409 mutex_unlock(&intel_pstate_driver_lock); 1410 return -EAGAIN; 1411 } 1412 1413 mutex_lock(&intel_pstate_limits_lock); 1414 1415 global.min_perf_pct = clamp_t(int, input, 1416 min_perf_pct_min(), global.max_perf_pct); 1417 1418 mutex_unlock(&intel_pstate_limits_lock); 1419 1420 if (intel_pstate_driver == &intel_pstate) 1421 intel_pstate_update_policies(); 1422 else 1423 update_qos_request(FREQ_QOS_MIN); 1424 1425 mutex_unlock(&intel_pstate_driver_lock); 1426 1427 return count; 1428 } 1429 1430 static ssize_t show_hwp_dynamic_boost(struct kobject *kobj, 1431 struct kobj_attribute *attr, char *buf) 1432 { 1433 return sprintf(buf, "%u\n", hwp_boost); 1434 } 1435 1436 static ssize_t store_hwp_dynamic_boost(struct kobject *a, 1437 struct kobj_attribute *b, 1438 const char *buf, size_t count) 1439 { 1440 unsigned int input; 1441 int ret; 1442 1443 ret = kstrtouint(buf, 10, &input); 1444 if (ret) 1445 return ret; 1446 1447 mutex_lock(&intel_pstate_driver_lock); 1448 hwp_boost = !!input; 1449 intel_pstate_update_policies(); 1450 mutex_unlock(&intel_pstate_driver_lock); 1451 1452 return count; 1453 } 1454 1455 static ssize_t show_energy_efficiency(struct kobject *kobj, struct kobj_attribute *attr, 1456 char *buf) 1457 { 1458 u64 power_ctl; 1459 int enable; 1460 1461 rdmsrl(MSR_IA32_POWER_CTL, power_ctl); 1462 enable = !!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE)); 1463 return sprintf(buf, "%d\n", !enable); 1464 } 1465 1466 static ssize_t store_energy_efficiency(struct kobject *a, struct kobj_attribute *b, 1467 const char *buf, size_t count) 1468 { 1469 bool input; 1470 int ret; 1471 1472 ret = kstrtobool(buf, &input); 1473 if (ret) 1474 return ret; 1475 1476 set_power_ctl_ee_state(input); 1477 1478 return count; 1479 } 1480 1481 show_one(max_perf_pct, max_perf_pct); 1482 show_one(min_perf_pct, min_perf_pct); 1483 1484 define_one_global_rw(status); 1485 define_one_global_rw(no_turbo); 1486 define_one_global_rw(max_perf_pct); 1487 define_one_global_rw(min_perf_pct); 1488 define_one_global_ro(turbo_pct); 1489 define_one_global_ro(num_pstates); 1490 define_one_global_rw(hwp_dynamic_boost); 1491 define_one_global_rw(energy_efficiency); 1492 1493 static struct attribute *intel_pstate_attributes[] = { 1494 &status.attr, 1495 &no_turbo.attr, 1496 NULL 1497 }; 1498 1499 static const struct attribute_group intel_pstate_attr_group = { 1500 .attrs = intel_pstate_attributes, 1501 }; 1502 1503 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[]; 1504 1505 static struct kobject *intel_pstate_kobject; 1506 1507 static void __init intel_pstate_sysfs_expose_params(void) 1508 { 1509 struct device *dev_root = bus_get_dev_root(&cpu_subsys); 1510 int rc; 1511 1512 if (dev_root) { 1513 intel_pstate_kobject = kobject_create_and_add("intel_pstate", &dev_root->kobj); 1514 put_device(dev_root); 1515 } 1516 if (WARN_ON(!intel_pstate_kobject)) 1517 return; 1518 1519 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group); 1520 if (WARN_ON(rc)) 1521 return; 1522 1523 if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) { 1524 rc = sysfs_create_file(intel_pstate_kobject, &turbo_pct.attr); 1525 WARN_ON(rc); 1526 1527 rc = sysfs_create_file(intel_pstate_kobject, &num_pstates.attr); 1528 WARN_ON(rc); 1529 } 1530 1531 /* 1532 * If per cpu limits are enforced there are no global limits, so 1533 * return without creating max/min_perf_pct attributes 1534 */ 1535 if (per_cpu_limits) 1536 return; 1537 1538 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr); 1539 WARN_ON(rc); 1540 1541 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr); 1542 WARN_ON(rc); 1543 1544 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids)) { 1545 rc = sysfs_create_file(intel_pstate_kobject, &energy_efficiency.attr); 1546 WARN_ON(rc); 1547 } 1548 } 1549 1550 static void __init intel_pstate_sysfs_remove(void) 1551 { 1552 if (!intel_pstate_kobject) 1553 return; 1554 1555 sysfs_remove_group(intel_pstate_kobject, &intel_pstate_attr_group); 1556 1557 if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) { 1558 sysfs_remove_file(intel_pstate_kobject, &num_pstates.attr); 1559 sysfs_remove_file(intel_pstate_kobject, &turbo_pct.attr); 1560 } 1561 1562 if (!per_cpu_limits) { 1563 sysfs_remove_file(intel_pstate_kobject, &max_perf_pct.attr); 1564 sysfs_remove_file(intel_pstate_kobject, &min_perf_pct.attr); 1565 1566 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids)) 1567 sysfs_remove_file(intel_pstate_kobject, &energy_efficiency.attr); 1568 } 1569 1570 kobject_put(intel_pstate_kobject); 1571 } 1572 1573 static void intel_pstate_sysfs_expose_hwp_dynamic_boost(void) 1574 { 1575 int rc; 1576 1577 if (!hwp_active) 1578 return; 1579 1580 rc = sysfs_create_file(intel_pstate_kobject, &hwp_dynamic_boost.attr); 1581 WARN_ON_ONCE(rc); 1582 } 1583 1584 static void intel_pstate_sysfs_hide_hwp_dynamic_boost(void) 1585 { 1586 if (!hwp_active) 1587 return; 1588 1589 sysfs_remove_file(intel_pstate_kobject, &hwp_dynamic_boost.attr); 1590 } 1591 1592 /************************** sysfs end ************************/ 1593 1594 static void intel_pstate_notify_work(struct work_struct *work) 1595 { 1596 struct cpudata *cpudata = 1597 container_of(to_delayed_work(work), struct cpudata, hwp_notify_work); 1598 struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpudata->cpu); 1599 1600 if (policy) { 1601 intel_pstate_get_hwp_cap(cpudata); 1602 __intel_pstate_update_max_freq(cpudata, policy); 1603 1604 cpufreq_cpu_release(policy); 1605 } 1606 1607 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0); 1608 } 1609 1610 static DEFINE_SPINLOCK(hwp_notify_lock); 1611 static cpumask_t hwp_intr_enable_mask; 1612 1613 void notify_hwp_interrupt(void) 1614 { 1615 unsigned int this_cpu = smp_processor_id(); 1616 struct cpudata *cpudata; 1617 unsigned long flags; 1618 u64 value; 1619 1620 if (!READ_ONCE(hwp_active) || !boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) 1621 return; 1622 1623 rdmsrl_safe(MSR_HWP_STATUS, &value); 1624 if (!(value & 0x01)) 1625 return; 1626 1627 spin_lock_irqsave(&hwp_notify_lock, flags); 1628 1629 if (!cpumask_test_cpu(this_cpu, &hwp_intr_enable_mask)) 1630 goto ack_intr; 1631 1632 /* 1633 * Currently we never free all_cpu_data. And we can't reach here 1634 * without this allocated. But for safety for future changes, added 1635 * check. 1636 */ 1637 if (unlikely(!READ_ONCE(all_cpu_data))) 1638 goto ack_intr; 1639 1640 /* 1641 * The free is done during cleanup, when cpufreq registry is failed. 1642 * We wouldn't be here if it fails on init or switch status. But for 1643 * future changes, added check. 1644 */ 1645 cpudata = READ_ONCE(all_cpu_data[this_cpu]); 1646 if (unlikely(!cpudata)) 1647 goto ack_intr; 1648 1649 schedule_delayed_work(&cpudata->hwp_notify_work, msecs_to_jiffies(10)); 1650 1651 spin_unlock_irqrestore(&hwp_notify_lock, flags); 1652 1653 return; 1654 1655 ack_intr: 1656 wrmsrl_safe(MSR_HWP_STATUS, 0); 1657 spin_unlock_irqrestore(&hwp_notify_lock, flags); 1658 } 1659 1660 static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata) 1661 { 1662 unsigned long flags; 1663 1664 if (!boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) 1665 return; 1666 1667 /* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */ 1668 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00); 1669 1670 spin_lock_irqsave(&hwp_notify_lock, flags); 1671 if (cpumask_test_and_clear_cpu(cpudata->cpu, &hwp_intr_enable_mask)) 1672 cancel_delayed_work(&cpudata->hwp_notify_work); 1673 spin_unlock_irqrestore(&hwp_notify_lock, flags); 1674 } 1675 1676 static void intel_pstate_enable_hwp_interrupt(struct cpudata *cpudata) 1677 { 1678 /* Enable HWP notification interrupt for guaranteed performance change */ 1679 if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) { 1680 unsigned long flags; 1681 1682 spin_lock_irqsave(&hwp_notify_lock, flags); 1683 INIT_DELAYED_WORK(&cpudata->hwp_notify_work, intel_pstate_notify_work); 1684 cpumask_set_cpu(cpudata->cpu, &hwp_intr_enable_mask); 1685 spin_unlock_irqrestore(&hwp_notify_lock, flags); 1686 1687 /* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */ 1688 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x01); 1689 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0); 1690 } 1691 } 1692 1693 static void intel_pstate_update_epp_defaults(struct cpudata *cpudata) 1694 { 1695 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0); 1696 1697 /* 1698 * If the EPP is set by firmware, which means that firmware enabled HWP 1699 * - Is equal or less than 0x80 (default balance_perf EPP) 1700 * - But less performance oriented than performance EPP 1701 * then use this as new balance_perf EPP. 1702 */ 1703 if (hwp_forced && cpudata->epp_default <= HWP_EPP_BALANCE_PERFORMANCE && 1704 cpudata->epp_default > HWP_EPP_PERFORMANCE) { 1705 epp_values[EPP_INDEX_BALANCE_PERFORMANCE] = cpudata->epp_default; 1706 return; 1707 } 1708 1709 /* 1710 * If this CPU gen doesn't call for change in balance_perf 1711 * EPP return. 1712 */ 1713 if (epp_values[EPP_INDEX_BALANCE_PERFORMANCE] == HWP_EPP_BALANCE_PERFORMANCE) 1714 return; 1715 1716 /* 1717 * Use hard coded value per gen to update the balance_perf 1718 * and default EPP. 1719 */ 1720 cpudata->epp_default = epp_values[EPP_INDEX_BALANCE_PERFORMANCE]; 1721 intel_pstate_set_epp(cpudata, cpudata->epp_default); 1722 } 1723 1724 static void intel_pstate_hwp_enable(struct cpudata *cpudata) 1725 { 1726 /* First disable HWP notification interrupt till we activate again */ 1727 if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) 1728 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00); 1729 1730 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1); 1731 1732 intel_pstate_enable_hwp_interrupt(cpudata); 1733 1734 if (cpudata->epp_default >= 0) 1735 return; 1736 1737 intel_pstate_update_epp_defaults(cpudata); 1738 } 1739 1740 static int atom_get_min_pstate(int not_used) 1741 { 1742 u64 value; 1743 1744 rdmsrl(MSR_ATOM_CORE_RATIOS, value); 1745 return (value >> 8) & 0x7F; 1746 } 1747 1748 static int atom_get_max_pstate(int not_used) 1749 { 1750 u64 value; 1751 1752 rdmsrl(MSR_ATOM_CORE_RATIOS, value); 1753 return (value >> 16) & 0x7F; 1754 } 1755 1756 static int atom_get_turbo_pstate(int not_used) 1757 { 1758 u64 value; 1759 1760 rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value); 1761 return value & 0x7F; 1762 } 1763 1764 static u64 atom_get_val(struct cpudata *cpudata, int pstate) 1765 { 1766 u64 val; 1767 int32_t vid_fp; 1768 u32 vid; 1769 1770 val = (u64)pstate << 8; 1771 if (global.no_turbo && !global.turbo_disabled) 1772 val |= (u64)1 << 32; 1773 1774 vid_fp = cpudata->vid.min + mul_fp( 1775 int_tofp(pstate - cpudata->pstate.min_pstate), 1776 cpudata->vid.ratio); 1777 1778 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max); 1779 vid = ceiling_fp(vid_fp); 1780 1781 if (pstate > cpudata->pstate.max_pstate) 1782 vid = cpudata->vid.turbo; 1783 1784 return val | vid; 1785 } 1786 1787 static int silvermont_get_scaling(void) 1788 { 1789 u64 value; 1790 int i; 1791 /* Defined in Table 35-6 from SDM (Sept 2015) */ 1792 static int silvermont_freq_table[] = { 1793 83300, 100000, 133300, 116700, 80000}; 1794 1795 rdmsrl(MSR_FSB_FREQ, value); 1796 i = value & 0x7; 1797 WARN_ON(i > 4); 1798 1799 return silvermont_freq_table[i]; 1800 } 1801 1802 static int airmont_get_scaling(void) 1803 { 1804 u64 value; 1805 int i; 1806 /* Defined in Table 35-10 from SDM (Sept 2015) */ 1807 static int airmont_freq_table[] = { 1808 83300, 100000, 133300, 116700, 80000, 1809 93300, 90000, 88900, 87500}; 1810 1811 rdmsrl(MSR_FSB_FREQ, value); 1812 i = value & 0xF; 1813 WARN_ON(i > 8); 1814 1815 return airmont_freq_table[i]; 1816 } 1817 1818 static void atom_get_vid(struct cpudata *cpudata) 1819 { 1820 u64 value; 1821 1822 rdmsrl(MSR_ATOM_CORE_VIDS, value); 1823 cpudata->vid.min = int_tofp((value >> 8) & 0x7f); 1824 cpudata->vid.max = int_tofp((value >> 16) & 0x7f); 1825 cpudata->vid.ratio = div_fp( 1826 cpudata->vid.max - cpudata->vid.min, 1827 int_tofp(cpudata->pstate.max_pstate - 1828 cpudata->pstate.min_pstate)); 1829 1830 rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value); 1831 cpudata->vid.turbo = value & 0x7f; 1832 } 1833 1834 static int core_get_min_pstate(int cpu) 1835 { 1836 u64 value; 1837 1838 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &value); 1839 return (value >> 40) & 0xFF; 1840 } 1841 1842 static int core_get_max_pstate_physical(int cpu) 1843 { 1844 u64 value; 1845 1846 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &value); 1847 return (value >> 8) & 0xFF; 1848 } 1849 1850 static int core_get_tdp_ratio(int cpu, u64 plat_info) 1851 { 1852 /* Check how many TDP levels present */ 1853 if (plat_info & 0x600000000) { 1854 u64 tdp_ctrl; 1855 u64 tdp_ratio; 1856 int tdp_msr; 1857 int err; 1858 1859 /* Get the TDP level (0, 1, 2) to get ratios */ 1860 err = rdmsrl_safe_on_cpu(cpu, MSR_CONFIG_TDP_CONTROL, &tdp_ctrl); 1861 if (err) 1862 return err; 1863 1864 /* TDP MSR are continuous starting at 0x648 */ 1865 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03); 1866 err = rdmsrl_safe_on_cpu(cpu, tdp_msr, &tdp_ratio); 1867 if (err) 1868 return err; 1869 1870 /* For level 1 and 2, bits[23:16] contain the ratio */ 1871 if (tdp_ctrl & 0x03) 1872 tdp_ratio >>= 16; 1873 1874 tdp_ratio &= 0xff; /* ratios are only 8 bits long */ 1875 pr_debug("tdp_ratio %x\n", (int)tdp_ratio); 1876 1877 return (int)tdp_ratio; 1878 } 1879 1880 return -ENXIO; 1881 } 1882 1883 static int core_get_max_pstate(int cpu) 1884 { 1885 u64 tar; 1886 u64 plat_info; 1887 int max_pstate; 1888 int tdp_ratio; 1889 int err; 1890 1891 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &plat_info); 1892 max_pstate = (plat_info >> 8) & 0xFF; 1893 1894 tdp_ratio = core_get_tdp_ratio(cpu, plat_info); 1895 if (tdp_ratio <= 0) 1896 return max_pstate; 1897 1898 if (hwp_active) { 1899 /* Turbo activation ratio is not used on HWP platforms */ 1900 return tdp_ratio; 1901 } 1902 1903 err = rdmsrl_safe_on_cpu(cpu, MSR_TURBO_ACTIVATION_RATIO, &tar); 1904 if (!err) { 1905 int tar_levels; 1906 1907 /* Do some sanity checking for safety */ 1908 tar_levels = tar & 0xff; 1909 if (tdp_ratio - 1 == tar_levels) { 1910 max_pstate = tar_levels; 1911 pr_debug("max_pstate=TAC %x\n", max_pstate); 1912 } 1913 } 1914 1915 return max_pstate; 1916 } 1917 1918 static int core_get_turbo_pstate(int cpu) 1919 { 1920 u64 value; 1921 int nont, ret; 1922 1923 rdmsrl_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value); 1924 nont = core_get_max_pstate(cpu); 1925 ret = (value) & 255; 1926 if (ret <= nont) 1927 ret = nont; 1928 return ret; 1929 } 1930 1931 static u64 core_get_val(struct cpudata *cpudata, int pstate) 1932 { 1933 u64 val; 1934 1935 val = (u64)pstate << 8; 1936 if (global.no_turbo && !global.turbo_disabled) 1937 val |= (u64)1 << 32; 1938 1939 return val; 1940 } 1941 1942 static int knl_get_aperf_mperf_shift(void) 1943 { 1944 return 10; 1945 } 1946 1947 static int knl_get_turbo_pstate(int cpu) 1948 { 1949 u64 value; 1950 int nont, ret; 1951 1952 rdmsrl_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value); 1953 nont = core_get_max_pstate(cpu); 1954 ret = (((value) >> 8) & 0xFF); 1955 if (ret <= nont) 1956 ret = nont; 1957 return ret; 1958 } 1959 1960 static void hybrid_get_type(void *data) 1961 { 1962 u8 *cpu_type = data; 1963 1964 *cpu_type = get_this_hybrid_cpu_type(); 1965 } 1966 1967 static int hwp_get_cpu_scaling(int cpu) 1968 { 1969 u8 cpu_type = 0; 1970 1971 smp_call_function_single(cpu, hybrid_get_type, &cpu_type, 1); 1972 /* P-cores have a smaller perf level-to-freqency scaling factor. */ 1973 if (cpu_type == 0x40) 1974 return hybrid_scaling_factor; 1975 1976 /* Use default core scaling for E-cores */ 1977 if (cpu_type == 0x20) 1978 return core_get_scaling(); 1979 1980 /* 1981 * If reached here, this system is either non-hybrid (like Tiger 1982 * Lake) or hybrid-capable (like Alder Lake or Raptor Lake) with 1983 * no E cores (in which case CPUID for hybrid support is 0). 1984 * 1985 * The CPPC nominal_frequency field is 0 for non-hybrid systems, 1986 * so the default core scaling will be used for them. 1987 */ 1988 return intel_pstate_cppc_get_scaling(cpu); 1989 } 1990 1991 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate) 1992 { 1993 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu); 1994 cpu->pstate.current_pstate = pstate; 1995 /* 1996 * Generally, there is no guarantee that this code will always run on 1997 * the CPU being updated, so force the register update to run on the 1998 * right CPU. 1999 */ 2000 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL, 2001 pstate_funcs.get_val(cpu, pstate)); 2002 } 2003 2004 static void intel_pstate_set_min_pstate(struct cpudata *cpu) 2005 { 2006 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate); 2007 } 2008 2009 static void intel_pstate_max_within_limits(struct cpudata *cpu) 2010 { 2011 int pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio); 2012 2013 update_turbo_state(); 2014 intel_pstate_set_pstate(cpu, pstate); 2015 } 2016 2017 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu) 2018 { 2019 int perf_ctl_max_phys = pstate_funcs.get_max_physical(cpu->cpu); 2020 int perf_ctl_scaling = pstate_funcs.get_scaling(); 2021 2022 cpu->pstate.min_pstate = pstate_funcs.get_min(cpu->cpu); 2023 cpu->pstate.max_pstate_physical = perf_ctl_max_phys; 2024 cpu->pstate.perf_ctl_scaling = perf_ctl_scaling; 2025 2026 if (hwp_active && !hwp_mode_bdw) { 2027 __intel_pstate_get_hwp_cap(cpu); 2028 2029 if (pstate_funcs.get_cpu_scaling) { 2030 cpu->pstate.scaling = pstate_funcs.get_cpu_scaling(cpu->cpu); 2031 if (cpu->pstate.scaling != perf_ctl_scaling) 2032 intel_pstate_hybrid_hwp_adjust(cpu); 2033 } else { 2034 cpu->pstate.scaling = perf_ctl_scaling; 2035 } 2036 } else { 2037 cpu->pstate.scaling = perf_ctl_scaling; 2038 cpu->pstate.max_pstate = pstate_funcs.get_max(cpu->cpu); 2039 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(cpu->cpu); 2040 } 2041 2042 if (cpu->pstate.scaling == perf_ctl_scaling) { 2043 cpu->pstate.min_freq = cpu->pstate.min_pstate * perf_ctl_scaling; 2044 cpu->pstate.max_freq = cpu->pstate.max_pstate * perf_ctl_scaling; 2045 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * perf_ctl_scaling; 2046 } 2047 2048 if (pstate_funcs.get_aperf_mperf_shift) 2049 cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift(); 2050 2051 if (pstate_funcs.get_vid) 2052 pstate_funcs.get_vid(cpu); 2053 2054 intel_pstate_set_min_pstate(cpu); 2055 } 2056 2057 /* 2058 * Long hold time will keep high perf limits for long time, 2059 * which negatively impacts perf/watt for some workloads, 2060 * like specpower. 3ms is based on experiements on some 2061 * workoads. 2062 */ 2063 static int hwp_boost_hold_time_ns = 3 * NSEC_PER_MSEC; 2064 2065 static inline void intel_pstate_hwp_boost_up(struct cpudata *cpu) 2066 { 2067 u64 hwp_req = READ_ONCE(cpu->hwp_req_cached); 2068 u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached); 2069 u32 max_limit = (hwp_req & 0xff00) >> 8; 2070 u32 min_limit = (hwp_req & 0xff); 2071 u32 boost_level1; 2072 2073 /* 2074 * Cases to consider (User changes via sysfs or boot time): 2075 * If, P0 (Turbo max) = P1 (Guaranteed max) = min: 2076 * No boost, return. 2077 * If, P0 (Turbo max) > P1 (Guaranteed max) = min: 2078 * Should result in one level boost only for P0. 2079 * If, P0 (Turbo max) = P1 (Guaranteed max) > min: 2080 * Should result in two level boost: 2081 * (min + p1)/2 and P1. 2082 * If, P0 (Turbo max) > P1 (Guaranteed max) > min: 2083 * Should result in three level boost: 2084 * (min + p1)/2, P1 and P0. 2085 */ 2086 2087 /* If max and min are equal or already at max, nothing to boost */ 2088 if (max_limit == min_limit || cpu->hwp_boost_min >= max_limit) 2089 return; 2090 2091 if (!cpu->hwp_boost_min) 2092 cpu->hwp_boost_min = min_limit; 2093 2094 /* level at half way mark between min and guranteed */ 2095 boost_level1 = (HWP_GUARANTEED_PERF(hwp_cap) + min_limit) >> 1; 2096 2097 if (cpu->hwp_boost_min < boost_level1) 2098 cpu->hwp_boost_min = boost_level1; 2099 else if (cpu->hwp_boost_min < HWP_GUARANTEED_PERF(hwp_cap)) 2100 cpu->hwp_boost_min = HWP_GUARANTEED_PERF(hwp_cap); 2101 else if (cpu->hwp_boost_min == HWP_GUARANTEED_PERF(hwp_cap) && 2102 max_limit != HWP_GUARANTEED_PERF(hwp_cap)) 2103 cpu->hwp_boost_min = max_limit; 2104 else 2105 return; 2106 2107 hwp_req = (hwp_req & ~GENMASK_ULL(7, 0)) | cpu->hwp_boost_min; 2108 wrmsrl(MSR_HWP_REQUEST, hwp_req); 2109 cpu->last_update = cpu->sample.time; 2110 } 2111 2112 static inline void intel_pstate_hwp_boost_down(struct cpudata *cpu) 2113 { 2114 if (cpu->hwp_boost_min) { 2115 bool expired; 2116 2117 /* Check if we are idle for hold time to boost down */ 2118 expired = time_after64(cpu->sample.time, cpu->last_update + 2119 hwp_boost_hold_time_ns); 2120 if (expired) { 2121 wrmsrl(MSR_HWP_REQUEST, cpu->hwp_req_cached); 2122 cpu->hwp_boost_min = 0; 2123 } 2124 } 2125 cpu->last_update = cpu->sample.time; 2126 } 2127 2128 static inline void intel_pstate_update_util_hwp_local(struct cpudata *cpu, 2129 u64 time) 2130 { 2131 cpu->sample.time = time; 2132 2133 if (cpu->sched_flags & SCHED_CPUFREQ_IOWAIT) { 2134 bool do_io = false; 2135 2136 cpu->sched_flags = 0; 2137 /* 2138 * Set iowait_boost flag and update time. Since IO WAIT flag 2139 * is set all the time, we can't just conclude that there is 2140 * some IO bound activity is scheduled on this CPU with just 2141 * one occurrence. If we receive at least two in two 2142 * consecutive ticks, then we treat as boost candidate. 2143 */ 2144 if (time_before64(time, cpu->last_io_update + 2 * TICK_NSEC)) 2145 do_io = true; 2146 2147 cpu->last_io_update = time; 2148 2149 if (do_io) 2150 intel_pstate_hwp_boost_up(cpu); 2151 2152 } else { 2153 intel_pstate_hwp_boost_down(cpu); 2154 } 2155 } 2156 2157 static inline void intel_pstate_update_util_hwp(struct update_util_data *data, 2158 u64 time, unsigned int flags) 2159 { 2160 struct cpudata *cpu = container_of(data, struct cpudata, update_util); 2161 2162 cpu->sched_flags |= flags; 2163 2164 if (smp_processor_id() == cpu->cpu) 2165 intel_pstate_update_util_hwp_local(cpu, time); 2166 } 2167 2168 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu) 2169 { 2170 struct sample *sample = &cpu->sample; 2171 2172 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf); 2173 } 2174 2175 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time) 2176 { 2177 u64 aperf, mperf; 2178 unsigned long flags; 2179 u64 tsc; 2180 2181 local_irq_save(flags); 2182 rdmsrl(MSR_IA32_APERF, aperf); 2183 rdmsrl(MSR_IA32_MPERF, mperf); 2184 tsc = rdtsc(); 2185 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) { 2186 local_irq_restore(flags); 2187 return false; 2188 } 2189 local_irq_restore(flags); 2190 2191 cpu->last_sample_time = cpu->sample.time; 2192 cpu->sample.time = time; 2193 cpu->sample.aperf = aperf; 2194 cpu->sample.mperf = mperf; 2195 cpu->sample.tsc = tsc; 2196 cpu->sample.aperf -= cpu->prev_aperf; 2197 cpu->sample.mperf -= cpu->prev_mperf; 2198 cpu->sample.tsc -= cpu->prev_tsc; 2199 2200 cpu->prev_aperf = aperf; 2201 cpu->prev_mperf = mperf; 2202 cpu->prev_tsc = tsc; 2203 /* 2204 * First time this function is invoked in a given cycle, all of the 2205 * previous sample data fields are equal to zero or stale and they must 2206 * be populated with meaningful numbers for things to work, so assume 2207 * that sample.time will always be reset before setting the utilization 2208 * update hook and make the caller skip the sample then. 2209 */ 2210 if (cpu->last_sample_time) { 2211 intel_pstate_calc_avg_perf(cpu); 2212 return true; 2213 } 2214 return false; 2215 } 2216 2217 static inline int32_t get_avg_frequency(struct cpudata *cpu) 2218 { 2219 return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz); 2220 } 2221 2222 static inline int32_t get_avg_pstate(struct cpudata *cpu) 2223 { 2224 return mul_ext_fp(cpu->pstate.max_pstate_physical, 2225 cpu->sample.core_avg_perf); 2226 } 2227 2228 static inline int32_t get_target_pstate(struct cpudata *cpu) 2229 { 2230 struct sample *sample = &cpu->sample; 2231 int32_t busy_frac; 2232 int target, avg_pstate; 2233 2234 busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift, 2235 sample->tsc); 2236 2237 if (busy_frac < cpu->iowait_boost) 2238 busy_frac = cpu->iowait_boost; 2239 2240 sample->busy_scaled = busy_frac * 100; 2241 2242 target = global.no_turbo || global.turbo_disabled ? 2243 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate; 2244 target += target >> 2; 2245 target = mul_fp(target, busy_frac); 2246 if (target < cpu->pstate.min_pstate) 2247 target = cpu->pstate.min_pstate; 2248 2249 /* 2250 * If the average P-state during the previous cycle was higher than the 2251 * current target, add 50% of the difference to the target to reduce 2252 * possible performance oscillations and offset possible performance 2253 * loss related to moving the workload from one CPU to another within 2254 * a package/module. 2255 */ 2256 avg_pstate = get_avg_pstate(cpu); 2257 if (avg_pstate > target) 2258 target += (avg_pstate - target) >> 1; 2259 2260 return target; 2261 } 2262 2263 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate) 2264 { 2265 int min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio); 2266 int max_pstate = max(min_pstate, cpu->max_perf_ratio); 2267 2268 return clamp_t(int, pstate, min_pstate, max_pstate); 2269 } 2270 2271 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate) 2272 { 2273 if (pstate == cpu->pstate.current_pstate) 2274 return; 2275 2276 cpu->pstate.current_pstate = pstate; 2277 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate)); 2278 } 2279 2280 static void intel_pstate_adjust_pstate(struct cpudata *cpu) 2281 { 2282 int from = cpu->pstate.current_pstate; 2283 struct sample *sample; 2284 int target_pstate; 2285 2286 update_turbo_state(); 2287 2288 target_pstate = get_target_pstate(cpu); 2289 target_pstate = intel_pstate_prepare_request(cpu, target_pstate); 2290 trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu); 2291 intel_pstate_update_pstate(cpu, target_pstate); 2292 2293 sample = &cpu->sample; 2294 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf), 2295 fp_toint(sample->busy_scaled), 2296 from, 2297 cpu->pstate.current_pstate, 2298 sample->mperf, 2299 sample->aperf, 2300 sample->tsc, 2301 get_avg_frequency(cpu), 2302 fp_toint(cpu->iowait_boost * 100)); 2303 } 2304 2305 static void intel_pstate_update_util(struct update_util_data *data, u64 time, 2306 unsigned int flags) 2307 { 2308 struct cpudata *cpu = container_of(data, struct cpudata, update_util); 2309 u64 delta_ns; 2310 2311 /* Don't allow remote callbacks */ 2312 if (smp_processor_id() != cpu->cpu) 2313 return; 2314 2315 delta_ns = time - cpu->last_update; 2316 if (flags & SCHED_CPUFREQ_IOWAIT) { 2317 /* Start over if the CPU may have been idle. */ 2318 if (delta_ns > TICK_NSEC) { 2319 cpu->iowait_boost = ONE_EIGHTH_FP; 2320 } else if (cpu->iowait_boost >= ONE_EIGHTH_FP) { 2321 cpu->iowait_boost <<= 1; 2322 if (cpu->iowait_boost > int_tofp(1)) 2323 cpu->iowait_boost = int_tofp(1); 2324 } else { 2325 cpu->iowait_boost = ONE_EIGHTH_FP; 2326 } 2327 } else if (cpu->iowait_boost) { 2328 /* Clear iowait_boost if the CPU may have been idle. */ 2329 if (delta_ns > TICK_NSEC) 2330 cpu->iowait_boost = 0; 2331 else 2332 cpu->iowait_boost >>= 1; 2333 } 2334 cpu->last_update = time; 2335 delta_ns = time - cpu->sample.time; 2336 if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL) 2337 return; 2338 2339 if (intel_pstate_sample(cpu, time)) 2340 intel_pstate_adjust_pstate(cpu); 2341 } 2342 2343 static struct pstate_funcs core_funcs = { 2344 .get_max = core_get_max_pstate, 2345 .get_max_physical = core_get_max_pstate_physical, 2346 .get_min = core_get_min_pstate, 2347 .get_turbo = core_get_turbo_pstate, 2348 .get_scaling = core_get_scaling, 2349 .get_val = core_get_val, 2350 }; 2351 2352 static const struct pstate_funcs silvermont_funcs = { 2353 .get_max = atom_get_max_pstate, 2354 .get_max_physical = atom_get_max_pstate, 2355 .get_min = atom_get_min_pstate, 2356 .get_turbo = atom_get_turbo_pstate, 2357 .get_val = atom_get_val, 2358 .get_scaling = silvermont_get_scaling, 2359 .get_vid = atom_get_vid, 2360 }; 2361 2362 static const struct pstate_funcs airmont_funcs = { 2363 .get_max = atom_get_max_pstate, 2364 .get_max_physical = atom_get_max_pstate, 2365 .get_min = atom_get_min_pstate, 2366 .get_turbo = atom_get_turbo_pstate, 2367 .get_val = atom_get_val, 2368 .get_scaling = airmont_get_scaling, 2369 .get_vid = atom_get_vid, 2370 }; 2371 2372 static const struct pstate_funcs knl_funcs = { 2373 .get_max = core_get_max_pstate, 2374 .get_max_physical = core_get_max_pstate_physical, 2375 .get_min = core_get_min_pstate, 2376 .get_turbo = knl_get_turbo_pstate, 2377 .get_aperf_mperf_shift = knl_get_aperf_mperf_shift, 2378 .get_scaling = core_get_scaling, 2379 .get_val = core_get_val, 2380 }; 2381 2382 #define X86_MATCH(model, policy) \ 2383 X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \ 2384 X86_FEATURE_APERFMPERF, &policy) 2385 2386 static const struct x86_cpu_id intel_pstate_cpu_ids[] = { 2387 X86_MATCH(SANDYBRIDGE, core_funcs), 2388 X86_MATCH(SANDYBRIDGE_X, core_funcs), 2389 X86_MATCH(ATOM_SILVERMONT, silvermont_funcs), 2390 X86_MATCH(IVYBRIDGE, core_funcs), 2391 X86_MATCH(HASWELL, core_funcs), 2392 X86_MATCH(BROADWELL, core_funcs), 2393 X86_MATCH(IVYBRIDGE_X, core_funcs), 2394 X86_MATCH(HASWELL_X, core_funcs), 2395 X86_MATCH(HASWELL_L, core_funcs), 2396 X86_MATCH(HASWELL_G, core_funcs), 2397 X86_MATCH(BROADWELL_G, core_funcs), 2398 X86_MATCH(ATOM_AIRMONT, airmont_funcs), 2399 X86_MATCH(SKYLAKE_L, core_funcs), 2400 X86_MATCH(BROADWELL_X, core_funcs), 2401 X86_MATCH(SKYLAKE, core_funcs), 2402 X86_MATCH(BROADWELL_D, core_funcs), 2403 X86_MATCH(XEON_PHI_KNL, knl_funcs), 2404 X86_MATCH(XEON_PHI_KNM, knl_funcs), 2405 X86_MATCH(ATOM_GOLDMONT, core_funcs), 2406 X86_MATCH(ATOM_GOLDMONT_PLUS, core_funcs), 2407 X86_MATCH(SKYLAKE_X, core_funcs), 2408 X86_MATCH(COMETLAKE, core_funcs), 2409 X86_MATCH(ICELAKE_X, core_funcs), 2410 X86_MATCH(TIGERLAKE, core_funcs), 2411 X86_MATCH(SAPPHIRERAPIDS_X, core_funcs), 2412 X86_MATCH(EMERALDRAPIDS_X, core_funcs), 2413 {} 2414 }; 2415 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids); 2416 2417 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = { 2418 X86_MATCH(BROADWELL_D, core_funcs), 2419 X86_MATCH(BROADWELL_X, core_funcs), 2420 X86_MATCH(SKYLAKE_X, core_funcs), 2421 X86_MATCH(ICELAKE_X, core_funcs), 2422 X86_MATCH(SAPPHIRERAPIDS_X, core_funcs), 2423 {} 2424 }; 2425 2426 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = { 2427 X86_MATCH(KABYLAKE, core_funcs), 2428 {} 2429 }; 2430 2431 static int intel_pstate_init_cpu(unsigned int cpunum) 2432 { 2433 struct cpudata *cpu; 2434 2435 cpu = all_cpu_data[cpunum]; 2436 2437 if (!cpu) { 2438 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL); 2439 if (!cpu) 2440 return -ENOMEM; 2441 2442 WRITE_ONCE(all_cpu_data[cpunum], cpu); 2443 2444 cpu->cpu = cpunum; 2445 2446 cpu->epp_default = -EINVAL; 2447 2448 if (hwp_active) { 2449 intel_pstate_hwp_enable(cpu); 2450 2451 if (intel_pstate_acpi_pm_profile_server()) 2452 hwp_boost = true; 2453 } 2454 } else if (hwp_active) { 2455 /* 2456 * Re-enable HWP in case this happens after a resume from ACPI 2457 * S3 if the CPU was offline during the whole system/resume 2458 * cycle. 2459 */ 2460 intel_pstate_hwp_reenable(cpu); 2461 } 2462 2463 cpu->epp_powersave = -EINVAL; 2464 cpu->epp_policy = 0; 2465 2466 intel_pstate_get_cpu_pstates(cpu); 2467 2468 pr_debug("controlling: cpu %d\n", cpunum); 2469 2470 return 0; 2471 } 2472 2473 static void intel_pstate_set_update_util_hook(unsigned int cpu_num) 2474 { 2475 struct cpudata *cpu = all_cpu_data[cpu_num]; 2476 2477 if (hwp_active && !hwp_boost) 2478 return; 2479 2480 if (cpu->update_util_set) 2481 return; 2482 2483 /* Prevent intel_pstate_update_util() from using stale data. */ 2484 cpu->sample.time = 0; 2485 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util, 2486 (hwp_active ? 2487 intel_pstate_update_util_hwp : 2488 intel_pstate_update_util)); 2489 cpu->update_util_set = true; 2490 } 2491 2492 static void intel_pstate_clear_update_util_hook(unsigned int cpu) 2493 { 2494 struct cpudata *cpu_data = all_cpu_data[cpu]; 2495 2496 if (!cpu_data->update_util_set) 2497 return; 2498 2499 cpufreq_remove_update_util_hook(cpu); 2500 cpu_data->update_util_set = false; 2501 synchronize_rcu(); 2502 } 2503 2504 static int intel_pstate_get_max_freq(struct cpudata *cpu) 2505 { 2506 return global.turbo_disabled || global.no_turbo ? 2507 cpu->pstate.max_freq : cpu->pstate.turbo_freq; 2508 } 2509 2510 static void intel_pstate_update_perf_limits(struct cpudata *cpu, 2511 unsigned int policy_min, 2512 unsigned int policy_max) 2513 { 2514 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling; 2515 int32_t max_policy_perf, min_policy_perf; 2516 2517 max_policy_perf = policy_max / perf_ctl_scaling; 2518 if (policy_max == policy_min) { 2519 min_policy_perf = max_policy_perf; 2520 } else { 2521 min_policy_perf = policy_min / perf_ctl_scaling; 2522 min_policy_perf = clamp_t(int32_t, min_policy_perf, 2523 0, max_policy_perf); 2524 } 2525 2526 /* 2527 * HWP needs some special consideration, because HWP_REQUEST uses 2528 * abstract values to represent performance rather than pure ratios. 2529 */ 2530 if (hwp_active && cpu->pstate.scaling != perf_ctl_scaling) { 2531 int scaling = cpu->pstate.scaling; 2532 int freq; 2533 2534 freq = max_policy_perf * perf_ctl_scaling; 2535 max_policy_perf = DIV_ROUND_UP(freq, scaling); 2536 freq = min_policy_perf * perf_ctl_scaling; 2537 min_policy_perf = DIV_ROUND_UP(freq, scaling); 2538 } 2539 2540 pr_debug("cpu:%d min_policy_perf:%d max_policy_perf:%d\n", 2541 cpu->cpu, min_policy_perf, max_policy_perf); 2542 2543 /* Normalize user input to [min_perf, max_perf] */ 2544 if (per_cpu_limits) { 2545 cpu->min_perf_ratio = min_policy_perf; 2546 cpu->max_perf_ratio = max_policy_perf; 2547 } else { 2548 int turbo_max = cpu->pstate.turbo_pstate; 2549 int32_t global_min, global_max; 2550 2551 /* Global limits are in percent of the maximum turbo P-state. */ 2552 global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100); 2553 global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100); 2554 global_min = clamp_t(int32_t, global_min, 0, global_max); 2555 2556 pr_debug("cpu:%d global_min:%d global_max:%d\n", cpu->cpu, 2557 global_min, global_max); 2558 2559 cpu->min_perf_ratio = max(min_policy_perf, global_min); 2560 cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf); 2561 cpu->max_perf_ratio = min(max_policy_perf, global_max); 2562 cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio); 2563 2564 /* Make sure min_perf <= max_perf */ 2565 cpu->min_perf_ratio = min(cpu->min_perf_ratio, 2566 cpu->max_perf_ratio); 2567 2568 } 2569 pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", cpu->cpu, 2570 cpu->max_perf_ratio, 2571 cpu->min_perf_ratio); 2572 } 2573 2574 static int intel_pstate_set_policy(struct cpufreq_policy *policy) 2575 { 2576 struct cpudata *cpu; 2577 2578 if (!policy->cpuinfo.max_freq) 2579 return -ENODEV; 2580 2581 pr_debug("set_policy cpuinfo.max %u policy->max %u\n", 2582 policy->cpuinfo.max_freq, policy->max); 2583 2584 cpu = all_cpu_data[policy->cpu]; 2585 cpu->policy = policy->policy; 2586 2587 mutex_lock(&intel_pstate_limits_lock); 2588 2589 intel_pstate_update_perf_limits(cpu, policy->min, policy->max); 2590 2591 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) { 2592 /* 2593 * NOHZ_FULL CPUs need this as the governor callback may not 2594 * be invoked on them. 2595 */ 2596 intel_pstate_clear_update_util_hook(policy->cpu); 2597 intel_pstate_max_within_limits(cpu); 2598 } else { 2599 intel_pstate_set_update_util_hook(policy->cpu); 2600 } 2601 2602 if (hwp_active) { 2603 /* 2604 * When hwp_boost was active before and dynamically it 2605 * was turned off, in that case we need to clear the 2606 * update util hook. 2607 */ 2608 if (!hwp_boost) 2609 intel_pstate_clear_update_util_hook(policy->cpu); 2610 intel_pstate_hwp_set(policy->cpu); 2611 } 2612 /* 2613 * policy->cur is never updated with the intel_pstate driver, but it 2614 * is used as a stale frequency value. So, keep it within limits. 2615 */ 2616 policy->cur = policy->min; 2617 2618 mutex_unlock(&intel_pstate_limits_lock); 2619 2620 return 0; 2621 } 2622 2623 static void intel_pstate_adjust_policy_max(struct cpudata *cpu, 2624 struct cpufreq_policy_data *policy) 2625 { 2626 if (!hwp_active && 2627 cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate && 2628 policy->max < policy->cpuinfo.max_freq && 2629 policy->max > cpu->pstate.max_freq) { 2630 pr_debug("policy->max > max non turbo frequency\n"); 2631 policy->max = policy->cpuinfo.max_freq; 2632 } 2633 } 2634 2635 static void intel_pstate_verify_cpu_policy(struct cpudata *cpu, 2636 struct cpufreq_policy_data *policy) 2637 { 2638 int max_freq; 2639 2640 update_turbo_state(); 2641 if (hwp_active) { 2642 intel_pstate_get_hwp_cap(cpu); 2643 max_freq = global.no_turbo || global.turbo_disabled ? 2644 cpu->pstate.max_freq : cpu->pstate.turbo_freq; 2645 } else { 2646 max_freq = intel_pstate_get_max_freq(cpu); 2647 } 2648 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, max_freq); 2649 2650 intel_pstate_adjust_policy_max(cpu, policy); 2651 } 2652 2653 static int intel_pstate_verify_policy(struct cpufreq_policy_data *policy) 2654 { 2655 intel_pstate_verify_cpu_policy(all_cpu_data[policy->cpu], policy); 2656 2657 return 0; 2658 } 2659 2660 static int intel_cpufreq_cpu_offline(struct cpufreq_policy *policy) 2661 { 2662 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2663 2664 pr_debug("CPU %d going offline\n", cpu->cpu); 2665 2666 if (cpu->suspended) 2667 return 0; 2668 2669 /* 2670 * If the CPU is an SMT thread and it goes offline with the performance 2671 * settings different from the minimum, it will prevent its sibling 2672 * from getting to lower performance levels, so force the minimum 2673 * performance on CPU offline to prevent that from happening. 2674 */ 2675 if (hwp_active) 2676 intel_pstate_hwp_offline(cpu); 2677 else 2678 intel_pstate_set_min_pstate(cpu); 2679 2680 intel_pstate_exit_perf_limits(policy); 2681 2682 return 0; 2683 } 2684 2685 static int intel_pstate_cpu_online(struct cpufreq_policy *policy) 2686 { 2687 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2688 2689 pr_debug("CPU %d going online\n", cpu->cpu); 2690 2691 intel_pstate_init_acpi_perf_limits(policy); 2692 2693 if (hwp_active) { 2694 /* 2695 * Re-enable HWP and clear the "suspended" flag to let "resume" 2696 * know that it need not do that. 2697 */ 2698 intel_pstate_hwp_reenable(cpu); 2699 cpu->suspended = false; 2700 } 2701 2702 return 0; 2703 } 2704 2705 static int intel_pstate_cpu_offline(struct cpufreq_policy *policy) 2706 { 2707 intel_pstate_clear_update_util_hook(policy->cpu); 2708 2709 return intel_cpufreq_cpu_offline(policy); 2710 } 2711 2712 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy) 2713 { 2714 pr_debug("CPU %d exiting\n", policy->cpu); 2715 2716 policy->fast_switch_possible = false; 2717 2718 return 0; 2719 } 2720 2721 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy) 2722 { 2723 struct cpudata *cpu; 2724 int rc; 2725 2726 rc = intel_pstate_init_cpu(policy->cpu); 2727 if (rc) 2728 return rc; 2729 2730 cpu = all_cpu_data[policy->cpu]; 2731 2732 cpu->max_perf_ratio = 0xFF; 2733 cpu->min_perf_ratio = 0; 2734 2735 /* cpuinfo and default policy values */ 2736 policy->cpuinfo.min_freq = cpu->pstate.min_freq; 2737 update_turbo_state(); 2738 global.turbo_disabled_mf = global.turbo_disabled; 2739 policy->cpuinfo.max_freq = global.turbo_disabled ? 2740 cpu->pstate.max_freq : cpu->pstate.turbo_freq; 2741 2742 policy->min = policy->cpuinfo.min_freq; 2743 policy->max = policy->cpuinfo.max_freq; 2744 2745 intel_pstate_init_acpi_perf_limits(policy); 2746 2747 policy->fast_switch_possible = true; 2748 2749 return 0; 2750 } 2751 2752 static int intel_pstate_cpu_init(struct cpufreq_policy *policy) 2753 { 2754 int ret = __intel_pstate_cpu_init(policy); 2755 2756 if (ret) 2757 return ret; 2758 2759 /* 2760 * Set the policy to powersave to provide a valid fallback value in case 2761 * the default cpufreq governor is neither powersave nor performance. 2762 */ 2763 policy->policy = CPUFREQ_POLICY_POWERSAVE; 2764 2765 if (hwp_active) { 2766 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2767 2768 cpu->epp_cached = intel_pstate_get_epp(cpu, 0); 2769 } 2770 2771 return 0; 2772 } 2773 2774 static struct cpufreq_driver intel_pstate = { 2775 .flags = CPUFREQ_CONST_LOOPS, 2776 .verify = intel_pstate_verify_policy, 2777 .setpolicy = intel_pstate_set_policy, 2778 .suspend = intel_pstate_suspend, 2779 .resume = intel_pstate_resume, 2780 .init = intel_pstate_cpu_init, 2781 .exit = intel_pstate_cpu_exit, 2782 .offline = intel_pstate_cpu_offline, 2783 .online = intel_pstate_cpu_online, 2784 .update_limits = intel_pstate_update_limits, 2785 .name = "intel_pstate", 2786 }; 2787 2788 static int intel_cpufreq_verify_policy(struct cpufreq_policy_data *policy) 2789 { 2790 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2791 2792 intel_pstate_verify_cpu_policy(cpu, policy); 2793 intel_pstate_update_perf_limits(cpu, policy->min, policy->max); 2794 2795 return 0; 2796 } 2797 2798 /* Use of trace in passive mode: 2799 * 2800 * In passive mode the trace core_busy field (also known as the 2801 * performance field, and lablelled as such on the graphs; also known as 2802 * core_avg_perf) is not needed and so is re-assigned to indicate if the 2803 * driver call was via the normal or fast switch path. Various graphs 2804 * output from the intel_pstate_tracer.py utility that include core_busy 2805 * (or performance or core_avg_perf) have a fixed y-axis from 0 to 100%, 2806 * so we use 10 to indicate the normal path through the driver, and 2807 * 90 to indicate the fast switch path through the driver. 2808 * The scaled_busy field is not used, and is set to 0. 2809 */ 2810 2811 #define INTEL_PSTATE_TRACE_TARGET 10 2812 #define INTEL_PSTATE_TRACE_FAST_SWITCH 90 2813 2814 static void intel_cpufreq_trace(struct cpudata *cpu, unsigned int trace_type, int old_pstate) 2815 { 2816 struct sample *sample; 2817 2818 if (!trace_pstate_sample_enabled()) 2819 return; 2820 2821 if (!intel_pstate_sample(cpu, ktime_get())) 2822 return; 2823 2824 sample = &cpu->sample; 2825 trace_pstate_sample(trace_type, 2826 0, 2827 old_pstate, 2828 cpu->pstate.current_pstate, 2829 sample->mperf, 2830 sample->aperf, 2831 sample->tsc, 2832 get_avg_frequency(cpu), 2833 fp_toint(cpu->iowait_boost * 100)); 2834 } 2835 2836 static void intel_cpufreq_hwp_update(struct cpudata *cpu, u32 min, u32 max, 2837 u32 desired, bool fast_switch) 2838 { 2839 u64 prev = READ_ONCE(cpu->hwp_req_cached), value = prev; 2840 2841 value &= ~HWP_MIN_PERF(~0L); 2842 value |= HWP_MIN_PERF(min); 2843 2844 value &= ~HWP_MAX_PERF(~0L); 2845 value |= HWP_MAX_PERF(max); 2846 2847 value &= ~HWP_DESIRED_PERF(~0L); 2848 value |= HWP_DESIRED_PERF(desired); 2849 2850 if (value == prev) 2851 return; 2852 2853 WRITE_ONCE(cpu->hwp_req_cached, value); 2854 if (fast_switch) 2855 wrmsrl(MSR_HWP_REQUEST, value); 2856 else 2857 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 2858 } 2859 2860 static void intel_cpufreq_perf_ctl_update(struct cpudata *cpu, 2861 u32 target_pstate, bool fast_switch) 2862 { 2863 if (fast_switch) 2864 wrmsrl(MSR_IA32_PERF_CTL, 2865 pstate_funcs.get_val(cpu, target_pstate)); 2866 else 2867 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL, 2868 pstate_funcs.get_val(cpu, target_pstate)); 2869 } 2870 2871 static int intel_cpufreq_update_pstate(struct cpufreq_policy *policy, 2872 int target_pstate, bool fast_switch) 2873 { 2874 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2875 int old_pstate = cpu->pstate.current_pstate; 2876 2877 target_pstate = intel_pstate_prepare_request(cpu, target_pstate); 2878 if (hwp_active) { 2879 int max_pstate = policy->strict_target ? 2880 target_pstate : cpu->max_perf_ratio; 2881 2882 intel_cpufreq_hwp_update(cpu, target_pstate, max_pstate, 0, 2883 fast_switch); 2884 } else if (target_pstate != old_pstate) { 2885 intel_cpufreq_perf_ctl_update(cpu, target_pstate, fast_switch); 2886 } 2887 2888 cpu->pstate.current_pstate = target_pstate; 2889 2890 intel_cpufreq_trace(cpu, fast_switch ? INTEL_PSTATE_TRACE_FAST_SWITCH : 2891 INTEL_PSTATE_TRACE_TARGET, old_pstate); 2892 2893 return target_pstate; 2894 } 2895 2896 static int intel_cpufreq_target(struct cpufreq_policy *policy, 2897 unsigned int target_freq, 2898 unsigned int relation) 2899 { 2900 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2901 struct cpufreq_freqs freqs; 2902 int target_pstate; 2903 2904 update_turbo_state(); 2905 2906 freqs.old = policy->cur; 2907 freqs.new = target_freq; 2908 2909 cpufreq_freq_transition_begin(policy, &freqs); 2910 2911 switch (relation) { 2912 case CPUFREQ_RELATION_L: 2913 target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling); 2914 break; 2915 case CPUFREQ_RELATION_H: 2916 target_pstate = freqs.new / cpu->pstate.scaling; 2917 break; 2918 default: 2919 target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling); 2920 break; 2921 } 2922 2923 target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, false); 2924 2925 freqs.new = target_pstate * cpu->pstate.scaling; 2926 2927 cpufreq_freq_transition_end(policy, &freqs, false); 2928 2929 return 0; 2930 } 2931 2932 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy, 2933 unsigned int target_freq) 2934 { 2935 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2936 int target_pstate; 2937 2938 update_turbo_state(); 2939 2940 target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling); 2941 2942 target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, true); 2943 2944 return target_pstate * cpu->pstate.scaling; 2945 } 2946 2947 static void intel_cpufreq_adjust_perf(unsigned int cpunum, 2948 unsigned long min_perf, 2949 unsigned long target_perf, 2950 unsigned long capacity) 2951 { 2952 struct cpudata *cpu = all_cpu_data[cpunum]; 2953 u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached); 2954 int old_pstate = cpu->pstate.current_pstate; 2955 int cap_pstate, min_pstate, max_pstate, target_pstate; 2956 2957 update_turbo_state(); 2958 cap_pstate = global.turbo_disabled ? HWP_GUARANTEED_PERF(hwp_cap) : 2959 HWP_HIGHEST_PERF(hwp_cap); 2960 2961 /* Optimization: Avoid unnecessary divisions. */ 2962 2963 target_pstate = cap_pstate; 2964 if (target_perf < capacity) 2965 target_pstate = DIV_ROUND_UP(cap_pstate * target_perf, capacity); 2966 2967 min_pstate = cap_pstate; 2968 if (min_perf < capacity) 2969 min_pstate = DIV_ROUND_UP(cap_pstate * min_perf, capacity); 2970 2971 if (min_pstate < cpu->pstate.min_pstate) 2972 min_pstate = cpu->pstate.min_pstate; 2973 2974 if (min_pstate < cpu->min_perf_ratio) 2975 min_pstate = cpu->min_perf_ratio; 2976 2977 max_pstate = min(cap_pstate, cpu->max_perf_ratio); 2978 if (max_pstate < min_pstate) 2979 max_pstate = min_pstate; 2980 2981 target_pstate = clamp_t(int, target_pstate, min_pstate, max_pstate); 2982 2983 intel_cpufreq_hwp_update(cpu, min_pstate, max_pstate, target_pstate, true); 2984 2985 cpu->pstate.current_pstate = target_pstate; 2986 intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_FAST_SWITCH, old_pstate); 2987 } 2988 2989 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy) 2990 { 2991 struct freq_qos_request *req; 2992 struct cpudata *cpu; 2993 struct device *dev; 2994 int ret, freq; 2995 2996 dev = get_cpu_device(policy->cpu); 2997 if (!dev) 2998 return -ENODEV; 2999 3000 ret = __intel_pstate_cpu_init(policy); 3001 if (ret) 3002 return ret; 3003 3004 policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY; 3005 /* This reflects the intel_pstate_get_cpu_pstates() setting. */ 3006 policy->cur = policy->cpuinfo.min_freq; 3007 3008 req = kcalloc(2, sizeof(*req), GFP_KERNEL); 3009 if (!req) { 3010 ret = -ENOMEM; 3011 goto pstate_exit; 3012 } 3013 3014 cpu = all_cpu_data[policy->cpu]; 3015 3016 if (hwp_active) { 3017 u64 value; 3018 3019 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY_HWP; 3020 3021 intel_pstate_get_hwp_cap(cpu); 3022 3023 rdmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, &value); 3024 WRITE_ONCE(cpu->hwp_req_cached, value); 3025 3026 cpu->epp_cached = intel_pstate_get_epp(cpu, value); 3027 } else { 3028 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY; 3029 } 3030 3031 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.min_perf_pct, 100); 3032 3033 ret = freq_qos_add_request(&policy->constraints, req, FREQ_QOS_MIN, 3034 freq); 3035 if (ret < 0) { 3036 dev_err(dev, "Failed to add min-freq constraint (%d)\n", ret); 3037 goto free_req; 3038 } 3039 3040 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.max_perf_pct, 100); 3041 3042 ret = freq_qos_add_request(&policy->constraints, req + 1, FREQ_QOS_MAX, 3043 freq); 3044 if (ret < 0) { 3045 dev_err(dev, "Failed to add max-freq constraint (%d)\n", ret); 3046 goto remove_min_req; 3047 } 3048 3049 policy->driver_data = req; 3050 3051 return 0; 3052 3053 remove_min_req: 3054 freq_qos_remove_request(req); 3055 free_req: 3056 kfree(req); 3057 pstate_exit: 3058 intel_pstate_exit_perf_limits(policy); 3059 3060 return ret; 3061 } 3062 3063 static int intel_cpufreq_cpu_exit(struct cpufreq_policy *policy) 3064 { 3065 struct freq_qos_request *req; 3066 3067 req = policy->driver_data; 3068 3069 freq_qos_remove_request(req + 1); 3070 freq_qos_remove_request(req); 3071 kfree(req); 3072 3073 return intel_pstate_cpu_exit(policy); 3074 } 3075 3076 static int intel_cpufreq_suspend(struct cpufreq_policy *policy) 3077 { 3078 intel_pstate_suspend(policy); 3079 3080 if (hwp_active) { 3081 struct cpudata *cpu = all_cpu_data[policy->cpu]; 3082 u64 value = READ_ONCE(cpu->hwp_req_cached); 3083 3084 /* 3085 * Clear the desired perf field in MSR_HWP_REQUEST in case 3086 * intel_cpufreq_adjust_perf() is in use and the last value 3087 * written by it may not be suitable. 3088 */ 3089 value &= ~HWP_DESIRED_PERF(~0L); 3090 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 3091 WRITE_ONCE(cpu->hwp_req_cached, value); 3092 } 3093 3094 return 0; 3095 } 3096 3097 static struct cpufreq_driver intel_cpufreq = { 3098 .flags = CPUFREQ_CONST_LOOPS, 3099 .verify = intel_cpufreq_verify_policy, 3100 .target = intel_cpufreq_target, 3101 .fast_switch = intel_cpufreq_fast_switch, 3102 .init = intel_cpufreq_cpu_init, 3103 .exit = intel_cpufreq_cpu_exit, 3104 .offline = intel_cpufreq_cpu_offline, 3105 .online = intel_pstate_cpu_online, 3106 .suspend = intel_cpufreq_suspend, 3107 .resume = intel_pstate_resume, 3108 .update_limits = intel_pstate_update_limits, 3109 .name = "intel_cpufreq", 3110 }; 3111 3112 static struct cpufreq_driver *default_driver; 3113 3114 static void intel_pstate_driver_cleanup(void) 3115 { 3116 unsigned int cpu; 3117 3118 cpus_read_lock(); 3119 for_each_online_cpu(cpu) { 3120 if (all_cpu_data[cpu]) { 3121 if (intel_pstate_driver == &intel_pstate) 3122 intel_pstate_clear_update_util_hook(cpu); 3123 3124 spin_lock(&hwp_notify_lock); 3125 kfree(all_cpu_data[cpu]); 3126 WRITE_ONCE(all_cpu_data[cpu], NULL); 3127 spin_unlock(&hwp_notify_lock); 3128 } 3129 } 3130 cpus_read_unlock(); 3131 3132 intel_pstate_driver = NULL; 3133 } 3134 3135 static int intel_pstate_register_driver(struct cpufreq_driver *driver) 3136 { 3137 int ret; 3138 3139 if (driver == &intel_pstate) 3140 intel_pstate_sysfs_expose_hwp_dynamic_boost(); 3141 3142 memset(&global, 0, sizeof(global)); 3143 global.max_perf_pct = 100; 3144 3145 intel_pstate_driver = driver; 3146 ret = cpufreq_register_driver(intel_pstate_driver); 3147 if (ret) { 3148 intel_pstate_driver_cleanup(); 3149 return ret; 3150 } 3151 3152 global.min_perf_pct = min_perf_pct_min(); 3153 3154 return 0; 3155 } 3156 3157 static ssize_t intel_pstate_show_status(char *buf) 3158 { 3159 if (!intel_pstate_driver) 3160 return sprintf(buf, "off\n"); 3161 3162 return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ? 3163 "active" : "passive"); 3164 } 3165 3166 static int intel_pstate_update_status(const char *buf, size_t size) 3167 { 3168 if (size == 3 && !strncmp(buf, "off", size)) { 3169 if (!intel_pstate_driver) 3170 return -EINVAL; 3171 3172 if (hwp_active) 3173 return -EBUSY; 3174 3175 cpufreq_unregister_driver(intel_pstate_driver); 3176 intel_pstate_driver_cleanup(); 3177 return 0; 3178 } 3179 3180 if (size == 6 && !strncmp(buf, "active", size)) { 3181 if (intel_pstate_driver) { 3182 if (intel_pstate_driver == &intel_pstate) 3183 return 0; 3184 3185 cpufreq_unregister_driver(intel_pstate_driver); 3186 } 3187 3188 return intel_pstate_register_driver(&intel_pstate); 3189 } 3190 3191 if (size == 7 && !strncmp(buf, "passive", size)) { 3192 if (intel_pstate_driver) { 3193 if (intel_pstate_driver == &intel_cpufreq) 3194 return 0; 3195 3196 cpufreq_unregister_driver(intel_pstate_driver); 3197 intel_pstate_sysfs_hide_hwp_dynamic_boost(); 3198 } 3199 3200 return intel_pstate_register_driver(&intel_cpufreq); 3201 } 3202 3203 return -EINVAL; 3204 } 3205 3206 static int no_load __initdata; 3207 static int no_hwp __initdata; 3208 static int hwp_only __initdata; 3209 static unsigned int force_load __initdata; 3210 3211 static int __init intel_pstate_msrs_not_valid(void) 3212 { 3213 if (!pstate_funcs.get_max(0) || 3214 !pstate_funcs.get_min(0) || 3215 !pstate_funcs.get_turbo(0)) 3216 return -ENODEV; 3217 3218 return 0; 3219 } 3220 3221 static void __init copy_cpu_funcs(struct pstate_funcs *funcs) 3222 { 3223 pstate_funcs.get_max = funcs->get_max; 3224 pstate_funcs.get_max_physical = funcs->get_max_physical; 3225 pstate_funcs.get_min = funcs->get_min; 3226 pstate_funcs.get_turbo = funcs->get_turbo; 3227 pstate_funcs.get_scaling = funcs->get_scaling; 3228 pstate_funcs.get_val = funcs->get_val; 3229 pstate_funcs.get_vid = funcs->get_vid; 3230 pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift; 3231 } 3232 3233 #ifdef CONFIG_ACPI 3234 3235 static bool __init intel_pstate_no_acpi_pss(void) 3236 { 3237 int i; 3238 3239 for_each_possible_cpu(i) { 3240 acpi_status status; 3241 union acpi_object *pss; 3242 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; 3243 struct acpi_processor *pr = per_cpu(processors, i); 3244 3245 if (!pr) 3246 continue; 3247 3248 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer); 3249 if (ACPI_FAILURE(status)) 3250 continue; 3251 3252 pss = buffer.pointer; 3253 if (pss && pss->type == ACPI_TYPE_PACKAGE) { 3254 kfree(pss); 3255 return false; 3256 } 3257 3258 kfree(pss); 3259 } 3260 3261 pr_debug("ACPI _PSS not found\n"); 3262 return true; 3263 } 3264 3265 static bool __init intel_pstate_no_acpi_pcch(void) 3266 { 3267 acpi_status status; 3268 acpi_handle handle; 3269 3270 status = acpi_get_handle(NULL, "\\_SB", &handle); 3271 if (ACPI_FAILURE(status)) 3272 goto not_found; 3273 3274 if (acpi_has_method(handle, "PCCH")) 3275 return false; 3276 3277 not_found: 3278 pr_debug("ACPI PCCH not found\n"); 3279 return true; 3280 } 3281 3282 static bool __init intel_pstate_has_acpi_ppc(void) 3283 { 3284 int i; 3285 3286 for_each_possible_cpu(i) { 3287 struct acpi_processor *pr = per_cpu(processors, i); 3288 3289 if (!pr) 3290 continue; 3291 if (acpi_has_method(pr->handle, "_PPC")) 3292 return true; 3293 } 3294 pr_debug("ACPI _PPC not found\n"); 3295 return false; 3296 } 3297 3298 enum { 3299 PSS, 3300 PPC, 3301 }; 3302 3303 /* Hardware vendor-specific info that has its own power management modes */ 3304 static struct acpi_platform_list plat_info[] __initdata = { 3305 {"HP ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, NULL, PSS}, 3306 {"ORACLE", "X4-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3307 {"ORACLE", "X4-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3308 {"ORACLE", "X4-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3309 {"ORACLE", "X3-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3310 {"ORACLE", "X3-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3311 {"ORACLE", "X3-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3312 {"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3313 {"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3314 {"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3315 {"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3316 {"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3317 {"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3318 {"ORACLE", "X6-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3319 {"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3320 { } /* End */ 3321 }; 3322 3323 #define BITMASK_OOB (BIT(8) | BIT(18)) 3324 3325 static bool __init intel_pstate_platform_pwr_mgmt_exists(void) 3326 { 3327 const struct x86_cpu_id *id; 3328 u64 misc_pwr; 3329 int idx; 3330 3331 id = x86_match_cpu(intel_pstate_cpu_oob_ids); 3332 if (id) { 3333 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr); 3334 if (misc_pwr & BITMASK_OOB) { 3335 pr_debug("Bit 8 or 18 in the MISC_PWR_MGMT MSR set\n"); 3336 pr_debug("P states are controlled in Out of Band mode by the firmware/hardware\n"); 3337 return true; 3338 } 3339 } 3340 3341 idx = acpi_match_platform_list(plat_info); 3342 if (idx < 0) 3343 return false; 3344 3345 switch (plat_info[idx].data) { 3346 case PSS: 3347 if (!intel_pstate_no_acpi_pss()) 3348 return false; 3349 3350 return intel_pstate_no_acpi_pcch(); 3351 case PPC: 3352 return intel_pstate_has_acpi_ppc() && !force_load; 3353 } 3354 3355 return false; 3356 } 3357 3358 static void intel_pstate_request_control_from_smm(void) 3359 { 3360 /* 3361 * It may be unsafe to request P-states control from SMM if _PPC support 3362 * has not been enabled. 3363 */ 3364 if (acpi_ppc) 3365 acpi_processor_pstate_control(); 3366 } 3367 #else /* CONFIG_ACPI not enabled */ 3368 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; } 3369 static inline bool intel_pstate_has_acpi_ppc(void) { return false; } 3370 static inline void intel_pstate_request_control_from_smm(void) {} 3371 #endif /* CONFIG_ACPI */ 3372 3373 #define INTEL_PSTATE_HWP_BROADWELL 0x01 3374 3375 #define X86_MATCH_HWP(model, hwp_mode) \ 3376 X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \ 3377 X86_FEATURE_HWP, hwp_mode) 3378 3379 static const struct x86_cpu_id hwp_support_ids[] __initconst = { 3380 X86_MATCH_HWP(BROADWELL_X, INTEL_PSTATE_HWP_BROADWELL), 3381 X86_MATCH_HWP(BROADWELL_D, INTEL_PSTATE_HWP_BROADWELL), 3382 X86_MATCH_HWP(ANY, 0), 3383 {} 3384 }; 3385 3386 static bool intel_pstate_hwp_is_enabled(void) 3387 { 3388 u64 value; 3389 3390 rdmsrl(MSR_PM_ENABLE, value); 3391 return !!(value & 0x1); 3392 } 3393 3394 static const struct x86_cpu_id intel_epp_balance_perf[] = { 3395 /* 3396 * Set EPP value as 102, this is the max suggested EPP 3397 * which can result in one core turbo frequency for 3398 * AlderLake Mobile CPUs. 3399 */ 3400 X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, 102), 3401 X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, 32), 3402 {} 3403 }; 3404 3405 static const struct x86_cpu_id intel_hybrid_scaling_factor[] = { 3406 X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE_L, HYBRID_SCALING_FACTOR_MTL), 3407 {} 3408 }; 3409 3410 static int __init intel_pstate_init(void) 3411 { 3412 static struct cpudata **_all_cpu_data; 3413 const struct x86_cpu_id *id; 3414 int rc; 3415 3416 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) 3417 return -ENODEV; 3418 3419 id = x86_match_cpu(hwp_support_ids); 3420 if (id) { 3421 hwp_forced = intel_pstate_hwp_is_enabled(); 3422 3423 if (hwp_forced) 3424 pr_info("HWP enabled by BIOS\n"); 3425 else if (no_load) 3426 return -ENODEV; 3427 3428 copy_cpu_funcs(&core_funcs); 3429 /* 3430 * Avoid enabling HWP for processors without EPP support, 3431 * because that means incomplete HWP implementation which is a 3432 * corner case and supporting it is generally problematic. 3433 * 3434 * If HWP is enabled already, though, there is no choice but to 3435 * deal with it. 3436 */ 3437 if ((!no_hwp && boot_cpu_has(X86_FEATURE_HWP_EPP)) || hwp_forced) { 3438 WRITE_ONCE(hwp_active, 1); 3439 hwp_mode_bdw = id->driver_data; 3440 intel_pstate.attr = hwp_cpufreq_attrs; 3441 intel_cpufreq.attr = hwp_cpufreq_attrs; 3442 intel_cpufreq.flags |= CPUFREQ_NEED_UPDATE_LIMITS; 3443 intel_cpufreq.adjust_perf = intel_cpufreq_adjust_perf; 3444 if (!default_driver) 3445 default_driver = &intel_pstate; 3446 3447 pstate_funcs.get_cpu_scaling = hwp_get_cpu_scaling; 3448 3449 goto hwp_cpu_matched; 3450 } 3451 pr_info("HWP not enabled\n"); 3452 } else { 3453 if (no_load) 3454 return -ENODEV; 3455 3456 id = x86_match_cpu(intel_pstate_cpu_ids); 3457 if (!id) { 3458 pr_info("CPU model not supported\n"); 3459 return -ENODEV; 3460 } 3461 3462 copy_cpu_funcs((struct pstate_funcs *)id->driver_data); 3463 } 3464 3465 if (intel_pstate_msrs_not_valid()) { 3466 pr_info("Invalid MSRs\n"); 3467 return -ENODEV; 3468 } 3469 /* Without HWP start in the passive mode. */ 3470 if (!default_driver) 3471 default_driver = &intel_cpufreq; 3472 3473 hwp_cpu_matched: 3474 /* 3475 * The Intel pstate driver will be ignored if the platform 3476 * firmware has its own power management modes. 3477 */ 3478 if (intel_pstate_platform_pwr_mgmt_exists()) { 3479 pr_info("P-states controlled by the platform\n"); 3480 return -ENODEV; 3481 } 3482 3483 if (!hwp_active && hwp_only) 3484 return -ENOTSUPP; 3485 3486 pr_info("Intel P-state driver initializing\n"); 3487 3488 _all_cpu_data = vzalloc(array_size(sizeof(void *), num_possible_cpus())); 3489 if (!_all_cpu_data) 3490 return -ENOMEM; 3491 3492 WRITE_ONCE(all_cpu_data, _all_cpu_data); 3493 3494 intel_pstate_request_control_from_smm(); 3495 3496 intel_pstate_sysfs_expose_params(); 3497 3498 if (hwp_active) { 3499 const struct x86_cpu_id *id = x86_match_cpu(intel_epp_balance_perf); 3500 const struct x86_cpu_id *hybrid_id = x86_match_cpu(intel_hybrid_scaling_factor); 3501 3502 if (id) 3503 epp_values[EPP_INDEX_BALANCE_PERFORMANCE] = id->driver_data; 3504 3505 if (hybrid_id) { 3506 hybrid_scaling_factor = hybrid_id->driver_data; 3507 pr_debug("hybrid scaling factor: %d\n", hybrid_scaling_factor); 3508 } 3509 3510 } 3511 3512 mutex_lock(&intel_pstate_driver_lock); 3513 rc = intel_pstate_register_driver(default_driver); 3514 mutex_unlock(&intel_pstate_driver_lock); 3515 if (rc) { 3516 intel_pstate_sysfs_remove(); 3517 return rc; 3518 } 3519 3520 if (hwp_active) { 3521 const struct x86_cpu_id *id; 3522 3523 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids); 3524 if (id) { 3525 set_power_ctl_ee_state(false); 3526 pr_info("Disabling energy efficiency optimization\n"); 3527 } 3528 3529 pr_info("HWP enabled\n"); 3530 } else if (boot_cpu_has(X86_FEATURE_HYBRID_CPU)) { 3531 pr_warn("Problematic setup: Hybrid processor with disabled HWP\n"); 3532 } 3533 3534 return 0; 3535 } 3536 device_initcall(intel_pstate_init); 3537 3538 static int __init intel_pstate_setup(char *str) 3539 { 3540 if (!str) 3541 return -EINVAL; 3542 3543 if (!strcmp(str, "disable")) 3544 no_load = 1; 3545 else if (!strcmp(str, "active")) 3546 default_driver = &intel_pstate; 3547 else if (!strcmp(str, "passive")) 3548 default_driver = &intel_cpufreq; 3549 3550 if (!strcmp(str, "no_hwp")) 3551 no_hwp = 1; 3552 3553 if (!strcmp(str, "force")) 3554 force_load = 1; 3555 if (!strcmp(str, "hwp_only")) 3556 hwp_only = 1; 3557 if (!strcmp(str, "per_cpu_perf_limits")) 3558 per_cpu_limits = true; 3559 3560 #ifdef CONFIG_ACPI 3561 if (!strcmp(str, "support_acpi_ppc")) 3562 acpi_ppc = true; 3563 #endif 3564 3565 return 0; 3566 } 3567 early_param("intel_pstate", intel_pstate_setup); 3568 3569 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>"); 3570 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors"); 3571