1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * intel_pstate.c: Native P state management for Intel processors 4 * 5 * (C) Copyright 2012 Intel Corporation 6 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com> 7 */ 8 9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10 11 #include <linux/kernel.h> 12 #include <linux/kernel_stat.h> 13 #include <linux/module.h> 14 #include <linux/ktime.h> 15 #include <linux/hrtimer.h> 16 #include <linux/tick.h> 17 #include <linux/slab.h> 18 #include <linux/sched/cpufreq.h> 19 #include <linux/sched/smt.h> 20 #include <linux/list.h> 21 #include <linux/cpu.h> 22 #include <linux/cpufreq.h> 23 #include <linux/sysfs.h> 24 #include <linux/types.h> 25 #include <linux/fs.h> 26 #include <linux/acpi.h> 27 #include <linux/vmalloc.h> 28 #include <linux/pm_qos.h> 29 #include <linux/bitfield.h> 30 #include <trace/events/power.h> 31 #include <linux/units.h> 32 33 #include <asm/cpu.h> 34 #include <asm/div64.h> 35 #include <asm/msr.h> 36 #include <asm/cpu_device_id.h> 37 #include <asm/cpufeature.h> 38 #include <asm/intel-family.h> 39 #include "../drivers/thermal/intel/thermal_interrupt.h" 40 41 #define INTEL_PSTATE_SAMPLING_INTERVAL (10 * NSEC_PER_MSEC) 42 43 #define INTEL_CPUFREQ_TRANSITION_LATENCY 20000 44 #define INTEL_CPUFREQ_TRANSITION_DELAY_HWP 5000 45 #define INTEL_CPUFREQ_TRANSITION_DELAY 500 46 47 #ifdef CONFIG_ACPI 48 #include <acpi/processor.h> 49 #include <acpi/cppc_acpi.h> 50 #endif 51 52 #define FRAC_BITS 8 53 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS) 54 #define fp_toint(X) ((X) >> FRAC_BITS) 55 56 #define ONE_EIGHTH_FP ((int64_t)1 << (FRAC_BITS - 3)) 57 58 #define EXT_BITS 6 59 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS) 60 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS) 61 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS) 62 63 static inline int32_t mul_fp(int32_t x, int32_t y) 64 { 65 return ((int64_t)x * (int64_t)y) >> FRAC_BITS; 66 } 67 68 static inline int32_t div_fp(s64 x, s64 y) 69 { 70 return div64_s64((int64_t)x << FRAC_BITS, y); 71 } 72 73 static inline int ceiling_fp(int32_t x) 74 { 75 int mask, ret; 76 77 ret = fp_toint(x); 78 mask = (1 << FRAC_BITS) - 1; 79 if (x & mask) 80 ret += 1; 81 return ret; 82 } 83 84 static inline u64 mul_ext_fp(u64 x, u64 y) 85 { 86 return (x * y) >> EXT_FRAC_BITS; 87 } 88 89 static inline u64 div_ext_fp(u64 x, u64 y) 90 { 91 return div64_u64(x << EXT_FRAC_BITS, y); 92 } 93 94 /** 95 * struct sample - Store performance sample 96 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average 97 * performance during last sample period 98 * @busy_scaled: Scaled busy value which is used to calculate next 99 * P state. This can be different than core_avg_perf 100 * to account for cpu idle period 101 * @aperf: Difference of actual performance frequency clock count 102 * read from APERF MSR between last and current sample 103 * @mperf: Difference of maximum performance frequency clock count 104 * read from MPERF MSR between last and current sample 105 * @tsc: Difference of time stamp counter between last and 106 * current sample 107 * @time: Current time from scheduler 108 * 109 * This structure is used in the cpudata structure to store performance sample 110 * data for choosing next P State. 111 */ 112 struct sample { 113 int32_t core_avg_perf; 114 int32_t busy_scaled; 115 u64 aperf; 116 u64 mperf; 117 u64 tsc; 118 u64 time; 119 }; 120 121 /** 122 * struct pstate_data - Store P state data 123 * @current_pstate: Current requested P state 124 * @min_pstate: Min P state possible for this platform 125 * @max_pstate: Max P state possible for this platform 126 * @max_pstate_physical:This is physical Max P state for a processor 127 * This can be higher than the max_pstate which can 128 * be limited by platform thermal design power limits 129 * @perf_ctl_scaling: PERF_CTL P-state to frequency scaling factor 130 * @scaling: Scaling factor between performance and frequency 131 * @turbo_pstate: Max Turbo P state possible for this platform 132 * @min_freq: @min_pstate frequency in cpufreq units 133 * @max_freq: @max_pstate frequency in cpufreq units 134 * @turbo_freq: @turbo_pstate frequency in cpufreq units 135 * 136 * Stores the per cpu model P state limits and current P state. 137 */ 138 struct pstate_data { 139 int current_pstate; 140 int min_pstate; 141 int max_pstate; 142 int max_pstate_physical; 143 int perf_ctl_scaling; 144 int scaling; 145 int turbo_pstate; 146 unsigned int min_freq; 147 unsigned int max_freq; 148 unsigned int turbo_freq; 149 }; 150 151 /** 152 * struct vid_data - Stores voltage information data 153 * @min: VID data for this platform corresponding to 154 * the lowest P state 155 * @max: VID data corresponding to the highest P State. 156 * @turbo: VID data for turbo P state 157 * @ratio: Ratio of (vid max - vid min) / 158 * (max P state - Min P State) 159 * 160 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling) 161 * This data is used in Atom platforms, where in addition to target P state, 162 * the voltage data needs to be specified to select next P State. 163 */ 164 struct vid_data { 165 int min; 166 int max; 167 int turbo; 168 int32_t ratio; 169 }; 170 171 /** 172 * struct global_params - Global parameters, mostly tunable via sysfs. 173 * @no_turbo: Whether or not to use turbo P-states. 174 * @turbo_disabled: Whether or not turbo P-states are available at all, 175 * based on the MSR_IA32_MISC_ENABLE value and whether or 176 * not the maximum reported turbo P-state is different from 177 * the maximum reported non-turbo one. 178 * @min_perf_pct: Minimum capacity limit in percent of the maximum turbo 179 * P-state capacity. 180 * @max_perf_pct: Maximum capacity limit in percent of the maximum turbo 181 * P-state capacity. 182 */ 183 struct global_params { 184 bool no_turbo; 185 bool turbo_disabled; 186 int max_perf_pct; 187 int min_perf_pct; 188 }; 189 190 /** 191 * struct cpudata - Per CPU instance data storage 192 * @cpu: CPU number for this instance data 193 * @policy: CPUFreq policy value 194 * @update_util: CPUFreq utility callback information 195 * @update_util_set: CPUFreq utility callback is set 196 * @iowait_boost: iowait-related boost fraction 197 * @last_update: Time of the last update. 198 * @pstate: Stores P state limits for this CPU 199 * @vid: Stores VID limits for this CPU 200 * @last_sample_time: Last Sample time 201 * @aperf_mperf_shift: APERF vs MPERF counting frequency difference 202 * @prev_aperf: Last APERF value read from APERF MSR 203 * @prev_mperf: Last MPERF value read from MPERF MSR 204 * @prev_tsc: Last timestamp counter (TSC) value 205 * @sample: Storage for storing last Sample data 206 * @min_perf_ratio: Minimum capacity in terms of PERF or HWP ratios 207 * @max_perf_ratio: Maximum capacity in terms of PERF or HWP ratios 208 * @acpi_perf_data: Stores ACPI perf information read from _PSS 209 * @valid_pss_table: Set to true for valid ACPI _PSS entries found 210 * @epp_powersave: Last saved HWP energy performance preference 211 * (EPP) or energy performance bias (EPB), 212 * when policy switched to performance 213 * @epp_policy: Last saved policy used to set EPP/EPB 214 * @epp_default: Power on default HWP energy performance 215 * preference/bias 216 * @epp_cached: Cached HWP energy-performance preference value 217 * @hwp_req_cached: Cached value of the last HWP Request MSR 218 * @hwp_cap_cached: Cached value of the last HWP Capabilities MSR 219 * @last_io_update: Last time when IO wake flag was set 220 * @capacity_perf: Highest perf used for scale invariance 221 * @sched_flags: Store scheduler flags for possible cross CPU update 222 * @hwp_boost_min: Last HWP boosted min performance 223 * @suspended: Whether or not the driver has been suspended. 224 * @pd_registered: Set when a perf domain is registered for this CPU. 225 * @hwp_notify_work: workqueue for HWP notifications. 226 * 227 * This structure stores per CPU instance data for all CPUs. 228 */ 229 struct cpudata { 230 int cpu; 231 232 unsigned int policy; 233 struct update_util_data update_util; 234 bool update_util_set; 235 236 struct pstate_data pstate; 237 struct vid_data vid; 238 239 u64 last_update; 240 u64 last_sample_time; 241 u64 aperf_mperf_shift; 242 u64 prev_aperf; 243 u64 prev_mperf; 244 u64 prev_tsc; 245 struct sample sample; 246 int32_t min_perf_ratio; 247 int32_t max_perf_ratio; 248 #ifdef CONFIG_ACPI 249 struct acpi_processor_performance acpi_perf_data; 250 bool valid_pss_table; 251 #endif 252 unsigned int iowait_boost; 253 s16 epp_powersave; 254 s16 epp_policy; 255 s16 epp_default; 256 s16 epp_cached; 257 u64 hwp_req_cached; 258 u64 hwp_cap_cached; 259 u64 last_io_update; 260 unsigned int capacity_perf; 261 unsigned int sched_flags; 262 u32 hwp_boost_min; 263 bool suspended; 264 #ifdef CONFIG_ENERGY_MODEL 265 bool pd_registered; 266 #endif 267 struct delayed_work hwp_notify_work; 268 }; 269 270 static struct cpudata **all_cpu_data; 271 272 /** 273 * struct pstate_funcs - Per CPU model specific callbacks 274 * @get_max: Callback to get maximum non turbo effective P state 275 * @get_max_physical: Callback to get maximum non turbo physical P state 276 * @get_min: Callback to get minimum P state 277 * @get_turbo: Callback to get turbo P state 278 * @get_scaling: Callback to get frequency scaling factor 279 * @get_cpu_scaling: Get frequency scaling factor for a given cpu 280 * @get_aperf_mperf_shift: Callback to get the APERF vs MPERF frequency difference 281 * @get_val: Callback to convert P state to actual MSR write value 282 * @get_vid: Callback to get VID data for Atom platforms 283 * 284 * Core and Atom CPU models have different way to get P State limits. This 285 * structure is used to store those callbacks. 286 */ 287 struct pstate_funcs { 288 int (*get_max)(int cpu); 289 int (*get_max_physical)(int cpu); 290 int (*get_min)(int cpu); 291 int (*get_turbo)(int cpu); 292 int (*get_scaling)(void); 293 int (*get_cpu_scaling)(int cpu); 294 int (*get_aperf_mperf_shift)(void); 295 u64 (*get_val)(struct cpudata*, int pstate); 296 void (*get_vid)(struct cpudata *); 297 }; 298 299 static struct pstate_funcs pstate_funcs __read_mostly; 300 301 static bool hwp_active __ro_after_init; 302 static int hwp_mode_bdw __ro_after_init; 303 static bool per_cpu_limits __ro_after_init; 304 static bool hwp_forced __ro_after_init; 305 static bool hwp_boost __read_mostly; 306 static bool hwp_is_hybrid; 307 308 static struct cpufreq_driver *intel_pstate_driver __read_mostly; 309 310 #define INTEL_PSTATE_CORE_SCALING 100000 311 #define HYBRID_SCALING_FACTOR_ADL 78741 312 #define HYBRID_SCALING_FACTOR_MTL 80000 313 #define HYBRID_SCALING_FACTOR_LNL 86957 314 315 static int hybrid_scaling_factor; 316 317 static inline int core_get_scaling(void) 318 { 319 return INTEL_PSTATE_CORE_SCALING; 320 } 321 322 #ifdef CONFIG_ACPI 323 static bool acpi_ppc; 324 #endif 325 326 static struct global_params global; 327 328 static DEFINE_MUTEX(intel_pstate_driver_lock); 329 static DEFINE_MUTEX(intel_pstate_limits_lock); 330 331 #ifdef CONFIG_ACPI 332 333 static bool intel_pstate_acpi_pm_profile_server(void) 334 { 335 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER || 336 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER) 337 return true; 338 339 return false; 340 } 341 342 static bool intel_pstate_get_ppc_enable_status(void) 343 { 344 if (intel_pstate_acpi_pm_profile_server()) 345 return true; 346 347 return acpi_ppc; 348 } 349 350 #ifdef CONFIG_ACPI_CPPC_LIB 351 352 /* The work item is needed to avoid CPU hotplug locking issues */ 353 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work) 354 { 355 sched_set_itmt_support(); 356 } 357 358 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn); 359 360 #define CPPC_MAX_PERF U8_MAX 361 362 static void intel_pstate_set_itmt_prio(int cpu) 363 { 364 struct cppc_perf_caps cppc_perf; 365 static u32 max_highest_perf = 0, min_highest_perf = U32_MAX; 366 int ret; 367 368 ret = cppc_get_perf_caps(cpu, &cppc_perf); 369 /* 370 * If CPPC is not available, fall back to MSR_HWP_CAPABILITIES bits [8:0]. 371 * 372 * Also, on some systems with overclocking enabled, CPPC.highest_perf is 373 * hardcoded to 0xff, so CPPC.highest_perf cannot be used to enable ITMT. 374 * Fall back to MSR_HWP_CAPABILITIES then too. 375 */ 376 if (ret || cppc_perf.highest_perf == CPPC_MAX_PERF) 377 cppc_perf.highest_perf = HWP_HIGHEST_PERF(READ_ONCE(all_cpu_data[cpu]->hwp_cap_cached)); 378 379 /* 380 * The priorities can be set regardless of whether or not 381 * sched_set_itmt_support(true) has been called and it is valid to 382 * update them at any time after it has been called. 383 */ 384 sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu); 385 386 if (max_highest_perf <= min_highest_perf) { 387 if (cppc_perf.highest_perf > max_highest_perf) 388 max_highest_perf = cppc_perf.highest_perf; 389 390 if (cppc_perf.highest_perf < min_highest_perf) 391 min_highest_perf = cppc_perf.highest_perf; 392 393 if (max_highest_perf > min_highest_perf) { 394 /* 395 * This code can be run during CPU online under the 396 * CPU hotplug locks, so sched_set_itmt_support() 397 * cannot be called from here. Queue up a work item 398 * to invoke it. 399 */ 400 schedule_work(&sched_itmt_work); 401 } 402 } 403 } 404 405 static int intel_pstate_get_cppc_guaranteed(int cpu) 406 { 407 struct cppc_perf_caps cppc_perf; 408 int ret; 409 410 ret = cppc_get_perf_caps(cpu, &cppc_perf); 411 if (ret) 412 return ret; 413 414 if (cppc_perf.guaranteed_perf) 415 return cppc_perf.guaranteed_perf; 416 417 return cppc_perf.nominal_perf; 418 } 419 420 static int intel_pstate_cppc_get_scaling(int cpu) 421 { 422 struct cppc_perf_caps cppc_perf; 423 424 /* 425 * Compute the perf-to-frequency scaling factor for the given CPU if 426 * possible, unless it would be 0. 427 */ 428 if (!cppc_get_perf_caps(cpu, &cppc_perf) && 429 cppc_perf.nominal_perf && cppc_perf.nominal_freq) 430 return div_u64(cppc_perf.nominal_freq * KHZ_PER_MHZ, 431 cppc_perf.nominal_perf); 432 433 return core_get_scaling(); 434 } 435 436 #else /* CONFIG_ACPI_CPPC_LIB */ 437 static inline void intel_pstate_set_itmt_prio(int cpu) 438 { 439 } 440 #endif /* CONFIG_ACPI_CPPC_LIB */ 441 442 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) 443 { 444 struct cpudata *cpu; 445 int ret; 446 int i; 447 448 if (hwp_active) { 449 intel_pstate_set_itmt_prio(policy->cpu); 450 return; 451 } 452 453 if (!intel_pstate_get_ppc_enable_status()) 454 return; 455 456 cpu = all_cpu_data[policy->cpu]; 457 458 ret = acpi_processor_register_performance(&cpu->acpi_perf_data, 459 policy->cpu); 460 if (ret) 461 return; 462 463 /* 464 * Check if the control value in _PSS is for PERF_CTL MSR, which should 465 * guarantee that the states returned by it map to the states in our 466 * list directly. 467 */ 468 if (cpu->acpi_perf_data.control_register.space_id != 469 ACPI_ADR_SPACE_FIXED_HARDWARE) 470 goto err; 471 472 /* 473 * If there is only one entry _PSS, simply ignore _PSS and continue as 474 * usual without taking _PSS into account 475 */ 476 if (cpu->acpi_perf_data.state_count < 2) 477 goto err; 478 479 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu); 480 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) { 481 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n", 482 (i == cpu->acpi_perf_data.state ? '*' : ' '), i, 483 (u32) cpu->acpi_perf_data.states[i].core_frequency, 484 (u32) cpu->acpi_perf_data.states[i].power, 485 (u32) cpu->acpi_perf_data.states[i].control); 486 } 487 488 cpu->valid_pss_table = true; 489 pr_debug("_PPC limits will be enforced\n"); 490 491 return; 492 493 err: 494 cpu->valid_pss_table = false; 495 acpi_processor_unregister_performance(policy->cpu); 496 } 497 498 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) 499 { 500 struct cpudata *cpu; 501 502 cpu = all_cpu_data[policy->cpu]; 503 if (!cpu->valid_pss_table) 504 return; 505 506 acpi_processor_unregister_performance(policy->cpu); 507 } 508 #else /* CONFIG_ACPI */ 509 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) 510 { 511 } 512 513 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) 514 { 515 } 516 517 static inline bool intel_pstate_acpi_pm_profile_server(void) 518 { 519 return false; 520 } 521 #endif /* CONFIG_ACPI */ 522 523 #ifndef CONFIG_ACPI_CPPC_LIB 524 static inline int intel_pstate_get_cppc_guaranteed(int cpu) 525 { 526 return -ENOTSUPP; 527 } 528 529 static int intel_pstate_cppc_get_scaling(int cpu) 530 { 531 return core_get_scaling(); 532 } 533 #endif /* CONFIG_ACPI_CPPC_LIB */ 534 535 static int intel_pstate_freq_to_hwp_rel(struct cpudata *cpu, int freq, 536 unsigned int relation) 537 { 538 if (freq == cpu->pstate.turbo_freq) 539 return cpu->pstate.turbo_pstate; 540 541 if (freq == cpu->pstate.max_freq) 542 return cpu->pstate.max_pstate; 543 544 switch (relation) { 545 case CPUFREQ_RELATION_H: 546 return freq / cpu->pstate.scaling; 547 case CPUFREQ_RELATION_C: 548 return DIV_ROUND_CLOSEST(freq, cpu->pstate.scaling); 549 } 550 551 return DIV_ROUND_UP(freq, cpu->pstate.scaling); 552 } 553 554 static int intel_pstate_freq_to_hwp(struct cpudata *cpu, int freq) 555 { 556 return intel_pstate_freq_to_hwp_rel(cpu, freq, CPUFREQ_RELATION_L); 557 } 558 559 /** 560 * intel_pstate_hybrid_hwp_adjust - Calibrate HWP performance levels. 561 * @cpu: Target CPU. 562 * 563 * On hybrid processors, HWP may expose more performance levels than there are 564 * P-states accessible through the PERF_CTL interface. If that happens, the 565 * scaling factor between HWP performance levels and CPU frequency will be less 566 * than the scaling factor between P-state values and CPU frequency. 567 * 568 * In that case, adjust the CPU parameters used in computations accordingly. 569 */ 570 static void intel_pstate_hybrid_hwp_adjust(struct cpudata *cpu) 571 { 572 int perf_ctl_max_phys = cpu->pstate.max_pstate_physical; 573 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling; 574 int perf_ctl_turbo = pstate_funcs.get_turbo(cpu->cpu); 575 int scaling = cpu->pstate.scaling; 576 int freq; 577 578 pr_debug("CPU%d: perf_ctl_max_phys = %d\n", cpu->cpu, perf_ctl_max_phys); 579 pr_debug("CPU%d: perf_ctl_turbo = %d\n", cpu->cpu, perf_ctl_turbo); 580 pr_debug("CPU%d: perf_ctl_scaling = %d\n", cpu->cpu, perf_ctl_scaling); 581 pr_debug("CPU%d: HWP_CAP guaranteed = %d\n", cpu->cpu, cpu->pstate.max_pstate); 582 pr_debug("CPU%d: HWP_CAP highest = %d\n", cpu->cpu, cpu->pstate.turbo_pstate); 583 pr_debug("CPU%d: HWP-to-frequency scaling factor: %d\n", cpu->cpu, scaling); 584 585 cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_pstate * scaling, 586 perf_ctl_scaling); 587 cpu->pstate.max_freq = rounddown(cpu->pstate.max_pstate * scaling, 588 perf_ctl_scaling); 589 590 freq = perf_ctl_max_phys * perf_ctl_scaling; 591 cpu->pstate.max_pstate_physical = intel_pstate_freq_to_hwp(cpu, freq); 592 593 freq = cpu->pstate.min_pstate * perf_ctl_scaling; 594 cpu->pstate.min_freq = freq; 595 /* 596 * Cast the min P-state value retrieved via pstate_funcs.get_min() to 597 * the effective range of HWP performance levels. 598 */ 599 cpu->pstate.min_pstate = intel_pstate_freq_to_hwp(cpu, freq); 600 } 601 602 static bool turbo_is_disabled(void) 603 { 604 u64 misc_en; 605 606 rdmsrq(MSR_IA32_MISC_ENABLE, misc_en); 607 608 return !!(misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE); 609 } 610 611 static int min_perf_pct_min(void) 612 { 613 struct cpudata *cpu = all_cpu_data[0]; 614 int turbo_pstate = cpu->pstate.turbo_pstate; 615 616 return turbo_pstate ? 617 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0; 618 } 619 620 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data) 621 { 622 s16 epp = -EOPNOTSUPP; 623 624 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 625 /* 626 * When hwp_req_data is 0, means that caller didn't read 627 * MSR_HWP_REQUEST, so need to read and get EPP. 628 */ 629 if (!hwp_req_data) { 630 epp = rdmsrq_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, 631 &hwp_req_data); 632 if (epp) 633 return epp; 634 } 635 epp = (hwp_req_data >> 24) & 0xff; 636 } 637 638 return epp; 639 } 640 641 /* 642 * EPP display strings corresponding to EPP index in the 643 * energy_perf_strings[] 644 * index String 645 *------------------------------------- 646 * 0 default 647 * 1 performance 648 * 2 balance_performance 649 * 3 balance_power 650 * 4 power 651 */ 652 653 enum energy_perf_value_index { 654 EPP_INDEX_DEFAULT = 0, 655 EPP_INDEX_PERFORMANCE, 656 EPP_INDEX_BALANCE_PERFORMANCE, 657 EPP_INDEX_BALANCE_POWERSAVE, 658 EPP_INDEX_POWERSAVE, 659 }; 660 661 static const char * const energy_perf_strings[] = { 662 [EPP_INDEX_DEFAULT] = "default", 663 [EPP_INDEX_PERFORMANCE] = "performance", 664 [EPP_INDEX_BALANCE_PERFORMANCE] = "balance_performance", 665 [EPP_INDEX_BALANCE_POWERSAVE] = "balance_power", 666 [EPP_INDEX_POWERSAVE] = "power", 667 NULL 668 }; 669 static unsigned int epp_values[] = { 670 [EPP_INDEX_DEFAULT] = 0, /* Unused index */ 671 [EPP_INDEX_PERFORMANCE] = HWP_EPP_PERFORMANCE, 672 [EPP_INDEX_BALANCE_PERFORMANCE] = HWP_EPP_BALANCE_PERFORMANCE, 673 [EPP_INDEX_BALANCE_POWERSAVE] = HWP_EPP_BALANCE_POWERSAVE, 674 [EPP_INDEX_POWERSAVE] = HWP_EPP_POWERSAVE, 675 }; 676 677 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data, int *raw_epp) 678 { 679 s16 epp; 680 int index = -EINVAL; 681 682 *raw_epp = 0; 683 epp = intel_pstate_get_epp(cpu_data, 0); 684 if (epp < 0) 685 return epp; 686 687 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 688 if (epp == epp_values[EPP_INDEX_PERFORMANCE]) 689 return EPP_INDEX_PERFORMANCE; 690 if (epp == epp_values[EPP_INDEX_BALANCE_PERFORMANCE]) 691 return EPP_INDEX_BALANCE_PERFORMANCE; 692 if (epp == epp_values[EPP_INDEX_BALANCE_POWERSAVE]) 693 return EPP_INDEX_BALANCE_POWERSAVE; 694 if (epp == epp_values[EPP_INDEX_POWERSAVE]) 695 return EPP_INDEX_POWERSAVE; 696 *raw_epp = epp; 697 return 0; 698 } else if (boot_cpu_has(X86_FEATURE_EPB)) { 699 /* 700 * Range: 701 * 0x00-0x03 : Performance 702 * 0x04-0x07 : Balance performance 703 * 0x08-0x0B : Balance power 704 * 0x0C-0x0F : Power 705 * The EPB is a 4 bit value, but our ranges restrict the 706 * value which can be set. Here only using top two bits 707 * effectively. 708 */ 709 index = (epp >> 2) + 1; 710 } 711 712 return index; 713 } 714 715 static int intel_pstate_set_epp(struct cpudata *cpu, u32 epp) 716 { 717 int ret; 718 719 /* 720 * Use the cached HWP Request MSR value, because in the active mode the 721 * register itself may be updated by intel_pstate_hwp_boost_up() or 722 * intel_pstate_hwp_boost_down() at any time. 723 */ 724 u64 value = READ_ONCE(cpu->hwp_req_cached); 725 726 value &= ~GENMASK_ULL(31, 24); 727 value |= (u64)epp << 24; 728 /* 729 * The only other updater of hwp_req_cached in the active mode, 730 * intel_pstate_hwp_set(), is called under the same lock as this 731 * function, so it cannot run in parallel with the update below. 732 */ 733 WRITE_ONCE(cpu->hwp_req_cached, value); 734 ret = wrmsrq_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 735 if (!ret) 736 cpu->epp_cached = epp; 737 738 return ret; 739 } 740 741 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data, 742 int pref_index, bool use_raw, 743 u32 raw_epp) 744 { 745 int epp = -EINVAL; 746 int ret = -EOPNOTSUPP; 747 748 if (!pref_index) 749 epp = cpu_data->epp_default; 750 751 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 752 if (use_raw) 753 epp = raw_epp; 754 else if (epp == -EINVAL) 755 epp = epp_values[pref_index]; 756 757 /* 758 * To avoid confusion, refuse to set EPP to any values different 759 * from 0 (performance) if the current policy is "performance", 760 * because those values would be overridden. 761 */ 762 if (epp > 0 && cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) 763 return -EBUSY; 764 765 ret = intel_pstate_set_epp(cpu_data, epp); 766 } 767 768 return ret; 769 } 770 771 static ssize_t show_energy_performance_available_preferences( 772 struct cpufreq_policy *policy, char *buf) 773 { 774 int i = 0; 775 int ret = 0; 776 777 while (energy_perf_strings[i] != NULL) 778 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]); 779 780 ret += sprintf(&buf[ret], "\n"); 781 782 return ret; 783 } 784 785 cpufreq_freq_attr_ro(energy_performance_available_preferences); 786 787 static struct cpufreq_driver intel_pstate; 788 789 static ssize_t store_energy_performance_preference( 790 struct cpufreq_policy *policy, const char *buf, size_t count) 791 { 792 struct cpudata *cpu = all_cpu_data[policy->cpu]; 793 char str_preference[21]; 794 bool raw = false; 795 ssize_t ret; 796 u32 epp = 0; 797 798 ret = sscanf(buf, "%20s", str_preference); 799 if (ret != 1) 800 return -EINVAL; 801 802 ret = match_string(energy_perf_strings, -1, str_preference); 803 if (ret < 0) { 804 if (!boot_cpu_has(X86_FEATURE_HWP_EPP)) 805 return ret; 806 807 ret = kstrtouint(buf, 10, &epp); 808 if (ret) 809 return ret; 810 811 if (epp > 255) 812 return -EINVAL; 813 814 raw = true; 815 } 816 817 /* 818 * This function runs with the policy R/W semaphore held, which 819 * guarantees that the driver pointer will not change while it is 820 * running. 821 */ 822 if (!intel_pstate_driver) 823 return -EAGAIN; 824 825 mutex_lock(&intel_pstate_limits_lock); 826 827 if (intel_pstate_driver == &intel_pstate) { 828 ret = intel_pstate_set_energy_pref_index(cpu, ret, raw, epp); 829 } else { 830 /* 831 * In the passive mode the governor needs to be stopped on the 832 * target CPU before the EPP update and restarted after it, 833 * which is super-heavy-weight, so make sure it is worth doing 834 * upfront. 835 */ 836 if (!raw) 837 epp = ret ? epp_values[ret] : cpu->epp_default; 838 839 if (cpu->epp_cached != epp) { 840 int err; 841 842 cpufreq_stop_governor(policy); 843 ret = intel_pstate_set_epp(cpu, epp); 844 err = cpufreq_start_governor(policy); 845 if (!ret) 846 ret = err; 847 } else { 848 ret = 0; 849 } 850 } 851 852 mutex_unlock(&intel_pstate_limits_lock); 853 854 return ret ?: count; 855 } 856 857 static ssize_t show_energy_performance_preference( 858 struct cpufreq_policy *policy, char *buf) 859 { 860 struct cpudata *cpu_data = all_cpu_data[policy->cpu]; 861 int preference, raw_epp; 862 863 preference = intel_pstate_get_energy_pref_index(cpu_data, &raw_epp); 864 if (preference < 0) 865 return preference; 866 867 if (raw_epp) 868 return sprintf(buf, "%d\n", raw_epp); 869 else 870 return sprintf(buf, "%s\n", energy_perf_strings[preference]); 871 } 872 873 cpufreq_freq_attr_rw(energy_performance_preference); 874 875 static ssize_t show_base_frequency(struct cpufreq_policy *policy, char *buf) 876 { 877 struct cpudata *cpu = all_cpu_data[policy->cpu]; 878 int ratio, freq; 879 880 ratio = intel_pstate_get_cppc_guaranteed(policy->cpu); 881 if (ratio <= 0) { 882 u64 cap; 883 884 rdmsrq_on_cpu(policy->cpu, MSR_HWP_CAPABILITIES, &cap); 885 ratio = HWP_GUARANTEED_PERF(cap); 886 } 887 888 freq = ratio * cpu->pstate.scaling; 889 if (cpu->pstate.scaling != cpu->pstate.perf_ctl_scaling) 890 freq = rounddown(freq, cpu->pstate.perf_ctl_scaling); 891 892 return sprintf(buf, "%d\n", freq); 893 } 894 895 cpufreq_freq_attr_ro(base_frequency); 896 897 enum hwp_cpufreq_attr_index { 898 HWP_BASE_FREQUENCY_INDEX = 0, 899 HWP_PERFORMANCE_PREFERENCE_INDEX, 900 HWP_PERFORMANCE_AVAILABLE_PREFERENCES_INDEX, 901 HWP_CPUFREQ_ATTR_COUNT, 902 }; 903 904 static struct freq_attr *hwp_cpufreq_attrs[] = { 905 [HWP_BASE_FREQUENCY_INDEX] = &base_frequency, 906 [HWP_PERFORMANCE_PREFERENCE_INDEX] = &energy_performance_preference, 907 [HWP_PERFORMANCE_AVAILABLE_PREFERENCES_INDEX] = 908 &energy_performance_available_preferences, 909 [HWP_CPUFREQ_ATTR_COUNT] = NULL, 910 }; 911 912 static bool no_cas __ro_after_init; 913 914 static struct cpudata *hybrid_max_perf_cpu __read_mostly; 915 /* 916 * Protects hybrid_max_perf_cpu, the capacity_perf fields in struct cpudata, 917 * and the x86 arch scale-invariance information from concurrent updates. 918 */ 919 static DEFINE_MUTEX(hybrid_capacity_lock); 920 921 #ifdef CONFIG_ENERGY_MODEL 922 #define HYBRID_EM_STATE_COUNT 4 923 924 static int hybrid_active_power(struct device *dev, unsigned long *power, 925 unsigned long *freq) 926 { 927 /* 928 * Create "utilization bins" of 0-40%, 40%-60%, 60%-80%, and 80%-100% 929 * of the maximum capacity such that two CPUs of the same type will be 930 * regarded as equally attractive if the utilization of each of them 931 * falls into the same bin, which should prevent tasks from being 932 * migrated between them too often. 933 * 934 * For this purpose, return the "frequency" of 2 for the first 935 * performance level and otherwise leave the value set by the caller. 936 */ 937 if (!*freq) 938 *freq = 2; 939 940 /* No power information. */ 941 *power = EM_MAX_POWER; 942 943 return 0; 944 } 945 946 static int hybrid_get_cost(struct device *dev, unsigned long freq, 947 unsigned long *cost) 948 { 949 struct pstate_data *pstate = &all_cpu_data[dev->id]->pstate; 950 struct cpu_cacheinfo *cacheinfo = get_cpu_cacheinfo(dev->id); 951 952 /* 953 * The smaller the perf-to-frequency scaling factor, the larger the IPC 954 * ratio between the given CPU and the least capable CPU in the system. 955 * Regard that IPC ratio as the primary cost component and assume that 956 * the scaling factors for different CPU types will differ by at least 957 * 5% and they will not be above INTEL_PSTATE_CORE_SCALING. 958 * 959 * Add the freq value to the cost, so that the cost of running on CPUs 960 * of the same type in different "utilization bins" is different. 961 */ 962 *cost = div_u64(100ULL * INTEL_PSTATE_CORE_SCALING, pstate->scaling) + freq; 963 /* 964 * Increase the cost slightly for CPUs able to access L3 to avoid 965 * touching it in case some other CPUs of the same type can do the work 966 * without it. 967 */ 968 if (cacheinfo) { 969 unsigned int i; 970 971 /* Check if L3 cache is there. */ 972 for (i = 0; i < cacheinfo->num_leaves; i++) { 973 if (cacheinfo->info_list[i].level == 3) { 974 *cost += 2; 975 break; 976 } 977 } 978 } 979 980 return 0; 981 } 982 983 static bool hybrid_register_perf_domain(unsigned int cpu) 984 { 985 static const struct em_data_callback cb 986 = EM_ADV_DATA_CB(hybrid_active_power, hybrid_get_cost); 987 struct cpudata *cpudata = all_cpu_data[cpu]; 988 struct device *cpu_dev; 989 990 /* 991 * Registering EM perf domains without enabling asymmetric CPU capacity 992 * support is not really useful and one domain should not be registered 993 * more than once. 994 */ 995 if (!hybrid_max_perf_cpu || cpudata->pd_registered) 996 return false; 997 998 cpu_dev = get_cpu_device(cpu); 999 if (!cpu_dev) 1000 return false; 1001 1002 if (em_dev_register_pd_no_update(cpu_dev, HYBRID_EM_STATE_COUNT, &cb, 1003 cpumask_of(cpu), false)) 1004 return false; 1005 1006 cpudata->pd_registered = true; 1007 1008 return true; 1009 } 1010 1011 static void hybrid_register_all_perf_domains(void) 1012 { 1013 unsigned int cpu; 1014 1015 for_each_online_cpu(cpu) 1016 hybrid_register_perf_domain(cpu); 1017 } 1018 1019 static void hybrid_update_perf_domain(struct cpudata *cpu) 1020 { 1021 if (cpu->pd_registered) 1022 em_adjust_cpu_capacity(cpu->cpu); 1023 } 1024 #else /* !CONFIG_ENERGY_MODEL */ 1025 static inline bool hybrid_register_perf_domain(unsigned int cpu) { return false; } 1026 static inline void hybrid_register_all_perf_domains(void) {} 1027 static inline void hybrid_update_perf_domain(struct cpudata *cpu) {} 1028 #endif /* CONFIG_ENERGY_MODEL */ 1029 1030 static void hybrid_set_cpu_capacity(struct cpudata *cpu) 1031 { 1032 arch_set_cpu_capacity(cpu->cpu, cpu->capacity_perf, 1033 hybrid_max_perf_cpu->capacity_perf, 1034 cpu->capacity_perf, 1035 cpu->pstate.max_pstate_physical); 1036 hybrid_update_perf_domain(cpu); 1037 1038 topology_set_cpu_scale(cpu->cpu, arch_scale_cpu_capacity(cpu->cpu)); 1039 1040 pr_debug("CPU%d: perf = %u, max. perf = %u, base perf = %d\n", cpu->cpu, 1041 cpu->capacity_perf, hybrid_max_perf_cpu->capacity_perf, 1042 cpu->pstate.max_pstate_physical); 1043 } 1044 1045 static void hybrid_clear_cpu_capacity(unsigned int cpunum) 1046 { 1047 arch_set_cpu_capacity(cpunum, 1, 1, 1, 1); 1048 } 1049 1050 static void hybrid_get_capacity_perf(struct cpudata *cpu) 1051 { 1052 if (READ_ONCE(global.no_turbo)) { 1053 cpu->capacity_perf = cpu->pstate.max_pstate_physical; 1054 return; 1055 } 1056 1057 cpu->capacity_perf = HWP_HIGHEST_PERF(READ_ONCE(cpu->hwp_cap_cached)); 1058 } 1059 1060 static void hybrid_set_capacity_of_cpus(void) 1061 { 1062 int cpunum; 1063 1064 for_each_online_cpu(cpunum) { 1065 struct cpudata *cpu = all_cpu_data[cpunum]; 1066 1067 if (cpu) 1068 hybrid_set_cpu_capacity(cpu); 1069 } 1070 } 1071 1072 static void hybrid_update_cpu_capacity_scaling(void) 1073 { 1074 struct cpudata *max_perf_cpu = NULL; 1075 unsigned int max_cap_perf = 0; 1076 int cpunum; 1077 1078 for_each_online_cpu(cpunum) { 1079 struct cpudata *cpu = all_cpu_data[cpunum]; 1080 1081 if (!cpu) 1082 continue; 1083 1084 /* 1085 * During initialization, CPU performance at full capacity needs 1086 * to be determined. 1087 */ 1088 if (!hybrid_max_perf_cpu) 1089 hybrid_get_capacity_perf(cpu); 1090 1091 /* 1092 * If hybrid_max_perf_cpu is not NULL at this point, it is 1093 * being replaced, so don't take it into account when looking 1094 * for the new one. 1095 */ 1096 if (cpu == hybrid_max_perf_cpu) 1097 continue; 1098 1099 if (cpu->capacity_perf > max_cap_perf) { 1100 max_cap_perf = cpu->capacity_perf; 1101 max_perf_cpu = cpu; 1102 } 1103 } 1104 1105 if (max_perf_cpu) { 1106 hybrid_max_perf_cpu = max_perf_cpu; 1107 hybrid_set_capacity_of_cpus(); 1108 } else { 1109 pr_info("Found no CPUs with nonzero maximum performance\n"); 1110 /* Revert to the flat CPU capacity structure. */ 1111 for_each_online_cpu(cpunum) 1112 hybrid_clear_cpu_capacity(cpunum); 1113 } 1114 } 1115 1116 static void __hybrid_refresh_cpu_capacity_scaling(void) 1117 { 1118 hybrid_max_perf_cpu = NULL; 1119 hybrid_update_cpu_capacity_scaling(); 1120 } 1121 1122 static void hybrid_refresh_cpu_capacity_scaling(void) 1123 { 1124 guard(mutex)(&hybrid_capacity_lock); 1125 1126 __hybrid_refresh_cpu_capacity_scaling(); 1127 /* 1128 * Perf domains are not registered before setting hybrid_max_perf_cpu, 1129 * so register them all after setting up CPU capacity scaling. 1130 */ 1131 hybrid_register_all_perf_domains(); 1132 } 1133 1134 static void hybrid_init_cpu_capacity_scaling(bool refresh) 1135 { 1136 /* Bail out if enabling capacity-aware scheduling is prohibited. */ 1137 if (no_cas) 1138 return; 1139 1140 /* 1141 * If hybrid_max_perf_cpu is set at this point, the hybrid CPU capacity 1142 * scaling has been enabled already and the driver is just changing the 1143 * operation mode. 1144 */ 1145 if (refresh) { 1146 hybrid_refresh_cpu_capacity_scaling(); 1147 return; 1148 } 1149 1150 /* 1151 * On hybrid systems, use asym capacity instead of ITMT, but because 1152 * the capacity of SMT threads is not deterministic even approximately, 1153 * do not do that when SMT is in use. 1154 */ 1155 if (hwp_is_hybrid && !sched_smt_active() && arch_enable_hybrid_capacity_scale()) { 1156 hybrid_refresh_cpu_capacity_scaling(); 1157 /* 1158 * Disabling ITMT causes sched domains to be rebuilt to disable asym 1159 * packing and enable asym capacity and EAS. 1160 */ 1161 sched_clear_itmt_support(); 1162 } 1163 } 1164 1165 static bool hybrid_clear_max_perf_cpu(void) 1166 { 1167 bool ret; 1168 1169 guard(mutex)(&hybrid_capacity_lock); 1170 1171 ret = !!hybrid_max_perf_cpu; 1172 hybrid_max_perf_cpu = NULL; 1173 1174 return ret; 1175 } 1176 1177 static void __intel_pstate_get_hwp_cap(struct cpudata *cpu) 1178 { 1179 u64 cap; 1180 1181 rdmsrq_on_cpu(cpu->cpu, MSR_HWP_CAPABILITIES, &cap); 1182 WRITE_ONCE(cpu->hwp_cap_cached, cap); 1183 cpu->pstate.max_pstate = HWP_GUARANTEED_PERF(cap); 1184 cpu->pstate.turbo_pstate = HWP_HIGHEST_PERF(cap); 1185 } 1186 1187 static void intel_pstate_get_hwp_cap(struct cpudata *cpu) 1188 { 1189 int scaling = cpu->pstate.scaling; 1190 1191 __intel_pstate_get_hwp_cap(cpu); 1192 1193 cpu->pstate.max_freq = cpu->pstate.max_pstate * scaling; 1194 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * scaling; 1195 if (scaling != cpu->pstate.perf_ctl_scaling) { 1196 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling; 1197 1198 cpu->pstate.max_freq = rounddown(cpu->pstate.max_freq, 1199 perf_ctl_scaling); 1200 cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_freq, 1201 perf_ctl_scaling); 1202 } 1203 } 1204 1205 static void hybrid_update_capacity(struct cpudata *cpu) 1206 { 1207 unsigned int max_cap_perf; 1208 1209 mutex_lock(&hybrid_capacity_lock); 1210 1211 if (!hybrid_max_perf_cpu) 1212 goto unlock; 1213 1214 /* 1215 * The maximum performance of the CPU may have changed, but assume 1216 * that the performance of the other CPUs has not changed. 1217 */ 1218 max_cap_perf = hybrid_max_perf_cpu->capacity_perf; 1219 1220 intel_pstate_get_hwp_cap(cpu); 1221 1222 hybrid_get_capacity_perf(cpu); 1223 /* Should hybrid_max_perf_cpu be replaced by this CPU? */ 1224 if (cpu->capacity_perf > max_cap_perf) { 1225 hybrid_max_perf_cpu = cpu; 1226 hybrid_set_capacity_of_cpus(); 1227 goto unlock; 1228 } 1229 1230 /* If this CPU is hybrid_max_perf_cpu, should it be replaced? */ 1231 if (cpu == hybrid_max_perf_cpu && cpu->capacity_perf < max_cap_perf) { 1232 hybrid_update_cpu_capacity_scaling(); 1233 goto unlock; 1234 } 1235 1236 hybrid_set_cpu_capacity(cpu); 1237 /* 1238 * If the CPU was offline to start with and it is going online for the 1239 * first time, a perf domain needs to be registered for it if hybrid 1240 * capacity scaling has been enabled already. In that case, sched 1241 * domains need to be rebuilt to take the new perf domain into account. 1242 */ 1243 if (hybrid_register_perf_domain(cpu->cpu)) 1244 em_rebuild_sched_domains(); 1245 1246 unlock: 1247 mutex_unlock(&hybrid_capacity_lock); 1248 } 1249 1250 static void intel_pstate_hwp_set(unsigned int cpu) 1251 { 1252 struct cpudata *cpu_data = all_cpu_data[cpu]; 1253 int max, min; 1254 u64 value; 1255 s16 epp; 1256 1257 max = cpu_data->max_perf_ratio; 1258 min = cpu_data->min_perf_ratio; 1259 1260 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) 1261 min = max; 1262 1263 rdmsrq_on_cpu(cpu, MSR_HWP_REQUEST, &value); 1264 1265 value &= ~HWP_MIN_PERF(~0L); 1266 value |= HWP_MIN_PERF(min); 1267 1268 value &= ~HWP_MAX_PERF(~0L); 1269 value |= HWP_MAX_PERF(max); 1270 1271 if (cpu_data->epp_policy == cpu_data->policy) 1272 goto skip_epp; 1273 1274 cpu_data->epp_policy = cpu_data->policy; 1275 1276 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) { 1277 epp = intel_pstate_get_epp(cpu_data, value); 1278 cpu_data->epp_powersave = epp; 1279 /* If EPP read was failed, then don't try to write */ 1280 if (epp < 0) 1281 goto skip_epp; 1282 1283 epp = 0; 1284 } else { 1285 /* skip setting EPP, when saved value is invalid */ 1286 if (cpu_data->epp_powersave < 0) 1287 goto skip_epp; 1288 1289 /* 1290 * No need to restore EPP when it is not zero. This 1291 * means: 1292 * - Policy is not changed 1293 * - user has manually changed 1294 * - Error reading EPB 1295 */ 1296 epp = intel_pstate_get_epp(cpu_data, value); 1297 if (epp) 1298 goto skip_epp; 1299 1300 epp = cpu_data->epp_powersave; 1301 } 1302 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 1303 value &= ~GENMASK_ULL(31, 24); 1304 value |= (u64)epp << 24; 1305 } 1306 1307 skip_epp: 1308 WRITE_ONCE(cpu_data->hwp_req_cached, value); 1309 wrmsrq_on_cpu(cpu, MSR_HWP_REQUEST, value); 1310 } 1311 1312 static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata); 1313 1314 static void intel_pstate_hwp_offline(struct cpudata *cpu) 1315 { 1316 u64 value = READ_ONCE(cpu->hwp_req_cached); 1317 int min_perf; 1318 1319 intel_pstate_disable_hwp_interrupt(cpu); 1320 1321 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 1322 /* 1323 * In case the EPP has been set to "performance" by the 1324 * active mode "performance" scaling algorithm, replace that 1325 * temporary value with the cached EPP one. 1326 */ 1327 value &= ~GENMASK_ULL(31, 24); 1328 value |= HWP_ENERGY_PERF_PREFERENCE(cpu->epp_cached); 1329 /* 1330 * However, make sure that EPP will be set to "performance" when 1331 * the CPU is brought back online again and the "performance" 1332 * scaling algorithm is still in effect. 1333 */ 1334 cpu->epp_policy = CPUFREQ_POLICY_UNKNOWN; 1335 } 1336 1337 /* 1338 * Clear the desired perf field in the cached HWP request value to 1339 * prevent nonzero desired values from being leaked into the active 1340 * mode. 1341 */ 1342 value &= ~HWP_DESIRED_PERF(~0L); 1343 WRITE_ONCE(cpu->hwp_req_cached, value); 1344 1345 value &= ~GENMASK_ULL(31, 0); 1346 min_perf = HWP_LOWEST_PERF(READ_ONCE(cpu->hwp_cap_cached)); 1347 1348 /* Set hwp_max = hwp_min */ 1349 value |= HWP_MAX_PERF(min_perf); 1350 value |= HWP_MIN_PERF(min_perf); 1351 1352 /* Set EPP to min */ 1353 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) 1354 value |= HWP_ENERGY_PERF_PREFERENCE(HWP_EPP_POWERSAVE); 1355 1356 wrmsrq_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 1357 1358 mutex_lock(&hybrid_capacity_lock); 1359 1360 if (!hybrid_max_perf_cpu) { 1361 mutex_unlock(&hybrid_capacity_lock); 1362 1363 return; 1364 } 1365 1366 if (hybrid_max_perf_cpu == cpu) 1367 hybrid_update_cpu_capacity_scaling(); 1368 1369 mutex_unlock(&hybrid_capacity_lock); 1370 1371 /* Reset the capacity of the CPU going offline to the initial value. */ 1372 hybrid_clear_cpu_capacity(cpu->cpu); 1373 } 1374 1375 #define POWER_CTL_EE_ENABLE 1 1376 #define POWER_CTL_EE_DISABLE 2 1377 1378 /* Enable bit for Dynamic Efficiency Control (DEC) */ 1379 #define POWER_CTL_DEC_ENABLE 27 1380 1381 static int power_ctl_ee_state; 1382 1383 static void set_power_ctl_ee_state(bool input) 1384 { 1385 u64 power_ctl; 1386 1387 mutex_lock(&intel_pstate_driver_lock); 1388 rdmsrq(MSR_IA32_POWER_CTL, power_ctl); 1389 if (input) { 1390 power_ctl &= ~BIT(MSR_IA32_POWER_CTL_BIT_EE); 1391 power_ctl_ee_state = POWER_CTL_EE_ENABLE; 1392 } else { 1393 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE); 1394 power_ctl_ee_state = POWER_CTL_EE_DISABLE; 1395 } 1396 wrmsrq(MSR_IA32_POWER_CTL, power_ctl); 1397 mutex_unlock(&intel_pstate_driver_lock); 1398 } 1399 1400 static void intel_pstate_hwp_enable(struct cpudata *cpudata); 1401 1402 static void intel_pstate_hwp_reenable(struct cpudata *cpu) 1403 { 1404 intel_pstate_hwp_enable(cpu); 1405 wrmsrq_on_cpu(cpu->cpu, MSR_HWP_REQUEST, READ_ONCE(cpu->hwp_req_cached)); 1406 } 1407 1408 static int intel_pstate_suspend(struct cpufreq_policy *policy) 1409 { 1410 struct cpudata *cpu = all_cpu_data[policy->cpu]; 1411 1412 pr_debug("CPU %d suspending\n", cpu->cpu); 1413 1414 cpu->suspended = true; 1415 1416 /* disable HWP interrupt and cancel any pending work */ 1417 intel_pstate_disable_hwp_interrupt(cpu); 1418 1419 return 0; 1420 } 1421 1422 static int intel_pstate_resume(struct cpufreq_policy *policy) 1423 { 1424 struct cpudata *cpu = all_cpu_data[policy->cpu]; 1425 1426 pr_debug("CPU %d resuming\n", cpu->cpu); 1427 1428 /* Only restore if the system default is changed */ 1429 if (power_ctl_ee_state == POWER_CTL_EE_ENABLE) 1430 set_power_ctl_ee_state(true); 1431 else if (power_ctl_ee_state == POWER_CTL_EE_DISABLE) 1432 set_power_ctl_ee_state(false); 1433 1434 if (cpu->suspended && hwp_active) { 1435 mutex_lock(&intel_pstate_limits_lock); 1436 1437 /* Re-enable HWP, because "online" has not done that. */ 1438 intel_pstate_hwp_reenable(cpu); 1439 1440 mutex_unlock(&intel_pstate_limits_lock); 1441 } 1442 1443 cpu->suspended = false; 1444 1445 return 0; 1446 } 1447 1448 static void intel_pstate_update_policies(void) 1449 { 1450 int cpu; 1451 1452 for_each_possible_cpu(cpu) 1453 cpufreq_update_policy(cpu); 1454 } 1455 1456 static void __intel_pstate_update_max_freq(struct cpufreq_policy *policy, 1457 struct cpudata *cpudata) 1458 { 1459 guard(cpufreq_policy_write)(policy); 1460 1461 if (hwp_active) 1462 intel_pstate_get_hwp_cap(cpudata); 1463 1464 policy->cpuinfo.max_freq = READ_ONCE(global.no_turbo) ? 1465 cpudata->pstate.max_freq : cpudata->pstate.turbo_freq; 1466 1467 refresh_frequency_limits(policy); 1468 } 1469 1470 static bool intel_pstate_update_max_freq(struct cpudata *cpudata) 1471 { 1472 struct cpufreq_policy *policy __free(put_cpufreq_policy) = cpufreq_cpu_get(cpudata->cpu); 1473 if (!policy) 1474 return false; 1475 1476 __intel_pstate_update_max_freq(policy, cpudata); 1477 1478 return true; 1479 } 1480 1481 static void intel_pstate_update_limits(struct cpufreq_policy *policy) 1482 { 1483 struct cpudata *cpudata = all_cpu_data[policy->cpu]; 1484 1485 __intel_pstate_update_max_freq(policy, cpudata); 1486 1487 hybrid_update_capacity(cpudata); 1488 } 1489 1490 static void intel_pstate_update_limits_for_all(void) 1491 { 1492 int cpu; 1493 1494 for_each_possible_cpu(cpu) 1495 intel_pstate_update_max_freq(all_cpu_data[cpu]); 1496 1497 mutex_lock(&hybrid_capacity_lock); 1498 1499 if (hybrid_max_perf_cpu) 1500 __hybrid_refresh_cpu_capacity_scaling(); 1501 1502 mutex_unlock(&hybrid_capacity_lock); 1503 } 1504 1505 /************************** sysfs begin ************************/ 1506 #define show_one(file_name, object) \ 1507 static ssize_t show_##file_name \ 1508 (struct kobject *kobj, struct kobj_attribute *attr, char *buf) \ 1509 { \ 1510 return sprintf(buf, "%u\n", global.object); \ 1511 } 1512 1513 static ssize_t intel_pstate_show_status(char *buf); 1514 static int intel_pstate_update_status(const char *buf, size_t size); 1515 1516 static ssize_t show_status(struct kobject *kobj, 1517 struct kobj_attribute *attr, char *buf) 1518 { 1519 ssize_t ret; 1520 1521 mutex_lock(&intel_pstate_driver_lock); 1522 ret = intel_pstate_show_status(buf); 1523 mutex_unlock(&intel_pstate_driver_lock); 1524 1525 return ret; 1526 } 1527 1528 static ssize_t store_status(struct kobject *a, struct kobj_attribute *b, 1529 const char *buf, size_t count) 1530 { 1531 char *p = memchr(buf, '\n', count); 1532 int ret; 1533 1534 mutex_lock(&intel_pstate_driver_lock); 1535 ret = intel_pstate_update_status(buf, p ? p - buf : count); 1536 mutex_unlock(&intel_pstate_driver_lock); 1537 1538 return ret < 0 ? ret : count; 1539 } 1540 1541 static ssize_t show_turbo_pct(struct kobject *kobj, 1542 struct kobj_attribute *attr, char *buf) 1543 { 1544 struct cpudata *cpu; 1545 int total, no_turbo, turbo_pct; 1546 uint32_t turbo_fp; 1547 1548 mutex_lock(&intel_pstate_driver_lock); 1549 1550 if (!intel_pstate_driver) { 1551 mutex_unlock(&intel_pstate_driver_lock); 1552 return -EAGAIN; 1553 } 1554 1555 cpu = all_cpu_data[0]; 1556 1557 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; 1558 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1; 1559 turbo_fp = div_fp(no_turbo, total); 1560 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100))); 1561 1562 mutex_unlock(&intel_pstate_driver_lock); 1563 1564 return sprintf(buf, "%u\n", turbo_pct); 1565 } 1566 1567 static ssize_t show_num_pstates(struct kobject *kobj, 1568 struct kobj_attribute *attr, char *buf) 1569 { 1570 struct cpudata *cpu; 1571 int total; 1572 1573 mutex_lock(&intel_pstate_driver_lock); 1574 1575 if (!intel_pstate_driver) { 1576 mutex_unlock(&intel_pstate_driver_lock); 1577 return -EAGAIN; 1578 } 1579 1580 cpu = all_cpu_data[0]; 1581 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; 1582 1583 mutex_unlock(&intel_pstate_driver_lock); 1584 1585 return sprintf(buf, "%u\n", total); 1586 } 1587 1588 static ssize_t show_no_turbo(struct kobject *kobj, 1589 struct kobj_attribute *attr, char *buf) 1590 { 1591 ssize_t ret; 1592 1593 mutex_lock(&intel_pstate_driver_lock); 1594 1595 if (!intel_pstate_driver) { 1596 mutex_unlock(&intel_pstate_driver_lock); 1597 return -EAGAIN; 1598 } 1599 1600 ret = sprintf(buf, "%u\n", global.no_turbo); 1601 1602 mutex_unlock(&intel_pstate_driver_lock); 1603 1604 return ret; 1605 } 1606 1607 static ssize_t store_no_turbo(struct kobject *a, struct kobj_attribute *b, 1608 const char *buf, size_t count) 1609 { 1610 unsigned int input; 1611 bool no_turbo; 1612 1613 if (sscanf(buf, "%u", &input) != 1) 1614 return -EINVAL; 1615 1616 mutex_lock(&intel_pstate_driver_lock); 1617 1618 if (!intel_pstate_driver) { 1619 count = -EAGAIN; 1620 goto unlock_driver; 1621 } 1622 1623 no_turbo = !!clamp_t(int, input, 0, 1); 1624 1625 WRITE_ONCE(global.turbo_disabled, turbo_is_disabled()); 1626 if (global.turbo_disabled && !no_turbo) { 1627 pr_notice("Turbo disabled by BIOS or unavailable on processor\n"); 1628 count = -EPERM; 1629 if (global.no_turbo) 1630 goto unlock_driver; 1631 else 1632 no_turbo = 1; 1633 } 1634 1635 if (no_turbo == global.no_turbo) { 1636 goto unlock_driver; 1637 } 1638 1639 WRITE_ONCE(global.no_turbo, no_turbo); 1640 1641 mutex_lock(&intel_pstate_limits_lock); 1642 1643 if (no_turbo) { 1644 struct cpudata *cpu = all_cpu_data[0]; 1645 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate; 1646 1647 /* Squash the global minimum into the permitted range. */ 1648 if (global.min_perf_pct > pct) 1649 global.min_perf_pct = pct; 1650 } 1651 1652 mutex_unlock(&intel_pstate_limits_lock); 1653 1654 intel_pstate_update_limits_for_all(); 1655 arch_set_max_freq_ratio(no_turbo); 1656 1657 unlock_driver: 1658 mutex_unlock(&intel_pstate_driver_lock); 1659 1660 return count; 1661 } 1662 1663 static void update_cpu_qos_request(int cpu, enum freq_qos_req_type type) 1664 { 1665 struct cpudata *cpudata = all_cpu_data[cpu]; 1666 unsigned int freq = cpudata->pstate.turbo_freq; 1667 struct freq_qos_request *req; 1668 1669 struct cpufreq_policy *policy __free(put_cpufreq_policy) = cpufreq_cpu_get(cpu); 1670 if (!policy) 1671 return; 1672 1673 req = policy->driver_data; 1674 if (!req) 1675 return; 1676 1677 if (hwp_active) 1678 intel_pstate_get_hwp_cap(cpudata); 1679 1680 if (type == FREQ_QOS_MIN) { 1681 freq = DIV_ROUND_UP(freq * global.min_perf_pct, 100); 1682 } else { 1683 req++; 1684 freq = (freq * global.max_perf_pct) / 100; 1685 } 1686 1687 if (freq_qos_update_request(req, freq) < 0) 1688 pr_warn("Failed to update freq constraint: CPU%d\n", cpu); 1689 } 1690 1691 static void update_qos_requests(enum freq_qos_req_type type) 1692 { 1693 int i; 1694 1695 for_each_possible_cpu(i) 1696 update_cpu_qos_request(i, type); 1697 } 1698 1699 static ssize_t store_max_perf_pct(struct kobject *a, struct kobj_attribute *b, 1700 const char *buf, size_t count) 1701 { 1702 unsigned int input; 1703 int ret; 1704 1705 ret = sscanf(buf, "%u", &input); 1706 if (ret != 1) 1707 return -EINVAL; 1708 1709 mutex_lock(&intel_pstate_driver_lock); 1710 1711 if (!intel_pstate_driver) { 1712 mutex_unlock(&intel_pstate_driver_lock); 1713 return -EAGAIN; 1714 } 1715 1716 mutex_lock(&intel_pstate_limits_lock); 1717 1718 global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100); 1719 1720 mutex_unlock(&intel_pstate_limits_lock); 1721 1722 if (intel_pstate_driver == &intel_pstate) 1723 intel_pstate_update_policies(); 1724 else 1725 update_qos_requests(FREQ_QOS_MAX); 1726 1727 mutex_unlock(&intel_pstate_driver_lock); 1728 1729 return count; 1730 } 1731 1732 static ssize_t store_min_perf_pct(struct kobject *a, struct kobj_attribute *b, 1733 const char *buf, size_t count) 1734 { 1735 unsigned int input; 1736 int ret; 1737 1738 ret = sscanf(buf, "%u", &input); 1739 if (ret != 1) 1740 return -EINVAL; 1741 1742 mutex_lock(&intel_pstate_driver_lock); 1743 1744 if (!intel_pstate_driver) { 1745 mutex_unlock(&intel_pstate_driver_lock); 1746 return -EAGAIN; 1747 } 1748 1749 mutex_lock(&intel_pstate_limits_lock); 1750 1751 global.min_perf_pct = clamp_t(int, input, 1752 min_perf_pct_min(), global.max_perf_pct); 1753 1754 mutex_unlock(&intel_pstate_limits_lock); 1755 1756 if (intel_pstate_driver == &intel_pstate) 1757 intel_pstate_update_policies(); 1758 else 1759 update_qos_requests(FREQ_QOS_MIN); 1760 1761 mutex_unlock(&intel_pstate_driver_lock); 1762 1763 return count; 1764 } 1765 1766 static ssize_t show_hwp_dynamic_boost(struct kobject *kobj, 1767 struct kobj_attribute *attr, char *buf) 1768 { 1769 return sprintf(buf, "%u\n", hwp_boost); 1770 } 1771 1772 static ssize_t store_hwp_dynamic_boost(struct kobject *a, 1773 struct kobj_attribute *b, 1774 const char *buf, size_t count) 1775 { 1776 unsigned int input; 1777 int ret; 1778 1779 ret = kstrtouint(buf, 10, &input); 1780 if (ret) 1781 return ret; 1782 1783 mutex_lock(&intel_pstate_driver_lock); 1784 hwp_boost = !!input; 1785 intel_pstate_update_policies(); 1786 mutex_unlock(&intel_pstate_driver_lock); 1787 1788 return count; 1789 } 1790 1791 static ssize_t show_energy_efficiency(struct kobject *kobj, struct kobj_attribute *attr, 1792 char *buf) 1793 { 1794 u64 power_ctl; 1795 int enable; 1796 1797 rdmsrq(MSR_IA32_POWER_CTL, power_ctl); 1798 enable = !!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE)); 1799 return sprintf(buf, "%d\n", !enable); 1800 } 1801 1802 static ssize_t store_energy_efficiency(struct kobject *a, struct kobj_attribute *b, 1803 const char *buf, size_t count) 1804 { 1805 bool input; 1806 int ret; 1807 1808 ret = kstrtobool(buf, &input); 1809 if (ret) 1810 return ret; 1811 1812 set_power_ctl_ee_state(input); 1813 1814 return count; 1815 } 1816 1817 show_one(max_perf_pct, max_perf_pct); 1818 show_one(min_perf_pct, min_perf_pct); 1819 1820 define_one_global_rw(status); 1821 define_one_global_rw(no_turbo); 1822 define_one_global_rw(max_perf_pct); 1823 define_one_global_rw(min_perf_pct); 1824 define_one_global_ro(turbo_pct); 1825 define_one_global_ro(num_pstates); 1826 define_one_global_rw(hwp_dynamic_boost); 1827 define_one_global_rw(energy_efficiency); 1828 1829 static struct attribute *intel_pstate_attributes[] = { 1830 &status.attr, 1831 &no_turbo.attr, 1832 NULL 1833 }; 1834 1835 static const struct attribute_group intel_pstate_attr_group = { 1836 .attrs = intel_pstate_attributes, 1837 }; 1838 1839 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[]; 1840 1841 static struct kobject *intel_pstate_kobject; 1842 1843 static void __init intel_pstate_sysfs_expose_params(void) 1844 { 1845 struct device *dev_root = bus_get_dev_root(&cpu_subsys); 1846 int rc; 1847 1848 if (dev_root) { 1849 intel_pstate_kobject = kobject_create_and_add("intel_pstate", &dev_root->kobj); 1850 put_device(dev_root); 1851 } 1852 if (WARN_ON(!intel_pstate_kobject)) 1853 return; 1854 1855 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group); 1856 if (WARN_ON(rc)) 1857 return; 1858 1859 if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) { 1860 rc = sysfs_create_file(intel_pstate_kobject, &turbo_pct.attr); 1861 WARN_ON(rc); 1862 1863 rc = sysfs_create_file(intel_pstate_kobject, &num_pstates.attr); 1864 WARN_ON(rc); 1865 } 1866 1867 /* 1868 * If per cpu limits are enforced there are no global limits, so 1869 * return without creating max/min_perf_pct attributes 1870 */ 1871 if (per_cpu_limits) 1872 return; 1873 1874 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr); 1875 WARN_ON(rc); 1876 1877 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr); 1878 WARN_ON(rc); 1879 1880 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids)) { 1881 rc = sysfs_create_file(intel_pstate_kobject, &energy_efficiency.attr); 1882 WARN_ON(rc); 1883 } 1884 } 1885 1886 static void __init intel_pstate_sysfs_remove(void) 1887 { 1888 if (!intel_pstate_kobject) 1889 return; 1890 1891 sysfs_remove_group(intel_pstate_kobject, &intel_pstate_attr_group); 1892 1893 if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) { 1894 sysfs_remove_file(intel_pstate_kobject, &num_pstates.attr); 1895 sysfs_remove_file(intel_pstate_kobject, &turbo_pct.attr); 1896 } 1897 1898 if (!per_cpu_limits) { 1899 sysfs_remove_file(intel_pstate_kobject, &max_perf_pct.attr); 1900 sysfs_remove_file(intel_pstate_kobject, &min_perf_pct.attr); 1901 1902 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids)) 1903 sysfs_remove_file(intel_pstate_kobject, &energy_efficiency.attr); 1904 } 1905 1906 kobject_put(intel_pstate_kobject); 1907 } 1908 1909 static void intel_pstate_sysfs_expose_hwp_dynamic_boost(void) 1910 { 1911 int rc; 1912 1913 if (!hwp_active) 1914 return; 1915 1916 rc = sysfs_create_file(intel_pstate_kobject, &hwp_dynamic_boost.attr); 1917 WARN_ON_ONCE(rc); 1918 } 1919 1920 static void intel_pstate_sysfs_hide_hwp_dynamic_boost(void) 1921 { 1922 if (!hwp_active) 1923 return; 1924 1925 sysfs_remove_file(intel_pstate_kobject, &hwp_dynamic_boost.attr); 1926 } 1927 1928 /************************** sysfs end ************************/ 1929 1930 static void intel_pstate_notify_work(struct work_struct *work) 1931 { 1932 struct cpudata *cpudata = 1933 container_of(to_delayed_work(work), struct cpudata, hwp_notify_work); 1934 1935 if (intel_pstate_update_max_freq(cpudata)) { 1936 /* 1937 * The driver will not be unregistered while this function is 1938 * running, so update the capacity without acquiring the driver 1939 * lock. 1940 */ 1941 hybrid_update_capacity(cpudata); 1942 } 1943 1944 wrmsrq_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0); 1945 } 1946 1947 static DEFINE_RAW_SPINLOCK(hwp_notify_lock); 1948 static cpumask_t hwp_intr_enable_mask; 1949 1950 #define HWP_GUARANTEED_PERF_CHANGE_STATUS BIT(0) 1951 #define HWP_HIGHEST_PERF_CHANGE_STATUS BIT(3) 1952 1953 void notify_hwp_interrupt(void) 1954 { 1955 unsigned int this_cpu = smp_processor_id(); 1956 u64 value, status_mask; 1957 unsigned long flags; 1958 1959 if (!hwp_active || !cpu_feature_enabled(X86_FEATURE_HWP_NOTIFY)) 1960 return; 1961 1962 status_mask = HWP_GUARANTEED_PERF_CHANGE_STATUS; 1963 if (cpu_feature_enabled(X86_FEATURE_HWP_HIGHEST_PERF_CHANGE)) 1964 status_mask |= HWP_HIGHEST_PERF_CHANGE_STATUS; 1965 1966 rdmsrq_safe(MSR_HWP_STATUS, &value); 1967 if (!(value & status_mask)) 1968 return; 1969 1970 raw_spin_lock_irqsave(&hwp_notify_lock, flags); 1971 1972 if (!cpumask_test_cpu(this_cpu, &hwp_intr_enable_mask)) 1973 goto ack_intr; 1974 1975 schedule_delayed_work(&all_cpu_data[this_cpu]->hwp_notify_work, 1976 msecs_to_jiffies(10)); 1977 1978 raw_spin_unlock_irqrestore(&hwp_notify_lock, flags); 1979 1980 return; 1981 1982 ack_intr: 1983 wrmsrq_safe(MSR_HWP_STATUS, 0); 1984 raw_spin_unlock_irqrestore(&hwp_notify_lock, flags); 1985 } 1986 1987 static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata) 1988 { 1989 bool cancel_work; 1990 1991 if (!cpu_feature_enabled(X86_FEATURE_HWP_NOTIFY)) 1992 return; 1993 1994 /* wrmsrq_on_cpu has to be outside spinlock as this can result in IPC */ 1995 wrmsrq_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00); 1996 1997 raw_spin_lock_irq(&hwp_notify_lock); 1998 cancel_work = cpumask_test_and_clear_cpu(cpudata->cpu, &hwp_intr_enable_mask); 1999 raw_spin_unlock_irq(&hwp_notify_lock); 2000 2001 if (cancel_work) 2002 cancel_delayed_work_sync(&cpudata->hwp_notify_work); 2003 } 2004 2005 #define HWP_GUARANTEED_PERF_CHANGE_REQ BIT(0) 2006 #define HWP_HIGHEST_PERF_CHANGE_REQ BIT(2) 2007 2008 static void intel_pstate_enable_hwp_interrupt(struct cpudata *cpudata) 2009 { 2010 /* Enable HWP notification interrupt for performance change */ 2011 if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) { 2012 u64 interrupt_mask = HWP_GUARANTEED_PERF_CHANGE_REQ; 2013 2014 raw_spin_lock_irq(&hwp_notify_lock); 2015 INIT_DELAYED_WORK(&cpudata->hwp_notify_work, intel_pstate_notify_work); 2016 cpumask_set_cpu(cpudata->cpu, &hwp_intr_enable_mask); 2017 raw_spin_unlock_irq(&hwp_notify_lock); 2018 2019 if (cpu_feature_enabled(X86_FEATURE_HWP_HIGHEST_PERF_CHANGE)) 2020 interrupt_mask |= HWP_HIGHEST_PERF_CHANGE_REQ; 2021 2022 /* wrmsrq_on_cpu has to be outside spinlock as this can result in IPC */ 2023 wrmsrq_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, interrupt_mask); 2024 wrmsrq_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0); 2025 } 2026 } 2027 2028 static void intel_pstate_update_epp_defaults(struct cpudata *cpudata) 2029 { 2030 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0); 2031 2032 /* 2033 * If the EPP is set by firmware, which means that firmware enabled HWP 2034 * - Is equal or less than 0x80 (default balance_perf EPP) 2035 * - But less performance oriented than performance EPP 2036 * then use this as new balance_perf EPP. 2037 */ 2038 if (hwp_forced && cpudata->epp_default <= HWP_EPP_BALANCE_PERFORMANCE && 2039 cpudata->epp_default > HWP_EPP_PERFORMANCE) { 2040 epp_values[EPP_INDEX_BALANCE_PERFORMANCE] = cpudata->epp_default; 2041 return; 2042 } 2043 2044 /* 2045 * If this CPU gen doesn't call for change in balance_perf 2046 * EPP return. 2047 */ 2048 if (epp_values[EPP_INDEX_BALANCE_PERFORMANCE] == HWP_EPP_BALANCE_PERFORMANCE) 2049 return; 2050 2051 /* 2052 * Use hard coded value per gen to update the balance_perf 2053 * and default EPP. 2054 */ 2055 cpudata->epp_default = epp_values[EPP_INDEX_BALANCE_PERFORMANCE]; 2056 intel_pstate_set_epp(cpudata, cpudata->epp_default); 2057 } 2058 2059 static void intel_pstate_hwp_enable(struct cpudata *cpudata) 2060 { 2061 /* First disable HWP notification interrupt till we activate again */ 2062 if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) 2063 wrmsrq_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00); 2064 2065 wrmsrq_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1); 2066 2067 intel_pstate_enable_hwp_interrupt(cpudata); 2068 2069 if (cpudata->epp_default >= 0) 2070 return; 2071 2072 intel_pstate_update_epp_defaults(cpudata); 2073 } 2074 2075 static int atom_get_min_pstate(int not_used) 2076 { 2077 u64 value; 2078 2079 rdmsrq(MSR_ATOM_CORE_RATIOS, value); 2080 return (value >> 8) & 0x7F; 2081 } 2082 2083 static int atom_get_max_pstate(int not_used) 2084 { 2085 u64 value; 2086 2087 rdmsrq(MSR_ATOM_CORE_RATIOS, value); 2088 return (value >> 16) & 0x7F; 2089 } 2090 2091 static int atom_get_turbo_pstate(int not_used) 2092 { 2093 u64 value; 2094 2095 rdmsrq(MSR_ATOM_CORE_TURBO_RATIOS, value); 2096 return value & 0x7F; 2097 } 2098 2099 static u64 atom_get_val(struct cpudata *cpudata, int pstate) 2100 { 2101 u64 val; 2102 int32_t vid_fp; 2103 u32 vid; 2104 2105 val = (u64)pstate << 8; 2106 if (READ_ONCE(global.no_turbo) && !READ_ONCE(global.turbo_disabled) && 2107 cpu_feature_enabled(X86_FEATURE_IDA)) 2108 val |= (u64)1 << 32; 2109 2110 vid_fp = cpudata->vid.min + mul_fp( 2111 int_tofp(pstate - cpudata->pstate.min_pstate), 2112 cpudata->vid.ratio); 2113 2114 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max); 2115 vid = ceiling_fp(vid_fp); 2116 2117 if (pstate > cpudata->pstate.max_pstate) 2118 vid = cpudata->vid.turbo; 2119 2120 return val | vid; 2121 } 2122 2123 static int silvermont_get_scaling(void) 2124 { 2125 u64 value; 2126 int i; 2127 /* Defined in Table 35-6 from SDM (Sept 2015) */ 2128 static int silvermont_freq_table[] = { 2129 83300, 100000, 133300, 116700, 80000}; 2130 2131 rdmsrq(MSR_FSB_FREQ, value); 2132 i = value & 0x7; 2133 WARN_ON(i > 4); 2134 2135 return silvermont_freq_table[i]; 2136 } 2137 2138 static int airmont_get_scaling(void) 2139 { 2140 u64 value; 2141 int i; 2142 /* Defined in Table 35-10 from SDM (Sept 2015) */ 2143 static int airmont_freq_table[] = { 2144 83300, 100000, 133300, 116700, 80000, 2145 93300, 90000, 88900, 87500}; 2146 2147 rdmsrq(MSR_FSB_FREQ, value); 2148 i = value & 0xF; 2149 WARN_ON(i > 8); 2150 2151 return airmont_freq_table[i]; 2152 } 2153 2154 static void atom_get_vid(struct cpudata *cpudata) 2155 { 2156 u64 value; 2157 2158 rdmsrq(MSR_ATOM_CORE_VIDS, value); 2159 cpudata->vid.min = int_tofp((value >> 8) & 0x7f); 2160 cpudata->vid.max = int_tofp((value >> 16) & 0x7f); 2161 cpudata->vid.ratio = div_fp( 2162 cpudata->vid.max - cpudata->vid.min, 2163 int_tofp(cpudata->pstate.max_pstate - 2164 cpudata->pstate.min_pstate)); 2165 2166 rdmsrq(MSR_ATOM_CORE_TURBO_VIDS, value); 2167 cpudata->vid.turbo = value & 0x7f; 2168 } 2169 2170 static int core_get_min_pstate(int cpu) 2171 { 2172 u64 value; 2173 2174 rdmsrq_on_cpu(cpu, MSR_PLATFORM_INFO, &value); 2175 return (value >> 40) & 0xFF; 2176 } 2177 2178 static int core_get_max_pstate_physical(int cpu) 2179 { 2180 u64 value; 2181 2182 rdmsrq_on_cpu(cpu, MSR_PLATFORM_INFO, &value); 2183 return (value >> 8) & 0xFF; 2184 } 2185 2186 static int core_get_tdp_ratio(int cpu, u64 plat_info) 2187 { 2188 /* Check how many TDP levels present */ 2189 if (plat_info & 0x600000000) { 2190 u64 tdp_ctrl; 2191 u64 tdp_ratio; 2192 int tdp_msr; 2193 int err; 2194 2195 /* Get the TDP level (0, 1, 2) to get ratios */ 2196 err = rdmsrq_safe_on_cpu(cpu, MSR_CONFIG_TDP_CONTROL, &tdp_ctrl); 2197 if (err) 2198 return err; 2199 2200 /* TDP MSR are continuous starting at 0x648 */ 2201 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03); 2202 err = rdmsrq_safe_on_cpu(cpu, tdp_msr, &tdp_ratio); 2203 if (err) 2204 return err; 2205 2206 /* For level 1 and 2, bits[23:16] contain the ratio */ 2207 if (tdp_ctrl & 0x03) 2208 tdp_ratio >>= 16; 2209 2210 tdp_ratio &= 0xff; /* ratios are only 8 bits long */ 2211 pr_debug("tdp_ratio %x\n", (int)tdp_ratio); 2212 2213 return (int)tdp_ratio; 2214 } 2215 2216 return -ENXIO; 2217 } 2218 2219 static int core_get_max_pstate(int cpu) 2220 { 2221 u64 tar; 2222 u64 plat_info; 2223 int max_pstate; 2224 int tdp_ratio; 2225 int err; 2226 2227 rdmsrq_on_cpu(cpu, MSR_PLATFORM_INFO, &plat_info); 2228 max_pstate = (plat_info >> 8) & 0xFF; 2229 2230 tdp_ratio = core_get_tdp_ratio(cpu, plat_info); 2231 if (tdp_ratio <= 0) 2232 return max_pstate; 2233 2234 if (hwp_active) { 2235 /* Turbo activation ratio is not used on HWP platforms */ 2236 return tdp_ratio; 2237 } 2238 2239 err = rdmsrq_safe_on_cpu(cpu, MSR_TURBO_ACTIVATION_RATIO, &tar); 2240 if (!err) { 2241 int tar_levels; 2242 2243 /* Do some sanity checking for safety */ 2244 tar_levels = tar & 0xff; 2245 if (tdp_ratio - 1 == tar_levels) { 2246 max_pstate = tar_levels; 2247 pr_debug("max_pstate=TAC %x\n", max_pstate); 2248 } 2249 } 2250 2251 return max_pstate; 2252 } 2253 2254 static int core_get_turbo_pstate(int cpu) 2255 { 2256 u64 value; 2257 int nont, ret; 2258 2259 rdmsrq_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value); 2260 nont = core_get_max_pstate(cpu); 2261 ret = (value) & 255; 2262 if (ret <= nont) 2263 ret = nont; 2264 return ret; 2265 } 2266 2267 static u64 core_get_val(struct cpudata *cpudata, int pstate) 2268 { 2269 u64 val; 2270 2271 val = (u64)pstate << 8; 2272 if (READ_ONCE(global.no_turbo) && !READ_ONCE(global.turbo_disabled) && 2273 cpu_feature_enabled(X86_FEATURE_IDA)) 2274 val |= (u64)1 << 32; 2275 2276 return val; 2277 } 2278 2279 static int knl_get_aperf_mperf_shift(void) 2280 { 2281 return 10; 2282 } 2283 2284 static int knl_get_turbo_pstate(int cpu) 2285 { 2286 u64 value; 2287 int nont, ret; 2288 2289 rdmsrq_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value); 2290 nont = core_get_max_pstate(cpu); 2291 ret = (((value) >> 8) & 0xFF); 2292 if (ret <= nont) 2293 ret = nont; 2294 return ret; 2295 } 2296 2297 static int hwp_get_cpu_scaling(int cpu) 2298 { 2299 if (hybrid_scaling_factor) { 2300 struct cpuinfo_x86 *c = &cpu_data(cpu); 2301 u8 cpu_type = c->topo.intel_type; 2302 2303 /* 2304 * Return the hybrid scaling factor for P-cores and use the 2305 * default core scaling for E-cores. 2306 */ 2307 if (cpu_type == INTEL_CPU_TYPE_CORE) 2308 return hybrid_scaling_factor; 2309 2310 if (cpu_type == INTEL_CPU_TYPE_ATOM) 2311 return core_get_scaling(); 2312 } 2313 2314 /* Use core scaling on non-hybrid systems. */ 2315 if (!cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) 2316 return core_get_scaling(); 2317 2318 /* 2319 * The system is hybrid, but the hybrid scaling factor is not known or 2320 * the CPU type is not one of the above, so use CPPC to compute the 2321 * scaling factor for this CPU. 2322 */ 2323 return intel_pstate_cppc_get_scaling(cpu); 2324 } 2325 2326 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate) 2327 { 2328 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu); 2329 cpu->pstate.current_pstate = pstate; 2330 /* 2331 * Generally, there is no guarantee that this code will always run on 2332 * the CPU being updated, so force the register update to run on the 2333 * right CPU. 2334 */ 2335 wrmsrq_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL, 2336 pstate_funcs.get_val(cpu, pstate)); 2337 } 2338 2339 static void intel_pstate_set_min_pstate(struct cpudata *cpu) 2340 { 2341 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate); 2342 } 2343 2344 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu) 2345 { 2346 int perf_ctl_max_phys = pstate_funcs.get_max_physical(cpu->cpu); 2347 int perf_ctl_scaling = pstate_funcs.get_scaling(); 2348 2349 cpu->pstate.min_pstate = pstate_funcs.get_min(cpu->cpu); 2350 cpu->pstate.max_pstate_physical = perf_ctl_max_phys; 2351 cpu->pstate.perf_ctl_scaling = perf_ctl_scaling; 2352 2353 if (hwp_active && !hwp_mode_bdw) { 2354 __intel_pstate_get_hwp_cap(cpu); 2355 2356 if (pstate_funcs.get_cpu_scaling) { 2357 cpu->pstate.scaling = pstate_funcs.get_cpu_scaling(cpu->cpu); 2358 if (cpu->pstate.scaling != perf_ctl_scaling) { 2359 intel_pstate_hybrid_hwp_adjust(cpu); 2360 hwp_is_hybrid = true; 2361 } 2362 } else { 2363 cpu->pstate.scaling = perf_ctl_scaling; 2364 } 2365 /* 2366 * If the CPU is going online for the first time and it was 2367 * offline initially, asym capacity scaling needs to be updated. 2368 */ 2369 hybrid_update_capacity(cpu); 2370 } else { 2371 cpu->pstate.scaling = perf_ctl_scaling; 2372 cpu->pstate.max_pstate = pstate_funcs.get_max(cpu->cpu); 2373 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(cpu->cpu); 2374 } 2375 2376 if (cpu->pstate.scaling == perf_ctl_scaling) { 2377 cpu->pstate.min_freq = cpu->pstate.min_pstate * perf_ctl_scaling; 2378 cpu->pstate.max_freq = cpu->pstate.max_pstate * perf_ctl_scaling; 2379 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * perf_ctl_scaling; 2380 } 2381 2382 if (pstate_funcs.get_aperf_mperf_shift) 2383 cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift(); 2384 2385 if (pstate_funcs.get_vid) 2386 pstate_funcs.get_vid(cpu); 2387 2388 intel_pstate_set_min_pstate(cpu); 2389 } 2390 2391 /* 2392 * Long hold time will keep high perf limits for long time, 2393 * which negatively impacts perf/watt for some workloads, 2394 * like specpower. 3ms is based on experiements on some 2395 * workoads. 2396 */ 2397 static int hwp_boost_hold_time_ns = 3 * NSEC_PER_MSEC; 2398 2399 static inline void intel_pstate_hwp_boost_up(struct cpudata *cpu) 2400 { 2401 u64 hwp_req = READ_ONCE(cpu->hwp_req_cached); 2402 u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached); 2403 u32 max_limit = (hwp_req & 0xff00) >> 8; 2404 u32 min_limit = (hwp_req & 0xff); 2405 u32 boost_level1; 2406 2407 /* 2408 * Cases to consider (User changes via sysfs or boot time): 2409 * If, P0 (Turbo max) = P1 (Guaranteed max) = min: 2410 * No boost, return. 2411 * If, P0 (Turbo max) > P1 (Guaranteed max) = min: 2412 * Should result in one level boost only for P0. 2413 * If, P0 (Turbo max) = P1 (Guaranteed max) > min: 2414 * Should result in two level boost: 2415 * (min + p1)/2 and P1. 2416 * If, P0 (Turbo max) > P1 (Guaranteed max) > min: 2417 * Should result in three level boost: 2418 * (min + p1)/2, P1 and P0. 2419 */ 2420 2421 /* If max and min are equal or already at max, nothing to boost */ 2422 if (max_limit == min_limit || cpu->hwp_boost_min >= max_limit) 2423 return; 2424 2425 if (!cpu->hwp_boost_min) 2426 cpu->hwp_boost_min = min_limit; 2427 2428 /* level at half way mark between min and guranteed */ 2429 boost_level1 = (HWP_GUARANTEED_PERF(hwp_cap) + min_limit) >> 1; 2430 2431 if (cpu->hwp_boost_min < boost_level1) 2432 cpu->hwp_boost_min = boost_level1; 2433 else if (cpu->hwp_boost_min < HWP_GUARANTEED_PERF(hwp_cap)) 2434 cpu->hwp_boost_min = HWP_GUARANTEED_PERF(hwp_cap); 2435 else if (cpu->hwp_boost_min == HWP_GUARANTEED_PERF(hwp_cap) && 2436 max_limit != HWP_GUARANTEED_PERF(hwp_cap)) 2437 cpu->hwp_boost_min = max_limit; 2438 else 2439 return; 2440 2441 hwp_req = (hwp_req & ~GENMASK_ULL(7, 0)) | cpu->hwp_boost_min; 2442 wrmsrq(MSR_HWP_REQUEST, hwp_req); 2443 cpu->last_update = cpu->sample.time; 2444 } 2445 2446 static inline void intel_pstate_hwp_boost_down(struct cpudata *cpu) 2447 { 2448 if (cpu->hwp_boost_min) { 2449 bool expired; 2450 2451 /* Check if we are idle for hold time to boost down */ 2452 expired = time_after64(cpu->sample.time, cpu->last_update + 2453 hwp_boost_hold_time_ns); 2454 if (expired) { 2455 wrmsrq(MSR_HWP_REQUEST, cpu->hwp_req_cached); 2456 cpu->hwp_boost_min = 0; 2457 } 2458 } 2459 cpu->last_update = cpu->sample.time; 2460 } 2461 2462 static inline void intel_pstate_update_util_hwp_local(struct cpudata *cpu, 2463 u64 time) 2464 { 2465 cpu->sample.time = time; 2466 2467 if (cpu->sched_flags & SCHED_CPUFREQ_IOWAIT) { 2468 bool do_io = false; 2469 2470 cpu->sched_flags = 0; 2471 /* 2472 * Set iowait_boost flag and update time. Since IO WAIT flag 2473 * is set all the time, we can't just conclude that there is 2474 * some IO bound activity is scheduled on this CPU with just 2475 * one occurrence. If we receive at least two in two 2476 * consecutive ticks, then we treat as boost candidate. 2477 */ 2478 if (time_before64(time, cpu->last_io_update + 2 * TICK_NSEC)) 2479 do_io = true; 2480 2481 cpu->last_io_update = time; 2482 2483 if (do_io) 2484 intel_pstate_hwp_boost_up(cpu); 2485 2486 } else { 2487 intel_pstate_hwp_boost_down(cpu); 2488 } 2489 } 2490 2491 static inline void intel_pstate_update_util_hwp(struct update_util_data *data, 2492 u64 time, unsigned int flags) 2493 { 2494 struct cpudata *cpu = container_of(data, struct cpudata, update_util); 2495 2496 cpu->sched_flags |= flags; 2497 2498 if (smp_processor_id() == cpu->cpu) 2499 intel_pstate_update_util_hwp_local(cpu, time); 2500 } 2501 2502 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu) 2503 { 2504 struct sample *sample = &cpu->sample; 2505 2506 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf); 2507 } 2508 2509 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time) 2510 { 2511 u64 aperf, mperf; 2512 unsigned long flags; 2513 u64 tsc; 2514 2515 local_irq_save(flags); 2516 rdmsrq(MSR_IA32_APERF, aperf); 2517 rdmsrq(MSR_IA32_MPERF, mperf); 2518 tsc = rdtsc(); 2519 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) { 2520 local_irq_restore(flags); 2521 return false; 2522 } 2523 local_irq_restore(flags); 2524 2525 cpu->last_sample_time = cpu->sample.time; 2526 cpu->sample.time = time; 2527 cpu->sample.aperf = aperf; 2528 cpu->sample.mperf = mperf; 2529 cpu->sample.tsc = tsc; 2530 cpu->sample.aperf -= cpu->prev_aperf; 2531 cpu->sample.mperf -= cpu->prev_mperf; 2532 cpu->sample.tsc -= cpu->prev_tsc; 2533 2534 cpu->prev_aperf = aperf; 2535 cpu->prev_mperf = mperf; 2536 cpu->prev_tsc = tsc; 2537 /* 2538 * First time this function is invoked in a given cycle, all of the 2539 * previous sample data fields are equal to zero or stale and they must 2540 * be populated with meaningful numbers for things to work, so assume 2541 * that sample.time will always be reset before setting the utilization 2542 * update hook and make the caller skip the sample then. 2543 */ 2544 if (likely(cpu->last_sample_time)) { 2545 intel_pstate_calc_avg_perf(cpu); 2546 return true; 2547 } 2548 return false; 2549 } 2550 2551 static inline int32_t get_avg_frequency(struct cpudata *cpu) 2552 { 2553 return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz); 2554 } 2555 2556 static inline int32_t get_avg_pstate(struct cpudata *cpu) 2557 { 2558 return mul_ext_fp(cpu->pstate.max_pstate_physical, 2559 cpu->sample.core_avg_perf); 2560 } 2561 2562 static inline int32_t get_target_pstate(struct cpudata *cpu) 2563 { 2564 struct sample *sample = &cpu->sample; 2565 int32_t busy_frac; 2566 int target, avg_pstate; 2567 2568 busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift, 2569 sample->tsc); 2570 2571 if (busy_frac < cpu->iowait_boost) 2572 busy_frac = cpu->iowait_boost; 2573 2574 sample->busy_scaled = busy_frac * 100; 2575 2576 target = READ_ONCE(global.no_turbo) ? 2577 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate; 2578 target += target >> 2; 2579 target = mul_fp(target, busy_frac); 2580 if (target < cpu->pstate.min_pstate) 2581 target = cpu->pstate.min_pstate; 2582 2583 /* 2584 * If the average P-state during the previous cycle was higher than the 2585 * current target, add 50% of the difference to the target to reduce 2586 * possible performance oscillations and offset possible performance 2587 * loss related to moving the workload from one CPU to another within 2588 * a package/module. 2589 */ 2590 avg_pstate = get_avg_pstate(cpu); 2591 if (avg_pstate > target) 2592 target += (avg_pstate - target) >> 1; 2593 2594 return target; 2595 } 2596 2597 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate) 2598 { 2599 int min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio); 2600 int max_pstate = max(min_pstate, cpu->max_perf_ratio); 2601 2602 return clamp_t(int, pstate, min_pstate, max_pstate); 2603 } 2604 2605 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate) 2606 { 2607 if (pstate == cpu->pstate.current_pstate) 2608 return; 2609 2610 cpu->pstate.current_pstate = pstate; 2611 wrmsrq(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate)); 2612 } 2613 2614 static void intel_pstate_adjust_pstate(struct cpudata *cpu) 2615 { 2616 int from = cpu->pstate.current_pstate; 2617 struct sample *sample; 2618 int target_pstate; 2619 2620 target_pstate = get_target_pstate(cpu); 2621 target_pstate = intel_pstate_prepare_request(cpu, target_pstate); 2622 trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu); 2623 intel_pstate_update_pstate(cpu, target_pstate); 2624 2625 sample = &cpu->sample; 2626 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf), 2627 fp_toint(sample->busy_scaled), 2628 from, 2629 cpu->pstate.current_pstate, 2630 sample->mperf, 2631 sample->aperf, 2632 sample->tsc, 2633 get_avg_frequency(cpu), 2634 fp_toint(cpu->iowait_boost * 100)); 2635 } 2636 2637 static void intel_pstate_update_util(struct update_util_data *data, u64 time, 2638 unsigned int flags) 2639 { 2640 struct cpudata *cpu = container_of(data, struct cpudata, update_util); 2641 u64 delta_ns; 2642 2643 /* Don't allow remote callbacks */ 2644 if (smp_processor_id() != cpu->cpu) 2645 return; 2646 2647 delta_ns = time - cpu->last_update; 2648 if (flags & SCHED_CPUFREQ_IOWAIT) { 2649 /* Start over if the CPU may have been idle. */ 2650 if (delta_ns > TICK_NSEC) { 2651 cpu->iowait_boost = ONE_EIGHTH_FP; 2652 } else if (cpu->iowait_boost >= ONE_EIGHTH_FP) { 2653 cpu->iowait_boost <<= 1; 2654 if (cpu->iowait_boost > int_tofp(1)) 2655 cpu->iowait_boost = int_tofp(1); 2656 } else { 2657 cpu->iowait_boost = ONE_EIGHTH_FP; 2658 } 2659 } else if (cpu->iowait_boost) { 2660 /* Clear iowait_boost if the CPU may have been idle. */ 2661 if (delta_ns > TICK_NSEC) 2662 cpu->iowait_boost = 0; 2663 else 2664 cpu->iowait_boost >>= 1; 2665 } 2666 cpu->last_update = time; 2667 delta_ns = time - cpu->sample.time; 2668 if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL) 2669 return; 2670 2671 if (intel_pstate_sample(cpu, time)) 2672 intel_pstate_adjust_pstate(cpu); 2673 } 2674 2675 static struct pstate_funcs core_funcs = { 2676 .get_max = core_get_max_pstate, 2677 .get_max_physical = core_get_max_pstate_physical, 2678 .get_min = core_get_min_pstate, 2679 .get_turbo = core_get_turbo_pstate, 2680 .get_scaling = core_get_scaling, 2681 .get_val = core_get_val, 2682 }; 2683 2684 static const struct pstate_funcs silvermont_funcs = { 2685 .get_max = atom_get_max_pstate, 2686 .get_max_physical = atom_get_max_pstate, 2687 .get_min = atom_get_min_pstate, 2688 .get_turbo = atom_get_turbo_pstate, 2689 .get_val = atom_get_val, 2690 .get_scaling = silvermont_get_scaling, 2691 .get_vid = atom_get_vid, 2692 }; 2693 2694 static const struct pstate_funcs airmont_funcs = { 2695 .get_max = atom_get_max_pstate, 2696 .get_max_physical = atom_get_max_pstate, 2697 .get_min = atom_get_min_pstate, 2698 .get_turbo = atom_get_turbo_pstate, 2699 .get_val = atom_get_val, 2700 .get_scaling = airmont_get_scaling, 2701 .get_vid = atom_get_vid, 2702 }; 2703 2704 static const struct pstate_funcs knl_funcs = { 2705 .get_max = core_get_max_pstate, 2706 .get_max_physical = core_get_max_pstate_physical, 2707 .get_min = core_get_min_pstate, 2708 .get_turbo = knl_get_turbo_pstate, 2709 .get_aperf_mperf_shift = knl_get_aperf_mperf_shift, 2710 .get_scaling = core_get_scaling, 2711 .get_val = core_get_val, 2712 }; 2713 2714 #define X86_MATCH(vfm, policy) \ 2715 X86_MATCH_VFM_FEATURE(vfm, X86_FEATURE_APERFMPERF, &policy) 2716 2717 static const struct x86_cpu_id intel_pstate_cpu_ids[] = { 2718 X86_MATCH(INTEL_SANDYBRIDGE, core_funcs), 2719 X86_MATCH(INTEL_SANDYBRIDGE_X, core_funcs), 2720 X86_MATCH(INTEL_ATOM_SILVERMONT, silvermont_funcs), 2721 X86_MATCH(INTEL_IVYBRIDGE, core_funcs), 2722 X86_MATCH(INTEL_HASWELL, core_funcs), 2723 X86_MATCH(INTEL_BROADWELL, core_funcs), 2724 X86_MATCH(INTEL_IVYBRIDGE_X, core_funcs), 2725 X86_MATCH(INTEL_HASWELL_X, core_funcs), 2726 X86_MATCH(INTEL_HASWELL_L, core_funcs), 2727 X86_MATCH(INTEL_HASWELL_G, core_funcs), 2728 X86_MATCH(INTEL_BROADWELL_G, core_funcs), 2729 X86_MATCH(INTEL_ATOM_AIRMONT, airmont_funcs), 2730 X86_MATCH(INTEL_SKYLAKE_L, core_funcs), 2731 X86_MATCH(INTEL_BROADWELL_X, core_funcs), 2732 X86_MATCH(INTEL_SKYLAKE, core_funcs), 2733 X86_MATCH(INTEL_BROADWELL_D, core_funcs), 2734 X86_MATCH(INTEL_XEON_PHI_KNL, knl_funcs), 2735 X86_MATCH(INTEL_XEON_PHI_KNM, knl_funcs), 2736 X86_MATCH(INTEL_ATOM_GOLDMONT, core_funcs), 2737 X86_MATCH(INTEL_ATOM_GOLDMONT_PLUS, core_funcs), 2738 X86_MATCH(INTEL_SKYLAKE_X, core_funcs), 2739 X86_MATCH(INTEL_COMETLAKE, core_funcs), 2740 X86_MATCH(INTEL_ICELAKE_X, core_funcs), 2741 X86_MATCH(INTEL_TIGERLAKE, core_funcs), 2742 X86_MATCH(INTEL_SAPPHIRERAPIDS_X, core_funcs), 2743 X86_MATCH(INTEL_EMERALDRAPIDS_X, core_funcs), 2744 X86_MATCH(INTEL_GRANITERAPIDS_D, core_funcs), 2745 X86_MATCH(INTEL_GRANITERAPIDS_X, core_funcs), 2746 {} 2747 }; 2748 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids); 2749 2750 #ifdef CONFIG_ACPI 2751 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = { 2752 X86_MATCH(INTEL_BROADWELL_D, core_funcs), 2753 X86_MATCH(INTEL_BROADWELL_X, core_funcs), 2754 X86_MATCH(INTEL_SKYLAKE_X, core_funcs), 2755 X86_MATCH(INTEL_ICELAKE_X, core_funcs), 2756 X86_MATCH(INTEL_SAPPHIRERAPIDS_X, core_funcs), 2757 X86_MATCH(INTEL_EMERALDRAPIDS_X, core_funcs), 2758 X86_MATCH(INTEL_GRANITERAPIDS_D, core_funcs), 2759 X86_MATCH(INTEL_GRANITERAPIDS_X, core_funcs), 2760 X86_MATCH(INTEL_ATOM_CRESTMONT, core_funcs), 2761 X86_MATCH(INTEL_ATOM_CRESTMONT_X, core_funcs), 2762 X86_MATCH(INTEL_ATOM_DARKMONT_X, core_funcs), 2763 {} 2764 }; 2765 #endif 2766 2767 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = { 2768 X86_MATCH(INTEL_KABYLAKE, core_funcs), 2769 {} 2770 }; 2771 2772 static int intel_pstate_init_cpu(unsigned int cpunum) 2773 { 2774 struct cpudata *cpu; 2775 2776 cpu = all_cpu_data[cpunum]; 2777 2778 if (!cpu) { 2779 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL); 2780 if (!cpu) 2781 return -ENOMEM; 2782 2783 WRITE_ONCE(all_cpu_data[cpunum], cpu); 2784 2785 cpu->cpu = cpunum; 2786 2787 cpu->epp_default = -EINVAL; 2788 2789 if (hwp_active) { 2790 intel_pstate_hwp_enable(cpu); 2791 2792 if (intel_pstate_acpi_pm_profile_server()) 2793 hwp_boost = true; 2794 } 2795 } else if (hwp_active) { 2796 /* 2797 * Re-enable HWP in case this happens after a resume from ACPI 2798 * S3 if the CPU was offline during the whole system/resume 2799 * cycle. 2800 */ 2801 intel_pstate_hwp_reenable(cpu); 2802 } 2803 2804 cpu->epp_powersave = -EINVAL; 2805 cpu->epp_policy = CPUFREQ_POLICY_UNKNOWN; 2806 2807 intel_pstate_get_cpu_pstates(cpu); 2808 2809 pr_debug("controlling: cpu %d\n", cpunum); 2810 2811 return 0; 2812 } 2813 2814 static void intel_pstate_set_update_util_hook(unsigned int cpu_num) 2815 { 2816 struct cpudata *cpu = all_cpu_data[cpu_num]; 2817 2818 if (hwp_active && !hwp_boost) 2819 return; 2820 2821 if (cpu->update_util_set) 2822 return; 2823 2824 /* Prevent intel_pstate_update_util() from using stale data. */ 2825 cpu->sample.time = 0; 2826 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util, 2827 (hwp_active ? 2828 intel_pstate_update_util_hwp : 2829 intel_pstate_update_util)); 2830 cpu->update_util_set = true; 2831 } 2832 2833 static void intel_pstate_clear_update_util_hook(unsigned int cpu) 2834 { 2835 struct cpudata *cpu_data = all_cpu_data[cpu]; 2836 2837 if (!cpu_data->update_util_set) 2838 return; 2839 2840 cpufreq_remove_update_util_hook(cpu); 2841 cpu_data->update_util_set = false; 2842 synchronize_rcu(); 2843 } 2844 2845 static int intel_pstate_get_max_freq(struct cpudata *cpu) 2846 { 2847 return READ_ONCE(global.no_turbo) ? 2848 cpu->pstate.max_freq : cpu->pstate.turbo_freq; 2849 } 2850 2851 static void intel_pstate_update_perf_limits(struct cpudata *cpu, 2852 unsigned int policy_min, 2853 unsigned int policy_max) 2854 { 2855 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling; 2856 int32_t max_policy_perf, min_policy_perf; 2857 2858 max_policy_perf = policy_max / perf_ctl_scaling; 2859 if (policy_max == policy_min) { 2860 min_policy_perf = max_policy_perf; 2861 } else { 2862 min_policy_perf = policy_min / perf_ctl_scaling; 2863 min_policy_perf = clamp_t(int32_t, min_policy_perf, 2864 0, max_policy_perf); 2865 } 2866 2867 /* 2868 * HWP needs some special consideration, because HWP_REQUEST uses 2869 * abstract values to represent performance rather than pure ratios. 2870 */ 2871 if (hwp_active && cpu->pstate.scaling != perf_ctl_scaling) { 2872 int freq; 2873 2874 freq = max_policy_perf * perf_ctl_scaling; 2875 max_policy_perf = intel_pstate_freq_to_hwp(cpu, freq); 2876 freq = min_policy_perf * perf_ctl_scaling; 2877 min_policy_perf = intel_pstate_freq_to_hwp(cpu, freq); 2878 } 2879 2880 pr_debug("cpu:%d min_policy_perf:%d max_policy_perf:%d\n", 2881 cpu->cpu, min_policy_perf, max_policy_perf); 2882 2883 /* Normalize user input to [min_perf, max_perf] */ 2884 if (per_cpu_limits) { 2885 cpu->min_perf_ratio = min_policy_perf; 2886 cpu->max_perf_ratio = max_policy_perf; 2887 } else { 2888 int turbo_max = cpu->pstate.turbo_pstate; 2889 int32_t global_min, global_max; 2890 2891 /* Global limits are in percent of the maximum turbo P-state. */ 2892 global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100); 2893 global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100); 2894 global_min = clamp_t(int32_t, global_min, 0, global_max); 2895 2896 pr_debug("cpu:%d global_min:%d global_max:%d\n", cpu->cpu, 2897 global_min, global_max); 2898 2899 cpu->min_perf_ratio = max(min_policy_perf, global_min); 2900 cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf); 2901 cpu->max_perf_ratio = min(max_policy_perf, global_max); 2902 cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio); 2903 2904 /* Make sure min_perf <= max_perf */ 2905 cpu->min_perf_ratio = min(cpu->min_perf_ratio, 2906 cpu->max_perf_ratio); 2907 2908 } 2909 pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", cpu->cpu, 2910 cpu->max_perf_ratio, 2911 cpu->min_perf_ratio); 2912 } 2913 2914 static int intel_pstate_set_policy(struct cpufreq_policy *policy) 2915 { 2916 struct cpudata *cpu; 2917 2918 if (!policy->cpuinfo.max_freq) 2919 return -ENODEV; 2920 2921 pr_debug("set_policy cpuinfo.max %u policy->max %u\n", 2922 policy->cpuinfo.max_freq, policy->max); 2923 2924 cpu = all_cpu_data[policy->cpu]; 2925 cpu->policy = policy->policy; 2926 2927 mutex_lock(&intel_pstate_limits_lock); 2928 2929 intel_pstate_update_perf_limits(cpu, policy->min, policy->max); 2930 2931 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) { 2932 int pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio); 2933 2934 /* 2935 * NOHZ_FULL CPUs need this as the governor callback may not 2936 * be invoked on them. 2937 */ 2938 intel_pstate_clear_update_util_hook(policy->cpu); 2939 intel_pstate_set_pstate(cpu, pstate); 2940 } else { 2941 intel_pstate_set_update_util_hook(policy->cpu); 2942 } 2943 2944 if (hwp_active) { 2945 /* 2946 * When hwp_boost was active before and dynamically it 2947 * was turned off, in that case we need to clear the 2948 * update util hook. 2949 */ 2950 if (!hwp_boost) 2951 intel_pstate_clear_update_util_hook(policy->cpu); 2952 intel_pstate_hwp_set(policy->cpu); 2953 } 2954 /* 2955 * policy->cur is never updated with the intel_pstate driver, but it 2956 * is used as a stale frequency value. So, keep it within limits. 2957 */ 2958 policy->cur = policy->min; 2959 2960 mutex_unlock(&intel_pstate_limits_lock); 2961 2962 return 0; 2963 } 2964 2965 static void intel_pstate_adjust_policy_max(struct cpudata *cpu, 2966 struct cpufreq_policy_data *policy) 2967 { 2968 if (!hwp_active && 2969 cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate && 2970 policy->max < policy->cpuinfo.max_freq && 2971 policy->max > cpu->pstate.max_freq) { 2972 pr_debug("policy->max > max non turbo frequency\n"); 2973 policy->max = policy->cpuinfo.max_freq; 2974 } 2975 } 2976 2977 static void intel_pstate_verify_cpu_policy(struct cpudata *cpu, 2978 struct cpufreq_policy_data *policy) 2979 { 2980 int max_freq; 2981 2982 if (hwp_active) { 2983 intel_pstate_get_hwp_cap(cpu); 2984 max_freq = READ_ONCE(global.no_turbo) ? 2985 cpu->pstate.max_freq : cpu->pstate.turbo_freq; 2986 } else { 2987 max_freq = intel_pstate_get_max_freq(cpu); 2988 } 2989 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, max_freq); 2990 2991 intel_pstate_adjust_policy_max(cpu, policy); 2992 } 2993 2994 static int intel_pstate_verify_policy(struct cpufreq_policy_data *policy) 2995 { 2996 intel_pstate_verify_cpu_policy(all_cpu_data[policy->cpu], policy); 2997 2998 return 0; 2999 } 3000 3001 static int intel_cpufreq_cpu_offline(struct cpufreq_policy *policy) 3002 { 3003 struct cpudata *cpu = all_cpu_data[policy->cpu]; 3004 3005 pr_debug("CPU %d going offline\n", cpu->cpu); 3006 3007 if (cpu->suspended) 3008 return 0; 3009 3010 /* 3011 * If the CPU is an SMT thread and it goes offline with the performance 3012 * settings different from the minimum, it will prevent its sibling 3013 * from getting to lower performance levels, so force the minimum 3014 * performance on CPU offline to prevent that from happening. 3015 */ 3016 if (hwp_active) 3017 intel_pstate_hwp_offline(cpu); 3018 else 3019 intel_pstate_set_min_pstate(cpu); 3020 3021 intel_pstate_exit_perf_limits(policy); 3022 3023 return 0; 3024 } 3025 3026 static int intel_pstate_cpu_online(struct cpufreq_policy *policy) 3027 { 3028 struct cpudata *cpu = all_cpu_data[policy->cpu]; 3029 3030 pr_debug("CPU %d going online\n", cpu->cpu); 3031 3032 intel_pstate_init_acpi_perf_limits(policy); 3033 3034 if (hwp_active) { 3035 /* 3036 * Re-enable HWP and clear the "suspended" flag to let "resume" 3037 * know that it need not do that. 3038 */ 3039 intel_pstate_hwp_reenable(cpu); 3040 cpu->suspended = false; 3041 3042 hybrid_update_capacity(cpu); 3043 } 3044 3045 return 0; 3046 } 3047 3048 static int intel_pstate_cpu_offline(struct cpufreq_policy *policy) 3049 { 3050 intel_pstate_clear_update_util_hook(policy->cpu); 3051 3052 return intel_cpufreq_cpu_offline(policy); 3053 } 3054 3055 static void intel_pstate_cpu_exit(struct cpufreq_policy *policy) 3056 { 3057 pr_debug("CPU %d exiting\n", policy->cpu); 3058 3059 policy->fast_switch_possible = false; 3060 } 3061 3062 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy) 3063 { 3064 struct cpudata *cpu; 3065 int rc; 3066 3067 rc = intel_pstate_init_cpu(policy->cpu); 3068 if (rc) 3069 return rc; 3070 3071 cpu = all_cpu_data[policy->cpu]; 3072 3073 cpu->max_perf_ratio = 0xFF; 3074 cpu->min_perf_ratio = 0; 3075 3076 /* cpuinfo and default policy values */ 3077 policy->cpuinfo.min_freq = cpu->pstate.min_freq; 3078 policy->cpuinfo.max_freq = READ_ONCE(global.no_turbo) ? 3079 cpu->pstate.max_freq : cpu->pstate.turbo_freq; 3080 3081 policy->min = policy->cpuinfo.min_freq; 3082 policy->max = policy->cpuinfo.max_freq; 3083 3084 intel_pstate_init_acpi_perf_limits(policy); 3085 3086 policy->fast_switch_possible = true; 3087 3088 return 0; 3089 } 3090 3091 static int intel_pstate_cpu_init(struct cpufreq_policy *policy) 3092 { 3093 int ret = __intel_pstate_cpu_init(policy); 3094 3095 if (ret) 3096 return ret; 3097 3098 /* 3099 * Set the policy to powersave to provide a valid fallback value in case 3100 * the default cpufreq governor is neither powersave nor performance. 3101 */ 3102 policy->policy = CPUFREQ_POLICY_POWERSAVE; 3103 3104 if (hwp_active) { 3105 struct cpudata *cpu = all_cpu_data[policy->cpu]; 3106 3107 cpu->epp_cached = intel_pstate_get_epp(cpu, 0); 3108 } 3109 3110 return 0; 3111 } 3112 3113 static struct cpufreq_driver intel_pstate = { 3114 .flags = CPUFREQ_CONST_LOOPS, 3115 .verify = intel_pstate_verify_policy, 3116 .setpolicy = intel_pstate_set_policy, 3117 .suspend = intel_pstate_suspend, 3118 .resume = intel_pstate_resume, 3119 .init = intel_pstate_cpu_init, 3120 .exit = intel_pstate_cpu_exit, 3121 .offline = intel_pstate_cpu_offline, 3122 .online = intel_pstate_cpu_online, 3123 .update_limits = intel_pstate_update_limits, 3124 .name = "intel_pstate", 3125 }; 3126 3127 static int intel_cpufreq_verify_policy(struct cpufreq_policy_data *policy) 3128 { 3129 struct cpudata *cpu = all_cpu_data[policy->cpu]; 3130 3131 intel_pstate_verify_cpu_policy(cpu, policy); 3132 intel_pstate_update_perf_limits(cpu, policy->min, policy->max); 3133 3134 return 0; 3135 } 3136 3137 /* Use of trace in passive mode: 3138 * 3139 * In passive mode the trace core_busy field (also known as the 3140 * performance field, and lablelled as such on the graphs; also known as 3141 * core_avg_perf) is not needed and so is re-assigned to indicate if the 3142 * driver call was via the normal or fast switch path. Various graphs 3143 * output from the intel_pstate_tracer.py utility that include core_busy 3144 * (or performance or core_avg_perf) have a fixed y-axis from 0 to 100%, 3145 * so we use 10 to indicate the normal path through the driver, and 3146 * 90 to indicate the fast switch path through the driver. 3147 * The scaled_busy field is not used, and is set to 0. 3148 */ 3149 3150 #define INTEL_PSTATE_TRACE_TARGET 10 3151 #define INTEL_PSTATE_TRACE_FAST_SWITCH 90 3152 3153 static void intel_cpufreq_trace(struct cpudata *cpu, unsigned int trace_type, int old_pstate) 3154 { 3155 struct sample *sample; 3156 3157 if (!trace_pstate_sample_enabled()) 3158 return; 3159 3160 if (!intel_pstate_sample(cpu, ktime_get())) 3161 return; 3162 3163 sample = &cpu->sample; 3164 trace_pstate_sample(trace_type, 3165 0, 3166 old_pstate, 3167 cpu->pstate.current_pstate, 3168 sample->mperf, 3169 sample->aperf, 3170 sample->tsc, 3171 get_avg_frequency(cpu), 3172 fp_toint(cpu->iowait_boost * 100)); 3173 } 3174 3175 static void intel_cpufreq_hwp_update(struct cpudata *cpu, u32 min, u32 max, 3176 u32 desired, bool fast_switch) 3177 { 3178 u64 prev = READ_ONCE(cpu->hwp_req_cached), value = prev; 3179 3180 value &= ~HWP_MIN_PERF(~0L); 3181 value |= HWP_MIN_PERF(min); 3182 3183 value &= ~HWP_MAX_PERF(~0L); 3184 value |= HWP_MAX_PERF(max); 3185 3186 value &= ~HWP_DESIRED_PERF(~0L); 3187 value |= HWP_DESIRED_PERF(desired); 3188 3189 if (value == prev) 3190 return; 3191 3192 WRITE_ONCE(cpu->hwp_req_cached, value); 3193 if (fast_switch) 3194 wrmsrq(MSR_HWP_REQUEST, value); 3195 else 3196 wrmsrq_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 3197 } 3198 3199 static void intel_cpufreq_perf_ctl_update(struct cpudata *cpu, 3200 u32 target_pstate, bool fast_switch) 3201 { 3202 if (fast_switch) 3203 wrmsrq(MSR_IA32_PERF_CTL, 3204 pstate_funcs.get_val(cpu, target_pstate)); 3205 else 3206 wrmsrq_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL, 3207 pstate_funcs.get_val(cpu, target_pstate)); 3208 } 3209 3210 static int intel_cpufreq_update_pstate(struct cpufreq_policy *policy, 3211 int target_pstate, bool fast_switch) 3212 { 3213 struct cpudata *cpu = all_cpu_data[policy->cpu]; 3214 int old_pstate = cpu->pstate.current_pstate; 3215 3216 target_pstate = intel_pstate_prepare_request(cpu, target_pstate); 3217 if (hwp_active) { 3218 int max_pstate = policy->strict_target ? 3219 target_pstate : cpu->max_perf_ratio; 3220 3221 intel_cpufreq_hwp_update(cpu, target_pstate, max_pstate, 3222 target_pstate, fast_switch); 3223 } else if (target_pstate != old_pstate) { 3224 intel_cpufreq_perf_ctl_update(cpu, target_pstate, fast_switch); 3225 } 3226 3227 cpu->pstate.current_pstate = target_pstate; 3228 3229 intel_cpufreq_trace(cpu, fast_switch ? INTEL_PSTATE_TRACE_FAST_SWITCH : 3230 INTEL_PSTATE_TRACE_TARGET, old_pstate); 3231 3232 return target_pstate; 3233 } 3234 3235 static int intel_cpufreq_target(struct cpufreq_policy *policy, 3236 unsigned int target_freq, 3237 unsigned int relation) 3238 { 3239 struct cpudata *cpu = all_cpu_data[policy->cpu]; 3240 struct cpufreq_freqs freqs; 3241 int target_pstate; 3242 3243 freqs.old = policy->cur; 3244 freqs.new = target_freq; 3245 3246 cpufreq_freq_transition_begin(policy, &freqs); 3247 3248 target_pstate = intel_pstate_freq_to_hwp_rel(cpu, freqs.new, relation); 3249 target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, false); 3250 3251 freqs.new = target_pstate * cpu->pstate.scaling; 3252 3253 cpufreq_freq_transition_end(policy, &freqs, false); 3254 3255 return 0; 3256 } 3257 3258 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy, 3259 unsigned int target_freq) 3260 { 3261 struct cpudata *cpu = all_cpu_data[policy->cpu]; 3262 int target_pstate; 3263 3264 target_pstate = intel_pstate_freq_to_hwp(cpu, target_freq); 3265 3266 target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, true); 3267 3268 return target_pstate * cpu->pstate.scaling; 3269 } 3270 3271 static void intel_cpufreq_adjust_perf(unsigned int cpunum, 3272 unsigned long min_perf, 3273 unsigned long target_perf, 3274 unsigned long capacity) 3275 { 3276 struct cpudata *cpu = all_cpu_data[cpunum]; 3277 u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached); 3278 int old_pstate = cpu->pstate.current_pstate; 3279 int cap_pstate, min_pstate, max_pstate, target_pstate; 3280 3281 cap_pstate = READ_ONCE(global.no_turbo) ? 3282 HWP_GUARANTEED_PERF(hwp_cap) : 3283 HWP_HIGHEST_PERF(hwp_cap); 3284 3285 /* Optimization: Avoid unnecessary divisions. */ 3286 3287 target_pstate = cap_pstate; 3288 if (target_perf < capacity) 3289 target_pstate = DIV_ROUND_UP(cap_pstate * target_perf, capacity); 3290 3291 min_pstate = cap_pstate; 3292 if (min_perf < capacity) 3293 min_pstate = DIV_ROUND_UP(cap_pstate * min_perf, capacity); 3294 3295 if (min_pstate < cpu->pstate.min_pstate) 3296 min_pstate = cpu->pstate.min_pstate; 3297 3298 if (min_pstate < cpu->min_perf_ratio) 3299 min_pstate = cpu->min_perf_ratio; 3300 3301 if (min_pstate > cpu->max_perf_ratio) 3302 min_pstate = cpu->max_perf_ratio; 3303 3304 max_pstate = min(cap_pstate, cpu->max_perf_ratio); 3305 if (max_pstate < min_pstate) 3306 max_pstate = min_pstate; 3307 3308 target_pstate = clamp_t(int, target_pstate, min_pstate, max_pstate); 3309 3310 intel_cpufreq_hwp_update(cpu, min_pstate, max_pstate, target_pstate, true); 3311 3312 cpu->pstate.current_pstate = target_pstate; 3313 intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_FAST_SWITCH, old_pstate); 3314 } 3315 3316 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy) 3317 { 3318 struct freq_qos_request *req; 3319 struct cpudata *cpu; 3320 struct device *dev; 3321 int ret, freq; 3322 3323 dev = get_cpu_device(policy->cpu); 3324 if (!dev) 3325 return -ENODEV; 3326 3327 ret = __intel_pstate_cpu_init(policy); 3328 if (ret) 3329 return ret; 3330 3331 policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY; 3332 /* This reflects the intel_pstate_get_cpu_pstates() setting. */ 3333 policy->cur = policy->cpuinfo.min_freq; 3334 3335 req = kcalloc(2, sizeof(*req), GFP_KERNEL); 3336 if (!req) { 3337 ret = -ENOMEM; 3338 goto pstate_exit; 3339 } 3340 3341 cpu = all_cpu_data[policy->cpu]; 3342 3343 if (hwp_active) { 3344 u64 value; 3345 3346 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY_HWP; 3347 3348 intel_pstate_get_hwp_cap(cpu); 3349 3350 rdmsrq_on_cpu(cpu->cpu, MSR_HWP_REQUEST, &value); 3351 WRITE_ONCE(cpu->hwp_req_cached, value); 3352 3353 cpu->epp_cached = intel_pstate_get_epp(cpu, value); 3354 } else { 3355 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY; 3356 } 3357 3358 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.min_perf_pct, 100); 3359 3360 ret = freq_qos_add_request(&policy->constraints, req, FREQ_QOS_MIN, 3361 freq); 3362 if (ret < 0) { 3363 dev_err(dev, "Failed to add min-freq constraint (%d)\n", ret); 3364 goto free_req; 3365 } 3366 3367 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.max_perf_pct, 100); 3368 3369 ret = freq_qos_add_request(&policy->constraints, req + 1, FREQ_QOS_MAX, 3370 freq); 3371 if (ret < 0) { 3372 dev_err(dev, "Failed to add max-freq constraint (%d)\n", ret); 3373 goto remove_min_req; 3374 } 3375 3376 policy->driver_data = req; 3377 3378 return 0; 3379 3380 remove_min_req: 3381 freq_qos_remove_request(req); 3382 free_req: 3383 kfree(req); 3384 pstate_exit: 3385 intel_pstate_exit_perf_limits(policy); 3386 3387 return ret; 3388 } 3389 3390 static void intel_cpufreq_cpu_exit(struct cpufreq_policy *policy) 3391 { 3392 struct freq_qos_request *req; 3393 3394 req = policy->driver_data; 3395 3396 freq_qos_remove_request(req + 1); 3397 freq_qos_remove_request(req); 3398 kfree(req); 3399 3400 intel_pstate_cpu_exit(policy); 3401 } 3402 3403 static int intel_cpufreq_suspend(struct cpufreq_policy *policy) 3404 { 3405 intel_pstate_suspend(policy); 3406 3407 if (hwp_active) { 3408 struct cpudata *cpu = all_cpu_data[policy->cpu]; 3409 u64 value = READ_ONCE(cpu->hwp_req_cached); 3410 3411 /* 3412 * Clear the desired perf field in MSR_HWP_REQUEST in case 3413 * intel_cpufreq_adjust_perf() is in use and the last value 3414 * written by it may not be suitable. 3415 */ 3416 value &= ~HWP_DESIRED_PERF(~0L); 3417 wrmsrq_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 3418 WRITE_ONCE(cpu->hwp_req_cached, value); 3419 } 3420 3421 return 0; 3422 } 3423 3424 static struct cpufreq_driver intel_cpufreq = { 3425 .flags = CPUFREQ_CONST_LOOPS, 3426 .verify = intel_cpufreq_verify_policy, 3427 .target = intel_cpufreq_target, 3428 .fast_switch = intel_cpufreq_fast_switch, 3429 .init = intel_cpufreq_cpu_init, 3430 .exit = intel_cpufreq_cpu_exit, 3431 .offline = intel_cpufreq_cpu_offline, 3432 .online = intel_pstate_cpu_online, 3433 .suspend = intel_cpufreq_suspend, 3434 .resume = intel_pstate_resume, 3435 .update_limits = intel_pstate_update_limits, 3436 .name = "intel_cpufreq", 3437 }; 3438 3439 static struct cpufreq_driver *default_driver; 3440 3441 static void intel_pstate_driver_cleanup(void) 3442 { 3443 unsigned int cpu; 3444 3445 cpus_read_lock(); 3446 for_each_online_cpu(cpu) { 3447 if (all_cpu_data[cpu]) { 3448 if (intel_pstate_driver == &intel_pstate) 3449 intel_pstate_clear_update_util_hook(cpu); 3450 3451 kfree(all_cpu_data[cpu]); 3452 WRITE_ONCE(all_cpu_data[cpu], NULL); 3453 } 3454 } 3455 cpus_read_unlock(); 3456 3457 intel_pstate_driver = NULL; 3458 } 3459 3460 static int intel_pstate_register_driver(struct cpufreq_driver *driver) 3461 { 3462 bool refresh_cpu_cap_scaling; 3463 int ret; 3464 3465 if (driver == &intel_pstate) 3466 intel_pstate_sysfs_expose_hwp_dynamic_boost(); 3467 3468 memset(&global, 0, sizeof(global)); 3469 global.max_perf_pct = 100; 3470 global.turbo_disabled = turbo_is_disabled(); 3471 global.no_turbo = global.turbo_disabled; 3472 3473 arch_set_max_freq_ratio(global.turbo_disabled); 3474 3475 refresh_cpu_cap_scaling = hybrid_clear_max_perf_cpu(); 3476 3477 intel_pstate_driver = driver; 3478 ret = cpufreq_register_driver(intel_pstate_driver); 3479 if (ret) { 3480 intel_pstate_driver_cleanup(); 3481 return ret; 3482 } 3483 3484 global.min_perf_pct = min_perf_pct_min(); 3485 3486 hybrid_init_cpu_capacity_scaling(refresh_cpu_cap_scaling); 3487 3488 return 0; 3489 } 3490 3491 static ssize_t intel_pstate_show_status(char *buf) 3492 { 3493 if (!intel_pstate_driver) 3494 return sprintf(buf, "off\n"); 3495 3496 return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ? 3497 "active" : "passive"); 3498 } 3499 3500 static int intel_pstate_update_status(const char *buf, size_t size) 3501 { 3502 if (size == 3 && !strncmp(buf, "off", size)) { 3503 if (!intel_pstate_driver) 3504 return -EINVAL; 3505 3506 if (hwp_active) 3507 return -EBUSY; 3508 3509 cpufreq_unregister_driver(intel_pstate_driver); 3510 intel_pstate_driver_cleanup(); 3511 return 0; 3512 } 3513 3514 if (size == 6 && !strncmp(buf, "active", size)) { 3515 if (intel_pstate_driver) { 3516 if (intel_pstate_driver == &intel_pstate) 3517 return 0; 3518 3519 cpufreq_unregister_driver(intel_pstate_driver); 3520 } 3521 3522 return intel_pstate_register_driver(&intel_pstate); 3523 } 3524 3525 if (size == 7 && !strncmp(buf, "passive", size)) { 3526 if (intel_pstate_driver) { 3527 if (intel_pstate_driver == &intel_cpufreq) 3528 return 0; 3529 3530 cpufreq_unregister_driver(intel_pstate_driver); 3531 intel_pstate_sysfs_hide_hwp_dynamic_boost(); 3532 } 3533 3534 return intel_pstate_register_driver(&intel_cpufreq); 3535 } 3536 3537 return -EINVAL; 3538 } 3539 3540 static int no_load __initdata; 3541 static int no_hwp __initdata; 3542 static int hwp_only __initdata; 3543 static unsigned int force_load __initdata; 3544 3545 static int __init intel_pstate_msrs_not_valid(void) 3546 { 3547 if (!pstate_funcs.get_max(0) || 3548 !pstate_funcs.get_min(0) || 3549 !pstate_funcs.get_turbo(0)) 3550 return -ENODEV; 3551 3552 return 0; 3553 } 3554 3555 static void __init copy_cpu_funcs(struct pstate_funcs *funcs) 3556 { 3557 pstate_funcs.get_max = funcs->get_max; 3558 pstate_funcs.get_max_physical = funcs->get_max_physical; 3559 pstate_funcs.get_min = funcs->get_min; 3560 pstate_funcs.get_turbo = funcs->get_turbo; 3561 pstate_funcs.get_scaling = funcs->get_scaling; 3562 pstate_funcs.get_val = funcs->get_val; 3563 pstate_funcs.get_vid = funcs->get_vid; 3564 pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift; 3565 } 3566 3567 #ifdef CONFIG_ACPI 3568 3569 static bool __init intel_pstate_no_acpi_pss(void) 3570 { 3571 int i; 3572 3573 for_each_possible_cpu(i) { 3574 acpi_status status; 3575 union acpi_object *pss; 3576 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; 3577 struct acpi_processor *pr = per_cpu(processors, i); 3578 3579 if (!pr) 3580 continue; 3581 3582 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer); 3583 if (ACPI_FAILURE(status)) 3584 continue; 3585 3586 pss = buffer.pointer; 3587 if (pss && pss->type == ACPI_TYPE_PACKAGE) { 3588 kfree(pss); 3589 return false; 3590 } 3591 3592 kfree(pss); 3593 } 3594 3595 pr_debug("ACPI _PSS not found\n"); 3596 return true; 3597 } 3598 3599 static bool __init intel_pstate_no_acpi_pcch(void) 3600 { 3601 acpi_status status; 3602 acpi_handle handle; 3603 3604 status = acpi_get_handle(NULL, "\\_SB", &handle); 3605 if (ACPI_FAILURE(status)) 3606 goto not_found; 3607 3608 if (acpi_has_method(handle, "PCCH")) 3609 return false; 3610 3611 not_found: 3612 pr_debug("ACPI PCCH not found\n"); 3613 return true; 3614 } 3615 3616 static bool __init intel_pstate_has_acpi_ppc(void) 3617 { 3618 int i; 3619 3620 for_each_possible_cpu(i) { 3621 struct acpi_processor *pr = per_cpu(processors, i); 3622 3623 if (!pr) 3624 continue; 3625 if (acpi_has_method(pr->handle, "_PPC")) 3626 return true; 3627 } 3628 pr_debug("ACPI _PPC not found\n"); 3629 return false; 3630 } 3631 3632 enum { 3633 PSS, 3634 PPC, 3635 }; 3636 3637 /* Hardware vendor-specific info that has its own power management modes */ 3638 static struct acpi_platform_list plat_info[] __initdata = { 3639 {"HP ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, NULL, PSS}, 3640 {"ORACLE", "X4-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3641 {"ORACLE", "X4-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3642 {"ORACLE", "X4-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3643 {"ORACLE", "X3-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3644 {"ORACLE", "X3-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3645 {"ORACLE", "X3-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3646 {"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3647 {"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3648 {"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3649 {"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3650 {"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3651 {"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3652 {"ORACLE", "X6-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3653 {"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3654 { } /* End */ 3655 }; 3656 3657 #define BITMASK_OOB (BIT(8) | BIT(18)) 3658 3659 static bool __init intel_pstate_platform_pwr_mgmt_exists(void) 3660 { 3661 const struct x86_cpu_id *id; 3662 u64 misc_pwr; 3663 int idx; 3664 3665 id = x86_match_cpu(intel_pstate_cpu_oob_ids); 3666 if (id) { 3667 rdmsrq(MSR_MISC_PWR_MGMT, misc_pwr); 3668 if (misc_pwr & BITMASK_OOB) { 3669 pr_debug("Bit 8 or 18 in the MISC_PWR_MGMT MSR set\n"); 3670 pr_debug("P states are controlled in Out of Band mode by the firmware/hardware\n"); 3671 return true; 3672 } 3673 } 3674 3675 idx = acpi_match_platform_list(plat_info); 3676 if (idx < 0) 3677 return false; 3678 3679 switch (plat_info[idx].data) { 3680 case PSS: 3681 if (!intel_pstate_no_acpi_pss()) 3682 return false; 3683 3684 return intel_pstate_no_acpi_pcch(); 3685 case PPC: 3686 return intel_pstate_has_acpi_ppc() && !force_load; 3687 } 3688 3689 return false; 3690 } 3691 3692 static void intel_pstate_request_control_from_smm(void) 3693 { 3694 /* 3695 * It may be unsafe to request P-states control from SMM if _PPC support 3696 * has not been enabled. 3697 */ 3698 if (acpi_ppc) 3699 acpi_processor_pstate_control(); 3700 } 3701 #else /* CONFIG_ACPI not enabled */ 3702 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; } 3703 static inline bool intel_pstate_has_acpi_ppc(void) { return false; } 3704 static inline void intel_pstate_request_control_from_smm(void) {} 3705 #endif /* CONFIG_ACPI */ 3706 3707 #define INTEL_PSTATE_HWP_BROADWELL 0x01 3708 3709 #define X86_MATCH_HWP(vfm, hwp_mode) \ 3710 X86_MATCH_VFM_FEATURE(vfm, X86_FEATURE_HWP, hwp_mode) 3711 3712 static const struct x86_cpu_id hwp_support_ids[] __initconst = { 3713 X86_MATCH_HWP(INTEL_BROADWELL_X, INTEL_PSTATE_HWP_BROADWELL), 3714 X86_MATCH_HWP(INTEL_BROADWELL_D, INTEL_PSTATE_HWP_BROADWELL), 3715 X86_MATCH_HWP(INTEL_ANY, 0), 3716 {} 3717 }; 3718 3719 static bool intel_pstate_hwp_is_enabled(void) 3720 { 3721 u64 value; 3722 3723 rdmsrq(MSR_PM_ENABLE, value); 3724 return !!(value & 0x1); 3725 } 3726 3727 #define POWERSAVE_MASK GENMASK(7, 0) 3728 #define BALANCE_POWER_MASK GENMASK(15, 8) 3729 #define BALANCE_PERFORMANCE_MASK GENMASK(23, 16) 3730 #define PERFORMANCE_MASK GENMASK(31, 24) 3731 3732 #define HWP_SET_EPP_VALUES(powersave, balance_power, balance_perf, performance) \ 3733 (FIELD_PREP_CONST(POWERSAVE_MASK, powersave) |\ 3734 FIELD_PREP_CONST(BALANCE_POWER_MASK, balance_power) |\ 3735 FIELD_PREP_CONST(BALANCE_PERFORMANCE_MASK, balance_perf) |\ 3736 FIELD_PREP_CONST(PERFORMANCE_MASK, performance)) 3737 3738 #define HWP_SET_DEF_BALANCE_PERF_EPP(balance_perf) \ 3739 (HWP_SET_EPP_VALUES(HWP_EPP_POWERSAVE, HWP_EPP_BALANCE_POWERSAVE,\ 3740 balance_perf, HWP_EPP_PERFORMANCE)) 3741 3742 static const struct x86_cpu_id intel_epp_default[] = { 3743 /* 3744 * Set EPP value as 102, this is the max suggested EPP 3745 * which can result in one core turbo frequency for 3746 * AlderLake Mobile CPUs. 3747 */ 3748 X86_MATCH_VFM(INTEL_ALDERLAKE_L, HWP_SET_DEF_BALANCE_PERF_EPP(102)), 3749 X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, HWP_SET_DEF_BALANCE_PERF_EPP(32)), 3750 X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, HWP_SET_DEF_BALANCE_PERF_EPP(32)), 3751 X86_MATCH_VFM(INTEL_GRANITERAPIDS_X, HWP_SET_DEF_BALANCE_PERF_EPP(32)), 3752 X86_MATCH_VFM(INTEL_GRANITERAPIDS_D, HWP_SET_DEF_BALANCE_PERF_EPP(32)), 3753 X86_MATCH_VFM(INTEL_METEORLAKE_L, HWP_SET_EPP_VALUES(HWP_EPP_POWERSAVE, 3754 179, 64, 16)), 3755 X86_MATCH_VFM(INTEL_ARROWLAKE, HWP_SET_EPP_VALUES(HWP_EPP_POWERSAVE, 3756 179, 64, 16)), 3757 {} 3758 }; 3759 3760 static const struct x86_cpu_id intel_hybrid_scaling_factor[] = { 3761 X86_MATCH_VFM(INTEL_ALDERLAKE, HYBRID_SCALING_FACTOR_ADL), 3762 X86_MATCH_VFM(INTEL_ALDERLAKE_L, HYBRID_SCALING_FACTOR_ADL), 3763 X86_MATCH_VFM(INTEL_RAPTORLAKE, HYBRID_SCALING_FACTOR_ADL), 3764 X86_MATCH_VFM(INTEL_RAPTORLAKE_P, HYBRID_SCALING_FACTOR_ADL), 3765 X86_MATCH_VFM(INTEL_RAPTORLAKE_S, HYBRID_SCALING_FACTOR_ADL), 3766 X86_MATCH_VFM(INTEL_METEORLAKE_L, HYBRID_SCALING_FACTOR_MTL), 3767 X86_MATCH_VFM(INTEL_LUNARLAKE_M, HYBRID_SCALING_FACTOR_LNL), 3768 {} 3769 }; 3770 3771 static bool hwp_check_epp(void) 3772 { 3773 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) 3774 return true; 3775 3776 /* Without EPP support, don't expose EPP-related sysfs attributes. */ 3777 hwp_cpufreq_attrs[HWP_PERFORMANCE_PREFERENCE_INDEX] = NULL; 3778 hwp_cpufreq_attrs[HWP_PERFORMANCE_AVAILABLE_PREFERENCES_INDEX] = NULL; 3779 3780 return false; 3781 } 3782 3783 static bool hwp_check_dec(void) 3784 { 3785 u64 power_ctl; 3786 3787 rdmsrq(MSR_IA32_POWER_CTL, power_ctl); 3788 return !!(power_ctl & BIT(POWER_CTL_DEC_ENABLE)); 3789 } 3790 3791 static int __init intel_pstate_init(void) 3792 { 3793 static struct cpudata **_all_cpu_data; 3794 const struct x86_cpu_id *id; 3795 int rc; 3796 3797 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) 3798 return -ENODEV; 3799 3800 /* 3801 * The Intel pstate driver will be ignored if the platform 3802 * firmware has its own power management modes. 3803 */ 3804 if (intel_pstate_platform_pwr_mgmt_exists()) { 3805 pr_info("P-states controlled by the platform\n"); 3806 return -ENODEV; 3807 } 3808 3809 id = x86_match_cpu(hwp_support_ids); 3810 if (id) { 3811 bool epp_present = hwp_check_epp(); 3812 3813 /* 3814 * If HWP is enabled already, there is no choice but to deal 3815 * with it. 3816 */ 3817 hwp_forced = intel_pstate_hwp_is_enabled(); 3818 if (hwp_forced) { 3819 pr_info("HWP enabled by BIOS\n"); 3820 no_hwp = 0; 3821 } else if (no_load) { 3822 return -ENODEV; 3823 } else if (!epp_present && !hwp_check_dec()) { 3824 /* 3825 * Avoid enabling HWP for processors without EPP support 3826 * unless the Dynamic Efficiency Control (DEC) enable 3827 * bit (MSR_IA32_POWER_CTL, bit 27) is set because that 3828 * means incomplete HWP implementation which is a corner 3829 * case and supporting it is generally problematic. 3830 */ 3831 no_hwp = 1; 3832 } 3833 3834 copy_cpu_funcs(&core_funcs); 3835 3836 if (!no_hwp) { 3837 hwp_active = true; 3838 hwp_mode_bdw = id->driver_data; 3839 intel_pstate.attr = hwp_cpufreq_attrs; 3840 intel_cpufreq.attr = hwp_cpufreq_attrs; 3841 intel_cpufreq.flags |= CPUFREQ_NEED_UPDATE_LIMITS; 3842 intel_cpufreq.adjust_perf = intel_cpufreq_adjust_perf; 3843 if (!default_driver) 3844 default_driver = &intel_pstate; 3845 3846 pstate_funcs.get_cpu_scaling = hwp_get_cpu_scaling; 3847 3848 goto hwp_cpu_matched; 3849 } 3850 pr_info("HWP not enabled\n"); 3851 } else { 3852 if (no_load) 3853 return -ENODEV; 3854 3855 id = x86_match_cpu(intel_pstate_cpu_ids); 3856 if (!id) { 3857 pr_info("CPU model not supported\n"); 3858 return -ENODEV; 3859 } 3860 3861 copy_cpu_funcs((struct pstate_funcs *)id->driver_data); 3862 } 3863 3864 if (intel_pstate_msrs_not_valid()) { 3865 pr_info("Invalid MSRs\n"); 3866 return -ENODEV; 3867 } 3868 /* Without HWP start in the passive mode. */ 3869 if (!default_driver) 3870 default_driver = &intel_cpufreq; 3871 3872 hwp_cpu_matched: 3873 if (!hwp_active && hwp_only) 3874 return -ENOTSUPP; 3875 3876 pr_info("Intel P-state driver initializing\n"); 3877 3878 _all_cpu_data = vzalloc(array_size(sizeof(void *), num_possible_cpus())); 3879 if (!_all_cpu_data) 3880 return -ENOMEM; 3881 3882 WRITE_ONCE(all_cpu_data, _all_cpu_data); 3883 3884 intel_pstate_request_control_from_smm(); 3885 3886 intel_pstate_sysfs_expose_params(); 3887 3888 if (hwp_active) { 3889 const struct x86_cpu_id *id = x86_match_cpu(intel_epp_default); 3890 const struct x86_cpu_id *hybrid_id = x86_match_cpu(intel_hybrid_scaling_factor); 3891 3892 if (id) { 3893 epp_values[EPP_INDEX_POWERSAVE] = 3894 FIELD_GET(POWERSAVE_MASK, id->driver_data); 3895 epp_values[EPP_INDEX_BALANCE_POWERSAVE] = 3896 FIELD_GET(BALANCE_POWER_MASK, id->driver_data); 3897 epp_values[EPP_INDEX_BALANCE_PERFORMANCE] = 3898 FIELD_GET(BALANCE_PERFORMANCE_MASK, id->driver_data); 3899 epp_values[EPP_INDEX_PERFORMANCE] = 3900 FIELD_GET(PERFORMANCE_MASK, id->driver_data); 3901 pr_debug("Updated EPPs powersave:%x balanced power:%x balanced perf:%x performance:%x\n", 3902 epp_values[EPP_INDEX_POWERSAVE], 3903 epp_values[EPP_INDEX_BALANCE_POWERSAVE], 3904 epp_values[EPP_INDEX_BALANCE_PERFORMANCE], 3905 epp_values[EPP_INDEX_PERFORMANCE]); 3906 } 3907 3908 if (hybrid_id) { 3909 hybrid_scaling_factor = hybrid_id->driver_data; 3910 pr_debug("hybrid scaling factor: %d\n", hybrid_scaling_factor); 3911 } 3912 3913 } 3914 3915 mutex_lock(&intel_pstate_driver_lock); 3916 rc = intel_pstate_register_driver(default_driver); 3917 mutex_unlock(&intel_pstate_driver_lock); 3918 if (rc) { 3919 intel_pstate_sysfs_remove(); 3920 return rc; 3921 } 3922 3923 if (hwp_active) { 3924 const struct x86_cpu_id *id; 3925 3926 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids); 3927 if (id) { 3928 set_power_ctl_ee_state(false); 3929 pr_info("Disabling energy efficiency optimization\n"); 3930 } 3931 3932 pr_info("HWP enabled\n"); 3933 } else if (boot_cpu_has(X86_FEATURE_HYBRID_CPU)) { 3934 pr_warn("Problematic setup: Hybrid processor with disabled HWP\n"); 3935 } 3936 3937 return 0; 3938 } 3939 device_initcall(intel_pstate_init); 3940 3941 static int __init intel_pstate_setup(char *str) 3942 { 3943 if (!str) 3944 return -EINVAL; 3945 3946 if (!strcmp(str, "disable")) 3947 no_load = 1; 3948 else if (!strcmp(str, "active")) 3949 default_driver = &intel_pstate; 3950 else if (!strcmp(str, "passive")) 3951 default_driver = &intel_cpufreq; 3952 3953 if (!strcmp(str, "no_hwp")) 3954 no_hwp = 1; 3955 3956 if (!strcmp(str, "no_cas")) 3957 no_cas = true; 3958 3959 if (!strcmp(str, "force")) 3960 force_load = 1; 3961 if (!strcmp(str, "hwp_only")) 3962 hwp_only = 1; 3963 if (!strcmp(str, "per_cpu_perf_limits")) 3964 per_cpu_limits = true; 3965 3966 #ifdef CONFIG_ACPI 3967 if (!strcmp(str, "support_acpi_ppc")) 3968 acpi_ppc = true; 3969 #endif 3970 3971 return 0; 3972 } 3973 early_param("intel_pstate", intel_pstate_setup); 3974 3975 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>"); 3976 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors"); 3977