1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * intel_pstate.c: Native P state management for Intel processors 4 * 5 * (C) Copyright 2012 Intel Corporation 6 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com> 7 */ 8 9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10 11 #include <linux/kernel.h> 12 #include <linux/kernel_stat.h> 13 #include <linux/module.h> 14 #include <linux/ktime.h> 15 #include <linux/hrtimer.h> 16 #include <linux/tick.h> 17 #include <linux/slab.h> 18 #include <linux/sched/cpufreq.h> 19 #include <linux/sched/smt.h> 20 #include <linux/list.h> 21 #include <linux/cpu.h> 22 #include <linux/cpufreq.h> 23 #include <linux/sysfs.h> 24 #include <linux/types.h> 25 #include <linux/fs.h> 26 #include <linux/acpi.h> 27 #include <linux/vmalloc.h> 28 #include <linux/pm_qos.h> 29 #include <linux/bitfield.h> 30 #include <trace/events/power.h> 31 #include <linux/units.h> 32 33 #include <asm/cpu.h> 34 #include <asm/div64.h> 35 #include <asm/msr.h> 36 #include <asm/cpu_device_id.h> 37 #include <asm/cpufeature.h> 38 #include <asm/intel-family.h> 39 #include "../drivers/thermal/intel/thermal_interrupt.h" 40 41 #define INTEL_PSTATE_SAMPLING_INTERVAL (10 * NSEC_PER_MSEC) 42 43 #define INTEL_CPUFREQ_TRANSITION_LATENCY 20000 44 #define INTEL_CPUFREQ_TRANSITION_DELAY_HWP 5000 45 #define INTEL_CPUFREQ_TRANSITION_DELAY 500 46 47 #ifdef CONFIG_ACPI 48 #include <acpi/processor.h> 49 #include <acpi/cppc_acpi.h> 50 #endif 51 52 #define FRAC_BITS 8 53 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS) 54 #define fp_toint(X) ((X) >> FRAC_BITS) 55 56 #define ONE_EIGHTH_FP ((int64_t)1 << (FRAC_BITS - 3)) 57 58 #define EXT_BITS 6 59 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS) 60 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS) 61 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS) 62 63 static inline int32_t mul_fp(int32_t x, int32_t y) 64 { 65 return ((int64_t)x * (int64_t)y) >> FRAC_BITS; 66 } 67 68 static inline int32_t div_fp(s64 x, s64 y) 69 { 70 return div64_s64((int64_t)x << FRAC_BITS, y); 71 } 72 73 static inline int ceiling_fp(int32_t x) 74 { 75 int mask, ret; 76 77 ret = fp_toint(x); 78 mask = (1 << FRAC_BITS) - 1; 79 if (x & mask) 80 ret += 1; 81 return ret; 82 } 83 84 static inline u64 mul_ext_fp(u64 x, u64 y) 85 { 86 return (x * y) >> EXT_FRAC_BITS; 87 } 88 89 static inline u64 div_ext_fp(u64 x, u64 y) 90 { 91 return div64_u64(x << EXT_FRAC_BITS, y); 92 } 93 94 /** 95 * struct sample - Store performance sample 96 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average 97 * performance during last sample period 98 * @busy_scaled: Scaled busy value which is used to calculate next 99 * P state. This can be different than core_avg_perf 100 * to account for cpu idle period 101 * @aperf: Difference of actual performance frequency clock count 102 * read from APERF MSR between last and current sample 103 * @mperf: Difference of maximum performance frequency clock count 104 * read from MPERF MSR between last and current sample 105 * @tsc: Difference of time stamp counter between last and 106 * current sample 107 * @time: Current time from scheduler 108 * 109 * This structure is used in the cpudata structure to store performance sample 110 * data for choosing next P State. 111 */ 112 struct sample { 113 int32_t core_avg_perf; 114 int32_t busy_scaled; 115 u64 aperf; 116 u64 mperf; 117 u64 tsc; 118 u64 time; 119 }; 120 121 /** 122 * struct pstate_data - Store P state data 123 * @current_pstate: Current requested P state 124 * @min_pstate: Min P state possible for this platform 125 * @max_pstate: Max P state possible for this platform 126 * @max_pstate_physical:This is physical Max P state for a processor 127 * This can be higher than the max_pstate which can 128 * be limited by platform thermal design power limits 129 * @perf_ctl_scaling: PERF_CTL P-state to frequency scaling factor 130 * @scaling: Scaling factor between performance and frequency 131 * @turbo_pstate: Max Turbo P state possible for this platform 132 * @min_freq: @min_pstate frequency in cpufreq units 133 * @max_freq: @max_pstate frequency in cpufreq units 134 * @turbo_freq: @turbo_pstate frequency in cpufreq units 135 * 136 * Stores the per cpu model P state limits and current P state. 137 */ 138 struct pstate_data { 139 int current_pstate; 140 int min_pstate; 141 int max_pstate; 142 int max_pstate_physical; 143 int perf_ctl_scaling; 144 int scaling; 145 int turbo_pstate; 146 unsigned int min_freq; 147 unsigned int max_freq; 148 unsigned int turbo_freq; 149 }; 150 151 /** 152 * struct vid_data - Stores voltage information data 153 * @min: VID data for this platform corresponding to 154 * the lowest P state 155 * @max: VID data corresponding to the highest P State. 156 * @turbo: VID data for turbo P state 157 * @ratio: Ratio of (vid max - vid min) / 158 * (max P state - Min P State) 159 * 160 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling) 161 * This data is used in Atom platforms, where in addition to target P state, 162 * the voltage data needs to be specified to select next P State. 163 */ 164 struct vid_data { 165 int min; 166 int max; 167 int turbo; 168 int32_t ratio; 169 }; 170 171 /** 172 * struct global_params - Global parameters, mostly tunable via sysfs. 173 * @no_turbo: Whether or not to use turbo P-states. 174 * @turbo_disabled: Whether or not turbo P-states are available at all, 175 * based on the MSR_IA32_MISC_ENABLE value and whether or 176 * not the maximum reported turbo P-state is different from 177 * the maximum reported non-turbo one. 178 * @min_perf_pct: Minimum capacity limit in percent of the maximum turbo 179 * P-state capacity. 180 * @max_perf_pct: Maximum capacity limit in percent of the maximum turbo 181 * P-state capacity. 182 */ 183 struct global_params { 184 bool no_turbo; 185 bool turbo_disabled; 186 int max_perf_pct; 187 int min_perf_pct; 188 }; 189 190 /** 191 * struct cpudata - Per CPU instance data storage 192 * @cpu: CPU number for this instance data 193 * @policy: CPUFreq policy value 194 * @update_util: CPUFreq utility callback information 195 * @update_util_set: CPUFreq utility callback is set 196 * @iowait_boost: iowait-related boost fraction 197 * @last_update: Time of the last update. 198 * @pstate: Stores P state limits for this CPU 199 * @vid: Stores VID limits for this CPU 200 * @last_sample_time: Last Sample time 201 * @aperf_mperf_shift: APERF vs MPERF counting frequency difference 202 * @prev_aperf: Last APERF value read from APERF MSR 203 * @prev_mperf: Last MPERF value read from MPERF MSR 204 * @prev_tsc: Last timestamp counter (TSC) value 205 * @sample: Storage for storing last Sample data 206 * @min_perf_ratio: Minimum capacity in terms of PERF or HWP ratios 207 * @max_perf_ratio: Maximum capacity in terms of PERF or HWP ratios 208 * @acpi_perf_data: Stores ACPI perf information read from _PSS 209 * @valid_pss_table: Set to true for valid ACPI _PSS entries found 210 * @epp_powersave: Last saved HWP energy performance preference 211 * (EPP) or energy performance bias (EPB), 212 * when policy switched to performance 213 * @epp_policy: Last saved policy used to set EPP/EPB 214 * @epp_default: Power on default HWP energy performance 215 * preference/bias 216 * @epp_cached: Cached HWP energy-performance preference value 217 * @hwp_req_cached: Cached value of the last HWP Request MSR 218 * @hwp_cap_cached: Cached value of the last HWP Capabilities MSR 219 * @last_io_update: Last time when IO wake flag was set 220 * @capacity_perf: Highest perf used for scale invariance 221 * @sched_flags: Store scheduler flags for possible cross CPU update 222 * @hwp_boost_min: Last HWP boosted min performance 223 * @suspended: Whether or not the driver has been suspended. 224 * @pd_registered: Set when a perf domain is registered for this CPU. 225 * @hwp_notify_work: workqueue for HWP notifications. 226 * 227 * This structure stores per CPU instance data for all CPUs. 228 */ 229 struct cpudata { 230 int cpu; 231 232 unsigned int policy; 233 struct update_util_data update_util; 234 bool update_util_set; 235 236 struct pstate_data pstate; 237 struct vid_data vid; 238 239 u64 last_update; 240 u64 last_sample_time; 241 u64 aperf_mperf_shift; 242 u64 prev_aperf; 243 u64 prev_mperf; 244 u64 prev_tsc; 245 struct sample sample; 246 int32_t min_perf_ratio; 247 int32_t max_perf_ratio; 248 #ifdef CONFIG_ACPI 249 struct acpi_processor_performance acpi_perf_data; 250 bool valid_pss_table; 251 #endif 252 unsigned int iowait_boost; 253 s16 epp_powersave; 254 s16 epp_policy; 255 s16 epp_default; 256 s16 epp_cached; 257 u64 hwp_req_cached; 258 u64 hwp_cap_cached; 259 u64 last_io_update; 260 unsigned int capacity_perf; 261 unsigned int sched_flags; 262 u32 hwp_boost_min; 263 bool suspended; 264 #ifdef CONFIG_ENERGY_MODEL 265 bool pd_registered; 266 #endif 267 struct delayed_work hwp_notify_work; 268 }; 269 270 static struct cpudata **all_cpu_data; 271 272 /** 273 * struct pstate_funcs - Per CPU model specific callbacks 274 * @get_max: Callback to get maximum non turbo effective P state 275 * @get_max_physical: Callback to get maximum non turbo physical P state 276 * @get_min: Callback to get minimum P state 277 * @get_turbo: Callback to get turbo P state 278 * @get_scaling: Callback to get frequency scaling factor 279 * @get_cpu_scaling: Get frequency scaling factor for a given cpu 280 * @get_aperf_mperf_shift: Callback to get the APERF vs MPERF frequency difference 281 * @get_val: Callback to convert P state to actual MSR write value 282 * @get_vid: Callback to get VID data for Atom platforms 283 * 284 * Core and Atom CPU models have different way to get P State limits. This 285 * structure is used to store those callbacks. 286 */ 287 struct pstate_funcs { 288 int (*get_max)(int cpu); 289 int (*get_max_physical)(int cpu); 290 int (*get_min)(int cpu); 291 int (*get_turbo)(int cpu); 292 int (*get_scaling)(void); 293 int (*get_cpu_scaling)(int cpu); 294 int (*get_aperf_mperf_shift)(void); 295 u64 (*get_val)(struct cpudata*, int pstate); 296 void (*get_vid)(struct cpudata *); 297 }; 298 299 static struct pstate_funcs pstate_funcs __read_mostly; 300 301 static bool hwp_active __ro_after_init; 302 static bool per_cpu_limits __ro_after_init; 303 static bool hwp_forced __ro_after_init; 304 static bool hwp_boost __read_mostly; 305 static bool hwp_is_hybrid; 306 static u32 hwp_desired_mask __read_mostly = ~0U; 307 308 static struct cpufreq_driver *intel_pstate_driver __read_mostly; 309 310 #define INTEL_PSTATE_CORE_SCALING 100000 311 #define HYBRID_SCALING_FACTOR_ADL 78741 312 #define HYBRID_SCALING_FACTOR_MTL 80000 313 #define HYBRID_SCALING_FACTOR_LNL 86957 314 315 static int hybrid_scaling_factor; 316 317 static inline int core_get_scaling(void) 318 { 319 return INTEL_PSTATE_CORE_SCALING; 320 } 321 322 #ifdef CONFIG_ACPI 323 static bool acpi_ppc; 324 #endif 325 326 static struct global_params global; 327 328 static DEFINE_MUTEX(intel_pstate_driver_lock); 329 static DEFINE_MUTEX(intel_pstate_limits_lock); 330 331 #ifdef CONFIG_ACPI 332 333 static bool intel_pstate_acpi_pm_profile_server(void) 334 { 335 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER || 336 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER) 337 return true; 338 339 return false; 340 } 341 342 static bool intel_pstate_get_ppc_enable_status(void) 343 { 344 if (intel_pstate_acpi_pm_profile_server()) 345 return true; 346 347 return acpi_ppc; 348 } 349 350 #ifdef CONFIG_ACPI_CPPC_LIB 351 352 /* The work item is needed to avoid CPU hotplug locking issues */ 353 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work) 354 { 355 sched_set_itmt_support(); 356 } 357 358 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn); 359 360 #define CPPC_MAX_PERF U8_MAX 361 362 static void intel_pstate_set_itmt_prio(int cpu) 363 { 364 struct cppc_perf_caps cppc_perf; 365 static u32 max_highest_perf = 0, min_highest_perf = U32_MAX; 366 int ret; 367 368 ret = cppc_get_perf_caps(cpu, &cppc_perf); 369 /* 370 * If CPPC is not available, fall back to MSR_HWP_CAPABILITIES bits [8:0]. 371 * 372 * Also, on some systems with overclocking enabled, CPPC.highest_perf is 373 * hardcoded to 0xff, so CPPC.highest_perf cannot be used to enable ITMT. 374 * Fall back to MSR_HWP_CAPABILITIES then too. 375 */ 376 if (ret || cppc_perf.highest_perf == CPPC_MAX_PERF) 377 cppc_perf.highest_perf = HWP_HIGHEST_PERF(READ_ONCE(all_cpu_data[cpu]->hwp_cap_cached)); 378 379 /* 380 * The priorities can be set regardless of whether or not 381 * sched_set_itmt_support(true) has been called and it is valid to 382 * update them at any time after it has been called. 383 */ 384 sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu); 385 386 if (max_highest_perf <= min_highest_perf) { 387 if (cppc_perf.highest_perf > max_highest_perf) 388 max_highest_perf = cppc_perf.highest_perf; 389 390 if (cppc_perf.highest_perf < min_highest_perf) 391 min_highest_perf = cppc_perf.highest_perf; 392 393 if (max_highest_perf > min_highest_perf) { 394 /* 395 * This code can be run during CPU online under the 396 * CPU hotplug locks, so sched_set_itmt_support() 397 * cannot be called from here. Queue up a work item 398 * to invoke it. 399 */ 400 schedule_work(&sched_itmt_work); 401 } 402 } 403 } 404 405 static int intel_pstate_get_cppc_guaranteed(int cpu) 406 { 407 struct cppc_perf_caps cppc_perf; 408 int ret; 409 410 ret = cppc_get_perf_caps(cpu, &cppc_perf); 411 if (ret) 412 return ret; 413 414 if (cppc_perf.guaranteed_perf) 415 return cppc_perf.guaranteed_perf; 416 417 return cppc_perf.nominal_perf; 418 } 419 420 static int intel_pstate_cppc_get_scaling(int cpu) 421 { 422 struct cppc_perf_caps cppc_perf; 423 424 /* 425 * Compute the perf-to-frequency scaling factor for the given CPU if 426 * possible, unless it would be 0. 427 */ 428 if (!cppc_get_perf_caps(cpu, &cppc_perf) && 429 cppc_perf.nominal_perf && cppc_perf.nominal_freq) 430 return div_u64(cppc_perf.nominal_freq * KHZ_PER_MHZ, 431 cppc_perf.nominal_perf); 432 433 return core_get_scaling(); 434 } 435 436 #else /* CONFIG_ACPI_CPPC_LIB */ 437 static inline void intel_pstate_set_itmt_prio(int cpu) 438 { 439 } 440 #endif /* CONFIG_ACPI_CPPC_LIB */ 441 442 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) 443 { 444 struct cpudata *cpu; 445 int ret; 446 int i; 447 448 if (hwp_active) { 449 intel_pstate_set_itmt_prio(policy->cpu); 450 return; 451 } 452 453 if (!intel_pstate_get_ppc_enable_status()) 454 return; 455 456 cpu = all_cpu_data[policy->cpu]; 457 458 ret = acpi_processor_register_performance(&cpu->acpi_perf_data, 459 policy->cpu); 460 if (ret) 461 return; 462 463 /* 464 * Check if the control value in _PSS is for PERF_CTL MSR, which should 465 * guarantee that the states returned by it map to the states in our 466 * list directly. 467 */ 468 if (cpu->acpi_perf_data.control_register.space_id != 469 ACPI_ADR_SPACE_FIXED_HARDWARE) 470 goto err; 471 472 /* 473 * If there is only one entry _PSS, simply ignore _PSS and continue as 474 * usual without taking _PSS into account 475 */ 476 if (cpu->acpi_perf_data.state_count < 2) 477 goto err; 478 479 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu); 480 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) { 481 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n", 482 (i == cpu->acpi_perf_data.state ? '*' : ' '), i, 483 (u32) cpu->acpi_perf_data.states[i].core_frequency, 484 (u32) cpu->acpi_perf_data.states[i].power, 485 (u32) cpu->acpi_perf_data.states[i].control); 486 } 487 488 cpu->valid_pss_table = true; 489 pr_debug("_PPC limits will be enforced\n"); 490 491 return; 492 493 err: 494 cpu->valid_pss_table = false; 495 acpi_processor_unregister_performance(policy->cpu); 496 } 497 498 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) 499 { 500 struct cpudata *cpu; 501 502 cpu = all_cpu_data[policy->cpu]; 503 if (!cpu->valid_pss_table) 504 return; 505 506 acpi_processor_unregister_performance(policy->cpu); 507 } 508 #else /* CONFIG_ACPI */ 509 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) 510 { 511 } 512 513 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) 514 { 515 } 516 517 static inline bool intel_pstate_acpi_pm_profile_server(void) 518 { 519 return false; 520 } 521 #endif /* CONFIG_ACPI */ 522 523 #ifndef CONFIG_ACPI_CPPC_LIB 524 static inline int intel_pstate_get_cppc_guaranteed(int cpu) 525 { 526 return -ENOTSUPP; 527 } 528 529 static int intel_pstate_cppc_get_scaling(int cpu) 530 { 531 return core_get_scaling(); 532 } 533 #endif /* CONFIG_ACPI_CPPC_LIB */ 534 535 static int intel_pstate_freq_to_hwp_rel(struct cpudata *cpu, int freq, 536 unsigned int relation) 537 { 538 if (freq == cpu->pstate.turbo_freq) 539 return cpu->pstate.turbo_pstate; 540 541 if (freq == cpu->pstate.max_freq) 542 return cpu->pstate.max_pstate; 543 544 switch (relation) { 545 case CPUFREQ_RELATION_H: 546 return freq / cpu->pstate.scaling; 547 case CPUFREQ_RELATION_C: 548 return DIV_ROUND_CLOSEST(freq, cpu->pstate.scaling); 549 } 550 551 return DIV_ROUND_UP(freq, cpu->pstate.scaling); 552 } 553 554 static int intel_pstate_freq_to_hwp(struct cpudata *cpu, int freq) 555 { 556 return intel_pstate_freq_to_hwp_rel(cpu, freq, CPUFREQ_RELATION_L); 557 } 558 559 static bool turbo_is_disabled(void) 560 { 561 u64 misc_en; 562 563 rdmsrq(MSR_IA32_MISC_ENABLE, misc_en); 564 565 return !!(misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE); 566 } 567 568 static int min_perf_pct_min(void) 569 { 570 struct cpudata *cpu = all_cpu_data[0]; 571 int turbo_pstate = cpu->pstate.turbo_pstate; 572 573 return turbo_pstate ? 574 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0; 575 } 576 577 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data) 578 { 579 s16 epp = -EOPNOTSUPP; 580 581 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 582 /* 583 * When hwp_req_data is 0, means that caller didn't read 584 * MSR_HWP_REQUEST, so need to read and get EPP. 585 */ 586 if (!hwp_req_data) { 587 epp = rdmsrq_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, 588 &hwp_req_data); 589 if (epp) 590 return epp; 591 } 592 epp = (hwp_req_data >> 24) & 0xff; 593 } 594 595 return epp; 596 } 597 598 /* 599 * EPP display strings corresponding to EPP index in the 600 * energy_perf_strings[] 601 * index String 602 *------------------------------------- 603 * 0 default 604 * 1 performance 605 * 2 balance_performance 606 * 3 balance_power 607 * 4 power 608 */ 609 610 enum energy_perf_value_index { 611 EPP_INDEX_DEFAULT = 0, 612 EPP_INDEX_PERFORMANCE, 613 EPP_INDEX_BALANCE_PERFORMANCE, 614 EPP_INDEX_BALANCE_POWERSAVE, 615 EPP_INDEX_POWERSAVE, 616 }; 617 618 static const char * const energy_perf_strings[] = { 619 [EPP_INDEX_DEFAULT] = "default", 620 [EPP_INDEX_PERFORMANCE] = "performance", 621 [EPP_INDEX_BALANCE_PERFORMANCE] = "balance_performance", 622 [EPP_INDEX_BALANCE_POWERSAVE] = "balance_power", 623 [EPP_INDEX_POWERSAVE] = "power", 624 NULL 625 }; 626 static unsigned int epp_values[] = { 627 [EPP_INDEX_DEFAULT] = 0, /* Unused index */ 628 [EPP_INDEX_PERFORMANCE] = HWP_EPP_PERFORMANCE, 629 [EPP_INDEX_BALANCE_PERFORMANCE] = HWP_EPP_BALANCE_PERFORMANCE, 630 [EPP_INDEX_BALANCE_POWERSAVE] = HWP_EPP_BALANCE_POWERSAVE, 631 [EPP_INDEX_POWERSAVE] = HWP_EPP_POWERSAVE, 632 }; 633 634 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data, int *raw_epp) 635 { 636 s16 epp; 637 int index = -EINVAL; 638 639 *raw_epp = 0; 640 epp = intel_pstate_get_epp(cpu_data, 0); 641 if (epp < 0) 642 return epp; 643 644 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 645 if (epp == epp_values[EPP_INDEX_PERFORMANCE]) 646 return EPP_INDEX_PERFORMANCE; 647 if (epp == epp_values[EPP_INDEX_BALANCE_PERFORMANCE]) 648 return EPP_INDEX_BALANCE_PERFORMANCE; 649 if (epp == epp_values[EPP_INDEX_BALANCE_POWERSAVE]) 650 return EPP_INDEX_BALANCE_POWERSAVE; 651 if (epp == epp_values[EPP_INDEX_POWERSAVE]) 652 return EPP_INDEX_POWERSAVE; 653 *raw_epp = epp; 654 return 0; 655 } else if (boot_cpu_has(X86_FEATURE_EPB)) { 656 /* 657 * Range: 658 * 0x00-0x03 : Performance 659 * 0x04-0x07 : Balance performance 660 * 0x08-0x0B : Balance power 661 * 0x0C-0x0F : Power 662 * The EPB is a 4 bit value, but our ranges restrict the 663 * value which can be set. Here only using top two bits 664 * effectively. 665 */ 666 index = (epp >> 2) + 1; 667 } 668 669 return index; 670 } 671 672 static int intel_pstate_set_epp(struct cpudata *cpu, u32 epp) 673 { 674 int ret; 675 676 /* 677 * Use the cached HWP Request MSR value, because in the active mode the 678 * register itself may be updated by intel_pstate_hwp_boost_up() or 679 * intel_pstate_hwp_boost_down() at any time. 680 */ 681 u64 value = READ_ONCE(cpu->hwp_req_cached); 682 683 value &= ~GENMASK_ULL(31, 24); 684 value |= (u64)epp << 24; 685 /* 686 * The only other updater of hwp_req_cached in the active mode, 687 * intel_pstate_hwp_set(), is called under the same lock as this 688 * function, so it cannot run in parallel with the update below. 689 */ 690 WRITE_ONCE(cpu->hwp_req_cached, value); 691 ret = wrmsrq_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 692 if (!ret) 693 cpu->epp_cached = epp; 694 695 return ret; 696 } 697 698 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data, 699 int pref_index, bool use_raw, 700 u32 raw_epp) 701 { 702 int epp = -EINVAL; 703 int ret = -EOPNOTSUPP; 704 705 if (!pref_index) 706 epp = cpu_data->epp_default; 707 708 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 709 if (use_raw) 710 epp = raw_epp; 711 else if (epp == -EINVAL) 712 epp = epp_values[pref_index]; 713 714 /* 715 * To avoid confusion, refuse to set EPP to any values different 716 * from 0 (performance) if the current policy is "performance", 717 * because those values would be overridden. 718 */ 719 if (epp > 0 && cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) 720 return -EBUSY; 721 722 ret = intel_pstate_set_epp(cpu_data, epp); 723 } 724 725 return ret; 726 } 727 728 static ssize_t show_energy_performance_available_preferences( 729 struct cpufreq_policy *policy, char *buf) 730 { 731 int i = 0; 732 int ret = 0; 733 734 while (energy_perf_strings[i] != NULL) 735 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]); 736 737 ret += sprintf(&buf[ret], "\n"); 738 739 return ret; 740 } 741 742 cpufreq_freq_attr_ro(energy_performance_available_preferences); 743 744 static struct cpufreq_driver intel_pstate; 745 746 static ssize_t store_energy_performance_preference( 747 struct cpufreq_policy *policy, const char *buf, size_t count) 748 { 749 struct cpudata *cpu = all_cpu_data[policy->cpu]; 750 char str_preference[21]; 751 bool raw = false; 752 ssize_t ret; 753 u32 epp = 0; 754 755 ret = sscanf(buf, "%20s", str_preference); 756 if (ret != 1) 757 return -EINVAL; 758 759 ret = match_string(energy_perf_strings, -1, str_preference); 760 if (ret < 0) { 761 if (!boot_cpu_has(X86_FEATURE_HWP_EPP)) 762 return ret; 763 764 ret = kstrtouint(buf, 10, &epp); 765 if (ret) 766 return ret; 767 768 if (epp > 255) 769 return -EINVAL; 770 771 raw = true; 772 } 773 774 /* 775 * This function runs with the policy R/W semaphore held, which 776 * guarantees that the driver pointer will not change while it is 777 * running. 778 */ 779 if (!intel_pstate_driver) 780 return -EAGAIN; 781 782 mutex_lock(&intel_pstate_limits_lock); 783 784 if (intel_pstate_driver == &intel_pstate) { 785 ret = intel_pstate_set_energy_pref_index(cpu, ret, raw, epp); 786 } else { 787 /* 788 * In the passive mode the governor needs to be stopped on the 789 * target CPU before the EPP update and restarted after it, 790 * which is super-heavy-weight, so make sure it is worth doing 791 * upfront. 792 */ 793 if (!raw) 794 epp = ret ? epp_values[ret] : cpu->epp_default; 795 796 if (cpu->epp_cached != epp) { 797 int err; 798 799 cpufreq_stop_governor(policy); 800 ret = intel_pstate_set_epp(cpu, epp); 801 err = cpufreq_start_governor(policy); 802 if (!ret) 803 ret = err; 804 } else { 805 ret = 0; 806 } 807 } 808 809 mutex_unlock(&intel_pstate_limits_lock); 810 811 return ret ?: count; 812 } 813 814 static ssize_t show_energy_performance_preference( 815 struct cpufreq_policy *policy, char *buf) 816 { 817 struct cpudata *cpu_data = all_cpu_data[policy->cpu]; 818 int preference, raw_epp; 819 820 preference = intel_pstate_get_energy_pref_index(cpu_data, &raw_epp); 821 if (preference < 0) 822 return preference; 823 824 if (raw_epp) 825 return sprintf(buf, "%d\n", raw_epp); 826 else 827 return sprintf(buf, "%s\n", energy_perf_strings[preference]); 828 } 829 830 cpufreq_freq_attr_rw(energy_performance_preference); 831 832 static ssize_t show_base_frequency(struct cpufreq_policy *policy, char *buf) 833 { 834 struct cpudata *cpu = all_cpu_data[policy->cpu]; 835 int ratio, freq; 836 837 ratio = intel_pstate_get_cppc_guaranteed(policy->cpu); 838 if (ratio <= 0) { 839 u64 cap; 840 841 rdmsrq_on_cpu(policy->cpu, MSR_HWP_CAPABILITIES, &cap); 842 ratio = HWP_GUARANTEED_PERF(cap); 843 } 844 845 freq = ratio * cpu->pstate.scaling; 846 if (cpu->pstate.scaling != cpu->pstate.perf_ctl_scaling) 847 freq = rounddown(freq, cpu->pstate.perf_ctl_scaling); 848 849 return sprintf(buf, "%d\n", freq); 850 } 851 852 cpufreq_freq_attr_ro(base_frequency); 853 854 enum hwp_cpufreq_attr_index { 855 HWP_BASE_FREQUENCY_INDEX = 0, 856 HWP_PERFORMANCE_PREFERENCE_INDEX, 857 HWP_PERFORMANCE_AVAILABLE_PREFERENCES_INDEX, 858 HWP_CPUFREQ_ATTR_COUNT, 859 }; 860 861 static struct freq_attr *hwp_cpufreq_attrs[] = { 862 [HWP_BASE_FREQUENCY_INDEX] = &base_frequency, 863 [HWP_PERFORMANCE_PREFERENCE_INDEX] = &energy_performance_preference, 864 [HWP_PERFORMANCE_AVAILABLE_PREFERENCES_INDEX] = 865 &energy_performance_available_preferences, 866 [HWP_CPUFREQ_ATTR_COUNT] = NULL, 867 }; 868 869 static u8 hybrid_get_cpu_type(unsigned int cpu) 870 { 871 return cpu_data(cpu).topo.intel_type; 872 } 873 874 static bool no_cas __ro_after_init; 875 876 static struct cpudata *hybrid_max_perf_cpu __read_mostly; 877 /* 878 * Protects hybrid_max_perf_cpu, the capacity_perf fields in struct cpudata, 879 * and the x86 arch scale-invariance information from concurrent updates. 880 */ 881 static DEFINE_MUTEX(hybrid_capacity_lock); 882 883 #ifdef CONFIG_ENERGY_MODEL 884 #define HYBRID_EM_STATE_COUNT 4 885 886 static int hybrid_active_power(struct device *dev, unsigned long *power, 887 unsigned long *freq) 888 { 889 /* 890 * Create four "states" corresponding to 40%, 60%, 80%, and 100% of the 891 * full capacity. 892 * 893 * For this purpose, return the "frequency" of 2 for the first 894 * performance level and otherwise leave the value set by the caller. 895 */ 896 if (!*freq) 897 *freq = 2; 898 899 /* No power information. */ 900 *power = EM_MAX_POWER; 901 902 return 0; 903 } 904 905 static bool hybrid_has_l3(unsigned int cpu) 906 { 907 struct cpu_cacheinfo *cacheinfo = get_cpu_cacheinfo(cpu); 908 unsigned int i; 909 910 if (!cacheinfo) 911 return false; 912 913 for (i = 0; i < cacheinfo->num_leaves; i++) { 914 if (cacheinfo->info_list[i].level == 3) 915 return true; 916 } 917 918 return false; 919 } 920 921 static int hybrid_get_cost(struct device *dev, unsigned long freq, 922 unsigned long *cost) 923 { 924 /* Facilitate load balancing between CPUs of the same type. */ 925 *cost = freq; 926 /* 927 * Adjust the cost depending on CPU type. 928 * 929 * The idea is to start loading up LPE-cores before E-cores and start 930 * to populate E-cores when LPE-cores are utilized above 60% of the 931 * capacity. Similarly, P-cores start to be populated when E-cores are 932 * utilized above 60% of the capacity. 933 */ 934 if (hybrid_get_cpu_type(dev->id) == INTEL_CPU_TYPE_CORE) /* P-core */ 935 *cost += 2; 936 else if (hybrid_has_l3(dev->id)) /* E-core */ 937 *cost += 1; 938 939 return 0; 940 } 941 942 static bool hybrid_register_perf_domain(unsigned int cpu) 943 { 944 static const struct em_data_callback cb 945 = EM_ADV_DATA_CB(hybrid_active_power, hybrid_get_cost); 946 struct cpudata *cpudata = all_cpu_data[cpu]; 947 struct device *cpu_dev; 948 949 /* 950 * Registering EM perf domains without enabling asymmetric CPU capacity 951 * support is not really useful and one domain should not be registered 952 * more than once. 953 */ 954 if (!hybrid_max_perf_cpu || cpudata->pd_registered) 955 return false; 956 957 cpu_dev = get_cpu_device(cpu); 958 if (!cpu_dev) 959 return false; 960 961 if (em_dev_register_pd_no_update(cpu_dev, HYBRID_EM_STATE_COUNT, &cb, 962 cpumask_of(cpu), false)) 963 return false; 964 965 cpudata->pd_registered = true; 966 967 return true; 968 } 969 970 static void hybrid_register_all_perf_domains(void) 971 { 972 unsigned int cpu; 973 974 for_each_online_cpu(cpu) 975 hybrid_register_perf_domain(cpu); 976 } 977 978 static void hybrid_update_perf_domain(struct cpudata *cpu) 979 { 980 if (cpu->pd_registered) 981 em_adjust_cpu_capacity(cpu->cpu); 982 } 983 #else /* !CONFIG_ENERGY_MODEL */ 984 static inline bool hybrid_register_perf_domain(unsigned int cpu) { return false; } 985 static inline void hybrid_register_all_perf_domains(void) {} 986 static inline void hybrid_update_perf_domain(struct cpudata *cpu) {} 987 #endif /* CONFIG_ENERGY_MODEL */ 988 989 static void hybrid_set_cpu_capacity(struct cpudata *cpu) 990 { 991 arch_set_cpu_capacity(cpu->cpu, cpu->capacity_perf, 992 hybrid_max_perf_cpu->capacity_perf, 993 cpu->capacity_perf, 994 cpu->pstate.max_pstate_physical); 995 hybrid_update_perf_domain(cpu); 996 997 topology_set_cpu_scale(cpu->cpu, arch_scale_cpu_capacity(cpu->cpu)); 998 999 pr_debug("CPU%d: capacity perf = %u, base perf = %u, sys max perf = %u\n", 1000 cpu->cpu, cpu->capacity_perf, cpu->pstate.max_pstate_physical, 1001 hybrid_max_perf_cpu->capacity_perf); 1002 } 1003 1004 static void hybrid_clear_cpu_capacity(unsigned int cpunum) 1005 { 1006 arch_set_cpu_capacity(cpunum, 1, 1, 1, 1); 1007 } 1008 1009 static void hybrid_get_capacity_perf(struct cpudata *cpu) 1010 { 1011 u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached); 1012 1013 if (READ_ONCE(global.no_turbo)) { 1014 cpu->capacity_perf = HWP_GUARANTEED_PERF(hwp_cap); 1015 return; 1016 } 1017 1018 cpu->capacity_perf = HWP_HIGHEST_PERF(hwp_cap); 1019 } 1020 1021 static void hybrid_set_capacity_of_cpus(void) 1022 { 1023 int cpunum; 1024 1025 for_each_online_cpu(cpunum) { 1026 struct cpudata *cpu = all_cpu_data[cpunum]; 1027 1028 if (cpu) 1029 hybrid_set_cpu_capacity(cpu); 1030 } 1031 } 1032 1033 static void hybrid_update_cpu_capacity_scaling(void) 1034 { 1035 struct cpudata *max_perf_cpu = NULL; 1036 unsigned int max_cap_perf = 0; 1037 int cpunum; 1038 1039 for_each_online_cpu(cpunum) { 1040 struct cpudata *cpu = all_cpu_data[cpunum]; 1041 1042 if (!cpu) 1043 continue; 1044 1045 /* 1046 * During initialization, CPU performance at full capacity needs 1047 * to be determined. 1048 */ 1049 if (!hybrid_max_perf_cpu) 1050 hybrid_get_capacity_perf(cpu); 1051 1052 /* 1053 * If hybrid_max_perf_cpu is not NULL at this point, it is 1054 * being replaced, so don't take it into account when looking 1055 * for the new one. 1056 */ 1057 if (cpu == hybrid_max_perf_cpu) 1058 continue; 1059 1060 if (cpu->capacity_perf > max_cap_perf) { 1061 max_cap_perf = cpu->capacity_perf; 1062 max_perf_cpu = cpu; 1063 } 1064 } 1065 1066 if (max_perf_cpu) { 1067 hybrid_max_perf_cpu = max_perf_cpu; 1068 hybrid_set_capacity_of_cpus(); 1069 } else { 1070 pr_info("Found no CPUs with nonzero maximum performance\n"); 1071 /* Revert to the flat CPU capacity structure. */ 1072 for_each_online_cpu(cpunum) 1073 hybrid_clear_cpu_capacity(cpunum); 1074 } 1075 } 1076 1077 static void __hybrid_refresh_cpu_capacity_scaling(void) 1078 { 1079 hybrid_max_perf_cpu = NULL; 1080 hybrid_update_cpu_capacity_scaling(); 1081 } 1082 1083 static void hybrid_refresh_cpu_capacity_scaling(void) 1084 { 1085 guard(mutex)(&hybrid_capacity_lock); 1086 1087 __hybrid_refresh_cpu_capacity_scaling(); 1088 /* 1089 * Perf domains are not registered before setting hybrid_max_perf_cpu, 1090 * so register them all after setting up CPU capacity scaling. 1091 */ 1092 hybrid_register_all_perf_domains(); 1093 } 1094 1095 static void hybrid_init_cpu_capacity_scaling(bool refresh) 1096 { 1097 /* Bail out if enabling capacity-aware scheduling is prohibited. */ 1098 if (no_cas) 1099 return; 1100 1101 /* 1102 * If hybrid_max_perf_cpu is set at this point, the hybrid CPU capacity 1103 * scaling has been enabled already and the driver is just changing the 1104 * operation mode. 1105 */ 1106 if (refresh) { 1107 hybrid_refresh_cpu_capacity_scaling(); 1108 return; 1109 } 1110 1111 /* 1112 * On hybrid systems, use asym capacity instead of ITMT, but because 1113 * the capacity of SMT threads is not deterministic even approximately, 1114 * do not do that when SMT is in use. 1115 */ 1116 if (hwp_is_hybrid && !cpu_smt_possible() && arch_enable_hybrid_capacity_scale()) { 1117 hybrid_refresh_cpu_capacity_scaling(); 1118 /* 1119 * Disabling ITMT causes sched domains to be rebuilt to disable asym 1120 * packing and enable asym capacity and EAS. 1121 */ 1122 sched_clear_itmt_support(); 1123 } 1124 } 1125 1126 static bool hybrid_clear_max_perf_cpu(void) 1127 { 1128 bool ret; 1129 1130 guard(mutex)(&hybrid_capacity_lock); 1131 1132 ret = !!hybrid_max_perf_cpu; 1133 hybrid_max_perf_cpu = NULL; 1134 1135 return ret; 1136 } 1137 1138 static void intel_pstate_update_freq_limits(struct cpudata *cpu) 1139 { 1140 int scaling = cpu->pstate.scaling; 1141 unsigned int turbo_freq = cpu->pstate.turbo_pstate * scaling; 1142 unsigned int max_freq = cpu->pstate.max_pstate * scaling; 1143 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling; 1144 1145 if (scaling != perf_ctl_scaling) { 1146 turbo_freq = rounddown(turbo_freq, perf_ctl_scaling); 1147 max_freq = rounddown(max_freq, perf_ctl_scaling); 1148 } 1149 1150 cpu->pstate.turbo_freq = turbo_freq; 1151 cpu->pstate.max_freq = max_freq; 1152 } 1153 1154 static void __intel_pstate_get_hwp_cap(struct cpudata *cpu) 1155 { 1156 u64 cap; 1157 1158 rdmsrq_on_cpu(cpu->cpu, MSR_HWP_CAPABILITIES, &cap); 1159 WRITE_ONCE(cpu->hwp_cap_cached, cap); 1160 cpu->pstate.max_pstate = HWP_GUARANTEED_PERF(cap); 1161 cpu->pstate.turbo_pstate = HWP_HIGHEST_PERF(cap); 1162 } 1163 1164 static void intel_pstate_get_hwp_cap(struct cpudata *cpu) 1165 { 1166 __intel_pstate_get_hwp_cap(cpu); 1167 intel_pstate_update_freq_limits(cpu); 1168 } 1169 1170 static void hybrid_update_capacity(struct cpudata *cpu) 1171 { 1172 unsigned int max_cap_perf; 1173 1174 mutex_lock(&hybrid_capacity_lock); 1175 1176 if (!hybrid_max_perf_cpu) 1177 goto unlock; 1178 1179 /* 1180 * The maximum performance of the CPU may have changed, but assume 1181 * that the performance of the other CPUs has not changed. 1182 */ 1183 max_cap_perf = hybrid_max_perf_cpu->capacity_perf; 1184 1185 intel_pstate_get_hwp_cap(cpu); 1186 1187 hybrid_get_capacity_perf(cpu); 1188 /* Should hybrid_max_perf_cpu be replaced by this CPU? */ 1189 if (cpu->capacity_perf > max_cap_perf) { 1190 hybrid_max_perf_cpu = cpu; 1191 hybrid_set_capacity_of_cpus(); 1192 goto unlock; 1193 } 1194 1195 /* If this CPU is hybrid_max_perf_cpu, should it be replaced? */ 1196 if (cpu == hybrid_max_perf_cpu && cpu->capacity_perf < max_cap_perf) { 1197 hybrid_update_cpu_capacity_scaling(); 1198 goto unlock; 1199 } 1200 1201 hybrid_set_cpu_capacity(cpu); 1202 /* 1203 * If the CPU was offline to start with and it is going online for the 1204 * first time, a perf domain needs to be registered for it if hybrid 1205 * capacity scaling has been enabled already. In that case, sched 1206 * domains need to be rebuilt to take the new perf domain into account. 1207 */ 1208 if (hybrid_register_perf_domain(cpu->cpu)) 1209 em_rebuild_sched_domains(); 1210 1211 unlock: 1212 mutex_unlock(&hybrid_capacity_lock); 1213 } 1214 1215 static void intel_pstate_hwp_set(unsigned int cpu) 1216 { 1217 struct cpudata *cpu_data = all_cpu_data[cpu]; 1218 int max, min; 1219 u64 value; 1220 s16 epp; 1221 1222 max = cpu_data->max_perf_ratio; 1223 min = cpu_data->min_perf_ratio; 1224 1225 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) 1226 min = max; 1227 1228 rdmsrq_on_cpu(cpu, MSR_HWP_REQUEST, &value); 1229 1230 value &= ~HWP_MIN_PERF(~0L); 1231 value |= HWP_MIN_PERF(min); 1232 1233 value &= ~HWP_MAX_PERF(~0L); 1234 value |= HWP_MAX_PERF(max); 1235 1236 if (cpu_data->epp_policy == cpu_data->policy) 1237 goto skip_epp; 1238 1239 cpu_data->epp_policy = cpu_data->policy; 1240 1241 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) { 1242 epp = intel_pstate_get_epp(cpu_data, value); 1243 cpu_data->epp_powersave = epp; 1244 /* If EPP read was failed, then don't try to write */ 1245 if (epp < 0) 1246 goto skip_epp; 1247 1248 epp = 0; 1249 } else { 1250 /* skip setting EPP, when saved value is invalid */ 1251 if (cpu_data->epp_powersave < 0) 1252 goto skip_epp; 1253 1254 /* 1255 * No need to restore EPP when it is not zero. This 1256 * means: 1257 * - Policy is not changed 1258 * - user has manually changed 1259 * - Error reading EPB 1260 */ 1261 epp = intel_pstate_get_epp(cpu_data, value); 1262 if (epp) 1263 goto skip_epp; 1264 1265 epp = cpu_data->epp_powersave; 1266 } 1267 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 1268 value &= ~GENMASK_ULL(31, 24); 1269 value |= (u64)epp << 24; 1270 } 1271 1272 skip_epp: 1273 WRITE_ONCE(cpu_data->hwp_req_cached, value); 1274 wrmsrq_on_cpu(cpu, MSR_HWP_REQUEST, value); 1275 } 1276 1277 static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata); 1278 1279 static void intel_pstate_hwp_offline(struct cpudata *cpu) 1280 { 1281 u64 value = READ_ONCE(cpu->hwp_req_cached); 1282 int min_perf; 1283 1284 intel_pstate_disable_hwp_interrupt(cpu); 1285 1286 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 1287 /* 1288 * In case the EPP has been set to "performance" by the 1289 * active mode "performance" scaling algorithm, replace that 1290 * temporary value with the cached EPP one. 1291 */ 1292 value &= ~GENMASK_ULL(31, 24); 1293 value |= HWP_ENERGY_PERF_PREFERENCE(cpu->epp_cached); 1294 /* 1295 * However, make sure that EPP will be set to "performance" when 1296 * the CPU is brought back online again and the "performance" 1297 * scaling algorithm is still in effect. 1298 */ 1299 cpu->epp_policy = CPUFREQ_POLICY_UNKNOWN; 1300 } 1301 1302 /* 1303 * Clear the desired perf field in the cached HWP request value to 1304 * prevent nonzero desired values from being leaked into the active 1305 * mode. 1306 */ 1307 value &= ~HWP_DESIRED_PERF(~0L); 1308 WRITE_ONCE(cpu->hwp_req_cached, value); 1309 1310 value &= ~GENMASK_ULL(31, 0); 1311 min_perf = HWP_LOWEST_PERF(READ_ONCE(cpu->hwp_cap_cached)); 1312 1313 /* Set hwp_max = hwp_min */ 1314 value |= HWP_MAX_PERF(min_perf); 1315 value |= HWP_MIN_PERF(min_perf); 1316 1317 /* Set EPP to min */ 1318 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) 1319 value |= HWP_ENERGY_PERF_PREFERENCE(HWP_EPP_POWERSAVE); 1320 1321 wrmsrq_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 1322 1323 mutex_lock(&hybrid_capacity_lock); 1324 1325 if (!hybrid_max_perf_cpu) { 1326 mutex_unlock(&hybrid_capacity_lock); 1327 1328 return; 1329 } 1330 1331 if (hybrid_max_perf_cpu == cpu) 1332 hybrid_update_cpu_capacity_scaling(); 1333 1334 mutex_unlock(&hybrid_capacity_lock); 1335 1336 /* Reset the capacity of the CPU going offline to the initial value. */ 1337 hybrid_clear_cpu_capacity(cpu->cpu); 1338 } 1339 1340 #define POWER_CTL_EE_ENABLE 1 1341 #define POWER_CTL_EE_DISABLE 2 1342 1343 /* Enable bit for Dynamic Efficiency Control (DEC) */ 1344 #define POWER_CTL_DEC_ENABLE 27 1345 1346 static int power_ctl_ee_state; 1347 1348 static void set_power_ctl_ee_state(bool input) 1349 { 1350 u64 power_ctl; 1351 1352 guard(mutex)(&intel_pstate_driver_lock); 1353 1354 rdmsrq(MSR_IA32_POWER_CTL, power_ctl); 1355 if (input) { 1356 power_ctl &= ~BIT(MSR_IA32_POWER_CTL_BIT_EE); 1357 power_ctl_ee_state = POWER_CTL_EE_ENABLE; 1358 } else { 1359 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE); 1360 power_ctl_ee_state = POWER_CTL_EE_DISABLE; 1361 } 1362 wrmsrq(MSR_IA32_POWER_CTL, power_ctl); 1363 } 1364 1365 static void intel_pstate_hwp_enable(struct cpudata *cpudata); 1366 1367 static void intel_pstate_hwp_reenable(struct cpudata *cpu) 1368 { 1369 intel_pstate_hwp_enable(cpu); 1370 wrmsrq_on_cpu(cpu->cpu, MSR_HWP_REQUEST, READ_ONCE(cpu->hwp_req_cached)); 1371 } 1372 1373 static int intel_pstate_suspend(struct cpufreq_policy *policy) 1374 { 1375 struct cpudata *cpu = all_cpu_data[policy->cpu]; 1376 1377 pr_debug("CPU %d suspending\n", cpu->cpu); 1378 1379 cpu->suspended = true; 1380 1381 /* disable HWP interrupt and cancel any pending work */ 1382 intel_pstate_disable_hwp_interrupt(cpu); 1383 1384 return 0; 1385 } 1386 1387 static int intel_pstate_resume(struct cpufreq_policy *policy) 1388 { 1389 struct cpudata *cpu = all_cpu_data[policy->cpu]; 1390 1391 pr_debug("CPU %d resuming\n", cpu->cpu); 1392 1393 /* Only restore if the system default is changed */ 1394 if (power_ctl_ee_state == POWER_CTL_EE_ENABLE) 1395 set_power_ctl_ee_state(true); 1396 else if (power_ctl_ee_state == POWER_CTL_EE_DISABLE) 1397 set_power_ctl_ee_state(false); 1398 1399 if (cpu->suspended && hwp_active) { 1400 mutex_lock(&intel_pstate_limits_lock); 1401 1402 /* Re-enable HWP, because "online" has not done that. */ 1403 intel_pstate_hwp_reenable(cpu); 1404 1405 mutex_unlock(&intel_pstate_limits_lock); 1406 } 1407 1408 cpu->suspended = false; 1409 1410 return 0; 1411 } 1412 1413 static void intel_pstate_update_policies(void) 1414 { 1415 int cpu; 1416 1417 for_each_possible_cpu(cpu) 1418 cpufreq_update_policy(cpu); 1419 } 1420 1421 static void __intel_pstate_update_max_freq(struct cpufreq_policy *policy, 1422 struct cpudata *cpudata) 1423 { 1424 guard(cpufreq_policy_write)(policy); 1425 1426 if (hwp_active) 1427 intel_pstate_get_hwp_cap(cpudata); 1428 1429 policy->cpuinfo.max_freq = READ_ONCE(global.no_turbo) ? 1430 cpudata->pstate.max_freq : cpudata->pstate.turbo_freq; 1431 1432 refresh_frequency_limits(policy); 1433 } 1434 1435 static bool intel_pstate_update_max_freq(int cpu) 1436 { 1437 struct cpufreq_policy *policy __free(put_cpufreq_policy) = cpufreq_cpu_get(cpu); 1438 if (!policy) 1439 return false; 1440 1441 __intel_pstate_update_max_freq(policy, all_cpu_data[cpu]); 1442 1443 return true; 1444 } 1445 1446 static void intel_pstate_update_limits(struct cpufreq_policy *policy) 1447 { 1448 struct cpudata *cpudata = all_cpu_data[policy->cpu]; 1449 1450 __intel_pstate_update_max_freq(policy, cpudata); 1451 1452 hybrid_update_capacity(cpudata); 1453 } 1454 1455 static void intel_pstate_update_limits_for_all(void) 1456 { 1457 int cpu; 1458 1459 for_each_possible_cpu(cpu) 1460 intel_pstate_update_max_freq(cpu); 1461 1462 mutex_lock(&hybrid_capacity_lock); 1463 1464 if (hybrid_max_perf_cpu) 1465 __hybrid_refresh_cpu_capacity_scaling(); 1466 1467 mutex_unlock(&hybrid_capacity_lock); 1468 } 1469 1470 /************************** sysfs begin ************************/ 1471 #define show_one(file_name, object) \ 1472 static ssize_t show_##file_name \ 1473 (struct kobject *kobj, struct kobj_attribute *attr, char *buf) \ 1474 { \ 1475 return sprintf(buf, "%u\n", global.object); \ 1476 } 1477 1478 static ssize_t intel_pstate_show_status(char *buf); 1479 static int intel_pstate_update_status(const char *buf, size_t size); 1480 1481 static ssize_t show_status(struct kobject *kobj, 1482 struct kobj_attribute *attr, char *buf) 1483 { 1484 guard(mutex)(&intel_pstate_driver_lock); 1485 1486 return intel_pstate_show_status(buf); 1487 } 1488 1489 static ssize_t store_status(struct kobject *a, struct kobj_attribute *b, 1490 const char *buf, size_t count) 1491 { 1492 char *p = memchr(buf, '\n', count); 1493 int ret; 1494 1495 guard(mutex)(&intel_pstate_driver_lock); 1496 1497 ret = intel_pstate_update_status(buf, p ? p - buf : count); 1498 if (ret < 0) 1499 return ret; 1500 1501 return count; 1502 } 1503 1504 static ssize_t show_turbo_pct(struct kobject *kobj, 1505 struct kobj_attribute *attr, char *buf) 1506 { 1507 struct cpudata *cpu; 1508 int total, no_turbo, turbo_pct; 1509 uint32_t turbo_fp; 1510 1511 guard(mutex)(&intel_pstate_driver_lock); 1512 1513 if (!intel_pstate_driver) 1514 return -EAGAIN; 1515 1516 cpu = all_cpu_data[0]; 1517 1518 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; 1519 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1; 1520 turbo_fp = div_fp(no_turbo, total); 1521 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100))); 1522 1523 return sprintf(buf, "%u\n", turbo_pct); 1524 } 1525 1526 static ssize_t show_num_pstates(struct kobject *kobj, 1527 struct kobj_attribute *attr, char *buf) 1528 { 1529 struct cpudata *cpu; 1530 int total; 1531 1532 guard(mutex)(&intel_pstate_driver_lock); 1533 1534 if (!intel_pstate_driver) 1535 return -EAGAIN; 1536 1537 cpu = all_cpu_data[0]; 1538 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; 1539 1540 return sprintf(buf, "%u\n", total); 1541 } 1542 1543 static ssize_t show_no_turbo(struct kobject *kobj, 1544 struct kobj_attribute *attr, char *buf) 1545 { 1546 guard(mutex)(&intel_pstate_driver_lock); 1547 1548 if (!intel_pstate_driver) 1549 return -EAGAIN; 1550 1551 return sprintf(buf, "%u\n", global.no_turbo); 1552 } 1553 1554 static ssize_t store_no_turbo(struct kobject *a, struct kobj_attribute *b, 1555 const char *buf, size_t count) 1556 { 1557 unsigned int input; 1558 bool no_turbo; 1559 1560 if (sscanf(buf, "%u", &input) != 1) 1561 return -EINVAL; 1562 1563 guard(mutex)(&intel_pstate_driver_lock); 1564 1565 if (!intel_pstate_driver) 1566 return -EAGAIN; 1567 1568 no_turbo = !!clamp_t(int, input, 0, 1); 1569 1570 WRITE_ONCE(global.turbo_disabled, turbo_is_disabled()); 1571 if (global.turbo_disabled && !no_turbo) { 1572 pr_notice("Turbo disabled by BIOS or unavailable on processor\n"); 1573 if (global.no_turbo) 1574 return -EPERM; 1575 1576 no_turbo = 1; 1577 } 1578 1579 if (no_turbo == global.no_turbo) 1580 return count; 1581 1582 WRITE_ONCE(global.no_turbo, no_turbo); 1583 1584 mutex_lock(&intel_pstate_limits_lock); 1585 1586 if (no_turbo) { 1587 struct cpudata *cpu = all_cpu_data[0]; 1588 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate; 1589 1590 /* Squash the global minimum into the permitted range. */ 1591 if (global.min_perf_pct > pct) 1592 global.min_perf_pct = pct; 1593 } 1594 1595 mutex_unlock(&intel_pstate_limits_lock); 1596 1597 intel_pstate_update_limits_for_all(); 1598 arch_set_max_freq_ratio(no_turbo); 1599 1600 return count; 1601 } 1602 1603 static void update_cpu_qos_request(int cpu, enum freq_qos_req_type type) 1604 { 1605 struct cpudata *cpudata = all_cpu_data[cpu]; 1606 struct freq_qos_request *req; 1607 unsigned int freq; 1608 1609 struct cpufreq_policy *policy __free(put_cpufreq_policy) = cpufreq_cpu_get(cpu); 1610 if (!policy) 1611 return; 1612 1613 req = policy->driver_data; 1614 if (!req) 1615 return; 1616 1617 if (hwp_active) 1618 intel_pstate_get_hwp_cap(cpudata); 1619 1620 freq = cpudata->pstate.turbo_freq; 1621 1622 if (type == FREQ_QOS_MIN) { 1623 freq = DIV_ROUND_UP(freq * global.min_perf_pct, 100); 1624 } else { 1625 req++; 1626 freq = (freq * global.max_perf_pct) / 100; 1627 } 1628 1629 if (freq_qos_update_request(req, freq) < 0) 1630 pr_warn("Failed to update freq constraint: CPU%d\n", cpu); 1631 } 1632 1633 static void update_qos_requests(enum freq_qos_req_type type) 1634 { 1635 int i; 1636 1637 for_each_possible_cpu(i) 1638 update_cpu_qos_request(i, type); 1639 } 1640 1641 static ssize_t store_max_perf_pct(struct kobject *a, struct kobj_attribute *b, 1642 const char *buf, size_t count) 1643 { 1644 unsigned int input; 1645 int ret; 1646 1647 ret = sscanf(buf, "%u", &input); 1648 if (ret != 1) 1649 return -EINVAL; 1650 1651 guard(mutex)(&intel_pstate_driver_lock); 1652 1653 if (!intel_pstate_driver) 1654 return -EAGAIN; 1655 1656 mutex_lock(&intel_pstate_limits_lock); 1657 1658 global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100); 1659 1660 mutex_unlock(&intel_pstate_limits_lock); 1661 1662 if (intel_pstate_driver == &intel_pstate) 1663 intel_pstate_update_policies(); 1664 else 1665 update_qos_requests(FREQ_QOS_MAX); 1666 1667 return count; 1668 } 1669 1670 static ssize_t store_min_perf_pct(struct kobject *a, struct kobj_attribute *b, 1671 const char *buf, size_t count) 1672 { 1673 unsigned int input; 1674 int ret; 1675 1676 ret = sscanf(buf, "%u", &input); 1677 if (ret != 1) 1678 return -EINVAL; 1679 1680 guard(mutex)(&intel_pstate_driver_lock); 1681 1682 if (!intel_pstate_driver) 1683 return -EAGAIN; 1684 1685 mutex_lock(&intel_pstate_limits_lock); 1686 1687 global.min_perf_pct = clamp_t(int, input, 1688 min_perf_pct_min(), global.max_perf_pct); 1689 1690 mutex_unlock(&intel_pstate_limits_lock); 1691 1692 if (intel_pstate_driver == &intel_pstate) 1693 intel_pstate_update_policies(); 1694 else 1695 update_qos_requests(FREQ_QOS_MIN); 1696 1697 return count; 1698 } 1699 1700 static ssize_t show_hwp_dynamic_boost(struct kobject *kobj, 1701 struct kobj_attribute *attr, char *buf) 1702 { 1703 return sprintf(buf, "%u\n", hwp_boost); 1704 } 1705 1706 static ssize_t store_hwp_dynamic_boost(struct kobject *a, 1707 struct kobj_attribute *b, 1708 const char *buf, size_t count) 1709 { 1710 unsigned int input; 1711 int ret; 1712 1713 ret = kstrtouint(buf, 10, &input); 1714 if (ret) 1715 return ret; 1716 1717 guard(mutex)(&intel_pstate_driver_lock); 1718 1719 hwp_boost = !!input; 1720 intel_pstate_update_policies(); 1721 1722 return count; 1723 } 1724 1725 static ssize_t show_energy_efficiency(struct kobject *kobj, struct kobj_attribute *attr, 1726 char *buf) 1727 { 1728 u64 power_ctl; 1729 int enable; 1730 1731 rdmsrq(MSR_IA32_POWER_CTL, power_ctl); 1732 enable = !!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE)); 1733 return sprintf(buf, "%d\n", !enable); 1734 } 1735 1736 static ssize_t store_energy_efficiency(struct kobject *a, struct kobj_attribute *b, 1737 const char *buf, size_t count) 1738 { 1739 bool input; 1740 int ret; 1741 1742 ret = kstrtobool(buf, &input); 1743 if (ret) 1744 return ret; 1745 1746 set_power_ctl_ee_state(input); 1747 1748 return count; 1749 } 1750 1751 show_one(max_perf_pct, max_perf_pct); 1752 show_one(min_perf_pct, min_perf_pct); 1753 1754 define_one_global_rw(status); 1755 define_one_global_rw(no_turbo); 1756 define_one_global_rw(max_perf_pct); 1757 define_one_global_rw(min_perf_pct); 1758 define_one_global_ro(turbo_pct); 1759 define_one_global_ro(num_pstates); 1760 define_one_global_rw(hwp_dynamic_boost); 1761 define_one_global_rw(energy_efficiency); 1762 1763 static struct attribute *intel_pstate_attributes[] = { 1764 &status.attr, 1765 &no_turbo.attr, 1766 NULL 1767 }; 1768 1769 static const struct attribute_group intel_pstate_attr_group = { 1770 .attrs = intel_pstate_attributes, 1771 }; 1772 1773 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[]; 1774 1775 static struct kobject *intel_pstate_kobject; 1776 1777 static void __init intel_pstate_sysfs_expose_params(void) 1778 { 1779 struct device *dev_root = bus_get_dev_root(&cpu_subsys); 1780 int rc; 1781 1782 if (dev_root) { 1783 intel_pstate_kobject = kobject_create_and_add("intel_pstate", &dev_root->kobj); 1784 put_device(dev_root); 1785 } 1786 if (WARN_ON(!intel_pstate_kobject)) 1787 return; 1788 1789 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group); 1790 if (WARN_ON(rc)) 1791 return; 1792 1793 if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) { 1794 rc = sysfs_create_file(intel_pstate_kobject, &turbo_pct.attr); 1795 WARN_ON(rc); 1796 1797 rc = sysfs_create_file(intel_pstate_kobject, &num_pstates.attr); 1798 WARN_ON(rc); 1799 } 1800 1801 /* 1802 * If per cpu limits are enforced there are no global limits, so 1803 * return without creating max/min_perf_pct attributes 1804 */ 1805 if (per_cpu_limits) 1806 return; 1807 1808 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr); 1809 WARN_ON(rc); 1810 1811 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr); 1812 WARN_ON(rc); 1813 1814 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids)) { 1815 rc = sysfs_create_file(intel_pstate_kobject, &energy_efficiency.attr); 1816 WARN_ON(rc); 1817 } 1818 } 1819 1820 static void __init intel_pstate_sysfs_remove(void) 1821 { 1822 if (!intel_pstate_kobject) 1823 return; 1824 1825 sysfs_remove_group(intel_pstate_kobject, &intel_pstate_attr_group); 1826 1827 if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) { 1828 sysfs_remove_file(intel_pstate_kobject, &num_pstates.attr); 1829 sysfs_remove_file(intel_pstate_kobject, &turbo_pct.attr); 1830 } 1831 1832 if (!per_cpu_limits) { 1833 sysfs_remove_file(intel_pstate_kobject, &max_perf_pct.attr); 1834 sysfs_remove_file(intel_pstate_kobject, &min_perf_pct.attr); 1835 1836 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids)) 1837 sysfs_remove_file(intel_pstate_kobject, &energy_efficiency.attr); 1838 } 1839 1840 kobject_put(intel_pstate_kobject); 1841 } 1842 1843 static void intel_pstate_sysfs_expose_hwp_dynamic_boost(void) 1844 { 1845 int rc; 1846 1847 if (!hwp_active) 1848 return; 1849 1850 rc = sysfs_create_file(intel_pstate_kobject, &hwp_dynamic_boost.attr); 1851 WARN_ON_ONCE(rc); 1852 } 1853 1854 static void intel_pstate_sysfs_hide_hwp_dynamic_boost(void) 1855 { 1856 if (!hwp_active) 1857 return; 1858 1859 sysfs_remove_file(intel_pstate_kobject, &hwp_dynamic_boost.attr); 1860 } 1861 1862 /************************** sysfs end ************************/ 1863 1864 static void intel_pstate_notify_work(struct work_struct *work) 1865 { 1866 struct cpudata *cpudata = 1867 container_of(to_delayed_work(work), struct cpudata, hwp_notify_work); 1868 1869 if (intel_pstate_update_max_freq(cpudata->cpu)) { 1870 /* 1871 * The driver will not be unregistered while this function is 1872 * running, so update the capacity without acquiring the driver 1873 * lock. 1874 */ 1875 hybrid_update_capacity(cpudata); 1876 } 1877 1878 wrmsrq_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0); 1879 } 1880 1881 static DEFINE_RAW_SPINLOCK(hwp_notify_lock); 1882 static cpumask_t hwp_intr_enable_mask; 1883 1884 #define HWP_GUARANTEED_PERF_CHANGE_STATUS BIT(0) 1885 #define HWP_HIGHEST_PERF_CHANGE_STATUS BIT(3) 1886 1887 void notify_hwp_interrupt(void) 1888 { 1889 unsigned int this_cpu = smp_processor_id(); 1890 u64 value, status_mask; 1891 unsigned long flags; 1892 1893 if (!hwp_active || !cpu_feature_enabled(X86_FEATURE_HWP_NOTIFY)) 1894 return; 1895 1896 status_mask = HWP_GUARANTEED_PERF_CHANGE_STATUS; 1897 if (cpu_feature_enabled(X86_FEATURE_HWP_HIGHEST_PERF_CHANGE)) 1898 status_mask |= HWP_HIGHEST_PERF_CHANGE_STATUS; 1899 1900 rdmsrq_safe(MSR_HWP_STATUS, &value); 1901 if (!(value & status_mask)) 1902 return; 1903 1904 raw_spin_lock_irqsave(&hwp_notify_lock, flags); 1905 1906 if (!cpumask_test_cpu(this_cpu, &hwp_intr_enable_mask)) 1907 goto ack_intr; 1908 1909 schedule_delayed_work(&all_cpu_data[this_cpu]->hwp_notify_work, 1910 msecs_to_jiffies(10)); 1911 1912 raw_spin_unlock_irqrestore(&hwp_notify_lock, flags); 1913 1914 return; 1915 1916 ack_intr: 1917 wrmsrq_safe(MSR_HWP_STATUS, 0); 1918 raw_spin_unlock_irqrestore(&hwp_notify_lock, flags); 1919 } 1920 1921 static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata) 1922 { 1923 bool cancel_work; 1924 1925 if (!cpu_feature_enabled(X86_FEATURE_HWP_NOTIFY)) 1926 return; 1927 1928 /* wrmsrq_on_cpu has to be outside spinlock as this can result in IPC */ 1929 wrmsrq_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00); 1930 1931 raw_spin_lock_irq(&hwp_notify_lock); 1932 cancel_work = cpumask_test_and_clear_cpu(cpudata->cpu, &hwp_intr_enable_mask); 1933 raw_spin_unlock_irq(&hwp_notify_lock); 1934 1935 if (cancel_work) 1936 cancel_delayed_work_sync(&cpudata->hwp_notify_work); 1937 } 1938 1939 #define HWP_GUARANTEED_PERF_CHANGE_REQ BIT(0) 1940 #define HWP_HIGHEST_PERF_CHANGE_REQ BIT(2) 1941 1942 static void intel_pstate_enable_hwp_interrupt(struct cpudata *cpudata) 1943 { 1944 /* Enable HWP notification interrupt for performance change */ 1945 if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) { 1946 u64 interrupt_mask = HWP_GUARANTEED_PERF_CHANGE_REQ; 1947 1948 raw_spin_lock_irq(&hwp_notify_lock); 1949 INIT_DELAYED_WORK(&cpudata->hwp_notify_work, intel_pstate_notify_work); 1950 cpumask_set_cpu(cpudata->cpu, &hwp_intr_enable_mask); 1951 raw_spin_unlock_irq(&hwp_notify_lock); 1952 1953 if (cpu_feature_enabled(X86_FEATURE_HWP_HIGHEST_PERF_CHANGE)) 1954 interrupt_mask |= HWP_HIGHEST_PERF_CHANGE_REQ; 1955 1956 /* wrmsrq_on_cpu has to be outside spinlock as this can result in IPC */ 1957 wrmsrq_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, interrupt_mask); 1958 wrmsrq_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0); 1959 } 1960 } 1961 1962 static void intel_pstate_update_epp_defaults(struct cpudata *cpudata) 1963 { 1964 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0); 1965 1966 /* 1967 * If the EPP is set by firmware, which means that firmware enabled HWP 1968 * - Is equal or less than 0x80 (default balance_perf EPP) 1969 * - But less performance oriented than performance EPP 1970 * then use this as new balance_perf EPP. 1971 */ 1972 if (hwp_forced && cpudata->epp_default <= HWP_EPP_BALANCE_PERFORMANCE && 1973 cpudata->epp_default > HWP_EPP_PERFORMANCE) { 1974 epp_values[EPP_INDEX_BALANCE_PERFORMANCE] = cpudata->epp_default; 1975 return; 1976 } 1977 1978 /* 1979 * If this CPU gen doesn't call for change in balance_perf 1980 * EPP return. 1981 */ 1982 if (epp_values[EPP_INDEX_BALANCE_PERFORMANCE] == HWP_EPP_BALANCE_PERFORMANCE) 1983 return; 1984 1985 /* 1986 * Use hard coded value per gen to update the balance_perf 1987 * and default EPP. 1988 */ 1989 cpudata->epp_default = epp_values[EPP_INDEX_BALANCE_PERFORMANCE]; 1990 intel_pstate_set_epp(cpudata, cpudata->epp_default); 1991 } 1992 1993 static void intel_pstate_hwp_enable(struct cpudata *cpudata) 1994 { 1995 /* First disable HWP notification interrupt till we activate again */ 1996 if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) 1997 wrmsrq_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00); 1998 1999 wrmsrq_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1); 2000 2001 intel_pstate_enable_hwp_interrupt(cpudata); 2002 2003 if (cpudata->epp_default >= 0) 2004 return; 2005 2006 intel_pstate_update_epp_defaults(cpudata); 2007 } 2008 2009 static u64 get_perf_ctl_val(int pstate) 2010 { 2011 u64 val; 2012 2013 val = (u64)pstate << 8; 2014 if (READ_ONCE(global.no_turbo) && !READ_ONCE(global.turbo_disabled) && 2015 cpu_feature_enabled(X86_FEATURE_IDA)) 2016 val |= (u64)1 << 32; 2017 2018 return val; 2019 } 2020 2021 static int atom_get_min_pstate(int not_used) 2022 { 2023 u64 value; 2024 2025 rdmsrq(MSR_ATOM_CORE_RATIOS, value); 2026 return (value >> 8) & 0x7F; 2027 } 2028 2029 static int atom_get_max_pstate(int not_used) 2030 { 2031 u64 value; 2032 2033 rdmsrq(MSR_ATOM_CORE_RATIOS, value); 2034 return (value >> 16) & 0x7F; 2035 } 2036 2037 static int atom_get_turbo_pstate(int not_used) 2038 { 2039 u64 value; 2040 2041 rdmsrq(MSR_ATOM_CORE_TURBO_RATIOS, value); 2042 return value & 0x7F; 2043 } 2044 2045 static u64 atom_get_val(struct cpudata *cpudata, int pstate) 2046 { 2047 u64 val = get_perf_ctl_val(pstate); 2048 int32_t vid_fp; 2049 u32 vid; 2050 2051 vid_fp = cpudata->vid.min + mul_fp( 2052 int_tofp(pstate - cpudata->pstate.min_pstate), 2053 cpudata->vid.ratio); 2054 2055 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max); 2056 vid = ceiling_fp(vid_fp); 2057 2058 if (pstate > cpudata->pstate.max_pstate) 2059 vid = cpudata->vid.turbo; 2060 2061 return val | vid; 2062 } 2063 2064 static int silvermont_get_scaling(void) 2065 { 2066 u64 value; 2067 int i; 2068 /* Defined in Table 35-6 from SDM (Sept 2015) */ 2069 static int silvermont_freq_table[] = { 2070 83300, 100000, 133300, 116700, 80000}; 2071 2072 rdmsrq(MSR_FSB_FREQ, value); 2073 i = value & 0x7; 2074 WARN_ON(i > 4); 2075 2076 return silvermont_freq_table[i]; 2077 } 2078 2079 static int airmont_get_scaling(void) 2080 { 2081 u64 value; 2082 int i; 2083 /* Defined in Table 35-10 from SDM (Sept 2015) */ 2084 static int airmont_freq_table[] = { 2085 83300, 100000, 133300, 116700, 80000, 2086 93300, 90000, 88900, 87500}; 2087 2088 rdmsrq(MSR_FSB_FREQ, value); 2089 i = value & 0xF; 2090 WARN_ON(i > 8); 2091 2092 return airmont_freq_table[i]; 2093 } 2094 2095 static void atom_get_vid(struct cpudata *cpudata) 2096 { 2097 u64 value; 2098 2099 rdmsrq(MSR_ATOM_CORE_VIDS, value); 2100 cpudata->vid.min = int_tofp((value >> 8) & 0x7f); 2101 cpudata->vid.max = int_tofp((value >> 16) & 0x7f); 2102 cpudata->vid.ratio = div_fp( 2103 cpudata->vid.max - cpudata->vid.min, 2104 int_tofp(cpudata->pstate.max_pstate - 2105 cpudata->pstate.min_pstate)); 2106 2107 rdmsrq(MSR_ATOM_CORE_TURBO_VIDS, value); 2108 cpudata->vid.turbo = value & 0x7f; 2109 } 2110 2111 static int core_get_min_pstate(int cpu) 2112 { 2113 u64 value; 2114 2115 rdmsrq_on_cpu(cpu, MSR_PLATFORM_INFO, &value); 2116 return (value >> 40) & 0xFF; 2117 } 2118 2119 static int core_get_max_pstate_physical(int cpu) 2120 { 2121 u64 value; 2122 2123 rdmsrq_on_cpu(cpu, MSR_PLATFORM_INFO, &value); 2124 return (value >> 8) & 0xFF; 2125 } 2126 2127 static int core_get_tdp_ratio(int cpu, u64 plat_info) 2128 { 2129 /* Check how many TDP levels present */ 2130 if (plat_info & 0x600000000) { 2131 u64 tdp_ctrl; 2132 u64 tdp_ratio; 2133 int tdp_msr; 2134 int err; 2135 2136 /* Get the TDP level (0, 1, 2) to get ratios */ 2137 err = rdmsrq_safe_on_cpu(cpu, MSR_CONFIG_TDP_CONTROL, &tdp_ctrl); 2138 if (err) 2139 return err; 2140 2141 /* TDP MSR are continuous starting at 0x648 */ 2142 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03); 2143 err = rdmsrq_safe_on_cpu(cpu, tdp_msr, &tdp_ratio); 2144 if (err) 2145 return err; 2146 2147 /* For level 1 and 2, bits[23:16] contain the ratio */ 2148 if (tdp_ctrl & 0x03) 2149 tdp_ratio >>= 16; 2150 2151 tdp_ratio &= 0xff; /* ratios are only 8 bits long */ 2152 pr_debug("tdp_ratio %x\n", (int)tdp_ratio); 2153 2154 return (int)tdp_ratio; 2155 } 2156 2157 return -ENXIO; 2158 } 2159 2160 static int core_get_max_pstate(int cpu) 2161 { 2162 u64 tar; 2163 u64 plat_info; 2164 int max_pstate; 2165 int tdp_ratio; 2166 int err; 2167 2168 rdmsrq_on_cpu(cpu, MSR_PLATFORM_INFO, &plat_info); 2169 max_pstate = (plat_info >> 8) & 0xFF; 2170 2171 tdp_ratio = core_get_tdp_ratio(cpu, plat_info); 2172 if (tdp_ratio <= 0) 2173 return max_pstate; 2174 2175 if (hwp_active) { 2176 /* Turbo activation ratio is not used on HWP platforms */ 2177 return tdp_ratio; 2178 } 2179 2180 err = rdmsrq_safe_on_cpu(cpu, MSR_TURBO_ACTIVATION_RATIO, &tar); 2181 if (!err) { 2182 int tar_levels; 2183 2184 /* Do some sanity checking for safety */ 2185 tar_levels = tar & 0xff; 2186 if (tdp_ratio - 1 == tar_levels) { 2187 max_pstate = tar_levels; 2188 pr_debug("max_pstate=TAC %x\n", max_pstate); 2189 } 2190 } 2191 2192 return max_pstate; 2193 } 2194 2195 static int core_get_turbo_pstate(int cpu) 2196 { 2197 u64 value; 2198 int nont, ret; 2199 2200 rdmsrq_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value); 2201 nont = core_get_max_pstate(cpu); 2202 ret = (value) & 255; 2203 if (ret <= nont) 2204 ret = nont; 2205 return ret; 2206 } 2207 2208 static u64 core_get_val(struct cpudata *cpudata, int pstate) 2209 { 2210 return get_perf_ctl_val(pstate); 2211 } 2212 2213 static int knl_get_aperf_mperf_shift(void) 2214 { 2215 return 10; 2216 } 2217 2218 static int knl_get_turbo_pstate(int cpu) 2219 { 2220 u64 value; 2221 int nont, ret; 2222 2223 rdmsrq_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value); 2224 nont = core_get_max_pstate(cpu); 2225 ret = (((value) >> 8) & 0xFF); 2226 if (ret <= nont) 2227 ret = nont; 2228 return ret; 2229 } 2230 2231 static int hwp_get_cpu_scaling(int cpu) 2232 { 2233 if (hybrid_scaling_factor) { 2234 /* 2235 * Return the hybrid scaling factor for P-cores and use the 2236 * default core scaling for E-cores. 2237 */ 2238 if (hybrid_get_cpu_type(cpu) != INTEL_CPU_TYPE_ATOM) 2239 return hybrid_scaling_factor; 2240 2241 return core_get_scaling(); 2242 } 2243 2244 /* Use core scaling on non-hybrid systems. */ 2245 if (!cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) 2246 return core_get_scaling(); 2247 2248 /* 2249 * The system is hybrid, but the hybrid scaling factor is not known or 2250 * the CPU type is not one of the above, so use CPPC to compute the 2251 * scaling factor for this CPU. 2252 */ 2253 return intel_pstate_cppc_get_scaling(cpu); 2254 } 2255 2256 static void intel_pstate_get_hwp_pstates(struct cpudata *cpu) 2257 { 2258 int perf_ctl_max_phys = cpu->pstate.max_pstate_physical; 2259 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling; 2260 int perf_ctl_turbo = cpu->pstate.turbo_pstate; 2261 int cpuid = cpu->cpu; 2262 2263 __intel_pstate_get_hwp_cap(cpu); 2264 2265 if (!pstate_funcs.get_cpu_scaling) 2266 return; 2267 2268 pr_debug("CPU%d: PERF_CTL max_phys = %d\n", cpuid, perf_ctl_max_phys); 2269 pr_debug("CPU%d: PERF_CTL turbo = %d\n", cpuid, perf_ctl_turbo); 2270 pr_debug("CPU%d: PERF_CTL scaling = %d\n", cpuid, perf_ctl_scaling); 2271 pr_debug("CPU%d: PERF_CTL min = %d\n", cpuid, cpu->pstate.min_pstate); 2272 pr_debug("CPU%d: HWP_CAP guaranteed = %d\n", cpuid, cpu->pstate.max_pstate); 2273 pr_debug("CPU%d: HWP_CAP highest = %d\n", cpuid, cpu->pstate.turbo_pstate); 2274 2275 cpu->pstate.scaling = pstate_funcs.get_cpu_scaling(cpuid); 2276 2277 pr_debug("CPU%d: HWP-to-frequency scaling = %d\n", cpuid, cpu->pstate.scaling); 2278 2279 /* 2280 * On hybrid processors, HWP may expose more performance levels than 2281 * there are P-states accessible through the PERF_CTL interface. If 2282 * that happens, the scaling between HWP performance levels and CPU 2283 * frequency will be less than the scaling between P-state values and 2284 * CPU frequency. In that case, update the maximum physical non-turbo 2285 * performance level accordingly. 2286 */ 2287 if (cpu->pstate.scaling != perf_ctl_scaling) { 2288 int freq; 2289 2290 freq = perf_ctl_max_phys * perf_ctl_scaling; 2291 cpu->pstate.max_pstate_physical = intel_pstate_freq_to_hwp(cpu, freq); 2292 2293 freq = cpu->pstate.min_freq; 2294 cpu->pstate.min_pstate = intel_pstate_freq_to_hwp(cpu, freq); 2295 2296 hwp_is_hybrid = true; 2297 } 2298 /* 2299 * If the CPU is going online for the first time and it was offline 2300 * initially, asym capacity scaling may need to be updated. 2301 */ 2302 hybrid_update_capacity(cpu); 2303 } 2304 2305 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu) 2306 { 2307 int perf_ctl_scaling = pstate_funcs.get_scaling(); 2308 2309 cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical(cpu->cpu); 2310 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(cpu->cpu); 2311 cpu->pstate.min_pstate = pstate_funcs.get_min(cpu->cpu); 2312 cpu->pstate.min_freq = cpu->pstate.min_pstate * perf_ctl_scaling; 2313 cpu->pstate.perf_ctl_scaling = perf_ctl_scaling; 2314 cpu->pstate.scaling = perf_ctl_scaling; 2315 2316 if (hwp_active) 2317 intel_pstate_get_hwp_pstates(cpu); 2318 else 2319 cpu->pstate.max_pstate = pstate_funcs.get_max(cpu->cpu); 2320 2321 intel_pstate_update_freq_limits(cpu); 2322 2323 if (pstate_funcs.get_aperf_mperf_shift) 2324 cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift(); 2325 2326 if (pstate_funcs.get_vid) 2327 pstate_funcs.get_vid(cpu); 2328 } 2329 2330 /* 2331 * Long hold time will keep high perf limits for long time, 2332 * which negatively impacts perf/watt for some workloads, 2333 * like specpower. 3ms is based on experiements on some 2334 * workoads. 2335 */ 2336 static int hwp_boost_hold_time_ns = 3 * NSEC_PER_MSEC; 2337 2338 static inline void intel_pstate_hwp_boost_up(struct cpudata *cpu) 2339 { 2340 u64 hwp_req = READ_ONCE(cpu->hwp_req_cached); 2341 u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached); 2342 u32 max_limit = (hwp_req & 0xff00) >> 8; 2343 u32 min_limit = (hwp_req & 0xff); 2344 u32 boost_level1; 2345 2346 /* 2347 * Cases to consider (User changes via sysfs or boot time): 2348 * If, P0 (Turbo max) = P1 (Guaranteed max) = min: 2349 * No boost, return. 2350 * If, P0 (Turbo max) > P1 (Guaranteed max) = min: 2351 * Should result in one level boost only for P0. 2352 * If, P0 (Turbo max) = P1 (Guaranteed max) > min: 2353 * Should result in two level boost: 2354 * (min + p1)/2 and P1. 2355 * If, P0 (Turbo max) > P1 (Guaranteed max) > min: 2356 * Should result in three level boost: 2357 * (min + p1)/2, P1 and P0. 2358 */ 2359 2360 /* If max and min are equal or already at max, nothing to boost */ 2361 if (max_limit == min_limit || cpu->hwp_boost_min >= max_limit) 2362 return; 2363 2364 if (!cpu->hwp_boost_min) 2365 cpu->hwp_boost_min = min_limit; 2366 2367 /* level at half way mark between min and guranteed */ 2368 boost_level1 = (HWP_GUARANTEED_PERF(hwp_cap) + min_limit) >> 1; 2369 2370 if (cpu->hwp_boost_min < boost_level1) 2371 cpu->hwp_boost_min = boost_level1; 2372 else if (cpu->hwp_boost_min < HWP_GUARANTEED_PERF(hwp_cap)) 2373 cpu->hwp_boost_min = HWP_GUARANTEED_PERF(hwp_cap); 2374 else if (cpu->hwp_boost_min == HWP_GUARANTEED_PERF(hwp_cap) && 2375 max_limit != HWP_GUARANTEED_PERF(hwp_cap)) 2376 cpu->hwp_boost_min = max_limit; 2377 else 2378 return; 2379 2380 hwp_req = (hwp_req & ~GENMASK_ULL(7, 0)) | cpu->hwp_boost_min; 2381 wrmsrq(MSR_HWP_REQUEST, hwp_req); 2382 cpu->last_update = cpu->sample.time; 2383 } 2384 2385 static inline void intel_pstate_hwp_boost_down(struct cpudata *cpu) 2386 { 2387 if (cpu->hwp_boost_min) { 2388 bool expired; 2389 2390 /* Check if we are idle for hold time to boost down */ 2391 expired = time_after64(cpu->sample.time, cpu->last_update + 2392 hwp_boost_hold_time_ns); 2393 if (expired) { 2394 wrmsrq(MSR_HWP_REQUEST, cpu->hwp_req_cached); 2395 cpu->hwp_boost_min = 0; 2396 } 2397 } 2398 cpu->last_update = cpu->sample.time; 2399 } 2400 2401 static inline void intel_pstate_update_util_hwp_local(struct cpudata *cpu, 2402 u64 time) 2403 { 2404 cpu->sample.time = time; 2405 2406 if (cpu->sched_flags & SCHED_CPUFREQ_IOWAIT) { 2407 bool do_io = false; 2408 2409 cpu->sched_flags = 0; 2410 /* 2411 * Set iowait_boost flag and update time. Since IO WAIT flag 2412 * is set all the time, we can't just conclude that there is 2413 * some IO bound activity is scheduled on this CPU with just 2414 * one occurrence. If we receive at least two in two 2415 * consecutive ticks, then we treat as boost candidate. 2416 */ 2417 if (time_before64(time, cpu->last_io_update + 2 * TICK_NSEC)) 2418 do_io = true; 2419 2420 cpu->last_io_update = time; 2421 2422 if (do_io) 2423 intel_pstate_hwp_boost_up(cpu); 2424 2425 } else { 2426 intel_pstate_hwp_boost_down(cpu); 2427 } 2428 } 2429 2430 static inline void intel_pstate_update_util_hwp(struct update_util_data *data, 2431 u64 time, unsigned int flags) 2432 { 2433 struct cpudata *cpu = container_of(data, struct cpudata, update_util); 2434 2435 cpu->sched_flags |= flags; 2436 2437 if (smp_processor_id() == cpu->cpu) 2438 intel_pstate_update_util_hwp_local(cpu, time); 2439 } 2440 2441 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu) 2442 { 2443 struct sample *sample = &cpu->sample; 2444 2445 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf); 2446 } 2447 2448 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time) 2449 { 2450 u64 aperf, mperf; 2451 unsigned long flags; 2452 u64 tsc; 2453 2454 local_irq_save(flags); 2455 rdmsrq(MSR_IA32_APERF, aperf); 2456 rdmsrq(MSR_IA32_MPERF, mperf); 2457 tsc = rdtsc(); 2458 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) { 2459 local_irq_restore(flags); 2460 return false; 2461 } 2462 local_irq_restore(flags); 2463 2464 cpu->last_sample_time = cpu->sample.time; 2465 cpu->sample.time = time; 2466 cpu->sample.aperf = aperf; 2467 cpu->sample.mperf = mperf; 2468 cpu->sample.tsc = tsc; 2469 cpu->sample.aperf -= cpu->prev_aperf; 2470 cpu->sample.mperf -= cpu->prev_mperf; 2471 cpu->sample.tsc -= cpu->prev_tsc; 2472 2473 cpu->prev_aperf = aperf; 2474 cpu->prev_mperf = mperf; 2475 cpu->prev_tsc = tsc; 2476 /* 2477 * First time this function is invoked in a given cycle, all of the 2478 * previous sample data fields are equal to zero or stale and they must 2479 * be populated with meaningful numbers for things to work, so assume 2480 * that sample.time will always be reset before setting the utilization 2481 * update hook and make the caller skip the sample then. 2482 */ 2483 if (likely(cpu->last_sample_time)) { 2484 intel_pstate_calc_avg_perf(cpu); 2485 return true; 2486 } 2487 return false; 2488 } 2489 2490 static inline int32_t get_avg_frequency(struct cpudata *cpu) 2491 { 2492 return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz); 2493 } 2494 2495 static inline int32_t get_avg_pstate(struct cpudata *cpu) 2496 { 2497 return mul_ext_fp(cpu->pstate.max_pstate_physical, 2498 cpu->sample.core_avg_perf); 2499 } 2500 2501 static inline int32_t get_target_pstate(struct cpudata *cpu) 2502 { 2503 struct sample *sample = &cpu->sample; 2504 int32_t busy_frac; 2505 int target, avg_pstate; 2506 2507 busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift, 2508 sample->tsc); 2509 2510 if (busy_frac < cpu->iowait_boost) 2511 busy_frac = cpu->iowait_boost; 2512 2513 sample->busy_scaled = busy_frac * 100; 2514 2515 target = READ_ONCE(global.no_turbo) ? 2516 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate; 2517 target += target >> 2; 2518 target = mul_fp(target, busy_frac); 2519 if (target < cpu->pstate.min_pstate) 2520 target = cpu->pstate.min_pstate; 2521 2522 /* 2523 * If the average P-state during the previous cycle was higher than the 2524 * current target, add 50% of the difference to the target to reduce 2525 * possible performance oscillations and offset possible performance 2526 * loss related to moving the workload from one CPU to another within 2527 * a package/module. 2528 */ 2529 avg_pstate = get_avg_pstate(cpu); 2530 if (avg_pstate > target) 2531 target += (avg_pstate - target) >> 1; 2532 2533 return target; 2534 } 2535 2536 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate) 2537 { 2538 int min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio); 2539 int max_pstate = max(min_pstate, cpu->max_perf_ratio); 2540 2541 return clamp_t(int, pstate, min_pstate, max_pstate); 2542 } 2543 2544 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate) 2545 { 2546 if (pstate == cpu->pstate.current_pstate) 2547 return; 2548 2549 cpu->pstate.current_pstate = pstate; 2550 wrmsrq(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate)); 2551 } 2552 2553 static void intel_pstate_adjust_pstate(struct cpudata *cpu) 2554 { 2555 int from = cpu->pstate.current_pstate; 2556 struct sample *sample; 2557 int target_pstate; 2558 2559 target_pstate = get_target_pstate(cpu); 2560 target_pstate = intel_pstate_prepare_request(cpu, target_pstate); 2561 trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu); 2562 intel_pstate_update_pstate(cpu, target_pstate); 2563 2564 sample = &cpu->sample; 2565 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf), 2566 fp_toint(sample->busy_scaled), 2567 from, 2568 cpu->pstate.current_pstate, 2569 sample->mperf, 2570 sample->aperf, 2571 sample->tsc, 2572 get_avg_frequency(cpu), 2573 fp_toint(cpu->iowait_boost * 100)); 2574 } 2575 2576 static void intel_pstate_update_util(struct update_util_data *data, u64 time, 2577 unsigned int flags) 2578 { 2579 struct cpudata *cpu = container_of(data, struct cpudata, update_util); 2580 u64 delta_ns; 2581 2582 /* Don't allow remote callbacks */ 2583 if (smp_processor_id() != cpu->cpu) 2584 return; 2585 2586 delta_ns = time - cpu->last_update; 2587 if (flags & SCHED_CPUFREQ_IOWAIT) { 2588 /* Start over if the CPU may have been idle. */ 2589 if (delta_ns > TICK_NSEC) { 2590 cpu->iowait_boost = ONE_EIGHTH_FP; 2591 } else if (cpu->iowait_boost >= ONE_EIGHTH_FP) { 2592 cpu->iowait_boost <<= 1; 2593 if (cpu->iowait_boost > int_tofp(1)) 2594 cpu->iowait_boost = int_tofp(1); 2595 } else { 2596 cpu->iowait_boost = ONE_EIGHTH_FP; 2597 } 2598 } else if (cpu->iowait_boost) { 2599 /* Clear iowait_boost if the CPU may have been idle. */ 2600 if (delta_ns > TICK_NSEC) 2601 cpu->iowait_boost = 0; 2602 else 2603 cpu->iowait_boost >>= 1; 2604 } 2605 cpu->last_update = time; 2606 delta_ns = time - cpu->sample.time; 2607 if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL) 2608 return; 2609 2610 if (intel_pstate_sample(cpu, time)) 2611 intel_pstate_adjust_pstate(cpu); 2612 } 2613 2614 static struct pstate_funcs core_funcs = { 2615 .get_max = core_get_max_pstate, 2616 .get_max_physical = core_get_max_pstate_physical, 2617 .get_min = core_get_min_pstate, 2618 .get_turbo = core_get_turbo_pstate, 2619 .get_scaling = core_get_scaling, 2620 .get_val = core_get_val, 2621 }; 2622 2623 static const struct pstate_funcs silvermont_funcs = { 2624 .get_max = atom_get_max_pstate, 2625 .get_max_physical = atom_get_max_pstate, 2626 .get_min = atom_get_min_pstate, 2627 .get_turbo = atom_get_turbo_pstate, 2628 .get_val = atom_get_val, 2629 .get_scaling = silvermont_get_scaling, 2630 .get_vid = atom_get_vid, 2631 }; 2632 2633 static const struct pstate_funcs airmont_funcs = { 2634 .get_max = atom_get_max_pstate, 2635 .get_max_physical = atom_get_max_pstate, 2636 .get_min = atom_get_min_pstate, 2637 .get_turbo = atom_get_turbo_pstate, 2638 .get_val = atom_get_val, 2639 .get_scaling = airmont_get_scaling, 2640 .get_vid = atom_get_vid, 2641 }; 2642 2643 static const struct pstate_funcs knl_funcs = { 2644 .get_max = core_get_max_pstate, 2645 .get_max_physical = core_get_max_pstate_physical, 2646 .get_min = core_get_min_pstate, 2647 .get_turbo = knl_get_turbo_pstate, 2648 .get_aperf_mperf_shift = knl_get_aperf_mperf_shift, 2649 .get_scaling = core_get_scaling, 2650 .get_val = core_get_val, 2651 }; 2652 2653 #define X86_MATCH(vfm, policy) \ 2654 X86_MATCH_VFM_FEATURE(vfm, X86_FEATURE_APERFMPERF, &policy) 2655 2656 static const struct x86_cpu_id intel_pstate_cpu_ids[] = { 2657 X86_MATCH(INTEL_SANDYBRIDGE, core_funcs), 2658 X86_MATCH(INTEL_SANDYBRIDGE_X, core_funcs), 2659 X86_MATCH(INTEL_ATOM_SILVERMONT, silvermont_funcs), 2660 X86_MATCH(INTEL_IVYBRIDGE, core_funcs), 2661 X86_MATCH(INTEL_HASWELL, core_funcs), 2662 X86_MATCH(INTEL_BROADWELL, core_funcs), 2663 X86_MATCH(INTEL_IVYBRIDGE_X, core_funcs), 2664 X86_MATCH(INTEL_HASWELL_X, core_funcs), 2665 X86_MATCH(INTEL_HASWELL_L, core_funcs), 2666 X86_MATCH(INTEL_HASWELL_G, core_funcs), 2667 X86_MATCH(INTEL_BROADWELL_G, core_funcs), 2668 X86_MATCH(INTEL_ATOM_AIRMONT, airmont_funcs), 2669 X86_MATCH(INTEL_SKYLAKE_L, core_funcs), 2670 X86_MATCH(INTEL_BROADWELL_X, core_funcs), 2671 X86_MATCH(INTEL_SKYLAKE, core_funcs), 2672 X86_MATCH(INTEL_BROADWELL_D, core_funcs), 2673 X86_MATCH(INTEL_XEON_PHI_KNL, knl_funcs), 2674 X86_MATCH(INTEL_XEON_PHI_KNM, knl_funcs), 2675 X86_MATCH(INTEL_ATOM_GOLDMONT, core_funcs), 2676 X86_MATCH(INTEL_ATOM_GOLDMONT_PLUS, core_funcs), 2677 X86_MATCH(INTEL_SKYLAKE_X, core_funcs), 2678 X86_MATCH(INTEL_COMETLAKE, core_funcs), 2679 X86_MATCH(INTEL_ICELAKE_X, core_funcs), 2680 X86_MATCH(INTEL_TIGERLAKE, core_funcs), 2681 X86_MATCH(INTEL_SAPPHIRERAPIDS_X, core_funcs), 2682 X86_MATCH(INTEL_EMERALDRAPIDS_X, core_funcs), 2683 X86_MATCH(INTEL_GRANITERAPIDS_D, core_funcs), 2684 X86_MATCH(INTEL_GRANITERAPIDS_X, core_funcs), 2685 {} 2686 }; 2687 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids); 2688 2689 #ifdef CONFIG_ACPI 2690 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = { 2691 X86_MATCH(INTEL_BROADWELL_D, core_funcs), 2692 X86_MATCH(INTEL_BROADWELL_X, core_funcs), 2693 X86_MATCH(INTEL_SKYLAKE_X, core_funcs), 2694 X86_MATCH(INTEL_ICELAKE_X, core_funcs), 2695 X86_MATCH(INTEL_SAPPHIRERAPIDS_X, core_funcs), 2696 X86_MATCH(INTEL_EMERALDRAPIDS_X, core_funcs), 2697 X86_MATCH(INTEL_GRANITERAPIDS_D, core_funcs), 2698 X86_MATCH(INTEL_GRANITERAPIDS_X, core_funcs), 2699 X86_MATCH(INTEL_ATOM_CRESTMONT, core_funcs), 2700 X86_MATCH(INTEL_ATOM_CRESTMONT_X, core_funcs), 2701 X86_MATCH(INTEL_ATOM_DARKMONT_X, core_funcs), 2702 X86_MATCH(INTEL_DIAMONDRAPIDS_X, core_funcs), 2703 {} 2704 }; 2705 #endif 2706 2707 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = { 2708 X86_MATCH(INTEL_KABYLAKE, core_funcs), 2709 {} 2710 }; 2711 2712 static int intel_pstate_init_cpu(unsigned int cpunum) 2713 { 2714 struct cpudata *cpu; 2715 2716 cpu = all_cpu_data[cpunum]; 2717 2718 if (!cpu) { 2719 cpu = kzalloc_obj(*cpu); 2720 if (!cpu) 2721 return -ENOMEM; 2722 2723 WRITE_ONCE(all_cpu_data[cpunum], cpu); 2724 2725 cpu->cpu = cpunum; 2726 2727 cpu->epp_default = -EINVAL; 2728 2729 if (hwp_active) { 2730 intel_pstate_hwp_enable(cpu); 2731 2732 if (intel_pstate_acpi_pm_profile_server()) 2733 hwp_boost = true; 2734 } 2735 } else if (hwp_active) { 2736 /* 2737 * Re-enable HWP in case this happens after a resume from ACPI 2738 * S3 if the CPU was offline during the whole system/resume 2739 * cycle. 2740 */ 2741 intel_pstate_hwp_reenable(cpu); 2742 } 2743 2744 cpu->epp_powersave = -EINVAL; 2745 cpu->epp_policy = CPUFREQ_POLICY_UNKNOWN; 2746 2747 intel_pstate_get_cpu_pstates(cpu); 2748 2749 pr_debug("controlling: cpu %d\n", cpunum); 2750 2751 return 0; 2752 } 2753 2754 static void intel_pstate_set_update_util_hook(unsigned int cpu_num) 2755 { 2756 struct cpudata *cpu = all_cpu_data[cpu_num]; 2757 2758 if (hwp_active && !hwp_boost) 2759 return; 2760 2761 if (cpu->update_util_set) 2762 return; 2763 2764 /* Prevent intel_pstate_update_util() from using stale data. */ 2765 cpu->sample.time = 0; 2766 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util, 2767 (hwp_active ? 2768 intel_pstate_update_util_hwp : 2769 intel_pstate_update_util)); 2770 cpu->update_util_set = true; 2771 } 2772 2773 static void intel_pstate_clear_update_util_hook(unsigned int cpu) 2774 { 2775 struct cpudata *cpu_data = all_cpu_data[cpu]; 2776 2777 if (!cpu_data->update_util_set) 2778 return; 2779 2780 cpufreq_remove_update_util_hook(cpu); 2781 cpu_data->update_util_set = false; 2782 synchronize_rcu(); 2783 } 2784 2785 static int intel_pstate_get_max_freq(struct cpudata *cpu) 2786 { 2787 return READ_ONCE(global.no_turbo) ? 2788 cpu->pstate.max_freq : cpu->pstate.turbo_freq; 2789 } 2790 2791 static void intel_pstate_update_perf_limits(struct cpudata *cpu, 2792 unsigned int policy_min, 2793 unsigned int policy_max) 2794 { 2795 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling; 2796 int32_t max_policy_perf, min_policy_perf; 2797 2798 max_policy_perf = policy_max / perf_ctl_scaling; 2799 if (policy_max == policy_min) { 2800 min_policy_perf = max_policy_perf; 2801 } else { 2802 min_policy_perf = policy_min / perf_ctl_scaling; 2803 min_policy_perf = clamp_t(int32_t, min_policy_perf, 2804 0, max_policy_perf); 2805 } 2806 2807 /* 2808 * HWP needs some special consideration, because HWP_REQUEST uses 2809 * abstract values to represent performance rather than pure ratios. 2810 */ 2811 if (hwp_active && cpu->pstate.scaling != perf_ctl_scaling) { 2812 int freq; 2813 2814 freq = max_policy_perf * perf_ctl_scaling; 2815 max_policy_perf = intel_pstate_freq_to_hwp(cpu, freq); 2816 freq = min_policy_perf * perf_ctl_scaling; 2817 min_policy_perf = intel_pstate_freq_to_hwp(cpu, freq); 2818 } 2819 2820 pr_debug("cpu:%d min_policy_perf:%d max_policy_perf:%d\n", 2821 cpu->cpu, min_policy_perf, max_policy_perf); 2822 2823 /* Normalize user input to [min_perf, max_perf] */ 2824 if (per_cpu_limits) { 2825 cpu->min_perf_ratio = min_policy_perf; 2826 cpu->max_perf_ratio = max_policy_perf; 2827 } else { 2828 int turbo_max = cpu->pstate.turbo_pstate; 2829 int32_t global_min, global_max; 2830 2831 /* Global limits are in percent of the maximum turbo P-state. */ 2832 global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100); 2833 global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100); 2834 global_min = clamp_t(int32_t, global_min, 0, global_max); 2835 2836 pr_debug("cpu:%d global_min:%d global_max:%d\n", cpu->cpu, 2837 global_min, global_max); 2838 2839 cpu->min_perf_ratio = max(min_policy_perf, global_min); 2840 cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf); 2841 cpu->max_perf_ratio = min(max_policy_perf, global_max); 2842 cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio); 2843 2844 /* Make sure min_perf <= max_perf */ 2845 cpu->min_perf_ratio = min(cpu->min_perf_ratio, 2846 cpu->max_perf_ratio); 2847 2848 } 2849 pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", cpu->cpu, 2850 cpu->max_perf_ratio, 2851 cpu->min_perf_ratio); 2852 } 2853 2854 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate) 2855 { 2856 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu); 2857 cpu->pstate.current_pstate = pstate; 2858 /* 2859 * Generally, there is no guarantee that this code will always run on 2860 * the CPU being updated, so force the register update to run on the 2861 * right CPU. 2862 */ 2863 wrmsrq_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL, 2864 pstate_funcs.get_val(cpu, pstate)); 2865 } 2866 2867 static int intel_pstate_set_policy(struct cpufreq_policy *policy) 2868 { 2869 unsigned int freq = policy->min; 2870 struct cpudata *cpu; 2871 2872 if (!policy->cpuinfo.max_freq) 2873 return -ENODEV; 2874 2875 pr_debug("set_policy cpuinfo.max %u policy->max %u\n", 2876 policy->cpuinfo.max_freq, policy->max); 2877 2878 cpu = all_cpu_data[policy->cpu]; 2879 cpu->policy = policy->policy; 2880 2881 mutex_lock(&intel_pstate_limits_lock); 2882 2883 intel_pstate_update_perf_limits(cpu, policy->min, policy->max); 2884 2885 if (hwp_active) { 2886 /* 2887 * The active mode only requires an update util hook if HWP 2888 * boost is used and the policy is not "performance". 2889 */ 2890 if (hwp_boost && cpu->policy != CPUFREQ_POLICY_PERFORMANCE) { 2891 intel_pstate_set_update_util_hook(policy->cpu); 2892 } else { 2893 intel_pstate_clear_update_util_hook(policy->cpu); 2894 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) { 2895 freq = cpu->max_perf_ratio * cpu->pstate.scaling; 2896 if (cpu->pstate.scaling != cpu->pstate.perf_ctl_scaling) 2897 freq = rounddown(freq, cpu->pstate.perf_ctl_scaling); 2898 } 2899 } 2900 intel_pstate_hwp_set(policy->cpu); 2901 } else if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) { 2902 int pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio); 2903 2904 /* 2905 * NOHZ_FULL CPUs need this as the governor callback may not 2906 * be invoked on them. 2907 */ 2908 intel_pstate_clear_update_util_hook(policy->cpu); 2909 intel_pstate_set_pstate(cpu, pstate); 2910 freq = pstate * cpu->pstate.scaling; 2911 } else { 2912 intel_pstate_set_update_util_hook(policy->cpu); 2913 } 2914 /* 2915 * policy->cur is never updated in the intel_pstate driver, but it is 2916 * used as a stale frequency value, so set it to reflect the actual 2917 * requested P-state in the "performance" policy case and to the min 2918 * otherwise. 2919 */ 2920 policy->cur = freq; 2921 2922 mutex_unlock(&intel_pstate_limits_lock); 2923 2924 return 0; 2925 } 2926 2927 static void intel_pstate_adjust_policy_max(struct cpudata *cpu, 2928 struct cpufreq_policy_data *policy) 2929 { 2930 if (!hwp_active && 2931 cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate && 2932 policy->max < policy->cpuinfo.max_freq && 2933 policy->max > cpu->pstate.max_freq) { 2934 pr_debug("policy->max > max non turbo frequency\n"); 2935 policy->max = policy->cpuinfo.max_freq; 2936 } 2937 } 2938 2939 static void intel_pstate_verify_cpu_policy(struct cpudata *cpu, 2940 struct cpufreq_policy_data *policy) 2941 { 2942 int max_freq; 2943 2944 if (hwp_active) { 2945 intel_pstate_get_hwp_cap(cpu); 2946 max_freq = READ_ONCE(global.no_turbo) ? 2947 cpu->pstate.max_freq : cpu->pstate.turbo_freq; 2948 } else { 2949 max_freq = intel_pstate_get_max_freq(cpu); 2950 } 2951 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, max_freq); 2952 2953 intel_pstate_adjust_policy_max(cpu, policy); 2954 } 2955 2956 static int intel_pstate_verify_policy(struct cpufreq_policy_data *policy) 2957 { 2958 intel_pstate_verify_cpu_policy(all_cpu_data[policy->cpu], policy); 2959 2960 return 0; 2961 } 2962 2963 static void intel_pstate_set_min_pstate(struct cpudata *cpu) 2964 { 2965 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate); 2966 } 2967 2968 static int intel_cpufreq_cpu_offline(struct cpufreq_policy *policy) 2969 { 2970 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2971 2972 pr_debug("CPU %d going offline\n", cpu->cpu); 2973 2974 if (cpu->suspended) 2975 return 0; 2976 2977 /* 2978 * If the CPU is an SMT thread and it goes offline with the performance 2979 * settings different from the minimum, it will prevent its sibling 2980 * from getting to lower performance levels, so force the minimum 2981 * performance on CPU offline to prevent that from happening. 2982 */ 2983 if (hwp_active) { 2984 intel_pstate_hwp_offline(cpu); 2985 } else { 2986 intel_pstate_set_min_pstate(cpu); 2987 policy->cur = cpu->pstate.min_freq; 2988 } 2989 2990 intel_pstate_exit_perf_limits(policy); 2991 2992 return 0; 2993 } 2994 2995 static int intel_pstate_cpu_online(struct cpufreq_policy *policy) 2996 { 2997 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2998 2999 pr_debug("CPU %d going online\n", cpu->cpu); 3000 3001 intel_pstate_init_acpi_perf_limits(policy); 3002 3003 if (hwp_active) { 3004 /* 3005 * Re-enable HWP and clear the "suspended" flag to let "resume" 3006 * know that it need not do that. 3007 */ 3008 intel_pstate_hwp_reenable(cpu); 3009 cpu->suspended = false; 3010 3011 hybrid_update_capacity(cpu); 3012 } 3013 3014 return 0; 3015 } 3016 3017 static int intel_pstate_cpu_offline(struct cpufreq_policy *policy) 3018 { 3019 intel_pstate_clear_update_util_hook(policy->cpu); 3020 3021 return intel_cpufreq_cpu_offline(policy); 3022 } 3023 3024 static void intel_pstate_cpu_exit(struct cpufreq_policy *policy) 3025 { 3026 pr_debug("CPU %d exiting\n", policy->cpu); 3027 3028 policy->fast_switch_possible = false; 3029 } 3030 3031 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy) 3032 { 3033 struct cpudata *cpu; 3034 int rc; 3035 3036 rc = intel_pstate_init_cpu(policy->cpu); 3037 if (rc) 3038 return rc; 3039 3040 cpu = all_cpu_data[policy->cpu]; 3041 3042 cpu->max_perf_ratio = 0xFF; 3043 cpu->min_perf_ratio = 0; 3044 3045 /* cpuinfo and default policy values */ 3046 policy->cpuinfo.min_freq = cpu->pstate.min_freq; 3047 policy->cpuinfo.max_freq = READ_ONCE(global.no_turbo) ? 3048 cpu->pstate.max_freq : cpu->pstate.turbo_freq; 3049 3050 intel_pstate_init_acpi_perf_limits(policy); 3051 3052 policy->fast_switch_possible = true; 3053 3054 return 0; 3055 } 3056 3057 static int intel_pstate_cpu_init(struct cpufreq_policy *policy) 3058 { 3059 int ret = __intel_pstate_cpu_init(policy); 3060 struct cpudata *cpu; 3061 3062 if (ret) 3063 return ret; 3064 3065 /* 3066 * Set the policy to powersave to provide a valid fallback value in case 3067 * the default cpufreq governor is neither powersave nor performance. 3068 */ 3069 policy->policy = CPUFREQ_POLICY_POWERSAVE; 3070 3071 cpu = all_cpu_data[policy->cpu]; 3072 if (hwp_active) 3073 cpu->epp_cached = intel_pstate_get_epp(cpu, 0); 3074 else 3075 intel_pstate_set_min_pstate(cpu); 3076 3077 return 0; 3078 } 3079 3080 static struct cpufreq_driver intel_pstate = { 3081 .flags = CPUFREQ_CONST_LOOPS, 3082 .verify = intel_pstate_verify_policy, 3083 .setpolicy = intel_pstate_set_policy, 3084 .suspend = intel_pstate_suspend, 3085 .resume = intel_pstate_resume, 3086 .init = intel_pstate_cpu_init, 3087 .exit = intel_pstate_cpu_exit, 3088 .offline = intel_pstate_cpu_offline, 3089 .online = intel_pstate_cpu_online, 3090 .update_limits = intel_pstate_update_limits, 3091 .name = "intel_pstate", 3092 }; 3093 3094 static int intel_cpufreq_verify_policy(struct cpufreq_policy_data *policy) 3095 { 3096 struct cpudata *cpu = all_cpu_data[policy->cpu]; 3097 3098 intel_pstate_verify_cpu_policy(cpu, policy); 3099 intel_pstate_update_perf_limits(cpu, policy->min, policy->max); 3100 3101 return 0; 3102 } 3103 3104 /* Use of trace in passive mode: 3105 * 3106 * In passive mode the trace core_busy field (also known as the 3107 * performance field, and lablelled as such on the graphs; also known as 3108 * core_avg_perf) is not needed and so is re-assigned to indicate if the 3109 * driver call was via the normal or fast switch path. Various graphs 3110 * output from the intel_pstate_tracer.py utility that include core_busy 3111 * (or performance or core_avg_perf) have a fixed y-axis from 0 to 100%, 3112 * so we use 10 to indicate the normal path through the driver, and 3113 * 90 to indicate the fast switch path through the driver. 3114 * The scaled_busy field is not used, and is set to 0. 3115 */ 3116 3117 #define INTEL_PSTATE_TRACE_TARGET 10 3118 #define INTEL_PSTATE_TRACE_FAST_SWITCH 90 3119 3120 static void intel_cpufreq_trace(struct cpudata *cpu, unsigned int trace_type, int old_pstate) 3121 { 3122 struct sample *sample; 3123 3124 if (!trace_pstate_sample_enabled()) 3125 return; 3126 3127 if (!intel_pstate_sample(cpu, ktime_get())) 3128 return; 3129 3130 sample = &cpu->sample; 3131 trace_call__pstate_sample(trace_type, 3132 0, 3133 old_pstate, 3134 cpu->pstate.current_pstate, 3135 sample->mperf, 3136 sample->aperf, 3137 sample->tsc, 3138 get_avg_frequency(cpu), 3139 fp_toint(cpu->iowait_boost * 100)); 3140 } 3141 3142 static void intel_cpufreq_hwp_update(struct cpudata *cpu, u32 min, u32 max, 3143 u32 desired, bool fast_switch) 3144 { 3145 u64 prev = READ_ONCE(cpu->hwp_req_cached), value = prev; 3146 3147 value &= ~HWP_MIN_PERF(~0L); 3148 value |= HWP_MIN_PERF(min); 3149 3150 value &= ~HWP_MAX_PERF(~0L); 3151 value |= HWP_MAX_PERF(max); 3152 3153 value &= ~HWP_DESIRED_PERF(~0L); 3154 value |= HWP_DESIRED_PERF(desired & hwp_desired_mask); 3155 3156 if (value == prev) 3157 return; 3158 3159 WRITE_ONCE(cpu->hwp_req_cached, value); 3160 if (fast_switch) 3161 wrmsrq(MSR_HWP_REQUEST, value); 3162 else 3163 wrmsrq_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 3164 } 3165 3166 static void intel_cpufreq_perf_ctl_update(struct cpudata *cpu, 3167 u32 target_pstate, bool fast_switch) 3168 { 3169 if (fast_switch) 3170 wrmsrq(MSR_IA32_PERF_CTL, 3171 pstate_funcs.get_val(cpu, target_pstate)); 3172 else 3173 wrmsrq_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL, 3174 pstate_funcs.get_val(cpu, target_pstate)); 3175 } 3176 3177 static int intel_cpufreq_update_pstate(struct cpufreq_policy *policy, 3178 int target_pstate, bool fast_switch) 3179 { 3180 struct cpudata *cpu = all_cpu_data[policy->cpu]; 3181 int old_pstate = cpu->pstate.current_pstate; 3182 3183 target_pstate = intel_pstate_prepare_request(cpu, target_pstate); 3184 if (hwp_active) { 3185 int max_pstate = policy->strict_target ? 3186 target_pstate : cpu->max_perf_ratio; 3187 3188 intel_cpufreq_hwp_update(cpu, target_pstate, max_pstate, 3189 target_pstate, fast_switch); 3190 } else if (target_pstate != old_pstate) { 3191 intel_cpufreq_perf_ctl_update(cpu, target_pstate, fast_switch); 3192 } 3193 3194 cpu->pstate.current_pstate = target_pstate; 3195 3196 intel_cpufreq_trace(cpu, fast_switch ? INTEL_PSTATE_TRACE_FAST_SWITCH : 3197 INTEL_PSTATE_TRACE_TARGET, old_pstate); 3198 3199 return target_pstate; 3200 } 3201 3202 static int intel_cpufreq_target(struct cpufreq_policy *policy, 3203 unsigned int target_freq, 3204 unsigned int relation) 3205 { 3206 struct cpudata *cpu = all_cpu_data[policy->cpu]; 3207 struct cpufreq_freqs freqs; 3208 int target_pstate; 3209 3210 freqs.old = policy->cur; 3211 freqs.new = target_freq; 3212 3213 cpufreq_freq_transition_begin(policy, &freqs); 3214 3215 target_pstate = intel_pstate_freq_to_hwp_rel(cpu, freqs.new, relation); 3216 target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, false); 3217 3218 freqs.new = target_pstate * cpu->pstate.scaling; 3219 3220 cpufreq_freq_transition_end(policy, &freqs, false); 3221 3222 return 0; 3223 } 3224 3225 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy, 3226 unsigned int target_freq) 3227 { 3228 struct cpudata *cpu = all_cpu_data[policy->cpu]; 3229 int target_pstate; 3230 3231 target_pstate = intel_pstate_freq_to_hwp(cpu, target_freq); 3232 3233 target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, true); 3234 3235 return target_pstate * cpu->pstate.scaling; 3236 } 3237 3238 static void intel_cpufreq_adjust_perf(struct cpufreq_policy *policy, 3239 unsigned long min_perf, 3240 unsigned long target_perf, 3241 unsigned long max_perf, 3242 unsigned long capacity) 3243 { 3244 struct cpudata *cpu = all_cpu_data[policy->cpu]; 3245 u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached); 3246 int old_pstate = cpu->pstate.current_pstate; 3247 int cap_pstate, min_pstate, max_pstate, target_pstate; 3248 3249 cap_pstate = READ_ONCE(global.no_turbo) ? 3250 HWP_GUARANTEED_PERF(hwp_cap) : 3251 HWP_HIGHEST_PERF(hwp_cap); 3252 3253 /* Optimization: Avoid unnecessary divisions. */ 3254 3255 target_pstate = cap_pstate; 3256 if (target_perf < capacity) 3257 target_pstate = DIV_ROUND_UP(cap_pstate * target_perf, capacity); 3258 3259 min_pstate = cap_pstate; 3260 if (min_perf < capacity) 3261 min_pstate = DIV_ROUND_UP(cap_pstate * min_perf, capacity); 3262 3263 if (min_pstate < cpu->pstate.min_pstate) 3264 min_pstate = cpu->pstate.min_pstate; 3265 3266 if (min_pstate < cpu->min_perf_ratio) 3267 min_pstate = cpu->min_perf_ratio; 3268 3269 if (min_pstate > cpu->max_perf_ratio) 3270 min_pstate = cpu->max_perf_ratio; 3271 3272 max_pstate = cap_pstate; 3273 if (max_perf < capacity) 3274 max_pstate = DIV_ROUND_UP(cap_pstate * max_perf, capacity); 3275 3276 if (max_pstate > cpu->max_perf_ratio) 3277 max_pstate = cpu->max_perf_ratio; 3278 3279 if (max_pstate < min_pstate) 3280 max_pstate = min_pstate; 3281 3282 target_pstate = clamp_t(int, target_pstate, min_pstate, max_pstate); 3283 3284 intel_cpufreq_hwp_update(cpu, min_pstate, max_pstate, target_pstate, true); 3285 3286 cpu->pstate.current_pstate = target_pstate; 3287 intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_FAST_SWITCH, old_pstate); 3288 } 3289 3290 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy) 3291 { 3292 struct freq_qos_request *req; 3293 struct cpudata *cpu; 3294 struct device *dev; 3295 int ret, freq; 3296 3297 dev = get_cpu_device(policy->cpu); 3298 if (!dev) 3299 return -ENODEV; 3300 3301 ret = __intel_pstate_cpu_init(policy); 3302 if (ret) 3303 return ret; 3304 3305 policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY; 3306 3307 req = kzalloc_objs(*req, 2); 3308 if (!req) { 3309 ret = -ENOMEM; 3310 goto pstate_exit; 3311 } 3312 3313 cpu = all_cpu_data[policy->cpu]; 3314 3315 if (hwp_active) { 3316 u64 value; 3317 3318 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY_HWP; 3319 3320 intel_pstate_get_hwp_cap(cpu); 3321 3322 rdmsrq_on_cpu(cpu->cpu, MSR_HWP_REQUEST, &value); 3323 WRITE_ONCE(cpu->hwp_req_cached, value); 3324 3325 cpu->epp_cached = intel_pstate_get_epp(cpu, value); 3326 3327 intel_cpufreq_hwp_update(cpu, cpu->pstate.min_pstate, 3328 cpu->pstate.max_pstate, 3329 cpu->pstate.min_pstate, false); 3330 } else { 3331 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY; 3332 intel_pstate_set_min_pstate(cpu); 3333 } 3334 policy->cur = policy->cpuinfo.min_freq; 3335 3336 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.min_perf_pct, 100); 3337 3338 ret = freq_qos_add_request(&policy->constraints, req, FREQ_QOS_MIN, 3339 freq); 3340 if (ret < 0) { 3341 dev_err(dev, "Failed to add min-freq constraint (%d)\n", ret); 3342 goto free_req; 3343 } 3344 3345 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.max_perf_pct, 100); 3346 3347 ret = freq_qos_add_request(&policy->constraints, req + 1, FREQ_QOS_MAX, 3348 freq); 3349 if (ret < 0) { 3350 dev_err(dev, "Failed to add max-freq constraint (%d)\n", ret); 3351 goto remove_min_req; 3352 } 3353 3354 policy->driver_data = req; 3355 3356 return 0; 3357 3358 remove_min_req: 3359 freq_qos_remove_request(req); 3360 free_req: 3361 kfree(req); 3362 pstate_exit: 3363 intel_pstate_exit_perf_limits(policy); 3364 3365 return ret; 3366 } 3367 3368 static void intel_cpufreq_cpu_exit(struct cpufreq_policy *policy) 3369 { 3370 struct freq_qos_request *req; 3371 3372 req = policy->driver_data; 3373 3374 freq_qos_remove_request(req + 1); 3375 freq_qos_remove_request(req); 3376 kfree(req); 3377 3378 intel_pstate_cpu_exit(policy); 3379 } 3380 3381 static int intel_cpufreq_suspend(struct cpufreq_policy *policy) 3382 { 3383 intel_pstate_suspend(policy); 3384 3385 if (hwp_active) { 3386 struct cpudata *cpu = all_cpu_data[policy->cpu]; 3387 u64 value = READ_ONCE(cpu->hwp_req_cached); 3388 3389 /* 3390 * Clear the desired perf field in MSR_HWP_REQUEST in case 3391 * intel_cpufreq_adjust_perf() is in use and the last value 3392 * written by it may not be suitable. 3393 */ 3394 value &= ~HWP_DESIRED_PERF(~0L); 3395 wrmsrq_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 3396 WRITE_ONCE(cpu->hwp_req_cached, value); 3397 } 3398 3399 return 0; 3400 } 3401 3402 static struct cpufreq_driver intel_cpufreq = { 3403 .flags = CPUFREQ_CONST_LOOPS, 3404 .verify = intel_cpufreq_verify_policy, 3405 .target = intel_cpufreq_target, 3406 .fast_switch = intel_cpufreq_fast_switch, 3407 .init = intel_cpufreq_cpu_init, 3408 .exit = intel_cpufreq_cpu_exit, 3409 .offline = intel_cpufreq_cpu_offline, 3410 .online = intel_pstate_cpu_online, 3411 .suspend = intel_cpufreq_suspend, 3412 .resume = intel_pstate_resume, 3413 .update_limits = intel_pstate_update_limits, 3414 .name = "intel_cpufreq", 3415 }; 3416 3417 static struct cpufreq_driver *default_driver; 3418 3419 static void intel_pstate_driver_cleanup(void) 3420 { 3421 unsigned int cpu; 3422 3423 cpus_read_lock(); 3424 for_each_online_cpu(cpu) { 3425 if (all_cpu_data[cpu]) { 3426 if (intel_pstate_driver == &intel_pstate) 3427 intel_pstate_clear_update_util_hook(cpu); 3428 3429 kfree(all_cpu_data[cpu]); 3430 WRITE_ONCE(all_cpu_data[cpu], NULL); 3431 } 3432 } 3433 cpus_read_unlock(); 3434 3435 intel_pstate_driver = NULL; 3436 } 3437 3438 static int intel_pstate_register_driver(struct cpufreq_driver *driver) 3439 { 3440 bool refresh_cpu_cap_scaling; 3441 int ret; 3442 3443 if (driver == &intel_pstate) 3444 intel_pstate_sysfs_expose_hwp_dynamic_boost(); 3445 3446 memset(&global, 0, sizeof(global)); 3447 global.max_perf_pct = 100; 3448 global.turbo_disabled = turbo_is_disabled(); 3449 global.no_turbo = global.turbo_disabled; 3450 3451 arch_set_max_freq_ratio(global.turbo_disabled); 3452 3453 refresh_cpu_cap_scaling = hybrid_clear_max_perf_cpu(); 3454 3455 intel_pstate_driver = driver; 3456 ret = cpufreq_register_driver(intel_pstate_driver); 3457 if (ret) { 3458 intel_pstate_driver_cleanup(); 3459 return ret; 3460 } 3461 3462 global.min_perf_pct = min_perf_pct_min(); 3463 3464 hybrid_init_cpu_capacity_scaling(refresh_cpu_cap_scaling); 3465 3466 return 0; 3467 } 3468 3469 static ssize_t intel_pstate_show_status(char *buf) 3470 { 3471 if (!intel_pstate_driver) 3472 return sprintf(buf, "off\n"); 3473 3474 return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ? 3475 "active" : "passive"); 3476 } 3477 3478 static int intel_pstate_update_status(const char *buf, size_t size) 3479 { 3480 if (size == 3 && !strncmp(buf, "off", size)) { 3481 if (!intel_pstate_driver) 3482 return 0; 3483 3484 if (hwp_active) 3485 return -EBUSY; 3486 3487 cpufreq_unregister_driver(intel_pstate_driver); 3488 intel_pstate_driver_cleanup(); 3489 return 0; 3490 } 3491 3492 if (size == 6 && !strncmp(buf, "active", size)) { 3493 if (intel_pstate_driver) { 3494 if (intel_pstate_driver == &intel_pstate) 3495 return 0; 3496 3497 cpufreq_unregister_driver(intel_pstate_driver); 3498 } 3499 3500 return intel_pstate_register_driver(&intel_pstate); 3501 } 3502 3503 if (size == 7 && !strncmp(buf, "passive", size)) { 3504 if (intel_pstate_driver) { 3505 if (intel_pstate_driver == &intel_cpufreq) 3506 return 0; 3507 3508 cpufreq_unregister_driver(intel_pstate_driver); 3509 intel_pstate_sysfs_hide_hwp_dynamic_boost(); 3510 } 3511 3512 return intel_pstate_register_driver(&intel_cpufreq); 3513 } 3514 3515 return -EINVAL; 3516 } 3517 3518 static int no_load __initdata; 3519 static int no_hwp __initdata; 3520 static int hwp_only __initdata; 3521 static unsigned int force_load __initdata; 3522 3523 static int __init intel_pstate_msrs_not_valid(void) 3524 { 3525 if (!pstate_funcs.get_max(0) || 3526 !pstate_funcs.get_min(0) || 3527 !pstate_funcs.get_turbo(0)) 3528 return -ENODEV; 3529 3530 return 0; 3531 } 3532 3533 static void __init copy_cpu_funcs(struct pstate_funcs *funcs) 3534 { 3535 pstate_funcs.get_max = funcs->get_max; 3536 pstate_funcs.get_max_physical = funcs->get_max_physical; 3537 pstate_funcs.get_min = funcs->get_min; 3538 pstate_funcs.get_turbo = funcs->get_turbo; 3539 pstate_funcs.get_scaling = funcs->get_scaling; 3540 pstate_funcs.get_val = funcs->get_val; 3541 pstate_funcs.get_vid = funcs->get_vid; 3542 pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift; 3543 } 3544 3545 #ifdef CONFIG_ACPI 3546 3547 static bool __init intel_pstate_no_acpi_pss(void) 3548 { 3549 int i; 3550 3551 for_each_possible_cpu(i) { 3552 acpi_status status; 3553 union acpi_object *pss; 3554 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; 3555 struct acpi_processor *pr = per_cpu(processors, i); 3556 3557 if (!pr) 3558 continue; 3559 3560 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer); 3561 if (ACPI_FAILURE(status)) 3562 continue; 3563 3564 pss = buffer.pointer; 3565 if (pss && pss->type == ACPI_TYPE_PACKAGE) { 3566 kfree(pss); 3567 return false; 3568 } 3569 3570 kfree(pss); 3571 } 3572 3573 pr_debug("ACPI _PSS not found\n"); 3574 return true; 3575 } 3576 3577 static bool __init intel_pstate_no_acpi_pcch(void) 3578 { 3579 acpi_status status; 3580 acpi_handle handle; 3581 3582 status = acpi_get_handle(NULL, "\\_SB", &handle); 3583 if (ACPI_FAILURE(status)) 3584 goto not_found; 3585 3586 if (acpi_has_method(handle, "PCCH")) 3587 return false; 3588 3589 not_found: 3590 pr_debug("ACPI PCCH not found\n"); 3591 return true; 3592 } 3593 3594 static bool __init intel_pstate_has_acpi_ppc(void) 3595 { 3596 int i; 3597 3598 for_each_possible_cpu(i) { 3599 struct acpi_processor *pr = per_cpu(processors, i); 3600 3601 if (!pr) 3602 continue; 3603 if (acpi_has_method(pr->handle, "_PPC")) 3604 return true; 3605 } 3606 pr_debug("ACPI _PPC not found\n"); 3607 return false; 3608 } 3609 3610 enum { 3611 PSS, 3612 PPC, 3613 }; 3614 3615 /* Hardware vendor-specific info that has its own power management modes */ 3616 static struct acpi_platform_list plat_info[] __initdata = { 3617 {"HP ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, NULL, PSS}, 3618 {"ORACLE", "X4-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3619 {"ORACLE", "X4-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3620 {"ORACLE", "X4-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3621 {"ORACLE", "X3-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3622 {"ORACLE", "X3-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3623 {"ORACLE", "X3-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3624 {"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3625 {"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3626 {"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3627 {"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3628 {"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3629 {"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3630 {"ORACLE", "X6-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3631 {"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3632 { } /* End */ 3633 }; 3634 3635 #define BITMASK_OOB (BIT(8) | BIT(18)) 3636 3637 static bool __init intel_pstate_platform_pwr_mgmt_exists(void) 3638 { 3639 const struct x86_cpu_id *id; 3640 u64 misc_pwr; 3641 int idx; 3642 3643 id = x86_match_cpu(intel_pstate_cpu_oob_ids); 3644 if (id) { 3645 rdmsrq(MSR_MISC_PWR_MGMT, misc_pwr); 3646 if (misc_pwr & BITMASK_OOB) { 3647 pr_debug("Bit 8 or 18 in the MISC_PWR_MGMT MSR set\n"); 3648 pr_debug("P states are controlled in Out of Band mode by the firmware/hardware\n"); 3649 return true; 3650 } 3651 } 3652 3653 idx = acpi_match_platform_list(plat_info); 3654 if (idx < 0) 3655 return false; 3656 3657 switch (plat_info[idx].data) { 3658 case PSS: 3659 if (!intel_pstate_no_acpi_pss()) 3660 return false; 3661 3662 return intel_pstate_no_acpi_pcch(); 3663 case PPC: 3664 return intel_pstate_has_acpi_ppc() && !force_load; 3665 } 3666 3667 return false; 3668 } 3669 3670 static void intel_pstate_request_control_from_smm(void) 3671 { 3672 /* 3673 * It may be unsafe to request P-states control from SMM if _PPC support 3674 * has not been enabled. 3675 */ 3676 if (acpi_ppc) 3677 acpi_processor_pstate_control(); 3678 } 3679 #else /* CONFIG_ACPI not enabled */ 3680 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; } 3681 static inline bool intel_pstate_has_acpi_ppc(void) { return false; } 3682 static inline void intel_pstate_request_control_from_smm(void) {} 3683 #endif /* CONFIG_ACPI */ 3684 3685 #define INTEL_PSTATE_HWP_NOT_HYBRID 0x01 3686 3687 #define X86_MATCH_HWP(vfm, hwp_mode) \ 3688 X86_MATCH_VFM_FEATURE(vfm, X86_FEATURE_HWP, hwp_mode) 3689 3690 static const struct x86_cpu_id hwp_support_ids[] __initconst = { 3691 X86_MATCH_HWP(INTEL_BROADWELL_X, INTEL_PSTATE_HWP_NOT_HYBRID), 3692 X86_MATCH_HWP(INTEL_BROADWELL_D, INTEL_PSTATE_HWP_NOT_HYBRID), 3693 X86_MATCH_HWP(INTEL_ANY, 0), 3694 {} 3695 }; 3696 3697 static bool intel_pstate_hwp_is_enabled(void) 3698 { 3699 u64 value; 3700 3701 rdmsrq(MSR_PM_ENABLE, value); 3702 return !!(value & 0x1); 3703 } 3704 3705 #define POWERSAVE_MASK GENMASK(7, 0) 3706 #define BALANCE_POWER_MASK GENMASK(15, 8) 3707 #define BALANCE_PERFORMANCE_MASK GENMASK(23, 16) 3708 #define PERFORMANCE_MASK GENMASK(31, 24) 3709 3710 #define HWP_SET_EPP_VALUES(powersave, balance_power, balance_perf, performance) \ 3711 (FIELD_PREP_CONST(POWERSAVE_MASK, powersave) |\ 3712 FIELD_PREP_CONST(BALANCE_POWER_MASK, balance_power) |\ 3713 FIELD_PREP_CONST(BALANCE_PERFORMANCE_MASK, balance_perf) |\ 3714 FIELD_PREP_CONST(PERFORMANCE_MASK, performance)) 3715 3716 #define HWP_SET_DEF_BALANCE_PERF_EPP(balance_perf) \ 3717 (HWP_SET_EPP_VALUES(HWP_EPP_POWERSAVE, HWP_EPP_BALANCE_POWERSAVE,\ 3718 balance_perf, HWP_EPP_PERFORMANCE)) 3719 3720 static const struct x86_cpu_id intel_epp_default[] = { 3721 /* 3722 * Set EPP value as 102, this is the max suggested EPP 3723 * which can result in one core turbo frequency for 3724 * AlderLake Mobile CPUs. 3725 */ 3726 X86_MATCH_VFM(INTEL_ALDERLAKE_L, HWP_SET_DEF_BALANCE_PERF_EPP(102)), 3727 X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, HWP_SET_DEF_BALANCE_PERF_EPP(32)), 3728 X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, HWP_SET_DEF_BALANCE_PERF_EPP(32)), 3729 X86_MATCH_VFM(INTEL_GRANITERAPIDS_X, HWP_SET_DEF_BALANCE_PERF_EPP(32)), 3730 X86_MATCH_VFM(INTEL_GRANITERAPIDS_D, HWP_SET_DEF_BALANCE_PERF_EPP(32)), 3731 X86_MATCH_VFM(INTEL_METEORLAKE_L, HWP_SET_EPP_VALUES(HWP_EPP_POWERSAVE, 3732 179, 64, 16)), 3733 X86_MATCH_VFM(INTEL_ARROWLAKE, HWP_SET_EPP_VALUES(HWP_EPP_POWERSAVE, 3734 179, 64, 16)), 3735 {} 3736 }; 3737 3738 static const struct x86_cpu_id intel_hybrid_scaling_factor[] = { 3739 X86_MATCH_VFM(INTEL_ALDERLAKE, HYBRID_SCALING_FACTOR_ADL), 3740 X86_MATCH_VFM(INTEL_ALDERLAKE_L, HYBRID_SCALING_FACTOR_ADL), 3741 X86_MATCH_VFM(INTEL_RAPTORLAKE, HYBRID_SCALING_FACTOR_ADL), 3742 X86_MATCH_VFM(INTEL_RAPTORLAKE_P, HYBRID_SCALING_FACTOR_ADL), 3743 X86_MATCH_VFM(INTEL_RAPTORLAKE_S, HYBRID_SCALING_FACTOR_ADL), 3744 X86_MATCH_VFM(INTEL_BARTLETTLAKE, HYBRID_SCALING_FACTOR_ADL), 3745 X86_MATCH_VFM(INTEL_METEORLAKE_L, HYBRID_SCALING_FACTOR_MTL), 3746 X86_MATCH_VFM(INTEL_LUNARLAKE_M, HYBRID_SCALING_FACTOR_LNL), 3747 {} 3748 }; 3749 3750 static bool hwp_check_epp(void) 3751 { 3752 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) 3753 return true; 3754 3755 /* Without EPP support, don't expose EPP-related sysfs attributes. */ 3756 hwp_cpufreq_attrs[HWP_PERFORMANCE_PREFERENCE_INDEX] = NULL; 3757 hwp_cpufreq_attrs[HWP_PERFORMANCE_AVAILABLE_PREFERENCES_INDEX] = NULL; 3758 3759 return false; 3760 } 3761 3762 static bool hwp_check_dec(void) 3763 { 3764 u64 power_ctl = 0; 3765 3766 rdmsrq_safe(MSR_IA32_POWER_CTL, &power_ctl); 3767 return !!(power_ctl & BIT(POWER_CTL_DEC_ENABLE)); 3768 } 3769 3770 static int __init intel_pstate_init(void) 3771 { 3772 static struct cpudata **_all_cpu_data; 3773 const struct x86_cpu_id *id; 3774 int rc; 3775 3776 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) 3777 return -ENODEV; 3778 3779 /* 3780 * The Intel pstate driver will be ignored if the platform 3781 * firmware has its own power management modes. 3782 */ 3783 if (intel_pstate_platform_pwr_mgmt_exists()) { 3784 pr_info("P-states controlled by the platform\n"); 3785 return -ENODEV; 3786 } 3787 3788 id = x86_match_cpu(hwp_support_ids); 3789 if (id) { 3790 bool epp_present = hwp_check_epp(); 3791 bool dec_present = hwp_check_dec(); 3792 3793 /* 3794 * If HWP is enabled already, there is no choice but to deal 3795 * with it. 3796 */ 3797 hwp_forced = intel_pstate_hwp_is_enabled(); 3798 if (hwp_forced) { 3799 pr_info("HWP enabled by BIOS\n"); 3800 no_hwp = 0; 3801 } else if (no_load) { 3802 return -ENODEV; 3803 } else if (!epp_present && !dec_present) { 3804 /* 3805 * Avoid enabling HWP for processors without EPP support 3806 * unless the Dynamic Efficiency Control (DEC) enable 3807 * bit (MSR_IA32_POWER_CTL, bit 27) is set because that 3808 * means incomplete HWP implementation which is a corner 3809 * case and supporting it is generally problematic. 3810 */ 3811 no_hwp = 1; 3812 } 3813 3814 copy_cpu_funcs(&core_funcs); 3815 3816 if (!no_hwp) { 3817 hwp_active = true; 3818 intel_pstate.attr = hwp_cpufreq_attrs; 3819 intel_cpufreq.attr = hwp_cpufreq_attrs; 3820 intel_cpufreq.flags |= CPUFREQ_NEED_UPDATE_LIMITS; 3821 intel_cpufreq.adjust_perf = intel_cpufreq_adjust_perf; 3822 if (!default_driver) 3823 default_driver = &intel_pstate; 3824 3825 if (dec_present) 3826 hwp_desired_mask = 0; 3827 3828 if (!id->driver_data) 3829 pstate_funcs.get_cpu_scaling = hwp_get_cpu_scaling; 3830 3831 goto hwp_cpu_matched; 3832 } 3833 pr_info("HWP not enabled\n"); 3834 } else { 3835 if (no_load) 3836 return -ENODEV; 3837 3838 id = x86_match_cpu(intel_hybrid_scaling_factor); 3839 if (id) { 3840 pr_info("HWP-disabled hybrid CPU is not supported\n"); 3841 return -ENODEV; 3842 } 3843 3844 id = x86_match_cpu(intel_pstate_cpu_ids); 3845 if (!id) { 3846 pr_info("CPU model not supported\n"); 3847 return -ENODEV; 3848 } 3849 3850 copy_cpu_funcs((struct pstate_funcs *)id->driver_data); 3851 } 3852 3853 if (intel_pstate_msrs_not_valid()) { 3854 pr_info("Invalid MSRs\n"); 3855 return -ENODEV; 3856 } 3857 /* Without HWP start in the passive mode. */ 3858 if (!default_driver) 3859 default_driver = &intel_cpufreq; 3860 3861 hwp_cpu_matched: 3862 if (!hwp_active && hwp_only) 3863 return -ENOTSUPP; 3864 3865 pr_info("Intel P-state driver initializing\n"); 3866 3867 _all_cpu_data = vzalloc(array_size(sizeof(void *), num_possible_cpus())); 3868 if (!_all_cpu_data) 3869 return -ENOMEM; 3870 3871 WRITE_ONCE(all_cpu_data, _all_cpu_data); 3872 3873 intel_pstate_request_control_from_smm(); 3874 3875 intel_pstate_sysfs_expose_params(); 3876 3877 if (hwp_active) { 3878 const struct x86_cpu_id *id = x86_match_cpu(intel_epp_default); 3879 const struct x86_cpu_id *hybrid_id = x86_match_cpu(intel_hybrid_scaling_factor); 3880 3881 if (id) { 3882 epp_values[EPP_INDEX_POWERSAVE] = 3883 FIELD_GET(POWERSAVE_MASK, id->driver_data); 3884 epp_values[EPP_INDEX_BALANCE_POWERSAVE] = 3885 FIELD_GET(BALANCE_POWER_MASK, id->driver_data); 3886 epp_values[EPP_INDEX_BALANCE_PERFORMANCE] = 3887 FIELD_GET(BALANCE_PERFORMANCE_MASK, id->driver_data); 3888 epp_values[EPP_INDEX_PERFORMANCE] = 3889 FIELD_GET(PERFORMANCE_MASK, id->driver_data); 3890 pr_debug("Updated EPPs powersave:%x balanced power:%x balanced perf:%x performance:%x\n", 3891 epp_values[EPP_INDEX_POWERSAVE], 3892 epp_values[EPP_INDEX_BALANCE_POWERSAVE], 3893 epp_values[EPP_INDEX_BALANCE_PERFORMANCE], 3894 epp_values[EPP_INDEX_PERFORMANCE]); 3895 } 3896 3897 if (hybrid_id) { 3898 hybrid_scaling_factor = hybrid_id->driver_data; 3899 pr_debug("hybrid scaling factor: %d\n", hybrid_scaling_factor); 3900 } 3901 3902 } 3903 3904 scoped_guard(mutex, &intel_pstate_driver_lock) { 3905 rc = intel_pstate_register_driver(default_driver); 3906 } 3907 if (rc) { 3908 intel_pstate_sysfs_remove(); 3909 return rc; 3910 } 3911 3912 if (hwp_active) { 3913 const struct x86_cpu_id *id; 3914 3915 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids); 3916 if (id) { 3917 set_power_ctl_ee_state(false); 3918 pr_info("Disabling energy efficiency optimization\n"); 3919 } 3920 3921 pr_info("HWP enabled\n"); 3922 } else if (boot_cpu_has(X86_FEATURE_HYBRID_CPU)) { 3923 pr_warn("Problematic setup: Hybrid processor with disabled HWP\n"); 3924 } 3925 3926 return 0; 3927 } 3928 device_initcall(intel_pstate_init); 3929 3930 static int __init intel_pstate_setup(char *str) 3931 { 3932 if (!str) 3933 return -EINVAL; 3934 3935 if (!strcmp(str, "disable")) 3936 no_load = 1; 3937 else if (!strcmp(str, "active")) 3938 default_driver = &intel_pstate; 3939 else if (!strcmp(str, "passive")) 3940 default_driver = &intel_cpufreq; 3941 3942 if (!strcmp(str, "no_hwp")) 3943 no_hwp = 1; 3944 3945 if (!strcmp(str, "no_cas")) 3946 no_cas = true; 3947 3948 if (!strcmp(str, "force")) 3949 force_load = 1; 3950 if (!strcmp(str, "hwp_only")) 3951 hwp_only = 1; 3952 if (!strcmp(str, "per_cpu_perf_limits")) 3953 per_cpu_limits = true; 3954 3955 #ifdef CONFIG_ACPI 3956 if (!strcmp(str, "support_acpi_ppc")) 3957 acpi_ppc = true; 3958 #endif 3959 3960 return 0; 3961 } 3962 early_param("intel_pstate", intel_pstate_setup); 3963 3964 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>"); 3965 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors"); 3966