1 /* 2 * intel_pstate.c: Native P state management for Intel processors 3 * 4 * (C) Copyright 2012 Intel Corporation 5 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; version 2 10 * of the License. 11 */ 12 13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 14 15 #include <linux/kernel.h> 16 #include <linux/kernel_stat.h> 17 #include <linux/module.h> 18 #include <linux/ktime.h> 19 #include <linux/hrtimer.h> 20 #include <linux/tick.h> 21 #include <linux/slab.h> 22 #include <linux/sched.h> 23 #include <linux/list.h> 24 #include <linux/cpu.h> 25 #include <linux/cpufreq.h> 26 #include <linux/sysfs.h> 27 #include <linux/types.h> 28 #include <linux/fs.h> 29 #include <linux/debugfs.h> 30 #include <linux/acpi.h> 31 #include <linux/vmalloc.h> 32 #include <trace/events/power.h> 33 34 #include <asm/div64.h> 35 #include <asm/msr.h> 36 #include <asm/cpu_device_id.h> 37 #include <asm/cpufeature.h> 38 #include <asm/intel-family.h> 39 40 #define INTEL_CPUFREQ_TRANSITION_LATENCY 20000 41 42 #define ATOM_RATIOS 0x66a 43 #define ATOM_VIDS 0x66b 44 #define ATOM_TURBO_RATIOS 0x66c 45 #define ATOM_TURBO_VIDS 0x66d 46 47 #ifdef CONFIG_ACPI 48 #include <acpi/processor.h> 49 #include <acpi/cppc_acpi.h> 50 #endif 51 52 #define FRAC_BITS 8 53 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS) 54 #define fp_toint(X) ((X) >> FRAC_BITS) 55 56 #define EXT_BITS 6 57 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS) 58 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS) 59 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS) 60 61 static inline int32_t mul_fp(int32_t x, int32_t y) 62 { 63 return ((int64_t)x * (int64_t)y) >> FRAC_BITS; 64 } 65 66 static inline int32_t div_fp(s64 x, s64 y) 67 { 68 return div64_s64((int64_t)x << FRAC_BITS, y); 69 } 70 71 static inline int ceiling_fp(int32_t x) 72 { 73 int mask, ret; 74 75 ret = fp_toint(x); 76 mask = (1 << FRAC_BITS) - 1; 77 if (x & mask) 78 ret += 1; 79 return ret; 80 } 81 82 static inline u64 mul_ext_fp(u64 x, u64 y) 83 { 84 return (x * y) >> EXT_FRAC_BITS; 85 } 86 87 static inline u64 div_ext_fp(u64 x, u64 y) 88 { 89 return div64_u64(x << EXT_FRAC_BITS, y); 90 } 91 92 /** 93 * struct sample - Store performance sample 94 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average 95 * performance during last sample period 96 * @busy_scaled: Scaled busy value which is used to calculate next 97 * P state. This can be different than core_avg_perf 98 * to account for cpu idle period 99 * @aperf: Difference of actual performance frequency clock count 100 * read from APERF MSR between last and current sample 101 * @mperf: Difference of maximum performance frequency clock count 102 * read from MPERF MSR between last and current sample 103 * @tsc: Difference of time stamp counter between last and 104 * current sample 105 * @time: Current time from scheduler 106 * 107 * This structure is used in the cpudata structure to store performance sample 108 * data for choosing next P State. 109 */ 110 struct sample { 111 int32_t core_avg_perf; 112 int32_t busy_scaled; 113 u64 aperf; 114 u64 mperf; 115 u64 tsc; 116 u64 time; 117 }; 118 119 /** 120 * struct pstate_data - Store P state data 121 * @current_pstate: Current requested P state 122 * @min_pstate: Min P state possible for this platform 123 * @max_pstate: Max P state possible for this platform 124 * @max_pstate_physical:This is physical Max P state for a processor 125 * This can be higher than the max_pstate which can 126 * be limited by platform thermal design power limits 127 * @scaling: Scaling factor to convert frequency to cpufreq 128 * frequency units 129 * @turbo_pstate: Max Turbo P state possible for this platform 130 * @max_freq: @max_pstate frequency in cpufreq units 131 * @turbo_freq: @turbo_pstate frequency in cpufreq units 132 * 133 * Stores the per cpu model P state limits and current P state. 134 */ 135 struct pstate_data { 136 int current_pstate; 137 int min_pstate; 138 int max_pstate; 139 int max_pstate_physical; 140 int scaling; 141 int turbo_pstate; 142 unsigned int max_freq; 143 unsigned int turbo_freq; 144 }; 145 146 /** 147 * struct vid_data - Stores voltage information data 148 * @min: VID data for this platform corresponding to 149 * the lowest P state 150 * @max: VID data corresponding to the highest P State. 151 * @turbo: VID data for turbo P state 152 * @ratio: Ratio of (vid max - vid min) / 153 * (max P state - Min P State) 154 * 155 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling) 156 * This data is used in Atom platforms, where in addition to target P state, 157 * the voltage data needs to be specified to select next P State. 158 */ 159 struct vid_data { 160 int min; 161 int max; 162 int turbo; 163 int32_t ratio; 164 }; 165 166 /** 167 * struct _pid - Stores PID data 168 * @setpoint: Target set point for busyness or performance 169 * @integral: Storage for accumulated error values 170 * @p_gain: PID proportional gain 171 * @i_gain: PID integral gain 172 * @d_gain: PID derivative gain 173 * @deadband: PID deadband 174 * @last_err: Last error storage for integral part of PID calculation 175 * 176 * Stores PID coefficients and last error for PID controller. 177 */ 178 struct _pid { 179 int setpoint; 180 int32_t integral; 181 int32_t p_gain; 182 int32_t i_gain; 183 int32_t d_gain; 184 int deadband; 185 int32_t last_err; 186 }; 187 188 /** 189 * struct perf_limits - Store user and policy limits 190 * @no_turbo: User requested turbo state from intel_pstate sysfs 191 * @turbo_disabled: Platform turbo status either from msr 192 * MSR_IA32_MISC_ENABLE or when maximum available pstate 193 * matches the maximum turbo pstate 194 * @max_perf_pct: Effective maximum performance limit in percentage, this 195 * is minimum of either limits enforced by cpufreq policy 196 * or limits from user set limits via intel_pstate sysfs 197 * @min_perf_pct: Effective minimum performance limit in percentage, this 198 * is maximum of either limits enforced by cpufreq policy 199 * or limits from user set limits via intel_pstate sysfs 200 * @max_perf: This is a scaled value between 0 to 255 for max_perf_pct 201 * This value is used to limit max pstate 202 * @min_perf: This is a scaled value between 0 to 255 for min_perf_pct 203 * This value is used to limit min pstate 204 * @max_policy_pct: The maximum performance in percentage enforced by 205 * cpufreq setpolicy interface 206 * @max_sysfs_pct: The maximum performance in percentage enforced by 207 * intel pstate sysfs interface, unused when per cpu 208 * controls are enforced 209 * @min_policy_pct: The minimum performance in percentage enforced by 210 * cpufreq setpolicy interface 211 * @min_sysfs_pct: The minimum performance in percentage enforced by 212 * intel pstate sysfs interface, unused when per cpu 213 * controls are enforced 214 * 215 * Storage for user and policy defined limits. 216 */ 217 struct perf_limits { 218 int no_turbo; 219 int turbo_disabled; 220 int max_perf_pct; 221 int min_perf_pct; 222 int32_t max_perf; 223 int32_t min_perf; 224 int max_policy_pct; 225 int max_sysfs_pct; 226 int min_policy_pct; 227 int min_sysfs_pct; 228 }; 229 230 /** 231 * struct cpudata - Per CPU instance data storage 232 * @cpu: CPU number for this instance data 233 * @policy: CPUFreq policy value 234 * @update_util: CPUFreq utility callback information 235 * @update_util_set: CPUFreq utility callback is set 236 * @iowait_boost: iowait-related boost fraction 237 * @last_update: Time of the last update. 238 * @pstate: Stores P state limits for this CPU 239 * @vid: Stores VID limits for this CPU 240 * @pid: Stores PID parameters for this CPU 241 * @last_sample_time: Last Sample time 242 * @prev_aperf: Last APERF value read from APERF MSR 243 * @prev_mperf: Last MPERF value read from MPERF MSR 244 * @prev_tsc: Last timestamp counter (TSC) value 245 * @prev_cummulative_iowait: IO Wait time difference from last and 246 * current sample 247 * @sample: Storage for storing last Sample data 248 * @perf_limits: Pointer to perf_limit unique to this CPU 249 * Not all field in the structure are applicable 250 * when per cpu controls are enforced 251 * @acpi_perf_data: Stores ACPI perf information read from _PSS 252 * @valid_pss_table: Set to true for valid ACPI _PSS entries found 253 * @epp_powersave: Last saved HWP energy performance preference 254 * (EPP) or energy performance bias (EPB), 255 * when policy switched to performance 256 * @epp_policy: Last saved policy used to set EPP/EPB 257 * @epp_default: Power on default HWP energy performance 258 * preference/bias 259 * @epp_saved: Saved EPP/EPB during system suspend or CPU offline 260 * operation 261 * 262 * This structure stores per CPU instance data for all CPUs. 263 */ 264 struct cpudata { 265 int cpu; 266 267 unsigned int policy; 268 struct update_util_data update_util; 269 bool update_util_set; 270 271 struct pstate_data pstate; 272 struct vid_data vid; 273 struct _pid pid; 274 275 u64 last_update; 276 u64 last_sample_time; 277 u64 prev_aperf; 278 u64 prev_mperf; 279 u64 prev_tsc; 280 u64 prev_cummulative_iowait; 281 struct sample sample; 282 struct perf_limits *perf_limits; 283 #ifdef CONFIG_ACPI 284 struct acpi_processor_performance acpi_perf_data; 285 bool valid_pss_table; 286 #endif 287 unsigned int iowait_boost; 288 s16 epp_powersave; 289 s16 epp_policy; 290 s16 epp_default; 291 s16 epp_saved; 292 }; 293 294 static struct cpudata **all_cpu_data; 295 296 /** 297 * struct pstate_adjust_policy - Stores static PID configuration data 298 * @sample_rate_ms: PID calculation sample rate in ms 299 * @sample_rate_ns: Sample rate calculation in ns 300 * @deadband: PID deadband 301 * @setpoint: PID Setpoint 302 * @p_gain_pct: PID proportional gain 303 * @i_gain_pct: PID integral gain 304 * @d_gain_pct: PID derivative gain 305 * 306 * Stores per CPU model static PID configuration data. 307 */ 308 struct pstate_adjust_policy { 309 int sample_rate_ms; 310 s64 sample_rate_ns; 311 int deadband; 312 int setpoint; 313 int p_gain_pct; 314 int d_gain_pct; 315 int i_gain_pct; 316 }; 317 318 /** 319 * struct pstate_funcs - Per CPU model specific callbacks 320 * @get_max: Callback to get maximum non turbo effective P state 321 * @get_max_physical: Callback to get maximum non turbo physical P state 322 * @get_min: Callback to get minimum P state 323 * @get_turbo: Callback to get turbo P state 324 * @get_scaling: Callback to get frequency scaling factor 325 * @get_val: Callback to convert P state to actual MSR write value 326 * @get_vid: Callback to get VID data for Atom platforms 327 * @get_target_pstate: Callback to a function to calculate next P state to use 328 * 329 * Core and Atom CPU models have different way to get P State limits. This 330 * structure is used to store those callbacks. 331 */ 332 struct pstate_funcs { 333 int (*get_max)(void); 334 int (*get_max_physical)(void); 335 int (*get_min)(void); 336 int (*get_turbo)(void); 337 int (*get_scaling)(void); 338 u64 (*get_val)(struct cpudata*, int pstate); 339 void (*get_vid)(struct cpudata *); 340 int32_t (*get_target_pstate)(struct cpudata *); 341 }; 342 343 /** 344 * struct cpu_defaults- Per CPU model default config data 345 * @pid_policy: PID config data 346 * @funcs: Callback function data 347 */ 348 struct cpu_defaults { 349 struct pstate_adjust_policy pid_policy; 350 struct pstate_funcs funcs; 351 }; 352 353 static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu); 354 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu); 355 356 static struct pstate_adjust_policy pid_params __read_mostly; 357 static struct pstate_funcs pstate_funcs __read_mostly; 358 static int hwp_active __read_mostly; 359 static bool per_cpu_limits __read_mostly; 360 361 #ifdef CONFIG_ACPI 362 static bool acpi_ppc; 363 #endif 364 365 static struct perf_limits performance_limits = { 366 .no_turbo = 0, 367 .turbo_disabled = 0, 368 .max_perf_pct = 100, 369 .max_perf = int_ext_tofp(1), 370 .min_perf_pct = 100, 371 .min_perf = int_ext_tofp(1), 372 .max_policy_pct = 100, 373 .max_sysfs_pct = 100, 374 .min_policy_pct = 0, 375 .min_sysfs_pct = 0, 376 }; 377 378 static struct perf_limits powersave_limits = { 379 .no_turbo = 0, 380 .turbo_disabled = 0, 381 .max_perf_pct = 100, 382 .max_perf = int_ext_tofp(1), 383 .min_perf_pct = 0, 384 .min_perf = 0, 385 .max_policy_pct = 100, 386 .max_sysfs_pct = 100, 387 .min_policy_pct = 0, 388 .min_sysfs_pct = 0, 389 }; 390 391 #ifdef CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE 392 static struct perf_limits *limits = &performance_limits; 393 #else 394 static struct perf_limits *limits = &powersave_limits; 395 #endif 396 397 static DEFINE_MUTEX(intel_pstate_limits_lock); 398 399 #ifdef CONFIG_ACPI 400 401 static bool intel_pstate_get_ppc_enable_status(void) 402 { 403 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER || 404 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER) 405 return true; 406 407 return acpi_ppc; 408 } 409 410 #ifdef CONFIG_ACPI_CPPC_LIB 411 412 /* The work item is needed to avoid CPU hotplug locking issues */ 413 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work) 414 { 415 sched_set_itmt_support(); 416 } 417 418 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn); 419 420 static void intel_pstate_set_itmt_prio(int cpu) 421 { 422 struct cppc_perf_caps cppc_perf; 423 static u32 max_highest_perf = 0, min_highest_perf = U32_MAX; 424 int ret; 425 426 ret = cppc_get_perf_caps(cpu, &cppc_perf); 427 if (ret) 428 return; 429 430 /* 431 * The priorities can be set regardless of whether or not 432 * sched_set_itmt_support(true) has been called and it is valid to 433 * update them at any time after it has been called. 434 */ 435 sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu); 436 437 if (max_highest_perf <= min_highest_perf) { 438 if (cppc_perf.highest_perf > max_highest_perf) 439 max_highest_perf = cppc_perf.highest_perf; 440 441 if (cppc_perf.highest_perf < min_highest_perf) 442 min_highest_perf = cppc_perf.highest_perf; 443 444 if (max_highest_perf > min_highest_perf) { 445 /* 446 * This code can be run during CPU online under the 447 * CPU hotplug locks, so sched_set_itmt_support() 448 * cannot be called from here. Queue up a work item 449 * to invoke it. 450 */ 451 schedule_work(&sched_itmt_work); 452 } 453 } 454 } 455 #else 456 static void intel_pstate_set_itmt_prio(int cpu) 457 { 458 } 459 #endif 460 461 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) 462 { 463 struct cpudata *cpu; 464 int ret; 465 int i; 466 467 if (hwp_active) { 468 intel_pstate_set_itmt_prio(policy->cpu); 469 return; 470 } 471 472 if (!intel_pstate_get_ppc_enable_status()) 473 return; 474 475 cpu = all_cpu_data[policy->cpu]; 476 477 ret = acpi_processor_register_performance(&cpu->acpi_perf_data, 478 policy->cpu); 479 if (ret) 480 return; 481 482 /* 483 * Check if the control value in _PSS is for PERF_CTL MSR, which should 484 * guarantee that the states returned by it map to the states in our 485 * list directly. 486 */ 487 if (cpu->acpi_perf_data.control_register.space_id != 488 ACPI_ADR_SPACE_FIXED_HARDWARE) 489 goto err; 490 491 /* 492 * If there is only one entry _PSS, simply ignore _PSS and continue as 493 * usual without taking _PSS into account 494 */ 495 if (cpu->acpi_perf_data.state_count < 2) 496 goto err; 497 498 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu); 499 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) { 500 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n", 501 (i == cpu->acpi_perf_data.state ? '*' : ' '), i, 502 (u32) cpu->acpi_perf_data.states[i].core_frequency, 503 (u32) cpu->acpi_perf_data.states[i].power, 504 (u32) cpu->acpi_perf_data.states[i].control); 505 } 506 507 /* 508 * The _PSS table doesn't contain whole turbo frequency range. 509 * This just contains +1 MHZ above the max non turbo frequency, 510 * with control value corresponding to max turbo ratio. But 511 * when cpufreq set policy is called, it will call with this 512 * max frequency, which will cause a reduced performance as 513 * this driver uses real max turbo frequency as the max 514 * frequency. So correct this frequency in _PSS table to 515 * correct max turbo frequency based on the turbo state. 516 * Also need to convert to MHz as _PSS freq is in MHz. 517 */ 518 if (!limits->turbo_disabled) 519 cpu->acpi_perf_data.states[0].core_frequency = 520 policy->cpuinfo.max_freq / 1000; 521 cpu->valid_pss_table = true; 522 pr_debug("_PPC limits will be enforced\n"); 523 524 return; 525 526 err: 527 cpu->valid_pss_table = false; 528 acpi_processor_unregister_performance(policy->cpu); 529 } 530 531 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) 532 { 533 struct cpudata *cpu; 534 535 cpu = all_cpu_data[policy->cpu]; 536 if (!cpu->valid_pss_table) 537 return; 538 539 acpi_processor_unregister_performance(policy->cpu); 540 } 541 542 #else 543 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) 544 { 545 } 546 547 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) 548 { 549 } 550 #endif 551 552 static inline void pid_reset(struct _pid *pid, int setpoint, int busy, 553 int deadband, int integral) { 554 pid->setpoint = int_tofp(setpoint); 555 pid->deadband = int_tofp(deadband); 556 pid->integral = int_tofp(integral); 557 pid->last_err = int_tofp(setpoint) - int_tofp(busy); 558 } 559 560 static inline void pid_p_gain_set(struct _pid *pid, int percent) 561 { 562 pid->p_gain = div_fp(percent, 100); 563 } 564 565 static inline void pid_i_gain_set(struct _pid *pid, int percent) 566 { 567 pid->i_gain = div_fp(percent, 100); 568 } 569 570 static inline void pid_d_gain_set(struct _pid *pid, int percent) 571 { 572 pid->d_gain = div_fp(percent, 100); 573 } 574 575 static signed int pid_calc(struct _pid *pid, int32_t busy) 576 { 577 signed int result; 578 int32_t pterm, dterm, fp_error; 579 int32_t integral_limit; 580 581 fp_error = pid->setpoint - busy; 582 583 if (abs(fp_error) <= pid->deadband) 584 return 0; 585 586 pterm = mul_fp(pid->p_gain, fp_error); 587 588 pid->integral += fp_error; 589 590 /* 591 * We limit the integral here so that it will never 592 * get higher than 30. This prevents it from becoming 593 * too large an input over long periods of time and allows 594 * it to get factored out sooner. 595 * 596 * The value of 30 was chosen through experimentation. 597 */ 598 integral_limit = int_tofp(30); 599 if (pid->integral > integral_limit) 600 pid->integral = integral_limit; 601 if (pid->integral < -integral_limit) 602 pid->integral = -integral_limit; 603 604 dterm = mul_fp(pid->d_gain, fp_error - pid->last_err); 605 pid->last_err = fp_error; 606 607 result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm; 608 result = result + (1 << (FRAC_BITS-1)); 609 return (signed int)fp_toint(result); 610 } 611 612 static inline void intel_pstate_busy_pid_reset(struct cpudata *cpu) 613 { 614 pid_p_gain_set(&cpu->pid, pid_params.p_gain_pct); 615 pid_d_gain_set(&cpu->pid, pid_params.d_gain_pct); 616 pid_i_gain_set(&cpu->pid, pid_params.i_gain_pct); 617 618 pid_reset(&cpu->pid, pid_params.setpoint, 100, pid_params.deadband, 0); 619 } 620 621 static inline void intel_pstate_reset_all_pid(void) 622 { 623 unsigned int cpu; 624 625 for_each_online_cpu(cpu) { 626 if (all_cpu_data[cpu]) 627 intel_pstate_busy_pid_reset(all_cpu_data[cpu]); 628 } 629 } 630 631 static inline void update_turbo_state(void) 632 { 633 u64 misc_en; 634 struct cpudata *cpu; 635 636 cpu = all_cpu_data[0]; 637 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en); 638 limits->turbo_disabled = 639 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE || 640 cpu->pstate.max_pstate == cpu->pstate.turbo_pstate); 641 } 642 643 static s16 intel_pstate_get_epb(struct cpudata *cpu_data) 644 { 645 u64 epb; 646 int ret; 647 648 if (!static_cpu_has(X86_FEATURE_EPB)) 649 return -ENXIO; 650 651 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb); 652 if (ret) 653 return (s16)ret; 654 655 return (s16)(epb & 0x0f); 656 } 657 658 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data) 659 { 660 s16 epp; 661 662 if (static_cpu_has(X86_FEATURE_HWP_EPP)) { 663 /* 664 * When hwp_req_data is 0, means that caller didn't read 665 * MSR_HWP_REQUEST, so need to read and get EPP. 666 */ 667 if (!hwp_req_data) { 668 epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, 669 &hwp_req_data); 670 if (epp) 671 return epp; 672 } 673 epp = (hwp_req_data >> 24) & 0xff; 674 } else { 675 /* When there is no EPP present, HWP uses EPB settings */ 676 epp = intel_pstate_get_epb(cpu_data); 677 } 678 679 return epp; 680 } 681 682 static int intel_pstate_set_epb(int cpu, s16 pref) 683 { 684 u64 epb; 685 int ret; 686 687 if (!static_cpu_has(X86_FEATURE_EPB)) 688 return -ENXIO; 689 690 ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb); 691 if (ret) 692 return ret; 693 694 epb = (epb & ~0x0f) | pref; 695 wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb); 696 697 return 0; 698 } 699 700 /* 701 * EPP/EPB display strings corresponding to EPP index in the 702 * energy_perf_strings[] 703 * index String 704 *------------------------------------- 705 * 0 default 706 * 1 performance 707 * 2 balance_performance 708 * 3 balance_power 709 * 4 power 710 */ 711 static const char * const energy_perf_strings[] = { 712 "default", 713 "performance", 714 "balance_performance", 715 "balance_power", 716 "power", 717 NULL 718 }; 719 720 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data) 721 { 722 s16 epp; 723 int index = -EINVAL; 724 725 epp = intel_pstate_get_epp(cpu_data, 0); 726 if (epp < 0) 727 return epp; 728 729 if (static_cpu_has(X86_FEATURE_HWP_EPP)) { 730 /* 731 * Range: 732 * 0x00-0x3F : Performance 733 * 0x40-0x7F : Balance performance 734 * 0x80-0xBF : Balance power 735 * 0xC0-0xFF : Power 736 * The EPP is a 8 bit value, but our ranges restrict the 737 * value which can be set. Here only using top two bits 738 * effectively. 739 */ 740 index = (epp >> 6) + 1; 741 } else if (static_cpu_has(X86_FEATURE_EPB)) { 742 /* 743 * Range: 744 * 0x00-0x03 : Performance 745 * 0x04-0x07 : Balance performance 746 * 0x08-0x0B : Balance power 747 * 0x0C-0x0F : Power 748 * The EPB is a 4 bit value, but our ranges restrict the 749 * value which can be set. Here only using top two bits 750 * effectively. 751 */ 752 index = (epp >> 2) + 1; 753 } 754 755 return index; 756 } 757 758 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data, 759 int pref_index) 760 { 761 int epp = -EINVAL; 762 int ret; 763 764 if (!pref_index) 765 epp = cpu_data->epp_default; 766 767 mutex_lock(&intel_pstate_limits_lock); 768 769 if (static_cpu_has(X86_FEATURE_HWP_EPP)) { 770 u64 value; 771 772 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, &value); 773 if (ret) 774 goto return_pref; 775 776 value &= ~GENMASK_ULL(31, 24); 777 778 /* 779 * If epp is not default, convert from index into 780 * energy_perf_strings to epp value, by shifting 6 781 * bits left to use only top two bits in epp. 782 * The resultant epp need to shifted by 24 bits to 783 * epp position in MSR_HWP_REQUEST. 784 */ 785 if (epp == -EINVAL) 786 epp = (pref_index - 1) << 6; 787 788 value |= (u64)epp << 24; 789 ret = wrmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, value); 790 } else { 791 if (epp == -EINVAL) 792 epp = (pref_index - 1) << 2; 793 ret = intel_pstate_set_epb(cpu_data->cpu, epp); 794 } 795 return_pref: 796 mutex_unlock(&intel_pstate_limits_lock); 797 798 return ret; 799 } 800 801 static ssize_t show_energy_performance_available_preferences( 802 struct cpufreq_policy *policy, char *buf) 803 { 804 int i = 0; 805 int ret = 0; 806 807 while (energy_perf_strings[i] != NULL) 808 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]); 809 810 ret += sprintf(&buf[ret], "\n"); 811 812 return ret; 813 } 814 815 cpufreq_freq_attr_ro(energy_performance_available_preferences); 816 817 static ssize_t store_energy_performance_preference( 818 struct cpufreq_policy *policy, const char *buf, size_t count) 819 { 820 struct cpudata *cpu_data = all_cpu_data[policy->cpu]; 821 char str_preference[21]; 822 int ret, i = 0; 823 824 ret = sscanf(buf, "%20s", str_preference); 825 if (ret != 1) 826 return -EINVAL; 827 828 while (energy_perf_strings[i] != NULL) { 829 if (!strcmp(str_preference, energy_perf_strings[i])) { 830 intel_pstate_set_energy_pref_index(cpu_data, i); 831 return count; 832 } 833 ++i; 834 } 835 836 return -EINVAL; 837 } 838 839 static ssize_t show_energy_performance_preference( 840 struct cpufreq_policy *policy, char *buf) 841 { 842 struct cpudata *cpu_data = all_cpu_data[policy->cpu]; 843 int preference; 844 845 preference = intel_pstate_get_energy_pref_index(cpu_data); 846 if (preference < 0) 847 return preference; 848 849 return sprintf(buf, "%s\n", energy_perf_strings[preference]); 850 } 851 852 cpufreq_freq_attr_rw(energy_performance_preference); 853 854 static struct freq_attr *hwp_cpufreq_attrs[] = { 855 &energy_performance_preference, 856 &energy_performance_available_preferences, 857 NULL, 858 }; 859 860 static void intel_pstate_hwp_set(const struct cpumask *cpumask) 861 { 862 int min, hw_min, max, hw_max, cpu, range, adj_range; 863 struct perf_limits *perf_limits = limits; 864 u64 value, cap; 865 866 for_each_cpu(cpu, cpumask) { 867 int max_perf_pct, min_perf_pct; 868 struct cpudata *cpu_data = all_cpu_data[cpu]; 869 s16 epp; 870 871 if (per_cpu_limits) 872 perf_limits = all_cpu_data[cpu]->perf_limits; 873 874 rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap); 875 hw_min = HWP_LOWEST_PERF(cap); 876 hw_max = HWP_HIGHEST_PERF(cap); 877 range = hw_max - hw_min; 878 879 max_perf_pct = perf_limits->max_perf_pct; 880 min_perf_pct = perf_limits->min_perf_pct; 881 882 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value); 883 adj_range = min_perf_pct * range / 100; 884 min = hw_min + adj_range; 885 value &= ~HWP_MIN_PERF(~0L); 886 value |= HWP_MIN_PERF(min); 887 888 adj_range = max_perf_pct * range / 100; 889 max = hw_min + adj_range; 890 if (limits->no_turbo) { 891 hw_max = HWP_GUARANTEED_PERF(cap); 892 if (hw_max < max) 893 max = hw_max; 894 } 895 896 value &= ~HWP_MAX_PERF(~0L); 897 value |= HWP_MAX_PERF(max); 898 899 if (cpu_data->epp_policy == cpu_data->policy) 900 goto skip_epp; 901 902 cpu_data->epp_policy = cpu_data->policy; 903 904 if (cpu_data->epp_saved >= 0) { 905 epp = cpu_data->epp_saved; 906 cpu_data->epp_saved = -EINVAL; 907 goto update_epp; 908 } 909 910 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) { 911 epp = intel_pstate_get_epp(cpu_data, value); 912 cpu_data->epp_powersave = epp; 913 /* If EPP read was failed, then don't try to write */ 914 if (epp < 0) 915 goto skip_epp; 916 917 918 epp = 0; 919 } else { 920 /* skip setting EPP, when saved value is invalid */ 921 if (cpu_data->epp_powersave < 0) 922 goto skip_epp; 923 924 /* 925 * No need to restore EPP when it is not zero. This 926 * means: 927 * - Policy is not changed 928 * - user has manually changed 929 * - Error reading EPB 930 */ 931 epp = intel_pstate_get_epp(cpu_data, value); 932 if (epp) 933 goto skip_epp; 934 935 epp = cpu_data->epp_powersave; 936 } 937 update_epp: 938 if (static_cpu_has(X86_FEATURE_HWP_EPP)) { 939 value &= ~GENMASK_ULL(31, 24); 940 value |= (u64)epp << 24; 941 } else { 942 intel_pstate_set_epb(cpu, epp); 943 } 944 skip_epp: 945 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value); 946 } 947 } 948 949 static int intel_pstate_hwp_set_policy(struct cpufreq_policy *policy) 950 { 951 if (hwp_active) 952 intel_pstate_hwp_set(policy->cpus); 953 954 return 0; 955 } 956 957 static int intel_pstate_hwp_save_state(struct cpufreq_policy *policy) 958 { 959 struct cpudata *cpu_data = all_cpu_data[policy->cpu]; 960 961 if (!hwp_active) 962 return 0; 963 964 cpu_data->epp_saved = intel_pstate_get_epp(cpu_data, 0); 965 966 return 0; 967 } 968 969 static int intel_pstate_resume(struct cpufreq_policy *policy) 970 { 971 if (!hwp_active) 972 return 0; 973 974 all_cpu_data[policy->cpu]->epp_policy = 0; 975 976 return intel_pstate_hwp_set_policy(policy); 977 } 978 979 static void intel_pstate_hwp_set_online_cpus(void) 980 { 981 get_online_cpus(); 982 intel_pstate_hwp_set(cpu_online_mask); 983 put_online_cpus(); 984 } 985 986 /************************** debugfs begin ************************/ 987 static int pid_param_set(void *data, u64 val) 988 { 989 *(u32 *)data = val; 990 intel_pstate_reset_all_pid(); 991 return 0; 992 } 993 994 static int pid_param_get(void *data, u64 *val) 995 { 996 *val = *(u32 *)data; 997 return 0; 998 } 999 DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get, pid_param_set, "%llu\n"); 1000 1001 struct pid_param { 1002 char *name; 1003 void *value; 1004 }; 1005 1006 static struct pid_param pid_files[] = { 1007 {"sample_rate_ms", &pid_params.sample_rate_ms}, 1008 {"d_gain_pct", &pid_params.d_gain_pct}, 1009 {"i_gain_pct", &pid_params.i_gain_pct}, 1010 {"deadband", &pid_params.deadband}, 1011 {"setpoint", &pid_params.setpoint}, 1012 {"p_gain_pct", &pid_params.p_gain_pct}, 1013 {NULL, NULL} 1014 }; 1015 1016 static void __init intel_pstate_debug_expose_params(void) 1017 { 1018 struct dentry *debugfs_parent; 1019 int i = 0; 1020 1021 if (hwp_active || 1022 pstate_funcs.get_target_pstate == get_target_pstate_use_cpu_load) 1023 return; 1024 1025 debugfs_parent = debugfs_create_dir("pstate_snb", NULL); 1026 if (IS_ERR_OR_NULL(debugfs_parent)) 1027 return; 1028 while (pid_files[i].name) { 1029 debugfs_create_file(pid_files[i].name, 0660, 1030 debugfs_parent, pid_files[i].value, 1031 &fops_pid_param); 1032 i++; 1033 } 1034 } 1035 1036 /************************** debugfs end ************************/ 1037 1038 /************************** sysfs begin ************************/ 1039 #define show_one(file_name, object) \ 1040 static ssize_t show_##file_name \ 1041 (struct kobject *kobj, struct attribute *attr, char *buf) \ 1042 { \ 1043 return sprintf(buf, "%u\n", limits->object); \ 1044 } 1045 1046 static ssize_t show_turbo_pct(struct kobject *kobj, 1047 struct attribute *attr, char *buf) 1048 { 1049 struct cpudata *cpu; 1050 int total, no_turbo, turbo_pct; 1051 uint32_t turbo_fp; 1052 1053 cpu = all_cpu_data[0]; 1054 1055 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; 1056 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1; 1057 turbo_fp = div_fp(no_turbo, total); 1058 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100))); 1059 return sprintf(buf, "%u\n", turbo_pct); 1060 } 1061 1062 static ssize_t show_num_pstates(struct kobject *kobj, 1063 struct attribute *attr, char *buf) 1064 { 1065 struct cpudata *cpu; 1066 int total; 1067 1068 cpu = all_cpu_data[0]; 1069 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; 1070 return sprintf(buf, "%u\n", total); 1071 } 1072 1073 static ssize_t show_no_turbo(struct kobject *kobj, 1074 struct attribute *attr, char *buf) 1075 { 1076 ssize_t ret; 1077 1078 update_turbo_state(); 1079 if (limits->turbo_disabled) 1080 ret = sprintf(buf, "%u\n", limits->turbo_disabled); 1081 else 1082 ret = sprintf(buf, "%u\n", limits->no_turbo); 1083 1084 return ret; 1085 } 1086 1087 static ssize_t store_no_turbo(struct kobject *a, struct attribute *b, 1088 const char *buf, size_t count) 1089 { 1090 unsigned int input; 1091 int ret; 1092 1093 ret = sscanf(buf, "%u", &input); 1094 if (ret != 1) 1095 return -EINVAL; 1096 1097 mutex_lock(&intel_pstate_limits_lock); 1098 1099 update_turbo_state(); 1100 if (limits->turbo_disabled) { 1101 pr_warn("Turbo disabled by BIOS or unavailable on processor\n"); 1102 mutex_unlock(&intel_pstate_limits_lock); 1103 return -EPERM; 1104 } 1105 1106 limits->no_turbo = clamp_t(int, input, 0, 1); 1107 1108 if (hwp_active) 1109 intel_pstate_hwp_set_online_cpus(); 1110 1111 mutex_unlock(&intel_pstate_limits_lock); 1112 1113 return count; 1114 } 1115 1116 static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b, 1117 const char *buf, size_t count) 1118 { 1119 unsigned int input; 1120 int ret; 1121 1122 ret = sscanf(buf, "%u", &input); 1123 if (ret != 1) 1124 return -EINVAL; 1125 1126 mutex_lock(&intel_pstate_limits_lock); 1127 1128 limits->max_sysfs_pct = clamp_t(int, input, 0 , 100); 1129 limits->max_perf_pct = min(limits->max_policy_pct, 1130 limits->max_sysfs_pct); 1131 limits->max_perf_pct = max(limits->min_policy_pct, 1132 limits->max_perf_pct); 1133 limits->max_perf_pct = max(limits->min_perf_pct, 1134 limits->max_perf_pct); 1135 limits->max_perf = div_ext_fp(limits->max_perf_pct, 100); 1136 1137 if (hwp_active) 1138 intel_pstate_hwp_set_online_cpus(); 1139 1140 mutex_unlock(&intel_pstate_limits_lock); 1141 1142 return count; 1143 } 1144 1145 static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b, 1146 const char *buf, size_t count) 1147 { 1148 unsigned int input; 1149 int ret; 1150 1151 ret = sscanf(buf, "%u", &input); 1152 if (ret != 1) 1153 return -EINVAL; 1154 1155 mutex_lock(&intel_pstate_limits_lock); 1156 1157 limits->min_sysfs_pct = clamp_t(int, input, 0 , 100); 1158 limits->min_perf_pct = max(limits->min_policy_pct, 1159 limits->min_sysfs_pct); 1160 limits->min_perf_pct = min(limits->max_policy_pct, 1161 limits->min_perf_pct); 1162 limits->min_perf_pct = min(limits->max_perf_pct, 1163 limits->min_perf_pct); 1164 limits->min_perf = div_ext_fp(limits->min_perf_pct, 100); 1165 1166 if (hwp_active) 1167 intel_pstate_hwp_set_online_cpus(); 1168 1169 mutex_unlock(&intel_pstate_limits_lock); 1170 1171 return count; 1172 } 1173 1174 show_one(max_perf_pct, max_perf_pct); 1175 show_one(min_perf_pct, min_perf_pct); 1176 1177 define_one_global_rw(no_turbo); 1178 define_one_global_rw(max_perf_pct); 1179 define_one_global_rw(min_perf_pct); 1180 define_one_global_ro(turbo_pct); 1181 define_one_global_ro(num_pstates); 1182 1183 static struct attribute *intel_pstate_attributes[] = { 1184 &no_turbo.attr, 1185 &turbo_pct.attr, 1186 &num_pstates.attr, 1187 NULL 1188 }; 1189 1190 static struct attribute_group intel_pstate_attr_group = { 1191 .attrs = intel_pstate_attributes, 1192 }; 1193 1194 static void __init intel_pstate_sysfs_expose_params(void) 1195 { 1196 struct kobject *intel_pstate_kobject; 1197 int rc; 1198 1199 intel_pstate_kobject = kobject_create_and_add("intel_pstate", 1200 &cpu_subsys.dev_root->kobj); 1201 if (WARN_ON(!intel_pstate_kobject)) 1202 return; 1203 1204 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group); 1205 if (WARN_ON(rc)) 1206 return; 1207 1208 /* 1209 * If per cpu limits are enforced there are no global limits, so 1210 * return without creating max/min_perf_pct attributes 1211 */ 1212 if (per_cpu_limits) 1213 return; 1214 1215 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr); 1216 WARN_ON(rc); 1217 1218 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr); 1219 WARN_ON(rc); 1220 1221 } 1222 /************************** sysfs end ************************/ 1223 1224 static void intel_pstate_hwp_enable(struct cpudata *cpudata) 1225 { 1226 /* First disable HWP notification interrupt as we don't process them */ 1227 if (static_cpu_has(X86_FEATURE_HWP_NOTIFY)) 1228 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00); 1229 1230 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1); 1231 cpudata->epp_policy = 0; 1232 if (cpudata->epp_default == -EINVAL) 1233 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0); 1234 } 1235 1236 static int atom_get_min_pstate(void) 1237 { 1238 u64 value; 1239 1240 rdmsrl(ATOM_RATIOS, value); 1241 return (value >> 8) & 0x7F; 1242 } 1243 1244 static int atom_get_max_pstate(void) 1245 { 1246 u64 value; 1247 1248 rdmsrl(ATOM_RATIOS, value); 1249 return (value >> 16) & 0x7F; 1250 } 1251 1252 static int atom_get_turbo_pstate(void) 1253 { 1254 u64 value; 1255 1256 rdmsrl(ATOM_TURBO_RATIOS, value); 1257 return value & 0x7F; 1258 } 1259 1260 static u64 atom_get_val(struct cpudata *cpudata, int pstate) 1261 { 1262 u64 val; 1263 int32_t vid_fp; 1264 u32 vid; 1265 1266 val = (u64)pstate << 8; 1267 if (limits->no_turbo && !limits->turbo_disabled) 1268 val |= (u64)1 << 32; 1269 1270 vid_fp = cpudata->vid.min + mul_fp( 1271 int_tofp(pstate - cpudata->pstate.min_pstate), 1272 cpudata->vid.ratio); 1273 1274 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max); 1275 vid = ceiling_fp(vid_fp); 1276 1277 if (pstate > cpudata->pstate.max_pstate) 1278 vid = cpudata->vid.turbo; 1279 1280 return val | vid; 1281 } 1282 1283 static int silvermont_get_scaling(void) 1284 { 1285 u64 value; 1286 int i; 1287 /* Defined in Table 35-6 from SDM (Sept 2015) */ 1288 static int silvermont_freq_table[] = { 1289 83300, 100000, 133300, 116700, 80000}; 1290 1291 rdmsrl(MSR_FSB_FREQ, value); 1292 i = value & 0x7; 1293 WARN_ON(i > 4); 1294 1295 return silvermont_freq_table[i]; 1296 } 1297 1298 static int airmont_get_scaling(void) 1299 { 1300 u64 value; 1301 int i; 1302 /* Defined in Table 35-10 from SDM (Sept 2015) */ 1303 static int airmont_freq_table[] = { 1304 83300, 100000, 133300, 116700, 80000, 1305 93300, 90000, 88900, 87500}; 1306 1307 rdmsrl(MSR_FSB_FREQ, value); 1308 i = value & 0xF; 1309 WARN_ON(i > 8); 1310 1311 return airmont_freq_table[i]; 1312 } 1313 1314 static void atom_get_vid(struct cpudata *cpudata) 1315 { 1316 u64 value; 1317 1318 rdmsrl(ATOM_VIDS, value); 1319 cpudata->vid.min = int_tofp((value >> 8) & 0x7f); 1320 cpudata->vid.max = int_tofp((value >> 16) & 0x7f); 1321 cpudata->vid.ratio = div_fp( 1322 cpudata->vid.max - cpudata->vid.min, 1323 int_tofp(cpudata->pstate.max_pstate - 1324 cpudata->pstate.min_pstate)); 1325 1326 rdmsrl(ATOM_TURBO_VIDS, value); 1327 cpudata->vid.turbo = value & 0x7f; 1328 } 1329 1330 static int core_get_min_pstate(void) 1331 { 1332 u64 value; 1333 1334 rdmsrl(MSR_PLATFORM_INFO, value); 1335 return (value >> 40) & 0xFF; 1336 } 1337 1338 static int core_get_max_pstate_physical(void) 1339 { 1340 u64 value; 1341 1342 rdmsrl(MSR_PLATFORM_INFO, value); 1343 return (value >> 8) & 0xFF; 1344 } 1345 1346 static int core_get_max_pstate(void) 1347 { 1348 u64 tar; 1349 u64 plat_info; 1350 int max_pstate; 1351 int err; 1352 1353 rdmsrl(MSR_PLATFORM_INFO, plat_info); 1354 max_pstate = (plat_info >> 8) & 0xFF; 1355 1356 err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar); 1357 if (!err) { 1358 /* Do some sanity checking for safety */ 1359 if (plat_info & 0x600000000) { 1360 u64 tdp_ctrl; 1361 u64 tdp_ratio; 1362 int tdp_msr; 1363 1364 err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl); 1365 if (err) 1366 goto skip_tar; 1367 1368 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x3); 1369 err = rdmsrl_safe(tdp_msr, &tdp_ratio); 1370 if (err) 1371 goto skip_tar; 1372 1373 /* For level 1 and 2, bits[23:16] contain the ratio */ 1374 if (tdp_ctrl) 1375 tdp_ratio >>= 16; 1376 1377 tdp_ratio &= 0xff; /* ratios are only 8 bits long */ 1378 if (tdp_ratio - 1 == tar) { 1379 max_pstate = tar; 1380 pr_debug("max_pstate=TAC %x\n", max_pstate); 1381 } else { 1382 goto skip_tar; 1383 } 1384 } 1385 } 1386 1387 skip_tar: 1388 return max_pstate; 1389 } 1390 1391 static int core_get_turbo_pstate(void) 1392 { 1393 u64 value; 1394 int nont, ret; 1395 1396 rdmsrl(MSR_TURBO_RATIO_LIMIT, value); 1397 nont = core_get_max_pstate(); 1398 ret = (value) & 255; 1399 if (ret <= nont) 1400 ret = nont; 1401 return ret; 1402 } 1403 1404 static inline int core_get_scaling(void) 1405 { 1406 return 100000; 1407 } 1408 1409 static u64 core_get_val(struct cpudata *cpudata, int pstate) 1410 { 1411 u64 val; 1412 1413 val = (u64)pstate << 8; 1414 if (limits->no_turbo && !limits->turbo_disabled) 1415 val |= (u64)1 << 32; 1416 1417 return val; 1418 } 1419 1420 static int knl_get_turbo_pstate(void) 1421 { 1422 u64 value; 1423 int nont, ret; 1424 1425 rdmsrl(MSR_TURBO_RATIO_LIMIT, value); 1426 nont = core_get_max_pstate(); 1427 ret = (((value) >> 8) & 0xFF); 1428 if (ret <= nont) 1429 ret = nont; 1430 return ret; 1431 } 1432 1433 static struct cpu_defaults core_params = { 1434 .pid_policy = { 1435 .sample_rate_ms = 10, 1436 .deadband = 0, 1437 .setpoint = 97, 1438 .p_gain_pct = 20, 1439 .d_gain_pct = 0, 1440 .i_gain_pct = 0, 1441 }, 1442 .funcs = { 1443 .get_max = core_get_max_pstate, 1444 .get_max_physical = core_get_max_pstate_physical, 1445 .get_min = core_get_min_pstate, 1446 .get_turbo = core_get_turbo_pstate, 1447 .get_scaling = core_get_scaling, 1448 .get_val = core_get_val, 1449 .get_target_pstate = get_target_pstate_use_performance, 1450 }, 1451 }; 1452 1453 static const struct cpu_defaults silvermont_params = { 1454 .pid_policy = { 1455 .sample_rate_ms = 10, 1456 .deadband = 0, 1457 .setpoint = 60, 1458 .p_gain_pct = 14, 1459 .d_gain_pct = 0, 1460 .i_gain_pct = 4, 1461 }, 1462 .funcs = { 1463 .get_max = atom_get_max_pstate, 1464 .get_max_physical = atom_get_max_pstate, 1465 .get_min = atom_get_min_pstate, 1466 .get_turbo = atom_get_turbo_pstate, 1467 .get_val = atom_get_val, 1468 .get_scaling = silvermont_get_scaling, 1469 .get_vid = atom_get_vid, 1470 .get_target_pstate = get_target_pstate_use_cpu_load, 1471 }, 1472 }; 1473 1474 static const struct cpu_defaults airmont_params = { 1475 .pid_policy = { 1476 .sample_rate_ms = 10, 1477 .deadband = 0, 1478 .setpoint = 60, 1479 .p_gain_pct = 14, 1480 .d_gain_pct = 0, 1481 .i_gain_pct = 4, 1482 }, 1483 .funcs = { 1484 .get_max = atom_get_max_pstate, 1485 .get_max_physical = atom_get_max_pstate, 1486 .get_min = atom_get_min_pstate, 1487 .get_turbo = atom_get_turbo_pstate, 1488 .get_val = atom_get_val, 1489 .get_scaling = airmont_get_scaling, 1490 .get_vid = atom_get_vid, 1491 .get_target_pstate = get_target_pstate_use_cpu_load, 1492 }, 1493 }; 1494 1495 static const struct cpu_defaults knl_params = { 1496 .pid_policy = { 1497 .sample_rate_ms = 10, 1498 .deadband = 0, 1499 .setpoint = 97, 1500 .p_gain_pct = 20, 1501 .d_gain_pct = 0, 1502 .i_gain_pct = 0, 1503 }, 1504 .funcs = { 1505 .get_max = core_get_max_pstate, 1506 .get_max_physical = core_get_max_pstate_physical, 1507 .get_min = core_get_min_pstate, 1508 .get_turbo = knl_get_turbo_pstate, 1509 .get_scaling = core_get_scaling, 1510 .get_val = core_get_val, 1511 .get_target_pstate = get_target_pstate_use_performance, 1512 }, 1513 }; 1514 1515 static const struct cpu_defaults bxt_params = { 1516 .pid_policy = { 1517 .sample_rate_ms = 10, 1518 .deadband = 0, 1519 .setpoint = 60, 1520 .p_gain_pct = 14, 1521 .d_gain_pct = 0, 1522 .i_gain_pct = 4, 1523 }, 1524 .funcs = { 1525 .get_max = core_get_max_pstate, 1526 .get_max_physical = core_get_max_pstate_physical, 1527 .get_min = core_get_min_pstate, 1528 .get_turbo = core_get_turbo_pstate, 1529 .get_scaling = core_get_scaling, 1530 .get_val = core_get_val, 1531 .get_target_pstate = get_target_pstate_use_cpu_load, 1532 }, 1533 }; 1534 1535 static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max) 1536 { 1537 int max_perf = cpu->pstate.turbo_pstate; 1538 int max_perf_adj; 1539 int min_perf; 1540 struct perf_limits *perf_limits = limits; 1541 1542 if (limits->no_turbo || limits->turbo_disabled) 1543 max_perf = cpu->pstate.max_pstate; 1544 1545 if (per_cpu_limits) 1546 perf_limits = cpu->perf_limits; 1547 1548 /* 1549 * performance can be limited by user through sysfs, by cpufreq 1550 * policy, or by cpu specific default values determined through 1551 * experimentation. 1552 */ 1553 max_perf_adj = fp_ext_toint(max_perf * perf_limits->max_perf); 1554 *max = clamp_t(int, max_perf_adj, 1555 cpu->pstate.min_pstate, cpu->pstate.turbo_pstate); 1556 1557 min_perf = fp_ext_toint(max_perf * perf_limits->min_perf); 1558 *min = clamp_t(int, min_perf, cpu->pstate.min_pstate, max_perf); 1559 } 1560 1561 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate) 1562 { 1563 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu); 1564 cpu->pstate.current_pstate = pstate; 1565 /* 1566 * Generally, there is no guarantee that this code will always run on 1567 * the CPU being updated, so force the register update to run on the 1568 * right CPU. 1569 */ 1570 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL, 1571 pstate_funcs.get_val(cpu, pstate)); 1572 } 1573 1574 static void intel_pstate_set_min_pstate(struct cpudata *cpu) 1575 { 1576 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate); 1577 } 1578 1579 static void intel_pstate_max_within_limits(struct cpudata *cpu) 1580 { 1581 int min_pstate, max_pstate; 1582 1583 update_turbo_state(); 1584 intel_pstate_get_min_max(cpu, &min_pstate, &max_pstate); 1585 intel_pstate_set_pstate(cpu, max_pstate); 1586 } 1587 1588 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu) 1589 { 1590 cpu->pstate.min_pstate = pstate_funcs.get_min(); 1591 cpu->pstate.max_pstate = pstate_funcs.get_max(); 1592 cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical(); 1593 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(); 1594 cpu->pstate.scaling = pstate_funcs.get_scaling(); 1595 cpu->pstate.max_freq = cpu->pstate.max_pstate * cpu->pstate.scaling; 1596 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * cpu->pstate.scaling; 1597 1598 if (pstate_funcs.get_vid) 1599 pstate_funcs.get_vid(cpu); 1600 1601 intel_pstate_set_min_pstate(cpu); 1602 } 1603 1604 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu) 1605 { 1606 struct sample *sample = &cpu->sample; 1607 1608 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf); 1609 } 1610 1611 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time) 1612 { 1613 u64 aperf, mperf; 1614 unsigned long flags; 1615 u64 tsc; 1616 1617 local_irq_save(flags); 1618 rdmsrl(MSR_IA32_APERF, aperf); 1619 rdmsrl(MSR_IA32_MPERF, mperf); 1620 tsc = rdtsc(); 1621 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) { 1622 local_irq_restore(flags); 1623 return false; 1624 } 1625 local_irq_restore(flags); 1626 1627 cpu->last_sample_time = cpu->sample.time; 1628 cpu->sample.time = time; 1629 cpu->sample.aperf = aperf; 1630 cpu->sample.mperf = mperf; 1631 cpu->sample.tsc = tsc; 1632 cpu->sample.aperf -= cpu->prev_aperf; 1633 cpu->sample.mperf -= cpu->prev_mperf; 1634 cpu->sample.tsc -= cpu->prev_tsc; 1635 1636 cpu->prev_aperf = aperf; 1637 cpu->prev_mperf = mperf; 1638 cpu->prev_tsc = tsc; 1639 /* 1640 * First time this function is invoked in a given cycle, all of the 1641 * previous sample data fields are equal to zero or stale and they must 1642 * be populated with meaningful numbers for things to work, so assume 1643 * that sample.time will always be reset before setting the utilization 1644 * update hook and make the caller skip the sample then. 1645 */ 1646 return !!cpu->last_sample_time; 1647 } 1648 1649 static inline int32_t get_avg_frequency(struct cpudata *cpu) 1650 { 1651 return mul_ext_fp(cpu->sample.core_avg_perf, 1652 cpu->pstate.max_pstate_physical * cpu->pstate.scaling); 1653 } 1654 1655 static inline int32_t get_avg_pstate(struct cpudata *cpu) 1656 { 1657 return mul_ext_fp(cpu->pstate.max_pstate_physical, 1658 cpu->sample.core_avg_perf); 1659 } 1660 1661 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu) 1662 { 1663 struct sample *sample = &cpu->sample; 1664 int32_t busy_frac, boost; 1665 int target, avg_pstate; 1666 1667 busy_frac = div_fp(sample->mperf, sample->tsc); 1668 1669 boost = cpu->iowait_boost; 1670 cpu->iowait_boost >>= 1; 1671 1672 if (busy_frac < boost) 1673 busy_frac = boost; 1674 1675 sample->busy_scaled = busy_frac * 100; 1676 1677 target = limits->no_turbo || limits->turbo_disabled ? 1678 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate; 1679 target += target >> 2; 1680 target = mul_fp(target, busy_frac); 1681 if (target < cpu->pstate.min_pstate) 1682 target = cpu->pstate.min_pstate; 1683 1684 /* 1685 * If the average P-state during the previous cycle was higher than the 1686 * current target, add 50% of the difference to the target to reduce 1687 * possible performance oscillations and offset possible performance 1688 * loss related to moving the workload from one CPU to another within 1689 * a package/module. 1690 */ 1691 avg_pstate = get_avg_pstate(cpu); 1692 if (avg_pstate > target) 1693 target += (avg_pstate - target) >> 1; 1694 1695 return target; 1696 } 1697 1698 static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu) 1699 { 1700 int32_t perf_scaled, max_pstate, current_pstate, sample_ratio; 1701 u64 duration_ns; 1702 1703 /* 1704 * perf_scaled is the ratio of the average P-state during the last 1705 * sampling period to the P-state requested last time (in percent). 1706 * 1707 * That measures the system's response to the previous P-state 1708 * selection. 1709 */ 1710 max_pstate = cpu->pstate.max_pstate_physical; 1711 current_pstate = cpu->pstate.current_pstate; 1712 perf_scaled = mul_ext_fp(cpu->sample.core_avg_perf, 1713 div_fp(100 * max_pstate, current_pstate)); 1714 1715 /* 1716 * Since our utilization update callback will not run unless we are 1717 * in C0, check if the actual elapsed time is significantly greater (3x) 1718 * than our sample interval. If it is, then we were idle for a long 1719 * enough period of time to adjust our performance metric. 1720 */ 1721 duration_ns = cpu->sample.time - cpu->last_sample_time; 1722 if ((s64)duration_ns > pid_params.sample_rate_ns * 3) { 1723 sample_ratio = div_fp(pid_params.sample_rate_ns, duration_ns); 1724 perf_scaled = mul_fp(perf_scaled, sample_ratio); 1725 } else { 1726 sample_ratio = div_fp(100 * cpu->sample.mperf, cpu->sample.tsc); 1727 if (sample_ratio < int_tofp(1)) 1728 perf_scaled = 0; 1729 } 1730 1731 cpu->sample.busy_scaled = perf_scaled; 1732 return cpu->pstate.current_pstate - pid_calc(&cpu->pid, perf_scaled); 1733 } 1734 1735 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate) 1736 { 1737 int max_perf, min_perf; 1738 1739 intel_pstate_get_min_max(cpu, &min_perf, &max_perf); 1740 pstate = clamp_t(int, pstate, min_perf, max_perf); 1741 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu); 1742 return pstate; 1743 } 1744 1745 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate) 1746 { 1747 pstate = intel_pstate_prepare_request(cpu, pstate); 1748 if (pstate == cpu->pstate.current_pstate) 1749 return; 1750 1751 cpu->pstate.current_pstate = pstate; 1752 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate)); 1753 } 1754 1755 static inline void intel_pstate_adjust_busy_pstate(struct cpudata *cpu) 1756 { 1757 int from, target_pstate; 1758 struct sample *sample; 1759 1760 from = cpu->pstate.current_pstate; 1761 1762 target_pstate = cpu->policy == CPUFREQ_POLICY_PERFORMANCE ? 1763 cpu->pstate.turbo_pstate : pstate_funcs.get_target_pstate(cpu); 1764 1765 update_turbo_state(); 1766 1767 intel_pstate_update_pstate(cpu, target_pstate); 1768 1769 sample = &cpu->sample; 1770 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf), 1771 fp_toint(sample->busy_scaled), 1772 from, 1773 cpu->pstate.current_pstate, 1774 sample->mperf, 1775 sample->aperf, 1776 sample->tsc, 1777 get_avg_frequency(cpu), 1778 fp_toint(cpu->iowait_boost * 100)); 1779 } 1780 1781 static void intel_pstate_update_util(struct update_util_data *data, u64 time, 1782 unsigned int flags) 1783 { 1784 struct cpudata *cpu = container_of(data, struct cpudata, update_util); 1785 u64 delta_ns; 1786 1787 if (pstate_funcs.get_target_pstate == get_target_pstate_use_cpu_load) { 1788 if (flags & SCHED_CPUFREQ_IOWAIT) { 1789 cpu->iowait_boost = int_tofp(1); 1790 } else if (cpu->iowait_boost) { 1791 /* Clear iowait_boost if the CPU may have been idle. */ 1792 delta_ns = time - cpu->last_update; 1793 if (delta_ns > TICK_NSEC) 1794 cpu->iowait_boost = 0; 1795 } 1796 cpu->last_update = time; 1797 } 1798 1799 delta_ns = time - cpu->sample.time; 1800 if ((s64)delta_ns >= pid_params.sample_rate_ns) { 1801 bool sample_taken = intel_pstate_sample(cpu, time); 1802 1803 if (sample_taken) { 1804 intel_pstate_calc_avg_perf(cpu); 1805 if (!hwp_active) 1806 intel_pstate_adjust_busy_pstate(cpu); 1807 } 1808 } 1809 } 1810 1811 #define ICPU(model, policy) \ 1812 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\ 1813 (unsigned long)&policy } 1814 1815 static const struct x86_cpu_id intel_pstate_cpu_ids[] = { 1816 ICPU(INTEL_FAM6_SANDYBRIDGE, core_params), 1817 ICPU(INTEL_FAM6_SANDYBRIDGE_X, core_params), 1818 ICPU(INTEL_FAM6_ATOM_SILVERMONT1, silvermont_params), 1819 ICPU(INTEL_FAM6_IVYBRIDGE, core_params), 1820 ICPU(INTEL_FAM6_HASWELL_CORE, core_params), 1821 ICPU(INTEL_FAM6_BROADWELL_CORE, core_params), 1822 ICPU(INTEL_FAM6_IVYBRIDGE_X, core_params), 1823 ICPU(INTEL_FAM6_HASWELL_X, core_params), 1824 ICPU(INTEL_FAM6_HASWELL_ULT, core_params), 1825 ICPU(INTEL_FAM6_HASWELL_GT3E, core_params), 1826 ICPU(INTEL_FAM6_BROADWELL_GT3E, core_params), 1827 ICPU(INTEL_FAM6_ATOM_AIRMONT, airmont_params), 1828 ICPU(INTEL_FAM6_SKYLAKE_MOBILE, core_params), 1829 ICPU(INTEL_FAM6_BROADWELL_X, core_params), 1830 ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, core_params), 1831 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_params), 1832 ICPU(INTEL_FAM6_XEON_PHI_KNL, knl_params), 1833 ICPU(INTEL_FAM6_XEON_PHI_KNM, knl_params), 1834 ICPU(INTEL_FAM6_ATOM_GOLDMONT, bxt_params), 1835 {} 1836 }; 1837 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids); 1838 1839 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = { 1840 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_params), 1841 ICPU(INTEL_FAM6_BROADWELL_X, core_params), 1842 ICPU(INTEL_FAM6_SKYLAKE_X, core_params), 1843 {} 1844 }; 1845 1846 static int intel_pstate_init_cpu(unsigned int cpunum) 1847 { 1848 struct cpudata *cpu; 1849 1850 cpu = all_cpu_data[cpunum]; 1851 1852 if (!cpu) { 1853 unsigned int size = sizeof(struct cpudata); 1854 1855 if (per_cpu_limits) 1856 size += sizeof(struct perf_limits); 1857 1858 cpu = kzalloc(size, GFP_KERNEL); 1859 if (!cpu) 1860 return -ENOMEM; 1861 1862 all_cpu_data[cpunum] = cpu; 1863 if (per_cpu_limits) 1864 cpu->perf_limits = (struct perf_limits *)(cpu + 1); 1865 1866 cpu->epp_default = -EINVAL; 1867 cpu->epp_powersave = -EINVAL; 1868 cpu->epp_saved = -EINVAL; 1869 } 1870 1871 cpu = all_cpu_data[cpunum]; 1872 1873 cpu->cpu = cpunum; 1874 1875 if (hwp_active) { 1876 intel_pstate_hwp_enable(cpu); 1877 pid_params.sample_rate_ms = 50; 1878 pid_params.sample_rate_ns = 50 * NSEC_PER_MSEC; 1879 } 1880 1881 intel_pstate_get_cpu_pstates(cpu); 1882 1883 intel_pstate_busy_pid_reset(cpu); 1884 1885 pr_debug("controlling: cpu %d\n", cpunum); 1886 1887 return 0; 1888 } 1889 1890 static unsigned int intel_pstate_get(unsigned int cpu_num) 1891 { 1892 struct cpudata *cpu = all_cpu_data[cpu_num]; 1893 1894 return cpu ? get_avg_frequency(cpu) : 0; 1895 } 1896 1897 static void intel_pstate_set_update_util_hook(unsigned int cpu_num) 1898 { 1899 struct cpudata *cpu = all_cpu_data[cpu_num]; 1900 1901 if (cpu->update_util_set) 1902 return; 1903 1904 /* Prevent intel_pstate_update_util() from using stale data. */ 1905 cpu->sample.time = 0; 1906 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util, 1907 intel_pstate_update_util); 1908 cpu->update_util_set = true; 1909 } 1910 1911 static void intel_pstate_clear_update_util_hook(unsigned int cpu) 1912 { 1913 struct cpudata *cpu_data = all_cpu_data[cpu]; 1914 1915 if (!cpu_data->update_util_set) 1916 return; 1917 1918 cpufreq_remove_update_util_hook(cpu); 1919 cpu_data->update_util_set = false; 1920 synchronize_sched(); 1921 } 1922 1923 static void intel_pstate_set_performance_limits(struct perf_limits *limits) 1924 { 1925 limits->no_turbo = 0; 1926 limits->turbo_disabled = 0; 1927 limits->max_perf_pct = 100; 1928 limits->max_perf = int_ext_tofp(1); 1929 limits->min_perf_pct = 100; 1930 limits->min_perf = int_ext_tofp(1); 1931 limits->max_policy_pct = 100; 1932 limits->max_sysfs_pct = 100; 1933 limits->min_policy_pct = 0; 1934 limits->min_sysfs_pct = 0; 1935 } 1936 1937 static void intel_pstate_update_perf_limits(struct cpufreq_policy *policy, 1938 struct perf_limits *limits) 1939 { 1940 1941 limits->max_policy_pct = DIV_ROUND_UP(policy->max * 100, 1942 policy->cpuinfo.max_freq); 1943 limits->max_policy_pct = clamp_t(int, limits->max_policy_pct, 0, 100); 1944 if (policy->max == policy->min) { 1945 limits->min_policy_pct = limits->max_policy_pct; 1946 } else { 1947 limits->min_policy_pct = DIV_ROUND_UP(policy->min * 100, 1948 policy->cpuinfo.max_freq); 1949 limits->min_policy_pct = clamp_t(int, limits->min_policy_pct, 1950 0, 100); 1951 } 1952 1953 /* Normalize user input to [min_policy_pct, max_policy_pct] */ 1954 limits->min_perf_pct = max(limits->min_policy_pct, 1955 limits->min_sysfs_pct); 1956 limits->min_perf_pct = min(limits->max_policy_pct, 1957 limits->min_perf_pct); 1958 limits->max_perf_pct = min(limits->max_policy_pct, 1959 limits->max_sysfs_pct); 1960 limits->max_perf_pct = max(limits->min_policy_pct, 1961 limits->max_perf_pct); 1962 1963 /* Make sure min_perf_pct <= max_perf_pct */ 1964 limits->min_perf_pct = min(limits->max_perf_pct, limits->min_perf_pct); 1965 1966 limits->min_perf = div_ext_fp(limits->min_perf_pct, 100); 1967 limits->max_perf = div_ext_fp(limits->max_perf_pct, 100); 1968 limits->max_perf = round_up(limits->max_perf, EXT_FRAC_BITS); 1969 limits->min_perf = round_up(limits->min_perf, EXT_FRAC_BITS); 1970 1971 pr_debug("cpu:%d max_perf_pct:%d min_perf_pct:%d\n", policy->cpu, 1972 limits->max_perf_pct, limits->min_perf_pct); 1973 } 1974 1975 static int intel_pstate_set_policy(struct cpufreq_policy *policy) 1976 { 1977 struct cpudata *cpu; 1978 struct perf_limits *perf_limits = NULL; 1979 1980 if (!policy->cpuinfo.max_freq) 1981 return -ENODEV; 1982 1983 pr_debug("set_policy cpuinfo.max %u policy->max %u\n", 1984 policy->cpuinfo.max_freq, policy->max); 1985 1986 cpu = all_cpu_data[policy->cpu]; 1987 cpu->policy = policy->policy; 1988 1989 if (cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate && 1990 policy->max < policy->cpuinfo.max_freq && 1991 policy->max > cpu->pstate.max_pstate * cpu->pstate.scaling) { 1992 pr_debug("policy->max > max non turbo frequency\n"); 1993 policy->max = policy->cpuinfo.max_freq; 1994 } 1995 1996 if (per_cpu_limits) 1997 perf_limits = cpu->perf_limits; 1998 1999 mutex_lock(&intel_pstate_limits_lock); 2000 2001 if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) { 2002 if (!perf_limits) { 2003 limits = &performance_limits; 2004 perf_limits = limits; 2005 } 2006 if (policy->max >= policy->cpuinfo.max_freq) { 2007 pr_debug("set performance\n"); 2008 intel_pstate_set_performance_limits(perf_limits); 2009 goto out; 2010 } 2011 } else { 2012 pr_debug("set powersave\n"); 2013 if (!perf_limits) { 2014 limits = &powersave_limits; 2015 perf_limits = limits; 2016 } 2017 2018 } 2019 2020 intel_pstate_update_perf_limits(policy, perf_limits); 2021 out: 2022 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) { 2023 /* 2024 * NOHZ_FULL CPUs need this as the governor callback may not 2025 * be invoked on them. 2026 */ 2027 intel_pstate_clear_update_util_hook(policy->cpu); 2028 intel_pstate_max_within_limits(cpu); 2029 } 2030 2031 intel_pstate_set_update_util_hook(policy->cpu); 2032 2033 intel_pstate_hwp_set_policy(policy); 2034 2035 mutex_unlock(&intel_pstate_limits_lock); 2036 2037 return 0; 2038 } 2039 2040 static int intel_pstate_verify_policy(struct cpufreq_policy *policy) 2041 { 2042 cpufreq_verify_within_cpu_limits(policy); 2043 2044 if (policy->policy != CPUFREQ_POLICY_POWERSAVE && 2045 policy->policy != CPUFREQ_POLICY_PERFORMANCE) 2046 return -EINVAL; 2047 2048 return 0; 2049 } 2050 2051 static void intel_cpufreq_stop_cpu(struct cpufreq_policy *policy) 2052 { 2053 intel_pstate_set_min_pstate(all_cpu_data[policy->cpu]); 2054 } 2055 2056 static void intel_pstate_stop_cpu(struct cpufreq_policy *policy) 2057 { 2058 pr_debug("CPU %d exiting\n", policy->cpu); 2059 2060 intel_pstate_clear_update_util_hook(policy->cpu); 2061 if (hwp_active) 2062 intel_pstate_hwp_save_state(policy); 2063 else 2064 intel_cpufreq_stop_cpu(policy); 2065 } 2066 2067 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy) 2068 { 2069 intel_pstate_exit_perf_limits(policy); 2070 2071 policy->fast_switch_possible = false; 2072 2073 return 0; 2074 } 2075 2076 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy) 2077 { 2078 struct cpudata *cpu; 2079 int rc; 2080 2081 rc = intel_pstate_init_cpu(policy->cpu); 2082 if (rc) 2083 return rc; 2084 2085 cpu = all_cpu_data[policy->cpu]; 2086 2087 /* 2088 * We need sane value in the cpu->perf_limits, so inherit from global 2089 * perf_limits limits, which are seeded with values based on the 2090 * CONFIG_CPU_FREQ_DEFAULT_GOV_*, during boot up. 2091 */ 2092 if (per_cpu_limits) 2093 memcpy(cpu->perf_limits, limits, sizeof(struct perf_limits)); 2094 2095 policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling; 2096 policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling; 2097 2098 /* cpuinfo and default policy values */ 2099 policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling; 2100 update_turbo_state(); 2101 policy->cpuinfo.max_freq = limits->turbo_disabled ? 2102 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate; 2103 policy->cpuinfo.max_freq *= cpu->pstate.scaling; 2104 2105 intel_pstate_init_acpi_perf_limits(policy); 2106 cpumask_set_cpu(policy->cpu, policy->cpus); 2107 2108 policy->fast_switch_possible = true; 2109 2110 return 0; 2111 } 2112 2113 static int intel_pstate_cpu_init(struct cpufreq_policy *policy) 2114 { 2115 int ret = __intel_pstate_cpu_init(policy); 2116 2117 if (ret) 2118 return ret; 2119 2120 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; 2121 if (limits->min_perf_pct == 100 && limits->max_perf_pct == 100) 2122 policy->policy = CPUFREQ_POLICY_PERFORMANCE; 2123 else 2124 policy->policy = CPUFREQ_POLICY_POWERSAVE; 2125 2126 return 0; 2127 } 2128 2129 static struct cpufreq_driver intel_pstate = { 2130 .flags = CPUFREQ_CONST_LOOPS, 2131 .verify = intel_pstate_verify_policy, 2132 .setpolicy = intel_pstate_set_policy, 2133 .suspend = intel_pstate_hwp_save_state, 2134 .resume = intel_pstate_resume, 2135 .get = intel_pstate_get, 2136 .init = intel_pstate_cpu_init, 2137 .exit = intel_pstate_cpu_exit, 2138 .stop_cpu = intel_pstate_stop_cpu, 2139 .name = "intel_pstate", 2140 }; 2141 2142 static int intel_cpufreq_verify_policy(struct cpufreq_policy *policy) 2143 { 2144 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2145 struct perf_limits *perf_limits = limits; 2146 2147 update_turbo_state(); 2148 policy->cpuinfo.max_freq = limits->turbo_disabled ? 2149 cpu->pstate.max_freq : cpu->pstate.turbo_freq; 2150 2151 cpufreq_verify_within_cpu_limits(policy); 2152 2153 if (per_cpu_limits) 2154 perf_limits = cpu->perf_limits; 2155 2156 intel_pstate_update_perf_limits(policy, perf_limits); 2157 2158 return 0; 2159 } 2160 2161 static unsigned int intel_cpufreq_turbo_update(struct cpudata *cpu, 2162 struct cpufreq_policy *policy, 2163 unsigned int target_freq) 2164 { 2165 unsigned int max_freq; 2166 2167 update_turbo_state(); 2168 2169 max_freq = limits->no_turbo || limits->turbo_disabled ? 2170 cpu->pstate.max_freq : cpu->pstate.turbo_freq; 2171 policy->cpuinfo.max_freq = max_freq; 2172 if (policy->max > max_freq) 2173 policy->max = max_freq; 2174 2175 if (target_freq > max_freq) 2176 target_freq = max_freq; 2177 2178 return target_freq; 2179 } 2180 2181 static int intel_cpufreq_target(struct cpufreq_policy *policy, 2182 unsigned int target_freq, 2183 unsigned int relation) 2184 { 2185 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2186 struct cpufreq_freqs freqs; 2187 int target_pstate; 2188 2189 freqs.old = policy->cur; 2190 freqs.new = intel_cpufreq_turbo_update(cpu, policy, target_freq); 2191 2192 cpufreq_freq_transition_begin(policy, &freqs); 2193 switch (relation) { 2194 case CPUFREQ_RELATION_L: 2195 target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling); 2196 break; 2197 case CPUFREQ_RELATION_H: 2198 target_pstate = freqs.new / cpu->pstate.scaling; 2199 break; 2200 default: 2201 target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling); 2202 break; 2203 } 2204 target_pstate = intel_pstate_prepare_request(cpu, target_pstate); 2205 if (target_pstate != cpu->pstate.current_pstate) { 2206 cpu->pstate.current_pstate = target_pstate; 2207 wrmsrl_on_cpu(policy->cpu, MSR_IA32_PERF_CTL, 2208 pstate_funcs.get_val(cpu, target_pstate)); 2209 } 2210 cpufreq_freq_transition_end(policy, &freqs, false); 2211 2212 return 0; 2213 } 2214 2215 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy, 2216 unsigned int target_freq) 2217 { 2218 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2219 int target_pstate; 2220 2221 target_freq = intel_cpufreq_turbo_update(cpu, policy, target_freq); 2222 target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling); 2223 intel_pstate_update_pstate(cpu, target_pstate); 2224 return target_freq; 2225 } 2226 2227 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy) 2228 { 2229 int ret = __intel_pstate_cpu_init(policy); 2230 2231 if (ret) 2232 return ret; 2233 2234 policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY; 2235 /* This reflects the intel_pstate_get_cpu_pstates() setting. */ 2236 policy->cur = policy->cpuinfo.min_freq; 2237 2238 return 0; 2239 } 2240 2241 static struct cpufreq_driver intel_cpufreq = { 2242 .flags = CPUFREQ_CONST_LOOPS, 2243 .verify = intel_cpufreq_verify_policy, 2244 .target = intel_cpufreq_target, 2245 .fast_switch = intel_cpufreq_fast_switch, 2246 .init = intel_cpufreq_cpu_init, 2247 .exit = intel_pstate_cpu_exit, 2248 .stop_cpu = intel_cpufreq_stop_cpu, 2249 .name = "intel_cpufreq", 2250 }; 2251 2252 static struct cpufreq_driver *intel_pstate_driver = &intel_pstate; 2253 2254 static int no_load __initdata; 2255 static int no_hwp __initdata; 2256 static int hwp_only __initdata; 2257 static unsigned int force_load __initdata; 2258 2259 static int __init intel_pstate_msrs_not_valid(void) 2260 { 2261 if (!pstate_funcs.get_max() || 2262 !pstate_funcs.get_min() || 2263 !pstate_funcs.get_turbo()) 2264 return -ENODEV; 2265 2266 return 0; 2267 } 2268 2269 static void __init copy_pid_params(struct pstate_adjust_policy *policy) 2270 { 2271 pid_params.sample_rate_ms = policy->sample_rate_ms; 2272 pid_params.sample_rate_ns = pid_params.sample_rate_ms * NSEC_PER_MSEC; 2273 pid_params.p_gain_pct = policy->p_gain_pct; 2274 pid_params.i_gain_pct = policy->i_gain_pct; 2275 pid_params.d_gain_pct = policy->d_gain_pct; 2276 pid_params.deadband = policy->deadband; 2277 pid_params.setpoint = policy->setpoint; 2278 } 2279 2280 #ifdef CONFIG_ACPI 2281 static void intel_pstate_use_acpi_profile(void) 2282 { 2283 if (acpi_gbl_FADT.preferred_profile == PM_MOBILE) 2284 pstate_funcs.get_target_pstate = 2285 get_target_pstate_use_cpu_load; 2286 } 2287 #else 2288 static void intel_pstate_use_acpi_profile(void) 2289 { 2290 } 2291 #endif 2292 2293 static void __init copy_cpu_funcs(struct pstate_funcs *funcs) 2294 { 2295 pstate_funcs.get_max = funcs->get_max; 2296 pstate_funcs.get_max_physical = funcs->get_max_physical; 2297 pstate_funcs.get_min = funcs->get_min; 2298 pstate_funcs.get_turbo = funcs->get_turbo; 2299 pstate_funcs.get_scaling = funcs->get_scaling; 2300 pstate_funcs.get_val = funcs->get_val; 2301 pstate_funcs.get_vid = funcs->get_vid; 2302 pstate_funcs.get_target_pstate = funcs->get_target_pstate; 2303 2304 intel_pstate_use_acpi_profile(); 2305 } 2306 2307 #ifdef CONFIG_ACPI 2308 2309 static bool __init intel_pstate_no_acpi_pss(void) 2310 { 2311 int i; 2312 2313 for_each_possible_cpu(i) { 2314 acpi_status status; 2315 union acpi_object *pss; 2316 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; 2317 struct acpi_processor *pr = per_cpu(processors, i); 2318 2319 if (!pr) 2320 continue; 2321 2322 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer); 2323 if (ACPI_FAILURE(status)) 2324 continue; 2325 2326 pss = buffer.pointer; 2327 if (pss && pss->type == ACPI_TYPE_PACKAGE) { 2328 kfree(pss); 2329 return false; 2330 } 2331 2332 kfree(pss); 2333 } 2334 2335 return true; 2336 } 2337 2338 static bool __init intel_pstate_has_acpi_ppc(void) 2339 { 2340 int i; 2341 2342 for_each_possible_cpu(i) { 2343 struct acpi_processor *pr = per_cpu(processors, i); 2344 2345 if (!pr) 2346 continue; 2347 if (acpi_has_method(pr->handle, "_PPC")) 2348 return true; 2349 } 2350 return false; 2351 } 2352 2353 enum { 2354 PSS, 2355 PPC, 2356 }; 2357 2358 struct hw_vendor_info { 2359 u16 valid; 2360 char oem_id[ACPI_OEM_ID_SIZE]; 2361 char oem_table_id[ACPI_OEM_TABLE_ID_SIZE]; 2362 int oem_pwr_table; 2363 }; 2364 2365 /* Hardware vendor-specific info that has its own power management modes */ 2366 static struct hw_vendor_info vendor_info[] __initdata = { 2367 {1, "HP ", "ProLiant", PSS}, 2368 {1, "ORACLE", "X4-2 ", PPC}, 2369 {1, "ORACLE", "X4-2L ", PPC}, 2370 {1, "ORACLE", "X4-2B ", PPC}, 2371 {1, "ORACLE", "X3-2 ", PPC}, 2372 {1, "ORACLE", "X3-2L ", PPC}, 2373 {1, "ORACLE", "X3-2B ", PPC}, 2374 {1, "ORACLE", "X4470M2 ", PPC}, 2375 {1, "ORACLE", "X4270M3 ", PPC}, 2376 {1, "ORACLE", "X4270M2 ", PPC}, 2377 {1, "ORACLE", "X4170M2 ", PPC}, 2378 {1, "ORACLE", "X4170 M3", PPC}, 2379 {1, "ORACLE", "X4275 M3", PPC}, 2380 {1, "ORACLE", "X6-2 ", PPC}, 2381 {1, "ORACLE", "Sudbury ", PPC}, 2382 {0, "", ""}, 2383 }; 2384 2385 static bool __init intel_pstate_platform_pwr_mgmt_exists(void) 2386 { 2387 struct acpi_table_header hdr; 2388 struct hw_vendor_info *v_info; 2389 const struct x86_cpu_id *id; 2390 u64 misc_pwr; 2391 2392 id = x86_match_cpu(intel_pstate_cpu_oob_ids); 2393 if (id) { 2394 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr); 2395 if ( misc_pwr & (1 << 8)) 2396 return true; 2397 } 2398 2399 if (acpi_disabled || 2400 ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr))) 2401 return false; 2402 2403 for (v_info = vendor_info; v_info->valid; v_info++) { 2404 if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE) && 2405 !strncmp(hdr.oem_table_id, v_info->oem_table_id, 2406 ACPI_OEM_TABLE_ID_SIZE)) 2407 switch (v_info->oem_pwr_table) { 2408 case PSS: 2409 return intel_pstate_no_acpi_pss(); 2410 case PPC: 2411 return intel_pstate_has_acpi_ppc() && 2412 (!force_load); 2413 } 2414 } 2415 2416 return false; 2417 } 2418 2419 static void intel_pstate_request_control_from_smm(void) 2420 { 2421 /* 2422 * It may be unsafe to request P-states control from SMM if _PPC support 2423 * has not been enabled. 2424 */ 2425 if (acpi_ppc) 2426 acpi_processor_pstate_control(); 2427 } 2428 #else /* CONFIG_ACPI not enabled */ 2429 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; } 2430 static inline bool intel_pstate_has_acpi_ppc(void) { return false; } 2431 static inline void intel_pstate_request_control_from_smm(void) {} 2432 #endif /* CONFIG_ACPI */ 2433 2434 static const struct x86_cpu_id hwp_support_ids[] __initconst = { 2435 { X86_VENDOR_INTEL, 6, X86_MODEL_ANY, X86_FEATURE_HWP }, 2436 {} 2437 }; 2438 2439 static int __init intel_pstate_init(void) 2440 { 2441 int cpu, rc = 0; 2442 const struct x86_cpu_id *id; 2443 struct cpu_defaults *cpu_def; 2444 2445 if (no_load) 2446 return -ENODEV; 2447 2448 if (x86_match_cpu(hwp_support_ids) && !no_hwp) { 2449 copy_cpu_funcs(&core_params.funcs); 2450 hwp_active++; 2451 intel_pstate.attr = hwp_cpufreq_attrs; 2452 goto hwp_cpu_matched; 2453 } 2454 2455 id = x86_match_cpu(intel_pstate_cpu_ids); 2456 if (!id) 2457 return -ENODEV; 2458 2459 cpu_def = (struct cpu_defaults *)id->driver_data; 2460 2461 copy_pid_params(&cpu_def->pid_policy); 2462 copy_cpu_funcs(&cpu_def->funcs); 2463 2464 if (intel_pstate_msrs_not_valid()) 2465 return -ENODEV; 2466 2467 hwp_cpu_matched: 2468 /* 2469 * The Intel pstate driver will be ignored if the platform 2470 * firmware has its own power management modes. 2471 */ 2472 if (intel_pstate_platform_pwr_mgmt_exists()) 2473 return -ENODEV; 2474 2475 pr_info("Intel P-state driver initializing\n"); 2476 2477 all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus()); 2478 if (!all_cpu_data) 2479 return -ENOMEM; 2480 2481 if (!hwp_active && hwp_only) 2482 goto out; 2483 2484 intel_pstate_request_control_from_smm(); 2485 2486 rc = cpufreq_register_driver(intel_pstate_driver); 2487 if (rc) 2488 goto out; 2489 2490 intel_pstate_debug_expose_params(); 2491 intel_pstate_sysfs_expose_params(); 2492 2493 if (hwp_active) 2494 pr_info("HWP enabled\n"); 2495 2496 return rc; 2497 out: 2498 get_online_cpus(); 2499 for_each_online_cpu(cpu) { 2500 if (all_cpu_data[cpu]) { 2501 if (intel_pstate_driver == &intel_pstate) 2502 intel_pstate_clear_update_util_hook(cpu); 2503 2504 kfree(all_cpu_data[cpu]); 2505 } 2506 } 2507 2508 put_online_cpus(); 2509 vfree(all_cpu_data); 2510 return -ENODEV; 2511 } 2512 device_initcall(intel_pstate_init); 2513 2514 static int __init intel_pstate_setup(char *str) 2515 { 2516 if (!str) 2517 return -EINVAL; 2518 2519 if (!strcmp(str, "disable")) { 2520 no_load = 1; 2521 } else if (!strcmp(str, "passive")) { 2522 pr_info("Passive mode enabled\n"); 2523 intel_pstate_driver = &intel_cpufreq; 2524 no_hwp = 1; 2525 } 2526 if (!strcmp(str, "no_hwp")) { 2527 pr_info("HWP disabled\n"); 2528 no_hwp = 1; 2529 } 2530 if (!strcmp(str, "force")) 2531 force_load = 1; 2532 if (!strcmp(str, "hwp_only")) 2533 hwp_only = 1; 2534 if (!strcmp(str, "per_cpu_perf_limits")) 2535 per_cpu_limits = true; 2536 2537 #ifdef CONFIG_ACPI 2538 if (!strcmp(str, "support_acpi_ppc")) 2539 acpi_ppc = true; 2540 #endif 2541 2542 return 0; 2543 } 2544 early_param("intel_pstate", intel_pstate_setup); 2545 2546 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>"); 2547 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors"); 2548 MODULE_LICENSE("GPL"); 2549