1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * intel_pstate.c: Native P state management for Intel processors 4 * 5 * (C) Copyright 2012 Intel Corporation 6 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com> 7 */ 8 9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10 11 #include <linux/kernel.h> 12 #include <linux/kernel_stat.h> 13 #include <linux/module.h> 14 #include <linux/ktime.h> 15 #include <linux/hrtimer.h> 16 #include <linux/tick.h> 17 #include <linux/slab.h> 18 #include <linux/sched/cpufreq.h> 19 #include <linux/list.h> 20 #include <linux/cpu.h> 21 #include <linux/cpufreq.h> 22 #include <linux/sysfs.h> 23 #include <linux/types.h> 24 #include <linux/fs.h> 25 #include <linux/acpi.h> 26 #include <linux/vmalloc.h> 27 #include <linux/pm_qos.h> 28 #include <linux/bitfield.h> 29 #include <trace/events/power.h> 30 31 #include <asm/cpu.h> 32 #include <asm/div64.h> 33 #include <asm/msr.h> 34 #include <asm/cpu_device_id.h> 35 #include <asm/cpufeature.h> 36 #include <asm/intel-family.h> 37 #include "../drivers/thermal/intel/thermal_interrupt.h" 38 39 #define INTEL_PSTATE_SAMPLING_INTERVAL (10 * NSEC_PER_MSEC) 40 41 #define INTEL_CPUFREQ_TRANSITION_LATENCY 20000 42 #define INTEL_CPUFREQ_TRANSITION_DELAY_HWP 5000 43 #define INTEL_CPUFREQ_TRANSITION_DELAY 500 44 45 #ifdef CONFIG_ACPI 46 #include <acpi/processor.h> 47 #include <acpi/cppc_acpi.h> 48 #endif 49 50 #define FRAC_BITS 8 51 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS) 52 #define fp_toint(X) ((X) >> FRAC_BITS) 53 54 #define ONE_EIGHTH_FP ((int64_t)1 << (FRAC_BITS - 3)) 55 56 #define EXT_BITS 6 57 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS) 58 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS) 59 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS) 60 61 static inline int32_t mul_fp(int32_t x, int32_t y) 62 { 63 return ((int64_t)x * (int64_t)y) >> FRAC_BITS; 64 } 65 66 static inline int32_t div_fp(s64 x, s64 y) 67 { 68 return div64_s64((int64_t)x << FRAC_BITS, y); 69 } 70 71 static inline int ceiling_fp(int32_t x) 72 { 73 int mask, ret; 74 75 ret = fp_toint(x); 76 mask = (1 << FRAC_BITS) - 1; 77 if (x & mask) 78 ret += 1; 79 return ret; 80 } 81 82 static inline u64 mul_ext_fp(u64 x, u64 y) 83 { 84 return (x * y) >> EXT_FRAC_BITS; 85 } 86 87 static inline u64 div_ext_fp(u64 x, u64 y) 88 { 89 return div64_u64(x << EXT_FRAC_BITS, y); 90 } 91 92 /** 93 * struct sample - Store performance sample 94 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average 95 * performance during last sample period 96 * @busy_scaled: Scaled busy value which is used to calculate next 97 * P state. This can be different than core_avg_perf 98 * to account for cpu idle period 99 * @aperf: Difference of actual performance frequency clock count 100 * read from APERF MSR between last and current sample 101 * @mperf: Difference of maximum performance frequency clock count 102 * read from MPERF MSR between last and current sample 103 * @tsc: Difference of time stamp counter between last and 104 * current sample 105 * @time: Current time from scheduler 106 * 107 * This structure is used in the cpudata structure to store performance sample 108 * data for choosing next P State. 109 */ 110 struct sample { 111 int32_t core_avg_perf; 112 int32_t busy_scaled; 113 u64 aperf; 114 u64 mperf; 115 u64 tsc; 116 u64 time; 117 }; 118 119 /** 120 * struct pstate_data - Store P state data 121 * @current_pstate: Current requested P state 122 * @min_pstate: Min P state possible for this platform 123 * @max_pstate: Max P state possible for this platform 124 * @max_pstate_physical:This is physical Max P state for a processor 125 * This can be higher than the max_pstate which can 126 * be limited by platform thermal design power limits 127 * @perf_ctl_scaling: PERF_CTL P-state to frequency scaling factor 128 * @scaling: Scaling factor between performance and frequency 129 * @turbo_pstate: Max Turbo P state possible for this platform 130 * @min_freq: @min_pstate frequency in cpufreq units 131 * @max_freq: @max_pstate frequency in cpufreq units 132 * @turbo_freq: @turbo_pstate frequency in cpufreq units 133 * 134 * Stores the per cpu model P state limits and current P state. 135 */ 136 struct pstate_data { 137 int current_pstate; 138 int min_pstate; 139 int max_pstate; 140 int max_pstate_physical; 141 int perf_ctl_scaling; 142 int scaling; 143 int turbo_pstate; 144 unsigned int min_freq; 145 unsigned int max_freq; 146 unsigned int turbo_freq; 147 }; 148 149 /** 150 * struct vid_data - Stores voltage information data 151 * @min: VID data for this platform corresponding to 152 * the lowest P state 153 * @max: VID data corresponding to the highest P State. 154 * @turbo: VID data for turbo P state 155 * @ratio: Ratio of (vid max - vid min) / 156 * (max P state - Min P State) 157 * 158 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling) 159 * This data is used in Atom platforms, where in addition to target P state, 160 * the voltage data needs to be specified to select next P State. 161 */ 162 struct vid_data { 163 int min; 164 int max; 165 int turbo; 166 int32_t ratio; 167 }; 168 169 /** 170 * struct global_params - Global parameters, mostly tunable via sysfs. 171 * @no_turbo: Whether or not to use turbo P-states. 172 * @turbo_disabled: Whether or not turbo P-states are available at all, 173 * based on the MSR_IA32_MISC_ENABLE value and whether or 174 * not the maximum reported turbo P-state is different from 175 * the maximum reported non-turbo one. 176 * @min_perf_pct: Minimum capacity limit in percent of the maximum turbo 177 * P-state capacity. 178 * @max_perf_pct: Maximum capacity limit in percent of the maximum turbo 179 * P-state capacity. 180 */ 181 struct global_params { 182 bool no_turbo; 183 bool turbo_disabled; 184 int max_perf_pct; 185 int min_perf_pct; 186 }; 187 188 /** 189 * struct cpudata - Per CPU instance data storage 190 * @cpu: CPU number for this instance data 191 * @policy: CPUFreq policy value 192 * @update_util: CPUFreq utility callback information 193 * @update_util_set: CPUFreq utility callback is set 194 * @iowait_boost: iowait-related boost fraction 195 * @last_update: Time of the last update. 196 * @pstate: Stores P state limits for this CPU 197 * @vid: Stores VID limits for this CPU 198 * @last_sample_time: Last Sample time 199 * @aperf_mperf_shift: APERF vs MPERF counting frequency difference 200 * @prev_aperf: Last APERF value read from APERF MSR 201 * @prev_mperf: Last MPERF value read from MPERF MSR 202 * @prev_tsc: Last timestamp counter (TSC) value 203 * @sample: Storage for storing last Sample data 204 * @min_perf_ratio: Minimum capacity in terms of PERF or HWP ratios 205 * @max_perf_ratio: Maximum capacity in terms of PERF or HWP ratios 206 * @acpi_perf_data: Stores ACPI perf information read from _PSS 207 * @valid_pss_table: Set to true for valid ACPI _PSS entries found 208 * @epp_powersave: Last saved HWP energy performance preference 209 * (EPP) or energy performance bias (EPB), 210 * when policy switched to performance 211 * @epp_policy: Last saved policy used to set EPP/EPB 212 * @epp_default: Power on default HWP energy performance 213 * preference/bias 214 * @epp_cached: Cached HWP energy-performance preference value 215 * @hwp_req_cached: Cached value of the last HWP Request MSR 216 * @hwp_cap_cached: Cached value of the last HWP Capabilities MSR 217 * @last_io_update: Last time when IO wake flag was set 218 * @sched_flags: Store scheduler flags for possible cross CPU update 219 * @hwp_boost_min: Last HWP boosted min performance 220 * @suspended: Whether or not the driver has been suspended. 221 * @hwp_notify_work: workqueue for HWP notifications. 222 * 223 * This structure stores per CPU instance data for all CPUs. 224 */ 225 struct cpudata { 226 int cpu; 227 228 unsigned int policy; 229 struct update_util_data update_util; 230 bool update_util_set; 231 232 struct pstate_data pstate; 233 struct vid_data vid; 234 235 u64 last_update; 236 u64 last_sample_time; 237 u64 aperf_mperf_shift; 238 u64 prev_aperf; 239 u64 prev_mperf; 240 u64 prev_tsc; 241 struct sample sample; 242 int32_t min_perf_ratio; 243 int32_t max_perf_ratio; 244 #ifdef CONFIG_ACPI 245 struct acpi_processor_performance acpi_perf_data; 246 bool valid_pss_table; 247 #endif 248 unsigned int iowait_boost; 249 s16 epp_powersave; 250 s16 epp_policy; 251 s16 epp_default; 252 s16 epp_cached; 253 u64 hwp_req_cached; 254 u64 hwp_cap_cached; 255 u64 last_io_update; 256 unsigned int sched_flags; 257 u32 hwp_boost_min; 258 bool suspended; 259 struct delayed_work hwp_notify_work; 260 }; 261 262 static struct cpudata **all_cpu_data; 263 264 /** 265 * struct pstate_funcs - Per CPU model specific callbacks 266 * @get_max: Callback to get maximum non turbo effective P state 267 * @get_max_physical: Callback to get maximum non turbo physical P state 268 * @get_min: Callback to get minimum P state 269 * @get_turbo: Callback to get turbo P state 270 * @get_scaling: Callback to get frequency scaling factor 271 * @get_cpu_scaling: Get frequency scaling factor for a given cpu 272 * @get_aperf_mperf_shift: Callback to get the APERF vs MPERF frequency difference 273 * @get_val: Callback to convert P state to actual MSR write value 274 * @get_vid: Callback to get VID data for Atom platforms 275 * 276 * Core and Atom CPU models have different way to get P State limits. This 277 * structure is used to store those callbacks. 278 */ 279 struct pstate_funcs { 280 int (*get_max)(int cpu); 281 int (*get_max_physical)(int cpu); 282 int (*get_min)(int cpu); 283 int (*get_turbo)(int cpu); 284 int (*get_scaling)(void); 285 int (*get_cpu_scaling)(int cpu); 286 int (*get_aperf_mperf_shift)(void); 287 u64 (*get_val)(struct cpudata*, int pstate); 288 void (*get_vid)(struct cpudata *); 289 }; 290 291 static struct pstate_funcs pstate_funcs __read_mostly; 292 293 static bool hwp_active __ro_after_init; 294 static int hwp_mode_bdw __ro_after_init; 295 static bool per_cpu_limits __ro_after_init; 296 static bool hwp_forced __ro_after_init; 297 static bool hwp_boost __read_mostly; 298 299 static struct cpufreq_driver *intel_pstate_driver __read_mostly; 300 301 #define HYBRID_SCALING_FACTOR 78741 302 #define HYBRID_SCALING_FACTOR_MTL 80000 303 304 static int hybrid_scaling_factor = HYBRID_SCALING_FACTOR; 305 306 static inline int core_get_scaling(void) 307 { 308 return 100000; 309 } 310 311 #ifdef CONFIG_ACPI 312 static bool acpi_ppc; 313 #endif 314 315 static struct global_params global; 316 317 static DEFINE_MUTEX(intel_pstate_driver_lock); 318 static DEFINE_MUTEX(intel_pstate_limits_lock); 319 320 #ifdef CONFIG_ACPI 321 322 static bool intel_pstate_acpi_pm_profile_server(void) 323 { 324 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER || 325 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER) 326 return true; 327 328 return false; 329 } 330 331 static bool intel_pstate_get_ppc_enable_status(void) 332 { 333 if (intel_pstate_acpi_pm_profile_server()) 334 return true; 335 336 return acpi_ppc; 337 } 338 339 #ifdef CONFIG_ACPI_CPPC_LIB 340 341 /* The work item is needed to avoid CPU hotplug locking issues */ 342 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work) 343 { 344 sched_set_itmt_support(); 345 } 346 347 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn); 348 349 #define CPPC_MAX_PERF U8_MAX 350 351 static void intel_pstate_set_itmt_prio(int cpu) 352 { 353 struct cppc_perf_caps cppc_perf; 354 static u32 max_highest_perf = 0, min_highest_perf = U32_MAX; 355 int ret; 356 357 ret = cppc_get_perf_caps(cpu, &cppc_perf); 358 if (ret) 359 return; 360 361 /* 362 * On some systems with overclocking enabled, CPPC.highest_perf is hardcoded to 0xff. 363 * In this case we can't use CPPC.highest_perf to enable ITMT. 364 * In this case we can look at MSR_HWP_CAPABILITIES bits [8:0] to decide. 365 */ 366 if (cppc_perf.highest_perf == CPPC_MAX_PERF) 367 cppc_perf.highest_perf = HWP_HIGHEST_PERF(READ_ONCE(all_cpu_data[cpu]->hwp_cap_cached)); 368 369 /* 370 * The priorities can be set regardless of whether or not 371 * sched_set_itmt_support(true) has been called and it is valid to 372 * update them at any time after it has been called. 373 */ 374 sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu); 375 376 if (max_highest_perf <= min_highest_perf) { 377 if (cppc_perf.highest_perf > max_highest_perf) 378 max_highest_perf = cppc_perf.highest_perf; 379 380 if (cppc_perf.highest_perf < min_highest_perf) 381 min_highest_perf = cppc_perf.highest_perf; 382 383 if (max_highest_perf > min_highest_perf) { 384 /* 385 * This code can be run during CPU online under the 386 * CPU hotplug locks, so sched_set_itmt_support() 387 * cannot be called from here. Queue up a work item 388 * to invoke it. 389 */ 390 schedule_work(&sched_itmt_work); 391 } 392 } 393 } 394 395 static int intel_pstate_get_cppc_guaranteed(int cpu) 396 { 397 struct cppc_perf_caps cppc_perf; 398 int ret; 399 400 ret = cppc_get_perf_caps(cpu, &cppc_perf); 401 if (ret) 402 return ret; 403 404 if (cppc_perf.guaranteed_perf) 405 return cppc_perf.guaranteed_perf; 406 407 return cppc_perf.nominal_perf; 408 } 409 410 static int intel_pstate_cppc_get_scaling(int cpu) 411 { 412 struct cppc_perf_caps cppc_perf; 413 int ret; 414 415 ret = cppc_get_perf_caps(cpu, &cppc_perf); 416 417 /* 418 * If the nominal frequency and the nominal performance are not 419 * zero and the ratio between them is not 100, return the hybrid 420 * scaling factor. 421 */ 422 if (!ret && cppc_perf.nominal_perf && cppc_perf.nominal_freq && 423 cppc_perf.nominal_perf * 100 != cppc_perf.nominal_freq) 424 return hybrid_scaling_factor; 425 426 return core_get_scaling(); 427 } 428 429 #else /* CONFIG_ACPI_CPPC_LIB */ 430 static inline void intel_pstate_set_itmt_prio(int cpu) 431 { 432 } 433 #endif /* CONFIG_ACPI_CPPC_LIB */ 434 435 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) 436 { 437 struct cpudata *cpu; 438 int ret; 439 int i; 440 441 if (hwp_active) { 442 intel_pstate_set_itmt_prio(policy->cpu); 443 return; 444 } 445 446 if (!intel_pstate_get_ppc_enable_status()) 447 return; 448 449 cpu = all_cpu_data[policy->cpu]; 450 451 ret = acpi_processor_register_performance(&cpu->acpi_perf_data, 452 policy->cpu); 453 if (ret) 454 return; 455 456 /* 457 * Check if the control value in _PSS is for PERF_CTL MSR, which should 458 * guarantee that the states returned by it map to the states in our 459 * list directly. 460 */ 461 if (cpu->acpi_perf_data.control_register.space_id != 462 ACPI_ADR_SPACE_FIXED_HARDWARE) 463 goto err; 464 465 /* 466 * If there is only one entry _PSS, simply ignore _PSS and continue as 467 * usual without taking _PSS into account 468 */ 469 if (cpu->acpi_perf_data.state_count < 2) 470 goto err; 471 472 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu); 473 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) { 474 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n", 475 (i == cpu->acpi_perf_data.state ? '*' : ' '), i, 476 (u32) cpu->acpi_perf_data.states[i].core_frequency, 477 (u32) cpu->acpi_perf_data.states[i].power, 478 (u32) cpu->acpi_perf_data.states[i].control); 479 } 480 481 cpu->valid_pss_table = true; 482 pr_debug("_PPC limits will be enforced\n"); 483 484 return; 485 486 err: 487 cpu->valid_pss_table = false; 488 acpi_processor_unregister_performance(policy->cpu); 489 } 490 491 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) 492 { 493 struct cpudata *cpu; 494 495 cpu = all_cpu_data[policy->cpu]; 496 if (!cpu->valid_pss_table) 497 return; 498 499 acpi_processor_unregister_performance(policy->cpu); 500 } 501 #else /* CONFIG_ACPI */ 502 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) 503 { 504 } 505 506 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) 507 { 508 } 509 510 static inline bool intel_pstate_acpi_pm_profile_server(void) 511 { 512 return false; 513 } 514 #endif /* CONFIG_ACPI */ 515 516 #ifndef CONFIG_ACPI_CPPC_LIB 517 static inline int intel_pstate_get_cppc_guaranteed(int cpu) 518 { 519 return -ENOTSUPP; 520 } 521 522 static int intel_pstate_cppc_get_scaling(int cpu) 523 { 524 return core_get_scaling(); 525 } 526 #endif /* CONFIG_ACPI_CPPC_LIB */ 527 528 static int intel_pstate_freq_to_hwp_rel(struct cpudata *cpu, int freq, 529 unsigned int relation) 530 { 531 if (freq == cpu->pstate.turbo_freq) 532 return cpu->pstate.turbo_pstate; 533 534 if (freq == cpu->pstate.max_freq) 535 return cpu->pstate.max_pstate; 536 537 switch (relation) { 538 case CPUFREQ_RELATION_H: 539 return freq / cpu->pstate.scaling; 540 case CPUFREQ_RELATION_C: 541 return DIV_ROUND_CLOSEST(freq, cpu->pstate.scaling); 542 } 543 544 return DIV_ROUND_UP(freq, cpu->pstate.scaling); 545 } 546 547 static int intel_pstate_freq_to_hwp(struct cpudata *cpu, int freq) 548 { 549 return intel_pstate_freq_to_hwp_rel(cpu, freq, CPUFREQ_RELATION_L); 550 } 551 552 /** 553 * intel_pstate_hybrid_hwp_adjust - Calibrate HWP performance levels. 554 * @cpu: Target CPU. 555 * 556 * On hybrid processors, HWP may expose more performance levels than there are 557 * P-states accessible through the PERF_CTL interface. If that happens, the 558 * scaling factor between HWP performance levels and CPU frequency will be less 559 * than the scaling factor between P-state values and CPU frequency. 560 * 561 * In that case, adjust the CPU parameters used in computations accordingly. 562 */ 563 static void intel_pstate_hybrid_hwp_adjust(struct cpudata *cpu) 564 { 565 int perf_ctl_max_phys = cpu->pstate.max_pstate_physical; 566 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling; 567 int perf_ctl_turbo = pstate_funcs.get_turbo(cpu->cpu); 568 int scaling = cpu->pstate.scaling; 569 int freq; 570 571 pr_debug("CPU%d: perf_ctl_max_phys = %d\n", cpu->cpu, perf_ctl_max_phys); 572 pr_debug("CPU%d: perf_ctl_turbo = %d\n", cpu->cpu, perf_ctl_turbo); 573 pr_debug("CPU%d: perf_ctl_scaling = %d\n", cpu->cpu, perf_ctl_scaling); 574 pr_debug("CPU%d: HWP_CAP guaranteed = %d\n", cpu->cpu, cpu->pstate.max_pstate); 575 pr_debug("CPU%d: HWP_CAP highest = %d\n", cpu->cpu, cpu->pstate.turbo_pstate); 576 pr_debug("CPU%d: HWP-to-frequency scaling factor: %d\n", cpu->cpu, scaling); 577 578 cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_pstate * scaling, 579 perf_ctl_scaling); 580 cpu->pstate.max_freq = rounddown(cpu->pstate.max_pstate * scaling, 581 perf_ctl_scaling); 582 583 freq = perf_ctl_max_phys * perf_ctl_scaling; 584 cpu->pstate.max_pstate_physical = intel_pstate_freq_to_hwp(cpu, freq); 585 586 freq = cpu->pstate.min_pstate * perf_ctl_scaling; 587 cpu->pstate.min_freq = freq; 588 /* 589 * Cast the min P-state value retrieved via pstate_funcs.get_min() to 590 * the effective range of HWP performance levels. 591 */ 592 cpu->pstate.min_pstate = intel_pstate_freq_to_hwp(cpu, freq); 593 } 594 595 static bool turbo_is_disabled(void) 596 { 597 u64 misc_en; 598 599 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en); 600 601 return !!(misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE); 602 } 603 604 static int min_perf_pct_min(void) 605 { 606 struct cpudata *cpu = all_cpu_data[0]; 607 int turbo_pstate = cpu->pstate.turbo_pstate; 608 609 return turbo_pstate ? 610 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0; 611 } 612 613 static s16 intel_pstate_get_epb(struct cpudata *cpu_data) 614 { 615 u64 epb; 616 int ret; 617 618 if (!boot_cpu_has(X86_FEATURE_EPB)) 619 return -ENXIO; 620 621 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb); 622 if (ret) 623 return (s16)ret; 624 625 return (s16)(epb & 0x0f); 626 } 627 628 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data) 629 { 630 s16 epp; 631 632 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 633 /* 634 * When hwp_req_data is 0, means that caller didn't read 635 * MSR_HWP_REQUEST, so need to read and get EPP. 636 */ 637 if (!hwp_req_data) { 638 epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, 639 &hwp_req_data); 640 if (epp) 641 return epp; 642 } 643 epp = (hwp_req_data >> 24) & 0xff; 644 } else { 645 /* When there is no EPP present, HWP uses EPB settings */ 646 epp = intel_pstate_get_epb(cpu_data); 647 } 648 649 return epp; 650 } 651 652 static int intel_pstate_set_epb(int cpu, s16 pref) 653 { 654 u64 epb; 655 int ret; 656 657 if (!boot_cpu_has(X86_FEATURE_EPB)) 658 return -ENXIO; 659 660 ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb); 661 if (ret) 662 return ret; 663 664 epb = (epb & ~0x0f) | pref; 665 wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb); 666 667 return 0; 668 } 669 670 /* 671 * EPP/EPB display strings corresponding to EPP index in the 672 * energy_perf_strings[] 673 * index String 674 *------------------------------------- 675 * 0 default 676 * 1 performance 677 * 2 balance_performance 678 * 3 balance_power 679 * 4 power 680 */ 681 682 enum energy_perf_value_index { 683 EPP_INDEX_DEFAULT = 0, 684 EPP_INDEX_PERFORMANCE, 685 EPP_INDEX_BALANCE_PERFORMANCE, 686 EPP_INDEX_BALANCE_POWERSAVE, 687 EPP_INDEX_POWERSAVE, 688 }; 689 690 static const char * const energy_perf_strings[] = { 691 [EPP_INDEX_DEFAULT] = "default", 692 [EPP_INDEX_PERFORMANCE] = "performance", 693 [EPP_INDEX_BALANCE_PERFORMANCE] = "balance_performance", 694 [EPP_INDEX_BALANCE_POWERSAVE] = "balance_power", 695 [EPP_INDEX_POWERSAVE] = "power", 696 NULL 697 }; 698 static unsigned int epp_values[] = { 699 [EPP_INDEX_DEFAULT] = 0, /* Unused index */ 700 [EPP_INDEX_PERFORMANCE] = HWP_EPP_PERFORMANCE, 701 [EPP_INDEX_BALANCE_PERFORMANCE] = HWP_EPP_BALANCE_PERFORMANCE, 702 [EPP_INDEX_BALANCE_POWERSAVE] = HWP_EPP_BALANCE_POWERSAVE, 703 [EPP_INDEX_POWERSAVE] = HWP_EPP_POWERSAVE, 704 }; 705 706 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data, int *raw_epp) 707 { 708 s16 epp; 709 int index = -EINVAL; 710 711 *raw_epp = 0; 712 epp = intel_pstate_get_epp(cpu_data, 0); 713 if (epp < 0) 714 return epp; 715 716 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 717 if (epp == epp_values[EPP_INDEX_PERFORMANCE]) 718 return EPP_INDEX_PERFORMANCE; 719 if (epp == epp_values[EPP_INDEX_BALANCE_PERFORMANCE]) 720 return EPP_INDEX_BALANCE_PERFORMANCE; 721 if (epp == epp_values[EPP_INDEX_BALANCE_POWERSAVE]) 722 return EPP_INDEX_BALANCE_POWERSAVE; 723 if (epp == epp_values[EPP_INDEX_POWERSAVE]) 724 return EPP_INDEX_POWERSAVE; 725 *raw_epp = epp; 726 return 0; 727 } else if (boot_cpu_has(X86_FEATURE_EPB)) { 728 /* 729 * Range: 730 * 0x00-0x03 : Performance 731 * 0x04-0x07 : Balance performance 732 * 0x08-0x0B : Balance power 733 * 0x0C-0x0F : Power 734 * The EPB is a 4 bit value, but our ranges restrict the 735 * value which can be set. Here only using top two bits 736 * effectively. 737 */ 738 index = (epp >> 2) + 1; 739 } 740 741 return index; 742 } 743 744 static int intel_pstate_set_epp(struct cpudata *cpu, u32 epp) 745 { 746 int ret; 747 748 /* 749 * Use the cached HWP Request MSR value, because in the active mode the 750 * register itself may be updated by intel_pstate_hwp_boost_up() or 751 * intel_pstate_hwp_boost_down() at any time. 752 */ 753 u64 value = READ_ONCE(cpu->hwp_req_cached); 754 755 value &= ~GENMASK_ULL(31, 24); 756 value |= (u64)epp << 24; 757 /* 758 * The only other updater of hwp_req_cached in the active mode, 759 * intel_pstate_hwp_set(), is called under the same lock as this 760 * function, so it cannot run in parallel with the update below. 761 */ 762 WRITE_ONCE(cpu->hwp_req_cached, value); 763 ret = wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 764 if (!ret) 765 cpu->epp_cached = epp; 766 767 return ret; 768 } 769 770 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data, 771 int pref_index, bool use_raw, 772 u32 raw_epp) 773 { 774 int epp = -EINVAL; 775 int ret; 776 777 if (!pref_index) 778 epp = cpu_data->epp_default; 779 780 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 781 if (use_raw) 782 epp = raw_epp; 783 else if (epp == -EINVAL) 784 epp = epp_values[pref_index]; 785 786 /* 787 * To avoid confusion, refuse to set EPP to any values different 788 * from 0 (performance) if the current policy is "performance", 789 * because those values would be overridden. 790 */ 791 if (epp > 0 && cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) 792 return -EBUSY; 793 794 ret = intel_pstate_set_epp(cpu_data, epp); 795 } else { 796 if (epp == -EINVAL) 797 epp = (pref_index - 1) << 2; 798 ret = intel_pstate_set_epb(cpu_data->cpu, epp); 799 } 800 801 return ret; 802 } 803 804 static ssize_t show_energy_performance_available_preferences( 805 struct cpufreq_policy *policy, char *buf) 806 { 807 int i = 0; 808 int ret = 0; 809 810 while (energy_perf_strings[i] != NULL) 811 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]); 812 813 ret += sprintf(&buf[ret], "\n"); 814 815 return ret; 816 } 817 818 cpufreq_freq_attr_ro(energy_performance_available_preferences); 819 820 static struct cpufreq_driver intel_pstate; 821 822 static ssize_t store_energy_performance_preference( 823 struct cpufreq_policy *policy, const char *buf, size_t count) 824 { 825 struct cpudata *cpu = all_cpu_data[policy->cpu]; 826 char str_preference[21]; 827 bool raw = false; 828 ssize_t ret; 829 u32 epp = 0; 830 831 ret = sscanf(buf, "%20s", str_preference); 832 if (ret != 1) 833 return -EINVAL; 834 835 ret = match_string(energy_perf_strings, -1, str_preference); 836 if (ret < 0) { 837 if (!boot_cpu_has(X86_FEATURE_HWP_EPP)) 838 return ret; 839 840 ret = kstrtouint(buf, 10, &epp); 841 if (ret) 842 return ret; 843 844 if (epp > 255) 845 return -EINVAL; 846 847 raw = true; 848 } 849 850 /* 851 * This function runs with the policy R/W semaphore held, which 852 * guarantees that the driver pointer will not change while it is 853 * running. 854 */ 855 if (!intel_pstate_driver) 856 return -EAGAIN; 857 858 mutex_lock(&intel_pstate_limits_lock); 859 860 if (intel_pstate_driver == &intel_pstate) { 861 ret = intel_pstate_set_energy_pref_index(cpu, ret, raw, epp); 862 } else { 863 /* 864 * In the passive mode the governor needs to be stopped on the 865 * target CPU before the EPP update and restarted after it, 866 * which is super-heavy-weight, so make sure it is worth doing 867 * upfront. 868 */ 869 if (!raw) 870 epp = ret ? epp_values[ret] : cpu->epp_default; 871 872 if (cpu->epp_cached != epp) { 873 int err; 874 875 cpufreq_stop_governor(policy); 876 ret = intel_pstate_set_epp(cpu, epp); 877 err = cpufreq_start_governor(policy); 878 if (!ret) 879 ret = err; 880 } else { 881 ret = 0; 882 } 883 } 884 885 mutex_unlock(&intel_pstate_limits_lock); 886 887 return ret ?: count; 888 } 889 890 static ssize_t show_energy_performance_preference( 891 struct cpufreq_policy *policy, char *buf) 892 { 893 struct cpudata *cpu_data = all_cpu_data[policy->cpu]; 894 int preference, raw_epp; 895 896 preference = intel_pstate_get_energy_pref_index(cpu_data, &raw_epp); 897 if (preference < 0) 898 return preference; 899 900 if (raw_epp) 901 return sprintf(buf, "%d\n", raw_epp); 902 else 903 return sprintf(buf, "%s\n", energy_perf_strings[preference]); 904 } 905 906 cpufreq_freq_attr_rw(energy_performance_preference); 907 908 static ssize_t show_base_frequency(struct cpufreq_policy *policy, char *buf) 909 { 910 struct cpudata *cpu = all_cpu_data[policy->cpu]; 911 int ratio, freq; 912 913 ratio = intel_pstate_get_cppc_guaranteed(policy->cpu); 914 if (ratio <= 0) { 915 u64 cap; 916 917 rdmsrl_on_cpu(policy->cpu, MSR_HWP_CAPABILITIES, &cap); 918 ratio = HWP_GUARANTEED_PERF(cap); 919 } 920 921 freq = ratio * cpu->pstate.scaling; 922 if (cpu->pstate.scaling != cpu->pstate.perf_ctl_scaling) 923 freq = rounddown(freq, cpu->pstate.perf_ctl_scaling); 924 925 return sprintf(buf, "%d\n", freq); 926 } 927 928 cpufreq_freq_attr_ro(base_frequency); 929 930 static struct freq_attr *hwp_cpufreq_attrs[] = { 931 &energy_performance_preference, 932 &energy_performance_available_preferences, 933 &base_frequency, 934 NULL, 935 }; 936 937 static void __intel_pstate_get_hwp_cap(struct cpudata *cpu) 938 { 939 u64 cap; 940 941 rdmsrl_on_cpu(cpu->cpu, MSR_HWP_CAPABILITIES, &cap); 942 WRITE_ONCE(cpu->hwp_cap_cached, cap); 943 cpu->pstate.max_pstate = HWP_GUARANTEED_PERF(cap); 944 cpu->pstate.turbo_pstate = HWP_HIGHEST_PERF(cap); 945 } 946 947 static void intel_pstate_get_hwp_cap(struct cpudata *cpu) 948 { 949 int scaling = cpu->pstate.scaling; 950 951 __intel_pstate_get_hwp_cap(cpu); 952 953 cpu->pstate.max_freq = cpu->pstate.max_pstate * scaling; 954 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * scaling; 955 if (scaling != cpu->pstate.perf_ctl_scaling) { 956 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling; 957 958 cpu->pstate.max_freq = rounddown(cpu->pstate.max_freq, 959 perf_ctl_scaling); 960 cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_freq, 961 perf_ctl_scaling); 962 } 963 } 964 965 static void intel_pstate_hwp_set(unsigned int cpu) 966 { 967 struct cpudata *cpu_data = all_cpu_data[cpu]; 968 int max, min; 969 u64 value; 970 s16 epp; 971 972 max = cpu_data->max_perf_ratio; 973 min = cpu_data->min_perf_ratio; 974 975 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) 976 min = max; 977 978 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value); 979 980 value &= ~HWP_MIN_PERF(~0L); 981 value |= HWP_MIN_PERF(min); 982 983 value &= ~HWP_MAX_PERF(~0L); 984 value |= HWP_MAX_PERF(max); 985 986 if (cpu_data->epp_policy == cpu_data->policy) 987 goto skip_epp; 988 989 cpu_data->epp_policy = cpu_data->policy; 990 991 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) { 992 epp = intel_pstate_get_epp(cpu_data, value); 993 cpu_data->epp_powersave = epp; 994 /* If EPP read was failed, then don't try to write */ 995 if (epp < 0) 996 goto skip_epp; 997 998 epp = 0; 999 } else { 1000 /* skip setting EPP, when saved value is invalid */ 1001 if (cpu_data->epp_powersave < 0) 1002 goto skip_epp; 1003 1004 /* 1005 * No need to restore EPP when it is not zero. This 1006 * means: 1007 * - Policy is not changed 1008 * - user has manually changed 1009 * - Error reading EPB 1010 */ 1011 epp = intel_pstate_get_epp(cpu_data, value); 1012 if (epp) 1013 goto skip_epp; 1014 1015 epp = cpu_data->epp_powersave; 1016 } 1017 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 1018 value &= ~GENMASK_ULL(31, 24); 1019 value |= (u64)epp << 24; 1020 } else { 1021 intel_pstate_set_epb(cpu, epp); 1022 } 1023 skip_epp: 1024 WRITE_ONCE(cpu_data->hwp_req_cached, value); 1025 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value); 1026 } 1027 1028 static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata); 1029 1030 static void intel_pstate_hwp_offline(struct cpudata *cpu) 1031 { 1032 u64 value = READ_ONCE(cpu->hwp_req_cached); 1033 int min_perf; 1034 1035 intel_pstate_disable_hwp_interrupt(cpu); 1036 1037 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 1038 /* 1039 * In case the EPP has been set to "performance" by the 1040 * active mode "performance" scaling algorithm, replace that 1041 * temporary value with the cached EPP one. 1042 */ 1043 value &= ~GENMASK_ULL(31, 24); 1044 value |= HWP_ENERGY_PERF_PREFERENCE(cpu->epp_cached); 1045 /* 1046 * However, make sure that EPP will be set to "performance" when 1047 * the CPU is brought back online again and the "performance" 1048 * scaling algorithm is still in effect. 1049 */ 1050 cpu->epp_policy = CPUFREQ_POLICY_UNKNOWN; 1051 } 1052 1053 /* 1054 * Clear the desired perf field in the cached HWP request value to 1055 * prevent nonzero desired values from being leaked into the active 1056 * mode. 1057 */ 1058 value &= ~HWP_DESIRED_PERF(~0L); 1059 WRITE_ONCE(cpu->hwp_req_cached, value); 1060 1061 value &= ~GENMASK_ULL(31, 0); 1062 min_perf = HWP_LOWEST_PERF(READ_ONCE(cpu->hwp_cap_cached)); 1063 1064 /* Set hwp_max = hwp_min */ 1065 value |= HWP_MAX_PERF(min_perf); 1066 value |= HWP_MIN_PERF(min_perf); 1067 1068 /* Set EPP to min */ 1069 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) 1070 value |= HWP_ENERGY_PERF_PREFERENCE(HWP_EPP_POWERSAVE); 1071 1072 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 1073 } 1074 1075 #define POWER_CTL_EE_ENABLE 1 1076 #define POWER_CTL_EE_DISABLE 2 1077 1078 static int power_ctl_ee_state; 1079 1080 static void set_power_ctl_ee_state(bool input) 1081 { 1082 u64 power_ctl; 1083 1084 mutex_lock(&intel_pstate_driver_lock); 1085 rdmsrl(MSR_IA32_POWER_CTL, power_ctl); 1086 if (input) { 1087 power_ctl &= ~BIT(MSR_IA32_POWER_CTL_BIT_EE); 1088 power_ctl_ee_state = POWER_CTL_EE_ENABLE; 1089 } else { 1090 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE); 1091 power_ctl_ee_state = POWER_CTL_EE_DISABLE; 1092 } 1093 wrmsrl(MSR_IA32_POWER_CTL, power_ctl); 1094 mutex_unlock(&intel_pstate_driver_lock); 1095 } 1096 1097 static void intel_pstate_hwp_enable(struct cpudata *cpudata); 1098 1099 static void intel_pstate_hwp_reenable(struct cpudata *cpu) 1100 { 1101 intel_pstate_hwp_enable(cpu); 1102 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, READ_ONCE(cpu->hwp_req_cached)); 1103 } 1104 1105 static int intel_pstate_suspend(struct cpufreq_policy *policy) 1106 { 1107 struct cpudata *cpu = all_cpu_data[policy->cpu]; 1108 1109 pr_debug("CPU %d suspending\n", cpu->cpu); 1110 1111 cpu->suspended = true; 1112 1113 /* disable HWP interrupt and cancel any pending work */ 1114 intel_pstate_disable_hwp_interrupt(cpu); 1115 1116 return 0; 1117 } 1118 1119 static int intel_pstate_resume(struct cpufreq_policy *policy) 1120 { 1121 struct cpudata *cpu = all_cpu_data[policy->cpu]; 1122 1123 pr_debug("CPU %d resuming\n", cpu->cpu); 1124 1125 /* Only restore if the system default is changed */ 1126 if (power_ctl_ee_state == POWER_CTL_EE_ENABLE) 1127 set_power_ctl_ee_state(true); 1128 else if (power_ctl_ee_state == POWER_CTL_EE_DISABLE) 1129 set_power_ctl_ee_state(false); 1130 1131 if (cpu->suspended && hwp_active) { 1132 mutex_lock(&intel_pstate_limits_lock); 1133 1134 /* Re-enable HWP, because "online" has not done that. */ 1135 intel_pstate_hwp_reenable(cpu); 1136 1137 mutex_unlock(&intel_pstate_limits_lock); 1138 } 1139 1140 cpu->suspended = false; 1141 1142 return 0; 1143 } 1144 1145 static void intel_pstate_update_policies(void) 1146 { 1147 int cpu; 1148 1149 for_each_possible_cpu(cpu) 1150 cpufreq_update_policy(cpu); 1151 } 1152 1153 static void __intel_pstate_update_max_freq(struct cpudata *cpudata, 1154 struct cpufreq_policy *policy) 1155 { 1156 if (hwp_active) 1157 intel_pstate_get_hwp_cap(cpudata); 1158 1159 policy->cpuinfo.max_freq = READ_ONCE(global.no_turbo) ? 1160 cpudata->pstate.max_freq : cpudata->pstate.turbo_freq; 1161 1162 refresh_frequency_limits(policy); 1163 } 1164 1165 static void intel_pstate_update_limits(unsigned int cpu) 1166 { 1167 struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpu); 1168 1169 if (!policy) 1170 return; 1171 1172 __intel_pstate_update_max_freq(all_cpu_data[cpu], policy); 1173 1174 cpufreq_cpu_release(policy); 1175 } 1176 1177 static void intel_pstate_update_limits_for_all(void) 1178 { 1179 int cpu; 1180 1181 for_each_possible_cpu(cpu) 1182 intel_pstate_update_limits(cpu); 1183 } 1184 1185 /************************** sysfs begin ************************/ 1186 #define show_one(file_name, object) \ 1187 static ssize_t show_##file_name \ 1188 (struct kobject *kobj, struct kobj_attribute *attr, char *buf) \ 1189 { \ 1190 return sprintf(buf, "%u\n", global.object); \ 1191 } 1192 1193 static ssize_t intel_pstate_show_status(char *buf); 1194 static int intel_pstate_update_status(const char *buf, size_t size); 1195 1196 static ssize_t show_status(struct kobject *kobj, 1197 struct kobj_attribute *attr, char *buf) 1198 { 1199 ssize_t ret; 1200 1201 mutex_lock(&intel_pstate_driver_lock); 1202 ret = intel_pstate_show_status(buf); 1203 mutex_unlock(&intel_pstate_driver_lock); 1204 1205 return ret; 1206 } 1207 1208 static ssize_t store_status(struct kobject *a, struct kobj_attribute *b, 1209 const char *buf, size_t count) 1210 { 1211 char *p = memchr(buf, '\n', count); 1212 int ret; 1213 1214 mutex_lock(&intel_pstate_driver_lock); 1215 ret = intel_pstate_update_status(buf, p ? p - buf : count); 1216 mutex_unlock(&intel_pstate_driver_lock); 1217 1218 return ret < 0 ? ret : count; 1219 } 1220 1221 static ssize_t show_turbo_pct(struct kobject *kobj, 1222 struct kobj_attribute *attr, char *buf) 1223 { 1224 struct cpudata *cpu; 1225 int total, no_turbo, turbo_pct; 1226 uint32_t turbo_fp; 1227 1228 mutex_lock(&intel_pstate_driver_lock); 1229 1230 if (!intel_pstate_driver) { 1231 mutex_unlock(&intel_pstate_driver_lock); 1232 return -EAGAIN; 1233 } 1234 1235 cpu = all_cpu_data[0]; 1236 1237 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; 1238 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1; 1239 turbo_fp = div_fp(no_turbo, total); 1240 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100))); 1241 1242 mutex_unlock(&intel_pstate_driver_lock); 1243 1244 return sprintf(buf, "%u\n", turbo_pct); 1245 } 1246 1247 static ssize_t show_num_pstates(struct kobject *kobj, 1248 struct kobj_attribute *attr, char *buf) 1249 { 1250 struct cpudata *cpu; 1251 int total; 1252 1253 mutex_lock(&intel_pstate_driver_lock); 1254 1255 if (!intel_pstate_driver) { 1256 mutex_unlock(&intel_pstate_driver_lock); 1257 return -EAGAIN; 1258 } 1259 1260 cpu = all_cpu_data[0]; 1261 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; 1262 1263 mutex_unlock(&intel_pstate_driver_lock); 1264 1265 return sprintf(buf, "%u\n", total); 1266 } 1267 1268 static ssize_t show_no_turbo(struct kobject *kobj, 1269 struct kobj_attribute *attr, char *buf) 1270 { 1271 ssize_t ret; 1272 1273 mutex_lock(&intel_pstate_driver_lock); 1274 1275 if (!intel_pstate_driver) { 1276 mutex_unlock(&intel_pstate_driver_lock); 1277 return -EAGAIN; 1278 } 1279 1280 ret = sprintf(buf, "%u\n", global.no_turbo); 1281 1282 mutex_unlock(&intel_pstate_driver_lock); 1283 1284 return ret; 1285 } 1286 1287 static ssize_t store_no_turbo(struct kobject *a, struct kobj_attribute *b, 1288 const char *buf, size_t count) 1289 { 1290 unsigned int input; 1291 bool no_turbo; 1292 1293 if (sscanf(buf, "%u", &input) != 1) 1294 return -EINVAL; 1295 1296 mutex_lock(&intel_pstate_driver_lock); 1297 1298 if (!intel_pstate_driver) { 1299 count = -EAGAIN; 1300 goto unlock_driver; 1301 } 1302 1303 no_turbo = !!clamp_t(int, input, 0, 1); 1304 1305 if (no_turbo == global.no_turbo) 1306 goto unlock_driver; 1307 1308 if (global.turbo_disabled) { 1309 pr_notice_once("Turbo disabled by BIOS or unavailable on processor\n"); 1310 count = -EPERM; 1311 goto unlock_driver; 1312 } 1313 1314 WRITE_ONCE(global.no_turbo, no_turbo); 1315 1316 mutex_lock(&intel_pstate_limits_lock); 1317 1318 if (no_turbo) { 1319 struct cpudata *cpu = all_cpu_data[0]; 1320 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate; 1321 1322 /* Squash the global minimum into the permitted range. */ 1323 if (global.min_perf_pct > pct) 1324 global.min_perf_pct = pct; 1325 } 1326 1327 mutex_unlock(&intel_pstate_limits_lock); 1328 1329 intel_pstate_update_limits_for_all(); 1330 arch_set_max_freq_ratio(no_turbo); 1331 1332 unlock_driver: 1333 mutex_unlock(&intel_pstate_driver_lock); 1334 1335 return count; 1336 } 1337 1338 static void update_qos_request(enum freq_qos_req_type type) 1339 { 1340 struct freq_qos_request *req; 1341 struct cpufreq_policy *policy; 1342 int i; 1343 1344 for_each_possible_cpu(i) { 1345 struct cpudata *cpu = all_cpu_data[i]; 1346 unsigned int freq, perf_pct; 1347 1348 policy = cpufreq_cpu_get(i); 1349 if (!policy) 1350 continue; 1351 1352 req = policy->driver_data; 1353 cpufreq_cpu_put(policy); 1354 1355 if (!req) 1356 continue; 1357 1358 if (hwp_active) 1359 intel_pstate_get_hwp_cap(cpu); 1360 1361 if (type == FREQ_QOS_MIN) { 1362 perf_pct = global.min_perf_pct; 1363 } else { 1364 req++; 1365 perf_pct = global.max_perf_pct; 1366 } 1367 1368 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * perf_pct, 100); 1369 1370 if (freq_qos_update_request(req, freq) < 0) 1371 pr_warn("Failed to update freq constraint: CPU%d\n", i); 1372 } 1373 } 1374 1375 static ssize_t store_max_perf_pct(struct kobject *a, struct kobj_attribute *b, 1376 const char *buf, size_t count) 1377 { 1378 unsigned int input; 1379 int ret; 1380 1381 ret = sscanf(buf, "%u", &input); 1382 if (ret != 1) 1383 return -EINVAL; 1384 1385 mutex_lock(&intel_pstate_driver_lock); 1386 1387 if (!intel_pstate_driver) { 1388 mutex_unlock(&intel_pstate_driver_lock); 1389 return -EAGAIN; 1390 } 1391 1392 mutex_lock(&intel_pstate_limits_lock); 1393 1394 global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100); 1395 1396 mutex_unlock(&intel_pstate_limits_lock); 1397 1398 if (intel_pstate_driver == &intel_pstate) 1399 intel_pstate_update_policies(); 1400 else 1401 update_qos_request(FREQ_QOS_MAX); 1402 1403 mutex_unlock(&intel_pstate_driver_lock); 1404 1405 return count; 1406 } 1407 1408 static ssize_t store_min_perf_pct(struct kobject *a, struct kobj_attribute *b, 1409 const char *buf, size_t count) 1410 { 1411 unsigned int input; 1412 int ret; 1413 1414 ret = sscanf(buf, "%u", &input); 1415 if (ret != 1) 1416 return -EINVAL; 1417 1418 mutex_lock(&intel_pstate_driver_lock); 1419 1420 if (!intel_pstate_driver) { 1421 mutex_unlock(&intel_pstate_driver_lock); 1422 return -EAGAIN; 1423 } 1424 1425 mutex_lock(&intel_pstate_limits_lock); 1426 1427 global.min_perf_pct = clamp_t(int, input, 1428 min_perf_pct_min(), global.max_perf_pct); 1429 1430 mutex_unlock(&intel_pstate_limits_lock); 1431 1432 if (intel_pstate_driver == &intel_pstate) 1433 intel_pstate_update_policies(); 1434 else 1435 update_qos_request(FREQ_QOS_MIN); 1436 1437 mutex_unlock(&intel_pstate_driver_lock); 1438 1439 return count; 1440 } 1441 1442 static ssize_t show_hwp_dynamic_boost(struct kobject *kobj, 1443 struct kobj_attribute *attr, char *buf) 1444 { 1445 return sprintf(buf, "%u\n", hwp_boost); 1446 } 1447 1448 static ssize_t store_hwp_dynamic_boost(struct kobject *a, 1449 struct kobj_attribute *b, 1450 const char *buf, size_t count) 1451 { 1452 unsigned int input; 1453 int ret; 1454 1455 ret = kstrtouint(buf, 10, &input); 1456 if (ret) 1457 return ret; 1458 1459 mutex_lock(&intel_pstate_driver_lock); 1460 hwp_boost = !!input; 1461 intel_pstate_update_policies(); 1462 mutex_unlock(&intel_pstate_driver_lock); 1463 1464 return count; 1465 } 1466 1467 static ssize_t show_energy_efficiency(struct kobject *kobj, struct kobj_attribute *attr, 1468 char *buf) 1469 { 1470 u64 power_ctl; 1471 int enable; 1472 1473 rdmsrl(MSR_IA32_POWER_CTL, power_ctl); 1474 enable = !!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE)); 1475 return sprintf(buf, "%d\n", !enable); 1476 } 1477 1478 static ssize_t store_energy_efficiency(struct kobject *a, struct kobj_attribute *b, 1479 const char *buf, size_t count) 1480 { 1481 bool input; 1482 int ret; 1483 1484 ret = kstrtobool(buf, &input); 1485 if (ret) 1486 return ret; 1487 1488 set_power_ctl_ee_state(input); 1489 1490 return count; 1491 } 1492 1493 show_one(max_perf_pct, max_perf_pct); 1494 show_one(min_perf_pct, min_perf_pct); 1495 1496 define_one_global_rw(status); 1497 define_one_global_rw(no_turbo); 1498 define_one_global_rw(max_perf_pct); 1499 define_one_global_rw(min_perf_pct); 1500 define_one_global_ro(turbo_pct); 1501 define_one_global_ro(num_pstates); 1502 define_one_global_rw(hwp_dynamic_boost); 1503 define_one_global_rw(energy_efficiency); 1504 1505 static struct attribute *intel_pstate_attributes[] = { 1506 &status.attr, 1507 &no_turbo.attr, 1508 NULL 1509 }; 1510 1511 static const struct attribute_group intel_pstate_attr_group = { 1512 .attrs = intel_pstate_attributes, 1513 }; 1514 1515 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[]; 1516 1517 static struct kobject *intel_pstate_kobject; 1518 1519 static void __init intel_pstate_sysfs_expose_params(void) 1520 { 1521 struct device *dev_root = bus_get_dev_root(&cpu_subsys); 1522 int rc; 1523 1524 if (dev_root) { 1525 intel_pstate_kobject = kobject_create_and_add("intel_pstate", &dev_root->kobj); 1526 put_device(dev_root); 1527 } 1528 if (WARN_ON(!intel_pstate_kobject)) 1529 return; 1530 1531 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group); 1532 if (WARN_ON(rc)) 1533 return; 1534 1535 if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) { 1536 rc = sysfs_create_file(intel_pstate_kobject, &turbo_pct.attr); 1537 WARN_ON(rc); 1538 1539 rc = sysfs_create_file(intel_pstate_kobject, &num_pstates.attr); 1540 WARN_ON(rc); 1541 } 1542 1543 /* 1544 * If per cpu limits are enforced there are no global limits, so 1545 * return without creating max/min_perf_pct attributes 1546 */ 1547 if (per_cpu_limits) 1548 return; 1549 1550 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr); 1551 WARN_ON(rc); 1552 1553 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr); 1554 WARN_ON(rc); 1555 1556 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids)) { 1557 rc = sysfs_create_file(intel_pstate_kobject, &energy_efficiency.attr); 1558 WARN_ON(rc); 1559 } 1560 } 1561 1562 static void __init intel_pstate_sysfs_remove(void) 1563 { 1564 if (!intel_pstate_kobject) 1565 return; 1566 1567 sysfs_remove_group(intel_pstate_kobject, &intel_pstate_attr_group); 1568 1569 if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) { 1570 sysfs_remove_file(intel_pstate_kobject, &num_pstates.attr); 1571 sysfs_remove_file(intel_pstate_kobject, &turbo_pct.attr); 1572 } 1573 1574 if (!per_cpu_limits) { 1575 sysfs_remove_file(intel_pstate_kobject, &max_perf_pct.attr); 1576 sysfs_remove_file(intel_pstate_kobject, &min_perf_pct.attr); 1577 1578 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids)) 1579 sysfs_remove_file(intel_pstate_kobject, &energy_efficiency.attr); 1580 } 1581 1582 kobject_put(intel_pstate_kobject); 1583 } 1584 1585 static void intel_pstate_sysfs_expose_hwp_dynamic_boost(void) 1586 { 1587 int rc; 1588 1589 if (!hwp_active) 1590 return; 1591 1592 rc = sysfs_create_file(intel_pstate_kobject, &hwp_dynamic_boost.attr); 1593 WARN_ON_ONCE(rc); 1594 } 1595 1596 static void intel_pstate_sysfs_hide_hwp_dynamic_boost(void) 1597 { 1598 if (!hwp_active) 1599 return; 1600 1601 sysfs_remove_file(intel_pstate_kobject, &hwp_dynamic_boost.attr); 1602 } 1603 1604 /************************** sysfs end ************************/ 1605 1606 static void intel_pstate_notify_work(struct work_struct *work) 1607 { 1608 struct cpudata *cpudata = 1609 container_of(to_delayed_work(work), struct cpudata, hwp_notify_work); 1610 struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpudata->cpu); 1611 1612 if (policy) { 1613 __intel_pstate_update_max_freq(cpudata, policy); 1614 1615 cpufreq_cpu_release(policy); 1616 } 1617 1618 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0); 1619 } 1620 1621 static DEFINE_SPINLOCK(hwp_notify_lock); 1622 static cpumask_t hwp_intr_enable_mask; 1623 1624 void notify_hwp_interrupt(void) 1625 { 1626 unsigned int this_cpu = smp_processor_id(); 1627 unsigned long flags; 1628 u64 value; 1629 1630 if (!hwp_active || !boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) 1631 return; 1632 1633 rdmsrl_safe(MSR_HWP_STATUS, &value); 1634 if (!(value & 0x01)) 1635 return; 1636 1637 spin_lock_irqsave(&hwp_notify_lock, flags); 1638 1639 if (!cpumask_test_cpu(this_cpu, &hwp_intr_enable_mask)) 1640 goto ack_intr; 1641 1642 schedule_delayed_work(&all_cpu_data[this_cpu]->hwp_notify_work, 1643 msecs_to_jiffies(10)); 1644 1645 spin_unlock_irqrestore(&hwp_notify_lock, flags); 1646 1647 return; 1648 1649 ack_intr: 1650 wrmsrl_safe(MSR_HWP_STATUS, 0); 1651 spin_unlock_irqrestore(&hwp_notify_lock, flags); 1652 } 1653 1654 static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata) 1655 { 1656 bool cancel_work; 1657 1658 if (!boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) 1659 return; 1660 1661 /* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */ 1662 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00); 1663 1664 spin_lock_irq(&hwp_notify_lock); 1665 cancel_work = cpumask_test_and_clear_cpu(cpudata->cpu, &hwp_intr_enable_mask); 1666 spin_unlock_irq(&hwp_notify_lock); 1667 1668 if (cancel_work) 1669 cancel_delayed_work_sync(&cpudata->hwp_notify_work); 1670 } 1671 1672 static void intel_pstate_enable_hwp_interrupt(struct cpudata *cpudata) 1673 { 1674 /* Enable HWP notification interrupt for guaranteed performance change */ 1675 if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) { 1676 spin_lock_irq(&hwp_notify_lock); 1677 INIT_DELAYED_WORK(&cpudata->hwp_notify_work, intel_pstate_notify_work); 1678 cpumask_set_cpu(cpudata->cpu, &hwp_intr_enable_mask); 1679 spin_unlock_irq(&hwp_notify_lock); 1680 1681 /* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */ 1682 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x01); 1683 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0); 1684 } 1685 } 1686 1687 static void intel_pstate_update_epp_defaults(struct cpudata *cpudata) 1688 { 1689 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0); 1690 1691 /* 1692 * If the EPP is set by firmware, which means that firmware enabled HWP 1693 * - Is equal or less than 0x80 (default balance_perf EPP) 1694 * - But less performance oriented than performance EPP 1695 * then use this as new balance_perf EPP. 1696 */ 1697 if (hwp_forced && cpudata->epp_default <= HWP_EPP_BALANCE_PERFORMANCE && 1698 cpudata->epp_default > HWP_EPP_PERFORMANCE) { 1699 epp_values[EPP_INDEX_BALANCE_PERFORMANCE] = cpudata->epp_default; 1700 return; 1701 } 1702 1703 /* 1704 * If this CPU gen doesn't call for change in balance_perf 1705 * EPP return. 1706 */ 1707 if (epp_values[EPP_INDEX_BALANCE_PERFORMANCE] == HWP_EPP_BALANCE_PERFORMANCE) 1708 return; 1709 1710 /* 1711 * Use hard coded value per gen to update the balance_perf 1712 * and default EPP. 1713 */ 1714 cpudata->epp_default = epp_values[EPP_INDEX_BALANCE_PERFORMANCE]; 1715 intel_pstate_set_epp(cpudata, cpudata->epp_default); 1716 } 1717 1718 static void intel_pstate_hwp_enable(struct cpudata *cpudata) 1719 { 1720 /* First disable HWP notification interrupt till we activate again */ 1721 if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) 1722 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00); 1723 1724 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1); 1725 1726 intel_pstate_enable_hwp_interrupt(cpudata); 1727 1728 if (cpudata->epp_default >= 0) 1729 return; 1730 1731 intel_pstate_update_epp_defaults(cpudata); 1732 } 1733 1734 static int atom_get_min_pstate(int not_used) 1735 { 1736 u64 value; 1737 1738 rdmsrl(MSR_ATOM_CORE_RATIOS, value); 1739 return (value >> 8) & 0x7F; 1740 } 1741 1742 static int atom_get_max_pstate(int not_used) 1743 { 1744 u64 value; 1745 1746 rdmsrl(MSR_ATOM_CORE_RATIOS, value); 1747 return (value >> 16) & 0x7F; 1748 } 1749 1750 static int atom_get_turbo_pstate(int not_used) 1751 { 1752 u64 value; 1753 1754 rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value); 1755 return value & 0x7F; 1756 } 1757 1758 static u64 atom_get_val(struct cpudata *cpudata, int pstate) 1759 { 1760 u64 val; 1761 int32_t vid_fp; 1762 u32 vid; 1763 1764 val = (u64)pstate << 8; 1765 if (READ_ONCE(global.no_turbo) && !global.turbo_disabled) 1766 val |= (u64)1 << 32; 1767 1768 vid_fp = cpudata->vid.min + mul_fp( 1769 int_tofp(pstate - cpudata->pstate.min_pstate), 1770 cpudata->vid.ratio); 1771 1772 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max); 1773 vid = ceiling_fp(vid_fp); 1774 1775 if (pstate > cpudata->pstate.max_pstate) 1776 vid = cpudata->vid.turbo; 1777 1778 return val | vid; 1779 } 1780 1781 static int silvermont_get_scaling(void) 1782 { 1783 u64 value; 1784 int i; 1785 /* Defined in Table 35-6 from SDM (Sept 2015) */ 1786 static int silvermont_freq_table[] = { 1787 83300, 100000, 133300, 116700, 80000}; 1788 1789 rdmsrl(MSR_FSB_FREQ, value); 1790 i = value & 0x7; 1791 WARN_ON(i > 4); 1792 1793 return silvermont_freq_table[i]; 1794 } 1795 1796 static int airmont_get_scaling(void) 1797 { 1798 u64 value; 1799 int i; 1800 /* Defined in Table 35-10 from SDM (Sept 2015) */ 1801 static int airmont_freq_table[] = { 1802 83300, 100000, 133300, 116700, 80000, 1803 93300, 90000, 88900, 87500}; 1804 1805 rdmsrl(MSR_FSB_FREQ, value); 1806 i = value & 0xF; 1807 WARN_ON(i > 8); 1808 1809 return airmont_freq_table[i]; 1810 } 1811 1812 static void atom_get_vid(struct cpudata *cpudata) 1813 { 1814 u64 value; 1815 1816 rdmsrl(MSR_ATOM_CORE_VIDS, value); 1817 cpudata->vid.min = int_tofp((value >> 8) & 0x7f); 1818 cpudata->vid.max = int_tofp((value >> 16) & 0x7f); 1819 cpudata->vid.ratio = div_fp( 1820 cpudata->vid.max - cpudata->vid.min, 1821 int_tofp(cpudata->pstate.max_pstate - 1822 cpudata->pstate.min_pstate)); 1823 1824 rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value); 1825 cpudata->vid.turbo = value & 0x7f; 1826 } 1827 1828 static int core_get_min_pstate(int cpu) 1829 { 1830 u64 value; 1831 1832 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &value); 1833 return (value >> 40) & 0xFF; 1834 } 1835 1836 static int core_get_max_pstate_physical(int cpu) 1837 { 1838 u64 value; 1839 1840 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &value); 1841 return (value >> 8) & 0xFF; 1842 } 1843 1844 static int core_get_tdp_ratio(int cpu, u64 plat_info) 1845 { 1846 /* Check how many TDP levels present */ 1847 if (plat_info & 0x600000000) { 1848 u64 tdp_ctrl; 1849 u64 tdp_ratio; 1850 int tdp_msr; 1851 int err; 1852 1853 /* Get the TDP level (0, 1, 2) to get ratios */ 1854 err = rdmsrl_safe_on_cpu(cpu, MSR_CONFIG_TDP_CONTROL, &tdp_ctrl); 1855 if (err) 1856 return err; 1857 1858 /* TDP MSR are continuous starting at 0x648 */ 1859 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03); 1860 err = rdmsrl_safe_on_cpu(cpu, tdp_msr, &tdp_ratio); 1861 if (err) 1862 return err; 1863 1864 /* For level 1 and 2, bits[23:16] contain the ratio */ 1865 if (tdp_ctrl & 0x03) 1866 tdp_ratio >>= 16; 1867 1868 tdp_ratio &= 0xff; /* ratios are only 8 bits long */ 1869 pr_debug("tdp_ratio %x\n", (int)tdp_ratio); 1870 1871 return (int)tdp_ratio; 1872 } 1873 1874 return -ENXIO; 1875 } 1876 1877 static int core_get_max_pstate(int cpu) 1878 { 1879 u64 tar; 1880 u64 plat_info; 1881 int max_pstate; 1882 int tdp_ratio; 1883 int err; 1884 1885 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &plat_info); 1886 max_pstate = (plat_info >> 8) & 0xFF; 1887 1888 tdp_ratio = core_get_tdp_ratio(cpu, plat_info); 1889 if (tdp_ratio <= 0) 1890 return max_pstate; 1891 1892 if (hwp_active) { 1893 /* Turbo activation ratio is not used on HWP platforms */ 1894 return tdp_ratio; 1895 } 1896 1897 err = rdmsrl_safe_on_cpu(cpu, MSR_TURBO_ACTIVATION_RATIO, &tar); 1898 if (!err) { 1899 int tar_levels; 1900 1901 /* Do some sanity checking for safety */ 1902 tar_levels = tar & 0xff; 1903 if (tdp_ratio - 1 == tar_levels) { 1904 max_pstate = tar_levels; 1905 pr_debug("max_pstate=TAC %x\n", max_pstate); 1906 } 1907 } 1908 1909 return max_pstate; 1910 } 1911 1912 static int core_get_turbo_pstate(int cpu) 1913 { 1914 u64 value; 1915 int nont, ret; 1916 1917 rdmsrl_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value); 1918 nont = core_get_max_pstate(cpu); 1919 ret = (value) & 255; 1920 if (ret <= nont) 1921 ret = nont; 1922 return ret; 1923 } 1924 1925 static u64 core_get_val(struct cpudata *cpudata, int pstate) 1926 { 1927 u64 val; 1928 1929 val = (u64)pstate << 8; 1930 if (READ_ONCE(global.no_turbo) && !global.turbo_disabled) 1931 val |= (u64)1 << 32; 1932 1933 return val; 1934 } 1935 1936 static int knl_get_aperf_mperf_shift(void) 1937 { 1938 return 10; 1939 } 1940 1941 static int knl_get_turbo_pstate(int cpu) 1942 { 1943 u64 value; 1944 int nont, ret; 1945 1946 rdmsrl_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value); 1947 nont = core_get_max_pstate(cpu); 1948 ret = (((value) >> 8) & 0xFF); 1949 if (ret <= nont) 1950 ret = nont; 1951 return ret; 1952 } 1953 1954 static void hybrid_get_type(void *data) 1955 { 1956 u8 *cpu_type = data; 1957 1958 *cpu_type = get_this_hybrid_cpu_type(); 1959 } 1960 1961 static int hwp_get_cpu_scaling(int cpu) 1962 { 1963 u8 cpu_type = 0; 1964 1965 smp_call_function_single(cpu, hybrid_get_type, &cpu_type, 1); 1966 /* P-cores have a smaller perf level-to-freqency scaling factor. */ 1967 if (cpu_type == 0x40) 1968 return hybrid_scaling_factor; 1969 1970 /* Use default core scaling for E-cores */ 1971 if (cpu_type == 0x20) 1972 return core_get_scaling(); 1973 1974 /* 1975 * If reached here, this system is either non-hybrid (like Tiger 1976 * Lake) or hybrid-capable (like Alder Lake or Raptor Lake) with 1977 * no E cores (in which case CPUID for hybrid support is 0). 1978 * 1979 * The CPPC nominal_frequency field is 0 for non-hybrid systems, 1980 * so the default core scaling will be used for them. 1981 */ 1982 return intel_pstate_cppc_get_scaling(cpu); 1983 } 1984 1985 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate) 1986 { 1987 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu); 1988 cpu->pstate.current_pstate = pstate; 1989 /* 1990 * Generally, there is no guarantee that this code will always run on 1991 * the CPU being updated, so force the register update to run on the 1992 * right CPU. 1993 */ 1994 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL, 1995 pstate_funcs.get_val(cpu, pstate)); 1996 } 1997 1998 static void intel_pstate_set_min_pstate(struct cpudata *cpu) 1999 { 2000 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate); 2001 } 2002 2003 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu) 2004 { 2005 int perf_ctl_max_phys = pstate_funcs.get_max_physical(cpu->cpu); 2006 int perf_ctl_scaling = pstate_funcs.get_scaling(); 2007 2008 cpu->pstate.min_pstate = pstate_funcs.get_min(cpu->cpu); 2009 cpu->pstate.max_pstate_physical = perf_ctl_max_phys; 2010 cpu->pstate.perf_ctl_scaling = perf_ctl_scaling; 2011 2012 if (hwp_active && !hwp_mode_bdw) { 2013 __intel_pstate_get_hwp_cap(cpu); 2014 2015 if (pstate_funcs.get_cpu_scaling) { 2016 cpu->pstate.scaling = pstate_funcs.get_cpu_scaling(cpu->cpu); 2017 if (cpu->pstate.scaling != perf_ctl_scaling) 2018 intel_pstate_hybrid_hwp_adjust(cpu); 2019 } else { 2020 cpu->pstate.scaling = perf_ctl_scaling; 2021 } 2022 } else { 2023 cpu->pstate.scaling = perf_ctl_scaling; 2024 cpu->pstate.max_pstate = pstate_funcs.get_max(cpu->cpu); 2025 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(cpu->cpu); 2026 } 2027 2028 if (cpu->pstate.scaling == perf_ctl_scaling) { 2029 cpu->pstate.min_freq = cpu->pstate.min_pstate * perf_ctl_scaling; 2030 cpu->pstate.max_freq = cpu->pstate.max_pstate * perf_ctl_scaling; 2031 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * perf_ctl_scaling; 2032 } 2033 2034 if (pstate_funcs.get_aperf_mperf_shift) 2035 cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift(); 2036 2037 if (pstate_funcs.get_vid) 2038 pstate_funcs.get_vid(cpu); 2039 2040 intel_pstate_set_min_pstate(cpu); 2041 } 2042 2043 /* 2044 * Long hold time will keep high perf limits for long time, 2045 * which negatively impacts perf/watt for some workloads, 2046 * like specpower. 3ms is based on experiements on some 2047 * workoads. 2048 */ 2049 static int hwp_boost_hold_time_ns = 3 * NSEC_PER_MSEC; 2050 2051 static inline void intel_pstate_hwp_boost_up(struct cpudata *cpu) 2052 { 2053 u64 hwp_req = READ_ONCE(cpu->hwp_req_cached); 2054 u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached); 2055 u32 max_limit = (hwp_req & 0xff00) >> 8; 2056 u32 min_limit = (hwp_req & 0xff); 2057 u32 boost_level1; 2058 2059 /* 2060 * Cases to consider (User changes via sysfs or boot time): 2061 * If, P0 (Turbo max) = P1 (Guaranteed max) = min: 2062 * No boost, return. 2063 * If, P0 (Turbo max) > P1 (Guaranteed max) = min: 2064 * Should result in one level boost only for P0. 2065 * If, P0 (Turbo max) = P1 (Guaranteed max) > min: 2066 * Should result in two level boost: 2067 * (min + p1)/2 and P1. 2068 * If, P0 (Turbo max) > P1 (Guaranteed max) > min: 2069 * Should result in three level boost: 2070 * (min + p1)/2, P1 and P0. 2071 */ 2072 2073 /* If max and min are equal or already at max, nothing to boost */ 2074 if (max_limit == min_limit || cpu->hwp_boost_min >= max_limit) 2075 return; 2076 2077 if (!cpu->hwp_boost_min) 2078 cpu->hwp_boost_min = min_limit; 2079 2080 /* level at half way mark between min and guranteed */ 2081 boost_level1 = (HWP_GUARANTEED_PERF(hwp_cap) + min_limit) >> 1; 2082 2083 if (cpu->hwp_boost_min < boost_level1) 2084 cpu->hwp_boost_min = boost_level1; 2085 else if (cpu->hwp_boost_min < HWP_GUARANTEED_PERF(hwp_cap)) 2086 cpu->hwp_boost_min = HWP_GUARANTEED_PERF(hwp_cap); 2087 else if (cpu->hwp_boost_min == HWP_GUARANTEED_PERF(hwp_cap) && 2088 max_limit != HWP_GUARANTEED_PERF(hwp_cap)) 2089 cpu->hwp_boost_min = max_limit; 2090 else 2091 return; 2092 2093 hwp_req = (hwp_req & ~GENMASK_ULL(7, 0)) | cpu->hwp_boost_min; 2094 wrmsrl(MSR_HWP_REQUEST, hwp_req); 2095 cpu->last_update = cpu->sample.time; 2096 } 2097 2098 static inline void intel_pstate_hwp_boost_down(struct cpudata *cpu) 2099 { 2100 if (cpu->hwp_boost_min) { 2101 bool expired; 2102 2103 /* Check if we are idle for hold time to boost down */ 2104 expired = time_after64(cpu->sample.time, cpu->last_update + 2105 hwp_boost_hold_time_ns); 2106 if (expired) { 2107 wrmsrl(MSR_HWP_REQUEST, cpu->hwp_req_cached); 2108 cpu->hwp_boost_min = 0; 2109 } 2110 } 2111 cpu->last_update = cpu->sample.time; 2112 } 2113 2114 static inline void intel_pstate_update_util_hwp_local(struct cpudata *cpu, 2115 u64 time) 2116 { 2117 cpu->sample.time = time; 2118 2119 if (cpu->sched_flags & SCHED_CPUFREQ_IOWAIT) { 2120 bool do_io = false; 2121 2122 cpu->sched_flags = 0; 2123 /* 2124 * Set iowait_boost flag and update time. Since IO WAIT flag 2125 * is set all the time, we can't just conclude that there is 2126 * some IO bound activity is scheduled on this CPU with just 2127 * one occurrence. If we receive at least two in two 2128 * consecutive ticks, then we treat as boost candidate. 2129 */ 2130 if (time_before64(time, cpu->last_io_update + 2 * TICK_NSEC)) 2131 do_io = true; 2132 2133 cpu->last_io_update = time; 2134 2135 if (do_io) 2136 intel_pstate_hwp_boost_up(cpu); 2137 2138 } else { 2139 intel_pstate_hwp_boost_down(cpu); 2140 } 2141 } 2142 2143 static inline void intel_pstate_update_util_hwp(struct update_util_data *data, 2144 u64 time, unsigned int flags) 2145 { 2146 struct cpudata *cpu = container_of(data, struct cpudata, update_util); 2147 2148 cpu->sched_flags |= flags; 2149 2150 if (smp_processor_id() == cpu->cpu) 2151 intel_pstate_update_util_hwp_local(cpu, time); 2152 } 2153 2154 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu) 2155 { 2156 struct sample *sample = &cpu->sample; 2157 2158 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf); 2159 } 2160 2161 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time) 2162 { 2163 u64 aperf, mperf; 2164 unsigned long flags; 2165 u64 tsc; 2166 2167 local_irq_save(flags); 2168 rdmsrl(MSR_IA32_APERF, aperf); 2169 rdmsrl(MSR_IA32_MPERF, mperf); 2170 tsc = rdtsc(); 2171 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) { 2172 local_irq_restore(flags); 2173 return false; 2174 } 2175 local_irq_restore(flags); 2176 2177 cpu->last_sample_time = cpu->sample.time; 2178 cpu->sample.time = time; 2179 cpu->sample.aperf = aperf; 2180 cpu->sample.mperf = mperf; 2181 cpu->sample.tsc = tsc; 2182 cpu->sample.aperf -= cpu->prev_aperf; 2183 cpu->sample.mperf -= cpu->prev_mperf; 2184 cpu->sample.tsc -= cpu->prev_tsc; 2185 2186 cpu->prev_aperf = aperf; 2187 cpu->prev_mperf = mperf; 2188 cpu->prev_tsc = tsc; 2189 /* 2190 * First time this function is invoked in a given cycle, all of the 2191 * previous sample data fields are equal to zero or stale and they must 2192 * be populated with meaningful numbers for things to work, so assume 2193 * that sample.time will always be reset before setting the utilization 2194 * update hook and make the caller skip the sample then. 2195 */ 2196 if (cpu->last_sample_time) { 2197 intel_pstate_calc_avg_perf(cpu); 2198 return true; 2199 } 2200 return false; 2201 } 2202 2203 static inline int32_t get_avg_frequency(struct cpudata *cpu) 2204 { 2205 return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz); 2206 } 2207 2208 static inline int32_t get_avg_pstate(struct cpudata *cpu) 2209 { 2210 return mul_ext_fp(cpu->pstate.max_pstate_physical, 2211 cpu->sample.core_avg_perf); 2212 } 2213 2214 static inline int32_t get_target_pstate(struct cpudata *cpu) 2215 { 2216 struct sample *sample = &cpu->sample; 2217 int32_t busy_frac; 2218 int target, avg_pstate; 2219 2220 busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift, 2221 sample->tsc); 2222 2223 if (busy_frac < cpu->iowait_boost) 2224 busy_frac = cpu->iowait_boost; 2225 2226 sample->busy_scaled = busy_frac * 100; 2227 2228 target = READ_ONCE(global.no_turbo) ? 2229 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate; 2230 target += target >> 2; 2231 target = mul_fp(target, busy_frac); 2232 if (target < cpu->pstate.min_pstate) 2233 target = cpu->pstate.min_pstate; 2234 2235 /* 2236 * If the average P-state during the previous cycle was higher than the 2237 * current target, add 50% of the difference to the target to reduce 2238 * possible performance oscillations and offset possible performance 2239 * loss related to moving the workload from one CPU to another within 2240 * a package/module. 2241 */ 2242 avg_pstate = get_avg_pstate(cpu); 2243 if (avg_pstate > target) 2244 target += (avg_pstate - target) >> 1; 2245 2246 return target; 2247 } 2248 2249 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate) 2250 { 2251 int min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio); 2252 int max_pstate = max(min_pstate, cpu->max_perf_ratio); 2253 2254 return clamp_t(int, pstate, min_pstate, max_pstate); 2255 } 2256 2257 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate) 2258 { 2259 if (pstate == cpu->pstate.current_pstate) 2260 return; 2261 2262 cpu->pstate.current_pstate = pstate; 2263 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate)); 2264 } 2265 2266 static void intel_pstate_adjust_pstate(struct cpudata *cpu) 2267 { 2268 int from = cpu->pstate.current_pstate; 2269 struct sample *sample; 2270 int target_pstate; 2271 2272 target_pstate = get_target_pstate(cpu); 2273 target_pstate = intel_pstate_prepare_request(cpu, target_pstate); 2274 trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu); 2275 intel_pstate_update_pstate(cpu, target_pstate); 2276 2277 sample = &cpu->sample; 2278 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf), 2279 fp_toint(sample->busy_scaled), 2280 from, 2281 cpu->pstate.current_pstate, 2282 sample->mperf, 2283 sample->aperf, 2284 sample->tsc, 2285 get_avg_frequency(cpu), 2286 fp_toint(cpu->iowait_boost * 100)); 2287 } 2288 2289 static void intel_pstate_update_util(struct update_util_data *data, u64 time, 2290 unsigned int flags) 2291 { 2292 struct cpudata *cpu = container_of(data, struct cpudata, update_util); 2293 u64 delta_ns; 2294 2295 /* Don't allow remote callbacks */ 2296 if (smp_processor_id() != cpu->cpu) 2297 return; 2298 2299 delta_ns = time - cpu->last_update; 2300 if (flags & SCHED_CPUFREQ_IOWAIT) { 2301 /* Start over if the CPU may have been idle. */ 2302 if (delta_ns > TICK_NSEC) { 2303 cpu->iowait_boost = ONE_EIGHTH_FP; 2304 } else if (cpu->iowait_boost >= ONE_EIGHTH_FP) { 2305 cpu->iowait_boost <<= 1; 2306 if (cpu->iowait_boost > int_tofp(1)) 2307 cpu->iowait_boost = int_tofp(1); 2308 } else { 2309 cpu->iowait_boost = ONE_EIGHTH_FP; 2310 } 2311 } else if (cpu->iowait_boost) { 2312 /* Clear iowait_boost if the CPU may have been idle. */ 2313 if (delta_ns > TICK_NSEC) 2314 cpu->iowait_boost = 0; 2315 else 2316 cpu->iowait_boost >>= 1; 2317 } 2318 cpu->last_update = time; 2319 delta_ns = time - cpu->sample.time; 2320 if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL) 2321 return; 2322 2323 if (intel_pstate_sample(cpu, time)) 2324 intel_pstate_adjust_pstate(cpu); 2325 } 2326 2327 static struct pstate_funcs core_funcs = { 2328 .get_max = core_get_max_pstate, 2329 .get_max_physical = core_get_max_pstate_physical, 2330 .get_min = core_get_min_pstate, 2331 .get_turbo = core_get_turbo_pstate, 2332 .get_scaling = core_get_scaling, 2333 .get_val = core_get_val, 2334 }; 2335 2336 static const struct pstate_funcs silvermont_funcs = { 2337 .get_max = atom_get_max_pstate, 2338 .get_max_physical = atom_get_max_pstate, 2339 .get_min = atom_get_min_pstate, 2340 .get_turbo = atom_get_turbo_pstate, 2341 .get_val = atom_get_val, 2342 .get_scaling = silvermont_get_scaling, 2343 .get_vid = atom_get_vid, 2344 }; 2345 2346 static const struct pstate_funcs airmont_funcs = { 2347 .get_max = atom_get_max_pstate, 2348 .get_max_physical = atom_get_max_pstate, 2349 .get_min = atom_get_min_pstate, 2350 .get_turbo = atom_get_turbo_pstate, 2351 .get_val = atom_get_val, 2352 .get_scaling = airmont_get_scaling, 2353 .get_vid = atom_get_vid, 2354 }; 2355 2356 static const struct pstate_funcs knl_funcs = { 2357 .get_max = core_get_max_pstate, 2358 .get_max_physical = core_get_max_pstate_physical, 2359 .get_min = core_get_min_pstate, 2360 .get_turbo = knl_get_turbo_pstate, 2361 .get_aperf_mperf_shift = knl_get_aperf_mperf_shift, 2362 .get_scaling = core_get_scaling, 2363 .get_val = core_get_val, 2364 }; 2365 2366 #define X86_MATCH(model, policy) \ 2367 X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \ 2368 X86_FEATURE_APERFMPERF, &policy) 2369 2370 static const struct x86_cpu_id intel_pstate_cpu_ids[] = { 2371 X86_MATCH(SANDYBRIDGE, core_funcs), 2372 X86_MATCH(SANDYBRIDGE_X, core_funcs), 2373 X86_MATCH(ATOM_SILVERMONT, silvermont_funcs), 2374 X86_MATCH(IVYBRIDGE, core_funcs), 2375 X86_MATCH(HASWELL, core_funcs), 2376 X86_MATCH(BROADWELL, core_funcs), 2377 X86_MATCH(IVYBRIDGE_X, core_funcs), 2378 X86_MATCH(HASWELL_X, core_funcs), 2379 X86_MATCH(HASWELL_L, core_funcs), 2380 X86_MATCH(HASWELL_G, core_funcs), 2381 X86_MATCH(BROADWELL_G, core_funcs), 2382 X86_MATCH(ATOM_AIRMONT, airmont_funcs), 2383 X86_MATCH(SKYLAKE_L, core_funcs), 2384 X86_MATCH(BROADWELL_X, core_funcs), 2385 X86_MATCH(SKYLAKE, core_funcs), 2386 X86_MATCH(BROADWELL_D, core_funcs), 2387 X86_MATCH(XEON_PHI_KNL, knl_funcs), 2388 X86_MATCH(XEON_PHI_KNM, knl_funcs), 2389 X86_MATCH(ATOM_GOLDMONT, core_funcs), 2390 X86_MATCH(ATOM_GOLDMONT_PLUS, core_funcs), 2391 X86_MATCH(SKYLAKE_X, core_funcs), 2392 X86_MATCH(COMETLAKE, core_funcs), 2393 X86_MATCH(ICELAKE_X, core_funcs), 2394 X86_MATCH(TIGERLAKE, core_funcs), 2395 X86_MATCH(SAPPHIRERAPIDS_X, core_funcs), 2396 X86_MATCH(EMERALDRAPIDS_X, core_funcs), 2397 {} 2398 }; 2399 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids); 2400 2401 #ifdef CONFIG_ACPI 2402 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = { 2403 X86_MATCH(BROADWELL_D, core_funcs), 2404 X86_MATCH(BROADWELL_X, core_funcs), 2405 X86_MATCH(SKYLAKE_X, core_funcs), 2406 X86_MATCH(ICELAKE_X, core_funcs), 2407 X86_MATCH(SAPPHIRERAPIDS_X, core_funcs), 2408 {} 2409 }; 2410 #endif 2411 2412 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = { 2413 X86_MATCH(KABYLAKE, core_funcs), 2414 {} 2415 }; 2416 2417 static int intel_pstate_init_cpu(unsigned int cpunum) 2418 { 2419 struct cpudata *cpu; 2420 2421 cpu = all_cpu_data[cpunum]; 2422 2423 if (!cpu) { 2424 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL); 2425 if (!cpu) 2426 return -ENOMEM; 2427 2428 WRITE_ONCE(all_cpu_data[cpunum], cpu); 2429 2430 cpu->cpu = cpunum; 2431 2432 cpu->epp_default = -EINVAL; 2433 2434 if (hwp_active) { 2435 intel_pstate_hwp_enable(cpu); 2436 2437 if (intel_pstate_acpi_pm_profile_server()) 2438 hwp_boost = true; 2439 } 2440 } else if (hwp_active) { 2441 /* 2442 * Re-enable HWP in case this happens after a resume from ACPI 2443 * S3 if the CPU was offline during the whole system/resume 2444 * cycle. 2445 */ 2446 intel_pstate_hwp_reenable(cpu); 2447 } 2448 2449 cpu->epp_powersave = -EINVAL; 2450 cpu->epp_policy = 0; 2451 2452 intel_pstate_get_cpu_pstates(cpu); 2453 2454 pr_debug("controlling: cpu %d\n", cpunum); 2455 2456 return 0; 2457 } 2458 2459 static void intel_pstate_set_update_util_hook(unsigned int cpu_num) 2460 { 2461 struct cpudata *cpu = all_cpu_data[cpu_num]; 2462 2463 if (hwp_active && !hwp_boost) 2464 return; 2465 2466 if (cpu->update_util_set) 2467 return; 2468 2469 /* Prevent intel_pstate_update_util() from using stale data. */ 2470 cpu->sample.time = 0; 2471 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util, 2472 (hwp_active ? 2473 intel_pstate_update_util_hwp : 2474 intel_pstate_update_util)); 2475 cpu->update_util_set = true; 2476 } 2477 2478 static void intel_pstate_clear_update_util_hook(unsigned int cpu) 2479 { 2480 struct cpudata *cpu_data = all_cpu_data[cpu]; 2481 2482 if (!cpu_data->update_util_set) 2483 return; 2484 2485 cpufreq_remove_update_util_hook(cpu); 2486 cpu_data->update_util_set = false; 2487 synchronize_rcu(); 2488 } 2489 2490 static int intel_pstate_get_max_freq(struct cpudata *cpu) 2491 { 2492 return READ_ONCE(global.no_turbo) ? 2493 cpu->pstate.max_freq : cpu->pstate.turbo_freq; 2494 } 2495 2496 static void intel_pstate_update_perf_limits(struct cpudata *cpu, 2497 unsigned int policy_min, 2498 unsigned int policy_max) 2499 { 2500 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling; 2501 int32_t max_policy_perf, min_policy_perf; 2502 2503 max_policy_perf = policy_max / perf_ctl_scaling; 2504 if (policy_max == policy_min) { 2505 min_policy_perf = max_policy_perf; 2506 } else { 2507 min_policy_perf = policy_min / perf_ctl_scaling; 2508 min_policy_perf = clamp_t(int32_t, min_policy_perf, 2509 0, max_policy_perf); 2510 } 2511 2512 /* 2513 * HWP needs some special consideration, because HWP_REQUEST uses 2514 * abstract values to represent performance rather than pure ratios. 2515 */ 2516 if (hwp_active && cpu->pstate.scaling != perf_ctl_scaling) { 2517 int freq; 2518 2519 freq = max_policy_perf * perf_ctl_scaling; 2520 max_policy_perf = intel_pstate_freq_to_hwp(cpu, freq); 2521 freq = min_policy_perf * perf_ctl_scaling; 2522 min_policy_perf = intel_pstate_freq_to_hwp(cpu, freq); 2523 } 2524 2525 pr_debug("cpu:%d min_policy_perf:%d max_policy_perf:%d\n", 2526 cpu->cpu, min_policy_perf, max_policy_perf); 2527 2528 /* Normalize user input to [min_perf, max_perf] */ 2529 if (per_cpu_limits) { 2530 cpu->min_perf_ratio = min_policy_perf; 2531 cpu->max_perf_ratio = max_policy_perf; 2532 } else { 2533 int turbo_max = cpu->pstate.turbo_pstate; 2534 int32_t global_min, global_max; 2535 2536 /* Global limits are in percent of the maximum turbo P-state. */ 2537 global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100); 2538 global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100); 2539 global_min = clamp_t(int32_t, global_min, 0, global_max); 2540 2541 pr_debug("cpu:%d global_min:%d global_max:%d\n", cpu->cpu, 2542 global_min, global_max); 2543 2544 cpu->min_perf_ratio = max(min_policy_perf, global_min); 2545 cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf); 2546 cpu->max_perf_ratio = min(max_policy_perf, global_max); 2547 cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio); 2548 2549 /* Make sure min_perf <= max_perf */ 2550 cpu->min_perf_ratio = min(cpu->min_perf_ratio, 2551 cpu->max_perf_ratio); 2552 2553 } 2554 pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", cpu->cpu, 2555 cpu->max_perf_ratio, 2556 cpu->min_perf_ratio); 2557 } 2558 2559 static int intel_pstate_set_policy(struct cpufreq_policy *policy) 2560 { 2561 struct cpudata *cpu; 2562 2563 if (!policy->cpuinfo.max_freq) 2564 return -ENODEV; 2565 2566 pr_debug("set_policy cpuinfo.max %u policy->max %u\n", 2567 policy->cpuinfo.max_freq, policy->max); 2568 2569 cpu = all_cpu_data[policy->cpu]; 2570 cpu->policy = policy->policy; 2571 2572 mutex_lock(&intel_pstate_limits_lock); 2573 2574 intel_pstate_update_perf_limits(cpu, policy->min, policy->max); 2575 2576 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) { 2577 int pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio); 2578 2579 /* 2580 * NOHZ_FULL CPUs need this as the governor callback may not 2581 * be invoked on them. 2582 */ 2583 intel_pstate_clear_update_util_hook(policy->cpu); 2584 intel_pstate_set_pstate(cpu, pstate); 2585 } else { 2586 intel_pstate_set_update_util_hook(policy->cpu); 2587 } 2588 2589 if (hwp_active) { 2590 /* 2591 * When hwp_boost was active before and dynamically it 2592 * was turned off, in that case we need to clear the 2593 * update util hook. 2594 */ 2595 if (!hwp_boost) 2596 intel_pstate_clear_update_util_hook(policy->cpu); 2597 intel_pstate_hwp_set(policy->cpu); 2598 } 2599 /* 2600 * policy->cur is never updated with the intel_pstate driver, but it 2601 * is used as a stale frequency value. So, keep it within limits. 2602 */ 2603 policy->cur = policy->min; 2604 2605 mutex_unlock(&intel_pstate_limits_lock); 2606 2607 return 0; 2608 } 2609 2610 static void intel_pstate_adjust_policy_max(struct cpudata *cpu, 2611 struct cpufreq_policy_data *policy) 2612 { 2613 if (!hwp_active && 2614 cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate && 2615 policy->max < policy->cpuinfo.max_freq && 2616 policy->max > cpu->pstate.max_freq) { 2617 pr_debug("policy->max > max non turbo frequency\n"); 2618 policy->max = policy->cpuinfo.max_freq; 2619 } 2620 } 2621 2622 static void intel_pstate_verify_cpu_policy(struct cpudata *cpu, 2623 struct cpufreq_policy_data *policy) 2624 { 2625 int max_freq; 2626 2627 if (hwp_active) { 2628 intel_pstate_get_hwp_cap(cpu); 2629 max_freq = READ_ONCE(global.no_turbo) ? 2630 cpu->pstate.max_freq : cpu->pstate.turbo_freq; 2631 } else { 2632 max_freq = intel_pstate_get_max_freq(cpu); 2633 } 2634 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, max_freq); 2635 2636 intel_pstate_adjust_policy_max(cpu, policy); 2637 } 2638 2639 static int intel_pstate_verify_policy(struct cpufreq_policy_data *policy) 2640 { 2641 intel_pstate_verify_cpu_policy(all_cpu_data[policy->cpu], policy); 2642 2643 return 0; 2644 } 2645 2646 static int intel_cpufreq_cpu_offline(struct cpufreq_policy *policy) 2647 { 2648 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2649 2650 pr_debug("CPU %d going offline\n", cpu->cpu); 2651 2652 if (cpu->suspended) 2653 return 0; 2654 2655 /* 2656 * If the CPU is an SMT thread and it goes offline with the performance 2657 * settings different from the minimum, it will prevent its sibling 2658 * from getting to lower performance levels, so force the minimum 2659 * performance on CPU offline to prevent that from happening. 2660 */ 2661 if (hwp_active) 2662 intel_pstate_hwp_offline(cpu); 2663 else 2664 intel_pstate_set_min_pstate(cpu); 2665 2666 intel_pstate_exit_perf_limits(policy); 2667 2668 return 0; 2669 } 2670 2671 static int intel_pstate_cpu_online(struct cpufreq_policy *policy) 2672 { 2673 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2674 2675 pr_debug("CPU %d going online\n", cpu->cpu); 2676 2677 intel_pstate_init_acpi_perf_limits(policy); 2678 2679 if (hwp_active) { 2680 /* 2681 * Re-enable HWP and clear the "suspended" flag to let "resume" 2682 * know that it need not do that. 2683 */ 2684 intel_pstate_hwp_reenable(cpu); 2685 cpu->suspended = false; 2686 } 2687 2688 return 0; 2689 } 2690 2691 static int intel_pstate_cpu_offline(struct cpufreq_policy *policy) 2692 { 2693 intel_pstate_clear_update_util_hook(policy->cpu); 2694 2695 return intel_cpufreq_cpu_offline(policy); 2696 } 2697 2698 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy) 2699 { 2700 pr_debug("CPU %d exiting\n", policy->cpu); 2701 2702 policy->fast_switch_possible = false; 2703 2704 return 0; 2705 } 2706 2707 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy) 2708 { 2709 struct cpudata *cpu; 2710 int rc; 2711 2712 rc = intel_pstate_init_cpu(policy->cpu); 2713 if (rc) 2714 return rc; 2715 2716 cpu = all_cpu_data[policy->cpu]; 2717 2718 cpu->max_perf_ratio = 0xFF; 2719 cpu->min_perf_ratio = 0; 2720 2721 /* cpuinfo and default policy values */ 2722 policy->cpuinfo.min_freq = cpu->pstate.min_freq; 2723 policy->cpuinfo.max_freq = READ_ONCE(global.no_turbo) ? 2724 cpu->pstate.max_freq : cpu->pstate.turbo_freq; 2725 2726 policy->min = policy->cpuinfo.min_freq; 2727 policy->max = policy->cpuinfo.max_freq; 2728 2729 intel_pstate_init_acpi_perf_limits(policy); 2730 2731 policy->fast_switch_possible = true; 2732 2733 return 0; 2734 } 2735 2736 static int intel_pstate_cpu_init(struct cpufreq_policy *policy) 2737 { 2738 int ret = __intel_pstate_cpu_init(policy); 2739 2740 if (ret) 2741 return ret; 2742 2743 /* 2744 * Set the policy to powersave to provide a valid fallback value in case 2745 * the default cpufreq governor is neither powersave nor performance. 2746 */ 2747 policy->policy = CPUFREQ_POLICY_POWERSAVE; 2748 2749 if (hwp_active) { 2750 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2751 2752 cpu->epp_cached = intel_pstate_get_epp(cpu, 0); 2753 } 2754 2755 return 0; 2756 } 2757 2758 static struct cpufreq_driver intel_pstate = { 2759 .flags = CPUFREQ_CONST_LOOPS, 2760 .verify = intel_pstate_verify_policy, 2761 .setpolicy = intel_pstate_set_policy, 2762 .suspend = intel_pstate_suspend, 2763 .resume = intel_pstate_resume, 2764 .init = intel_pstate_cpu_init, 2765 .exit = intel_pstate_cpu_exit, 2766 .offline = intel_pstate_cpu_offline, 2767 .online = intel_pstate_cpu_online, 2768 .update_limits = intel_pstate_update_limits, 2769 .name = "intel_pstate", 2770 }; 2771 2772 static int intel_cpufreq_verify_policy(struct cpufreq_policy_data *policy) 2773 { 2774 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2775 2776 intel_pstate_verify_cpu_policy(cpu, policy); 2777 intel_pstate_update_perf_limits(cpu, policy->min, policy->max); 2778 2779 return 0; 2780 } 2781 2782 /* Use of trace in passive mode: 2783 * 2784 * In passive mode the trace core_busy field (also known as the 2785 * performance field, and lablelled as such on the graphs; also known as 2786 * core_avg_perf) is not needed and so is re-assigned to indicate if the 2787 * driver call was via the normal or fast switch path. Various graphs 2788 * output from the intel_pstate_tracer.py utility that include core_busy 2789 * (or performance or core_avg_perf) have a fixed y-axis from 0 to 100%, 2790 * so we use 10 to indicate the normal path through the driver, and 2791 * 90 to indicate the fast switch path through the driver. 2792 * The scaled_busy field is not used, and is set to 0. 2793 */ 2794 2795 #define INTEL_PSTATE_TRACE_TARGET 10 2796 #define INTEL_PSTATE_TRACE_FAST_SWITCH 90 2797 2798 static void intel_cpufreq_trace(struct cpudata *cpu, unsigned int trace_type, int old_pstate) 2799 { 2800 struct sample *sample; 2801 2802 if (!trace_pstate_sample_enabled()) 2803 return; 2804 2805 if (!intel_pstate_sample(cpu, ktime_get())) 2806 return; 2807 2808 sample = &cpu->sample; 2809 trace_pstate_sample(trace_type, 2810 0, 2811 old_pstate, 2812 cpu->pstate.current_pstate, 2813 sample->mperf, 2814 sample->aperf, 2815 sample->tsc, 2816 get_avg_frequency(cpu), 2817 fp_toint(cpu->iowait_boost * 100)); 2818 } 2819 2820 static void intel_cpufreq_hwp_update(struct cpudata *cpu, u32 min, u32 max, 2821 u32 desired, bool fast_switch) 2822 { 2823 u64 prev = READ_ONCE(cpu->hwp_req_cached), value = prev; 2824 2825 value &= ~HWP_MIN_PERF(~0L); 2826 value |= HWP_MIN_PERF(min); 2827 2828 value &= ~HWP_MAX_PERF(~0L); 2829 value |= HWP_MAX_PERF(max); 2830 2831 value &= ~HWP_DESIRED_PERF(~0L); 2832 value |= HWP_DESIRED_PERF(desired); 2833 2834 if (value == prev) 2835 return; 2836 2837 WRITE_ONCE(cpu->hwp_req_cached, value); 2838 if (fast_switch) 2839 wrmsrl(MSR_HWP_REQUEST, value); 2840 else 2841 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 2842 } 2843 2844 static void intel_cpufreq_perf_ctl_update(struct cpudata *cpu, 2845 u32 target_pstate, bool fast_switch) 2846 { 2847 if (fast_switch) 2848 wrmsrl(MSR_IA32_PERF_CTL, 2849 pstate_funcs.get_val(cpu, target_pstate)); 2850 else 2851 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL, 2852 pstate_funcs.get_val(cpu, target_pstate)); 2853 } 2854 2855 static int intel_cpufreq_update_pstate(struct cpufreq_policy *policy, 2856 int target_pstate, bool fast_switch) 2857 { 2858 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2859 int old_pstate = cpu->pstate.current_pstate; 2860 2861 target_pstate = intel_pstate_prepare_request(cpu, target_pstate); 2862 if (hwp_active) { 2863 int max_pstate = policy->strict_target ? 2864 target_pstate : cpu->max_perf_ratio; 2865 2866 intel_cpufreq_hwp_update(cpu, target_pstate, max_pstate, 0, 2867 fast_switch); 2868 } else if (target_pstate != old_pstate) { 2869 intel_cpufreq_perf_ctl_update(cpu, target_pstate, fast_switch); 2870 } 2871 2872 cpu->pstate.current_pstate = target_pstate; 2873 2874 intel_cpufreq_trace(cpu, fast_switch ? INTEL_PSTATE_TRACE_FAST_SWITCH : 2875 INTEL_PSTATE_TRACE_TARGET, old_pstate); 2876 2877 return target_pstate; 2878 } 2879 2880 static int intel_cpufreq_target(struct cpufreq_policy *policy, 2881 unsigned int target_freq, 2882 unsigned int relation) 2883 { 2884 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2885 struct cpufreq_freqs freqs; 2886 int target_pstate; 2887 2888 freqs.old = policy->cur; 2889 freqs.new = target_freq; 2890 2891 cpufreq_freq_transition_begin(policy, &freqs); 2892 2893 target_pstate = intel_pstate_freq_to_hwp_rel(cpu, freqs.new, relation); 2894 target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, false); 2895 2896 freqs.new = target_pstate * cpu->pstate.scaling; 2897 2898 cpufreq_freq_transition_end(policy, &freqs, false); 2899 2900 return 0; 2901 } 2902 2903 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy, 2904 unsigned int target_freq) 2905 { 2906 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2907 int target_pstate; 2908 2909 target_pstate = intel_pstate_freq_to_hwp(cpu, target_freq); 2910 2911 target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, true); 2912 2913 return target_pstate * cpu->pstate.scaling; 2914 } 2915 2916 static void intel_cpufreq_adjust_perf(unsigned int cpunum, 2917 unsigned long min_perf, 2918 unsigned long target_perf, 2919 unsigned long capacity) 2920 { 2921 struct cpudata *cpu = all_cpu_data[cpunum]; 2922 u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached); 2923 int old_pstate = cpu->pstate.current_pstate; 2924 int cap_pstate, min_pstate, max_pstate, target_pstate; 2925 2926 cap_pstate = READ_ONCE(global.no_turbo) ? 2927 HWP_GUARANTEED_PERF(hwp_cap) : 2928 HWP_HIGHEST_PERF(hwp_cap); 2929 2930 /* Optimization: Avoid unnecessary divisions. */ 2931 2932 target_pstate = cap_pstate; 2933 if (target_perf < capacity) 2934 target_pstate = DIV_ROUND_UP(cap_pstate * target_perf, capacity); 2935 2936 min_pstate = cap_pstate; 2937 if (min_perf < capacity) 2938 min_pstate = DIV_ROUND_UP(cap_pstate * min_perf, capacity); 2939 2940 if (min_pstate < cpu->pstate.min_pstate) 2941 min_pstate = cpu->pstate.min_pstate; 2942 2943 if (min_pstate < cpu->min_perf_ratio) 2944 min_pstate = cpu->min_perf_ratio; 2945 2946 if (min_pstate > cpu->max_perf_ratio) 2947 min_pstate = cpu->max_perf_ratio; 2948 2949 max_pstate = min(cap_pstate, cpu->max_perf_ratio); 2950 if (max_pstate < min_pstate) 2951 max_pstate = min_pstate; 2952 2953 target_pstate = clamp_t(int, target_pstate, min_pstate, max_pstate); 2954 2955 intel_cpufreq_hwp_update(cpu, min_pstate, max_pstate, target_pstate, true); 2956 2957 cpu->pstate.current_pstate = target_pstate; 2958 intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_FAST_SWITCH, old_pstate); 2959 } 2960 2961 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy) 2962 { 2963 struct freq_qos_request *req; 2964 struct cpudata *cpu; 2965 struct device *dev; 2966 int ret, freq; 2967 2968 dev = get_cpu_device(policy->cpu); 2969 if (!dev) 2970 return -ENODEV; 2971 2972 ret = __intel_pstate_cpu_init(policy); 2973 if (ret) 2974 return ret; 2975 2976 policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY; 2977 /* This reflects the intel_pstate_get_cpu_pstates() setting. */ 2978 policy->cur = policy->cpuinfo.min_freq; 2979 2980 req = kcalloc(2, sizeof(*req), GFP_KERNEL); 2981 if (!req) { 2982 ret = -ENOMEM; 2983 goto pstate_exit; 2984 } 2985 2986 cpu = all_cpu_data[policy->cpu]; 2987 2988 if (hwp_active) { 2989 u64 value; 2990 2991 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY_HWP; 2992 2993 intel_pstate_get_hwp_cap(cpu); 2994 2995 rdmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, &value); 2996 WRITE_ONCE(cpu->hwp_req_cached, value); 2997 2998 cpu->epp_cached = intel_pstate_get_epp(cpu, value); 2999 } else { 3000 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY; 3001 } 3002 3003 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.min_perf_pct, 100); 3004 3005 ret = freq_qos_add_request(&policy->constraints, req, FREQ_QOS_MIN, 3006 freq); 3007 if (ret < 0) { 3008 dev_err(dev, "Failed to add min-freq constraint (%d)\n", ret); 3009 goto free_req; 3010 } 3011 3012 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.max_perf_pct, 100); 3013 3014 ret = freq_qos_add_request(&policy->constraints, req + 1, FREQ_QOS_MAX, 3015 freq); 3016 if (ret < 0) { 3017 dev_err(dev, "Failed to add max-freq constraint (%d)\n", ret); 3018 goto remove_min_req; 3019 } 3020 3021 policy->driver_data = req; 3022 3023 return 0; 3024 3025 remove_min_req: 3026 freq_qos_remove_request(req); 3027 free_req: 3028 kfree(req); 3029 pstate_exit: 3030 intel_pstate_exit_perf_limits(policy); 3031 3032 return ret; 3033 } 3034 3035 static int intel_cpufreq_cpu_exit(struct cpufreq_policy *policy) 3036 { 3037 struct freq_qos_request *req; 3038 3039 req = policy->driver_data; 3040 3041 freq_qos_remove_request(req + 1); 3042 freq_qos_remove_request(req); 3043 kfree(req); 3044 3045 return intel_pstate_cpu_exit(policy); 3046 } 3047 3048 static int intel_cpufreq_suspend(struct cpufreq_policy *policy) 3049 { 3050 intel_pstate_suspend(policy); 3051 3052 if (hwp_active) { 3053 struct cpudata *cpu = all_cpu_data[policy->cpu]; 3054 u64 value = READ_ONCE(cpu->hwp_req_cached); 3055 3056 /* 3057 * Clear the desired perf field in MSR_HWP_REQUEST in case 3058 * intel_cpufreq_adjust_perf() is in use and the last value 3059 * written by it may not be suitable. 3060 */ 3061 value &= ~HWP_DESIRED_PERF(~0L); 3062 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 3063 WRITE_ONCE(cpu->hwp_req_cached, value); 3064 } 3065 3066 return 0; 3067 } 3068 3069 static struct cpufreq_driver intel_cpufreq = { 3070 .flags = CPUFREQ_CONST_LOOPS, 3071 .verify = intel_cpufreq_verify_policy, 3072 .target = intel_cpufreq_target, 3073 .fast_switch = intel_cpufreq_fast_switch, 3074 .init = intel_cpufreq_cpu_init, 3075 .exit = intel_cpufreq_cpu_exit, 3076 .offline = intel_cpufreq_cpu_offline, 3077 .online = intel_pstate_cpu_online, 3078 .suspend = intel_cpufreq_suspend, 3079 .resume = intel_pstate_resume, 3080 .update_limits = intel_pstate_update_limits, 3081 .name = "intel_cpufreq", 3082 }; 3083 3084 static struct cpufreq_driver *default_driver; 3085 3086 static void intel_pstate_driver_cleanup(void) 3087 { 3088 unsigned int cpu; 3089 3090 cpus_read_lock(); 3091 for_each_online_cpu(cpu) { 3092 if (all_cpu_data[cpu]) { 3093 if (intel_pstate_driver == &intel_pstate) 3094 intel_pstate_clear_update_util_hook(cpu); 3095 3096 kfree(all_cpu_data[cpu]); 3097 WRITE_ONCE(all_cpu_data[cpu], NULL); 3098 } 3099 } 3100 cpus_read_unlock(); 3101 3102 intel_pstate_driver = NULL; 3103 } 3104 3105 static int intel_pstate_register_driver(struct cpufreq_driver *driver) 3106 { 3107 int ret; 3108 3109 if (driver == &intel_pstate) 3110 intel_pstate_sysfs_expose_hwp_dynamic_boost(); 3111 3112 memset(&global, 0, sizeof(global)); 3113 global.max_perf_pct = 100; 3114 global.turbo_disabled = turbo_is_disabled(); 3115 global.no_turbo = global.turbo_disabled; 3116 3117 arch_set_max_freq_ratio(global.turbo_disabled); 3118 3119 intel_pstate_driver = driver; 3120 ret = cpufreq_register_driver(intel_pstate_driver); 3121 if (ret) { 3122 intel_pstate_driver_cleanup(); 3123 return ret; 3124 } 3125 3126 global.min_perf_pct = min_perf_pct_min(); 3127 3128 return 0; 3129 } 3130 3131 static ssize_t intel_pstate_show_status(char *buf) 3132 { 3133 if (!intel_pstate_driver) 3134 return sprintf(buf, "off\n"); 3135 3136 return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ? 3137 "active" : "passive"); 3138 } 3139 3140 static int intel_pstate_update_status(const char *buf, size_t size) 3141 { 3142 if (size == 3 && !strncmp(buf, "off", size)) { 3143 if (!intel_pstate_driver) 3144 return -EINVAL; 3145 3146 if (hwp_active) 3147 return -EBUSY; 3148 3149 cpufreq_unregister_driver(intel_pstate_driver); 3150 intel_pstate_driver_cleanup(); 3151 return 0; 3152 } 3153 3154 if (size == 6 && !strncmp(buf, "active", size)) { 3155 if (intel_pstate_driver) { 3156 if (intel_pstate_driver == &intel_pstate) 3157 return 0; 3158 3159 cpufreq_unregister_driver(intel_pstate_driver); 3160 } 3161 3162 return intel_pstate_register_driver(&intel_pstate); 3163 } 3164 3165 if (size == 7 && !strncmp(buf, "passive", size)) { 3166 if (intel_pstate_driver) { 3167 if (intel_pstate_driver == &intel_cpufreq) 3168 return 0; 3169 3170 cpufreq_unregister_driver(intel_pstate_driver); 3171 intel_pstate_sysfs_hide_hwp_dynamic_boost(); 3172 } 3173 3174 return intel_pstate_register_driver(&intel_cpufreq); 3175 } 3176 3177 return -EINVAL; 3178 } 3179 3180 static int no_load __initdata; 3181 static int no_hwp __initdata; 3182 static int hwp_only __initdata; 3183 static unsigned int force_load __initdata; 3184 3185 static int __init intel_pstate_msrs_not_valid(void) 3186 { 3187 if (!pstate_funcs.get_max(0) || 3188 !pstate_funcs.get_min(0) || 3189 !pstate_funcs.get_turbo(0)) 3190 return -ENODEV; 3191 3192 return 0; 3193 } 3194 3195 static void __init copy_cpu_funcs(struct pstate_funcs *funcs) 3196 { 3197 pstate_funcs.get_max = funcs->get_max; 3198 pstate_funcs.get_max_physical = funcs->get_max_physical; 3199 pstate_funcs.get_min = funcs->get_min; 3200 pstate_funcs.get_turbo = funcs->get_turbo; 3201 pstate_funcs.get_scaling = funcs->get_scaling; 3202 pstate_funcs.get_val = funcs->get_val; 3203 pstate_funcs.get_vid = funcs->get_vid; 3204 pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift; 3205 } 3206 3207 #ifdef CONFIG_ACPI 3208 3209 static bool __init intel_pstate_no_acpi_pss(void) 3210 { 3211 int i; 3212 3213 for_each_possible_cpu(i) { 3214 acpi_status status; 3215 union acpi_object *pss; 3216 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; 3217 struct acpi_processor *pr = per_cpu(processors, i); 3218 3219 if (!pr) 3220 continue; 3221 3222 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer); 3223 if (ACPI_FAILURE(status)) 3224 continue; 3225 3226 pss = buffer.pointer; 3227 if (pss && pss->type == ACPI_TYPE_PACKAGE) { 3228 kfree(pss); 3229 return false; 3230 } 3231 3232 kfree(pss); 3233 } 3234 3235 pr_debug("ACPI _PSS not found\n"); 3236 return true; 3237 } 3238 3239 static bool __init intel_pstate_no_acpi_pcch(void) 3240 { 3241 acpi_status status; 3242 acpi_handle handle; 3243 3244 status = acpi_get_handle(NULL, "\\_SB", &handle); 3245 if (ACPI_FAILURE(status)) 3246 goto not_found; 3247 3248 if (acpi_has_method(handle, "PCCH")) 3249 return false; 3250 3251 not_found: 3252 pr_debug("ACPI PCCH not found\n"); 3253 return true; 3254 } 3255 3256 static bool __init intel_pstate_has_acpi_ppc(void) 3257 { 3258 int i; 3259 3260 for_each_possible_cpu(i) { 3261 struct acpi_processor *pr = per_cpu(processors, i); 3262 3263 if (!pr) 3264 continue; 3265 if (acpi_has_method(pr->handle, "_PPC")) 3266 return true; 3267 } 3268 pr_debug("ACPI _PPC not found\n"); 3269 return false; 3270 } 3271 3272 enum { 3273 PSS, 3274 PPC, 3275 }; 3276 3277 /* Hardware vendor-specific info that has its own power management modes */ 3278 static struct acpi_platform_list plat_info[] __initdata = { 3279 {"HP ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, NULL, PSS}, 3280 {"ORACLE", "X4-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3281 {"ORACLE", "X4-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3282 {"ORACLE", "X4-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3283 {"ORACLE", "X3-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3284 {"ORACLE", "X3-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3285 {"ORACLE", "X3-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3286 {"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3287 {"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3288 {"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3289 {"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3290 {"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3291 {"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3292 {"ORACLE", "X6-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3293 {"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3294 { } /* End */ 3295 }; 3296 3297 #define BITMASK_OOB (BIT(8) | BIT(18)) 3298 3299 static bool __init intel_pstate_platform_pwr_mgmt_exists(void) 3300 { 3301 const struct x86_cpu_id *id; 3302 u64 misc_pwr; 3303 int idx; 3304 3305 id = x86_match_cpu(intel_pstate_cpu_oob_ids); 3306 if (id) { 3307 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr); 3308 if (misc_pwr & BITMASK_OOB) { 3309 pr_debug("Bit 8 or 18 in the MISC_PWR_MGMT MSR set\n"); 3310 pr_debug("P states are controlled in Out of Band mode by the firmware/hardware\n"); 3311 return true; 3312 } 3313 } 3314 3315 idx = acpi_match_platform_list(plat_info); 3316 if (idx < 0) 3317 return false; 3318 3319 switch (plat_info[idx].data) { 3320 case PSS: 3321 if (!intel_pstate_no_acpi_pss()) 3322 return false; 3323 3324 return intel_pstate_no_acpi_pcch(); 3325 case PPC: 3326 return intel_pstate_has_acpi_ppc() && !force_load; 3327 } 3328 3329 return false; 3330 } 3331 3332 static void intel_pstate_request_control_from_smm(void) 3333 { 3334 /* 3335 * It may be unsafe to request P-states control from SMM if _PPC support 3336 * has not been enabled. 3337 */ 3338 if (acpi_ppc) 3339 acpi_processor_pstate_control(); 3340 } 3341 #else /* CONFIG_ACPI not enabled */ 3342 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; } 3343 static inline bool intel_pstate_has_acpi_ppc(void) { return false; } 3344 static inline void intel_pstate_request_control_from_smm(void) {} 3345 #endif /* CONFIG_ACPI */ 3346 3347 #define INTEL_PSTATE_HWP_BROADWELL 0x01 3348 3349 #define X86_MATCH_HWP(model, hwp_mode) \ 3350 X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \ 3351 X86_FEATURE_HWP, hwp_mode) 3352 3353 static const struct x86_cpu_id hwp_support_ids[] __initconst = { 3354 X86_MATCH_HWP(BROADWELL_X, INTEL_PSTATE_HWP_BROADWELL), 3355 X86_MATCH_HWP(BROADWELL_D, INTEL_PSTATE_HWP_BROADWELL), 3356 X86_MATCH_HWP(ANY, 0), 3357 {} 3358 }; 3359 3360 static bool intel_pstate_hwp_is_enabled(void) 3361 { 3362 u64 value; 3363 3364 rdmsrl(MSR_PM_ENABLE, value); 3365 return !!(value & 0x1); 3366 } 3367 3368 #define POWERSAVE_MASK GENMASK(7, 0) 3369 #define BALANCE_POWER_MASK GENMASK(15, 8) 3370 #define BALANCE_PERFORMANCE_MASK GENMASK(23, 16) 3371 #define PERFORMANCE_MASK GENMASK(31, 24) 3372 3373 #define HWP_SET_EPP_VALUES(powersave, balance_power, balance_perf, performance) \ 3374 (FIELD_PREP_CONST(POWERSAVE_MASK, powersave) |\ 3375 FIELD_PREP_CONST(BALANCE_POWER_MASK, balance_power) |\ 3376 FIELD_PREP_CONST(BALANCE_PERFORMANCE_MASK, balance_perf) |\ 3377 FIELD_PREP_CONST(PERFORMANCE_MASK, performance)) 3378 3379 #define HWP_SET_DEF_BALANCE_PERF_EPP(balance_perf) \ 3380 (HWP_SET_EPP_VALUES(HWP_EPP_POWERSAVE, HWP_EPP_BALANCE_POWERSAVE,\ 3381 balance_perf, HWP_EPP_PERFORMANCE)) 3382 3383 static const struct x86_cpu_id intel_epp_default[] = { 3384 /* 3385 * Set EPP value as 102, this is the max suggested EPP 3386 * which can result in one core turbo frequency for 3387 * AlderLake Mobile CPUs. 3388 */ 3389 X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, HWP_SET_DEF_BALANCE_PERF_EPP(102)), 3390 X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, HWP_SET_DEF_BALANCE_PERF_EPP(32)), 3391 X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE_L, HWP_SET_EPP_VALUES(HWP_EPP_POWERSAVE, 3392 HWP_EPP_BALANCE_POWERSAVE, 115, 16)), 3393 {} 3394 }; 3395 3396 static const struct x86_cpu_id intel_hybrid_scaling_factor[] = { 3397 X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE_L, HYBRID_SCALING_FACTOR_MTL), 3398 {} 3399 }; 3400 3401 static int __init intel_pstate_init(void) 3402 { 3403 static struct cpudata **_all_cpu_data; 3404 const struct x86_cpu_id *id; 3405 int rc; 3406 3407 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) 3408 return -ENODEV; 3409 3410 id = x86_match_cpu(hwp_support_ids); 3411 if (id) { 3412 hwp_forced = intel_pstate_hwp_is_enabled(); 3413 3414 if (hwp_forced) 3415 pr_info("HWP enabled by BIOS\n"); 3416 else if (no_load) 3417 return -ENODEV; 3418 3419 copy_cpu_funcs(&core_funcs); 3420 /* 3421 * Avoid enabling HWP for processors without EPP support, 3422 * because that means incomplete HWP implementation which is a 3423 * corner case and supporting it is generally problematic. 3424 * 3425 * If HWP is enabled already, though, there is no choice but to 3426 * deal with it. 3427 */ 3428 if ((!no_hwp && boot_cpu_has(X86_FEATURE_HWP_EPP)) || hwp_forced) { 3429 hwp_active = true; 3430 hwp_mode_bdw = id->driver_data; 3431 intel_pstate.attr = hwp_cpufreq_attrs; 3432 intel_cpufreq.attr = hwp_cpufreq_attrs; 3433 intel_cpufreq.flags |= CPUFREQ_NEED_UPDATE_LIMITS; 3434 intel_cpufreq.adjust_perf = intel_cpufreq_adjust_perf; 3435 if (!default_driver) 3436 default_driver = &intel_pstate; 3437 3438 pstate_funcs.get_cpu_scaling = hwp_get_cpu_scaling; 3439 3440 goto hwp_cpu_matched; 3441 } 3442 pr_info("HWP not enabled\n"); 3443 } else { 3444 if (no_load) 3445 return -ENODEV; 3446 3447 id = x86_match_cpu(intel_pstate_cpu_ids); 3448 if (!id) { 3449 pr_info("CPU model not supported\n"); 3450 return -ENODEV; 3451 } 3452 3453 copy_cpu_funcs((struct pstate_funcs *)id->driver_data); 3454 } 3455 3456 if (intel_pstate_msrs_not_valid()) { 3457 pr_info("Invalid MSRs\n"); 3458 return -ENODEV; 3459 } 3460 /* Without HWP start in the passive mode. */ 3461 if (!default_driver) 3462 default_driver = &intel_cpufreq; 3463 3464 hwp_cpu_matched: 3465 /* 3466 * The Intel pstate driver will be ignored if the platform 3467 * firmware has its own power management modes. 3468 */ 3469 if (intel_pstate_platform_pwr_mgmt_exists()) { 3470 pr_info("P-states controlled by the platform\n"); 3471 return -ENODEV; 3472 } 3473 3474 if (!hwp_active && hwp_only) 3475 return -ENOTSUPP; 3476 3477 pr_info("Intel P-state driver initializing\n"); 3478 3479 _all_cpu_data = vzalloc(array_size(sizeof(void *), num_possible_cpus())); 3480 if (!_all_cpu_data) 3481 return -ENOMEM; 3482 3483 WRITE_ONCE(all_cpu_data, _all_cpu_data); 3484 3485 intel_pstate_request_control_from_smm(); 3486 3487 intel_pstate_sysfs_expose_params(); 3488 3489 if (hwp_active) { 3490 const struct x86_cpu_id *id = x86_match_cpu(intel_epp_default); 3491 const struct x86_cpu_id *hybrid_id = x86_match_cpu(intel_hybrid_scaling_factor); 3492 3493 if (id) { 3494 epp_values[EPP_INDEX_POWERSAVE] = 3495 FIELD_GET(POWERSAVE_MASK, id->driver_data); 3496 epp_values[EPP_INDEX_BALANCE_POWERSAVE] = 3497 FIELD_GET(BALANCE_POWER_MASK, id->driver_data); 3498 epp_values[EPP_INDEX_BALANCE_PERFORMANCE] = 3499 FIELD_GET(BALANCE_PERFORMANCE_MASK, id->driver_data); 3500 epp_values[EPP_INDEX_PERFORMANCE] = 3501 FIELD_GET(PERFORMANCE_MASK, id->driver_data); 3502 pr_debug("Updated EPPs powersave:%x balanced power:%x balanced perf:%x performance:%x\n", 3503 epp_values[EPP_INDEX_POWERSAVE], 3504 epp_values[EPP_INDEX_BALANCE_POWERSAVE], 3505 epp_values[EPP_INDEX_BALANCE_PERFORMANCE], 3506 epp_values[EPP_INDEX_PERFORMANCE]); 3507 } 3508 3509 if (hybrid_id) { 3510 hybrid_scaling_factor = hybrid_id->driver_data; 3511 pr_debug("hybrid scaling factor: %d\n", hybrid_scaling_factor); 3512 } 3513 3514 } 3515 3516 mutex_lock(&intel_pstate_driver_lock); 3517 rc = intel_pstate_register_driver(default_driver); 3518 mutex_unlock(&intel_pstate_driver_lock); 3519 if (rc) { 3520 intel_pstate_sysfs_remove(); 3521 return rc; 3522 } 3523 3524 if (hwp_active) { 3525 const struct x86_cpu_id *id; 3526 3527 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids); 3528 if (id) { 3529 set_power_ctl_ee_state(false); 3530 pr_info("Disabling energy efficiency optimization\n"); 3531 } 3532 3533 pr_info("HWP enabled\n"); 3534 } else if (boot_cpu_has(X86_FEATURE_HYBRID_CPU)) { 3535 pr_warn("Problematic setup: Hybrid processor with disabled HWP\n"); 3536 } 3537 3538 return 0; 3539 } 3540 device_initcall(intel_pstate_init); 3541 3542 static int __init intel_pstate_setup(char *str) 3543 { 3544 if (!str) 3545 return -EINVAL; 3546 3547 if (!strcmp(str, "disable")) 3548 no_load = 1; 3549 else if (!strcmp(str, "active")) 3550 default_driver = &intel_pstate; 3551 else if (!strcmp(str, "passive")) 3552 default_driver = &intel_cpufreq; 3553 3554 if (!strcmp(str, "no_hwp")) 3555 no_hwp = 1; 3556 3557 if (!strcmp(str, "force")) 3558 force_load = 1; 3559 if (!strcmp(str, "hwp_only")) 3560 hwp_only = 1; 3561 if (!strcmp(str, "per_cpu_perf_limits")) 3562 per_cpu_limits = true; 3563 3564 #ifdef CONFIG_ACPI 3565 if (!strcmp(str, "support_acpi_ppc")) 3566 acpi_ppc = true; 3567 #endif 3568 3569 return 0; 3570 } 3571 early_param("intel_pstate", intel_pstate_setup); 3572 3573 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>"); 3574 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors"); 3575