1 /* 2 * intel_pstate.c: Native P state management for Intel processors 3 * 4 * (C) Copyright 2012 Intel Corporation 5 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; version 2 10 * of the License. 11 */ 12 13 #include <linux/kernel.h> 14 #include <linux/kernel_stat.h> 15 #include <linux/module.h> 16 #include <linux/ktime.h> 17 #include <linux/hrtimer.h> 18 #include <linux/tick.h> 19 #include <linux/slab.h> 20 #include <linux/sched.h> 21 #include <linux/list.h> 22 #include <linux/cpu.h> 23 #include <linux/cpufreq.h> 24 #include <linux/sysfs.h> 25 #include <linux/types.h> 26 #include <linux/fs.h> 27 #include <linux/debugfs.h> 28 #include <linux/acpi.h> 29 #include <linux/vmalloc.h> 30 #include <trace/events/power.h> 31 32 #include <asm/div64.h> 33 #include <asm/msr.h> 34 #include <asm/cpu_device_id.h> 35 #include <asm/cpufeature.h> 36 37 #define BYT_RATIOS 0x66a 38 #define BYT_VIDS 0x66b 39 #define BYT_TURBO_RATIOS 0x66c 40 #define BYT_TURBO_VIDS 0x66d 41 42 #define FRAC_BITS 8 43 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS) 44 #define fp_toint(X) ((X) >> FRAC_BITS) 45 46 47 static inline int32_t mul_fp(int32_t x, int32_t y) 48 { 49 return ((int64_t)x * (int64_t)y) >> FRAC_BITS; 50 } 51 52 static inline int32_t div_fp(s64 x, s64 y) 53 { 54 return div64_s64((int64_t)x << FRAC_BITS, y); 55 } 56 57 static inline int ceiling_fp(int32_t x) 58 { 59 int mask, ret; 60 61 ret = fp_toint(x); 62 mask = (1 << FRAC_BITS) - 1; 63 if (x & mask) 64 ret += 1; 65 return ret; 66 } 67 68 struct sample { 69 int32_t core_pct_busy; 70 u64 aperf; 71 u64 mperf; 72 u64 tsc; 73 int freq; 74 ktime_t time; 75 }; 76 77 struct pstate_data { 78 int current_pstate; 79 int min_pstate; 80 int max_pstate; 81 int scaling; 82 int turbo_pstate; 83 }; 84 85 struct vid_data { 86 int min; 87 int max; 88 int turbo; 89 int32_t ratio; 90 }; 91 92 struct _pid { 93 int setpoint; 94 int32_t integral; 95 int32_t p_gain; 96 int32_t i_gain; 97 int32_t d_gain; 98 int deadband; 99 int32_t last_err; 100 }; 101 102 struct cpudata { 103 int cpu; 104 105 struct timer_list timer; 106 107 struct pstate_data pstate; 108 struct vid_data vid; 109 struct _pid pid; 110 111 ktime_t last_sample_time; 112 u64 prev_aperf; 113 u64 prev_mperf; 114 u64 prev_tsc; 115 struct sample sample; 116 }; 117 118 static struct cpudata **all_cpu_data; 119 struct pstate_adjust_policy { 120 int sample_rate_ms; 121 int deadband; 122 int setpoint; 123 int p_gain_pct; 124 int d_gain_pct; 125 int i_gain_pct; 126 }; 127 128 struct pstate_funcs { 129 int (*get_max)(void); 130 int (*get_min)(void); 131 int (*get_turbo)(void); 132 int (*get_scaling)(void); 133 void (*set)(struct cpudata*, int pstate); 134 void (*get_vid)(struct cpudata *); 135 }; 136 137 struct cpu_defaults { 138 struct pstate_adjust_policy pid_policy; 139 struct pstate_funcs funcs; 140 }; 141 142 static struct pstate_adjust_policy pid_params; 143 static struct pstate_funcs pstate_funcs; 144 static int hwp_active; 145 146 struct perf_limits { 147 int no_turbo; 148 int turbo_disabled; 149 int max_perf_pct; 150 int min_perf_pct; 151 int32_t max_perf; 152 int32_t min_perf; 153 int max_policy_pct; 154 int max_sysfs_pct; 155 int min_policy_pct; 156 int min_sysfs_pct; 157 }; 158 159 static struct perf_limits limits = { 160 .no_turbo = 0, 161 .turbo_disabled = 0, 162 .max_perf_pct = 100, 163 .max_perf = int_tofp(1), 164 .min_perf_pct = 0, 165 .min_perf = 0, 166 .max_policy_pct = 100, 167 .max_sysfs_pct = 100, 168 .min_policy_pct = 0, 169 .min_sysfs_pct = 0, 170 }; 171 172 static inline void pid_reset(struct _pid *pid, int setpoint, int busy, 173 int deadband, int integral) { 174 pid->setpoint = setpoint; 175 pid->deadband = deadband; 176 pid->integral = int_tofp(integral); 177 pid->last_err = int_tofp(setpoint) - int_tofp(busy); 178 } 179 180 static inline void pid_p_gain_set(struct _pid *pid, int percent) 181 { 182 pid->p_gain = div_fp(int_tofp(percent), int_tofp(100)); 183 } 184 185 static inline void pid_i_gain_set(struct _pid *pid, int percent) 186 { 187 pid->i_gain = div_fp(int_tofp(percent), int_tofp(100)); 188 } 189 190 static inline void pid_d_gain_set(struct _pid *pid, int percent) 191 { 192 pid->d_gain = div_fp(int_tofp(percent), int_tofp(100)); 193 } 194 195 static signed int pid_calc(struct _pid *pid, int32_t busy) 196 { 197 signed int result; 198 int32_t pterm, dterm, fp_error; 199 int32_t integral_limit; 200 201 fp_error = int_tofp(pid->setpoint) - busy; 202 203 if (abs(fp_error) <= int_tofp(pid->deadband)) 204 return 0; 205 206 pterm = mul_fp(pid->p_gain, fp_error); 207 208 pid->integral += fp_error; 209 210 /* 211 * We limit the integral here so that it will never 212 * get higher than 30. This prevents it from becoming 213 * too large an input over long periods of time and allows 214 * it to get factored out sooner. 215 * 216 * The value of 30 was chosen through experimentation. 217 */ 218 integral_limit = int_tofp(30); 219 if (pid->integral > integral_limit) 220 pid->integral = integral_limit; 221 if (pid->integral < -integral_limit) 222 pid->integral = -integral_limit; 223 224 dterm = mul_fp(pid->d_gain, fp_error - pid->last_err); 225 pid->last_err = fp_error; 226 227 result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm; 228 result = result + (1 << (FRAC_BITS-1)); 229 return (signed int)fp_toint(result); 230 } 231 232 static inline void intel_pstate_busy_pid_reset(struct cpudata *cpu) 233 { 234 pid_p_gain_set(&cpu->pid, pid_params.p_gain_pct); 235 pid_d_gain_set(&cpu->pid, pid_params.d_gain_pct); 236 pid_i_gain_set(&cpu->pid, pid_params.i_gain_pct); 237 238 pid_reset(&cpu->pid, pid_params.setpoint, 100, pid_params.deadband, 0); 239 } 240 241 static inline void intel_pstate_reset_all_pid(void) 242 { 243 unsigned int cpu; 244 245 for_each_online_cpu(cpu) { 246 if (all_cpu_data[cpu]) 247 intel_pstate_busy_pid_reset(all_cpu_data[cpu]); 248 } 249 } 250 251 static inline void update_turbo_state(void) 252 { 253 u64 misc_en; 254 struct cpudata *cpu; 255 256 cpu = all_cpu_data[0]; 257 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en); 258 limits.turbo_disabled = 259 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE || 260 cpu->pstate.max_pstate == cpu->pstate.turbo_pstate); 261 } 262 263 #define PCT_TO_HWP(x) (x * 255 / 100) 264 static void intel_pstate_hwp_set(void) 265 { 266 int min, max, cpu; 267 u64 value, freq; 268 269 get_online_cpus(); 270 271 for_each_online_cpu(cpu) { 272 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value); 273 min = PCT_TO_HWP(limits.min_perf_pct); 274 value &= ~HWP_MIN_PERF(~0L); 275 value |= HWP_MIN_PERF(min); 276 277 max = PCT_TO_HWP(limits.max_perf_pct); 278 if (limits.no_turbo) { 279 rdmsrl( MSR_HWP_CAPABILITIES, freq); 280 max = HWP_GUARANTEED_PERF(freq); 281 } 282 283 value &= ~HWP_MAX_PERF(~0L); 284 value |= HWP_MAX_PERF(max); 285 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value); 286 } 287 288 put_online_cpus(); 289 } 290 291 /************************** debugfs begin ************************/ 292 static int pid_param_set(void *data, u64 val) 293 { 294 *(u32 *)data = val; 295 intel_pstate_reset_all_pid(); 296 return 0; 297 } 298 299 static int pid_param_get(void *data, u64 *val) 300 { 301 *val = *(u32 *)data; 302 return 0; 303 } 304 DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get, pid_param_set, "%llu\n"); 305 306 struct pid_param { 307 char *name; 308 void *value; 309 }; 310 311 static struct pid_param pid_files[] = { 312 {"sample_rate_ms", &pid_params.sample_rate_ms}, 313 {"d_gain_pct", &pid_params.d_gain_pct}, 314 {"i_gain_pct", &pid_params.i_gain_pct}, 315 {"deadband", &pid_params.deadband}, 316 {"setpoint", &pid_params.setpoint}, 317 {"p_gain_pct", &pid_params.p_gain_pct}, 318 {NULL, NULL} 319 }; 320 321 static void __init intel_pstate_debug_expose_params(void) 322 { 323 struct dentry *debugfs_parent; 324 int i = 0; 325 326 if (hwp_active) 327 return; 328 debugfs_parent = debugfs_create_dir("pstate_snb", NULL); 329 if (IS_ERR_OR_NULL(debugfs_parent)) 330 return; 331 while (pid_files[i].name) { 332 debugfs_create_file(pid_files[i].name, 0660, 333 debugfs_parent, pid_files[i].value, 334 &fops_pid_param); 335 i++; 336 } 337 } 338 339 /************************** debugfs end ************************/ 340 341 /************************** sysfs begin ************************/ 342 #define show_one(file_name, object) \ 343 static ssize_t show_##file_name \ 344 (struct kobject *kobj, struct attribute *attr, char *buf) \ 345 { \ 346 return sprintf(buf, "%u\n", limits.object); \ 347 } 348 349 static ssize_t show_turbo_pct(struct kobject *kobj, 350 struct attribute *attr, char *buf) 351 { 352 struct cpudata *cpu; 353 int total, no_turbo, turbo_pct; 354 uint32_t turbo_fp; 355 356 cpu = all_cpu_data[0]; 357 358 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; 359 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1; 360 turbo_fp = div_fp(int_tofp(no_turbo), int_tofp(total)); 361 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100))); 362 return sprintf(buf, "%u\n", turbo_pct); 363 } 364 365 static ssize_t show_num_pstates(struct kobject *kobj, 366 struct attribute *attr, char *buf) 367 { 368 struct cpudata *cpu; 369 int total; 370 371 cpu = all_cpu_data[0]; 372 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; 373 return sprintf(buf, "%u\n", total); 374 } 375 376 static ssize_t show_no_turbo(struct kobject *kobj, 377 struct attribute *attr, char *buf) 378 { 379 ssize_t ret; 380 381 update_turbo_state(); 382 if (limits.turbo_disabled) 383 ret = sprintf(buf, "%u\n", limits.turbo_disabled); 384 else 385 ret = sprintf(buf, "%u\n", limits.no_turbo); 386 387 return ret; 388 } 389 390 static ssize_t store_no_turbo(struct kobject *a, struct attribute *b, 391 const char *buf, size_t count) 392 { 393 unsigned int input; 394 int ret; 395 396 ret = sscanf(buf, "%u", &input); 397 if (ret != 1) 398 return -EINVAL; 399 400 update_turbo_state(); 401 if (limits.turbo_disabled) { 402 pr_warn("intel_pstate: Turbo disabled by BIOS or unavailable on processor\n"); 403 return -EPERM; 404 } 405 406 limits.no_turbo = clamp_t(int, input, 0, 1); 407 408 if (hwp_active) 409 intel_pstate_hwp_set(); 410 411 return count; 412 } 413 414 static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b, 415 const char *buf, size_t count) 416 { 417 unsigned int input; 418 int ret; 419 420 ret = sscanf(buf, "%u", &input); 421 if (ret != 1) 422 return -EINVAL; 423 424 limits.max_sysfs_pct = clamp_t(int, input, 0 , 100); 425 limits.max_perf_pct = min(limits.max_policy_pct, limits.max_sysfs_pct); 426 limits.max_perf = div_fp(int_tofp(limits.max_perf_pct), int_tofp(100)); 427 428 if (hwp_active) 429 intel_pstate_hwp_set(); 430 return count; 431 } 432 433 static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b, 434 const char *buf, size_t count) 435 { 436 unsigned int input; 437 int ret; 438 439 ret = sscanf(buf, "%u", &input); 440 if (ret != 1) 441 return -EINVAL; 442 443 limits.min_sysfs_pct = clamp_t(int, input, 0 , 100); 444 limits.min_perf_pct = max(limits.min_policy_pct, limits.min_sysfs_pct); 445 limits.min_perf = div_fp(int_tofp(limits.min_perf_pct), int_tofp(100)); 446 447 if (hwp_active) 448 intel_pstate_hwp_set(); 449 return count; 450 } 451 452 show_one(max_perf_pct, max_perf_pct); 453 show_one(min_perf_pct, min_perf_pct); 454 455 define_one_global_rw(no_turbo); 456 define_one_global_rw(max_perf_pct); 457 define_one_global_rw(min_perf_pct); 458 define_one_global_ro(turbo_pct); 459 define_one_global_ro(num_pstates); 460 461 static struct attribute *intel_pstate_attributes[] = { 462 &no_turbo.attr, 463 &max_perf_pct.attr, 464 &min_perf_pct.attr, 465 &turbo_pct.attr, 466 &num_pstates.attr, 467 NULL 468 }; 469 470 static struct attribute_group intel_pstate_attr_group = { 471 .attrs = intel_pstate_attributes, 472 }; 473 474 static void __init intel_pstate_sysfs_expose_params(void) 475 { 476 struct kobject *intel_pstate_kobject; 477 int rc; 478 479 intel_pstate_kobject = kobject_create_and_add("intel_pstate", 480 &cpu_subsys.dev_root->kobj); 481 BUG_ON(!intel_pstate_kobject); 482 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group); 483 BUG_ON(rc); 484 } 485 /************************** sysfs end ************************/ 486 487 static void intel_pstate_hwp_enable(void) 488 { 489 hwp_active++; 490 pr_info("intel_pstate: HWP enabled\n"); 491 492 wrmsrl( MSR_PM_ENABLE, 0x1); 493 } 494 495 static int byt_get_min_pstate(void) 496 { 497 u64 value; 498 499 rdmsrl(BYT_RATIOS, value); 500 return (value >> 8) & 0x7F; 501 } 502 503 static int byt_get_max_pstate(void) 504 { 505 u64 value; 506 507 rdmsrl(BYT_RATIOS, value); 508 return (value >> 16) & 0x7F; 509 } 510 511 static int byt_get_turbo_pstate(void) 512 { 513 u64 value; 514 515 rdmsrl(BYT_TURBO_RATIOS, value); 516 return value & 0x7F; 517 } 518 519 static void byt_set_pstate(struct cpudata *cpudata, int pstate) 520 { 521 u64 val; 522 int32_t vid_fp; 523 u32 vid; 524 525 val = pstate << 8; 526 if (limits.no_turbo && !limits.turbo_disabled) 527 val |= (u64)1 << 32; 528 529 vid_fp = cpudata->vid.min + mul_fp( 530 int_tofp(pstate - cpudata->pstate.min_pstate), 531 cpudata->vid.ratio); 532 533 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max); 534 vid = ceiling_fp(vid_fp); 535 536 if (pstate > cpudata->pstate.max_pstate) 537 vid = cpudata->vid.turbo; 538 539 val |= vid; 540 541 wrmsrl_on_cpu(cpudata->cpu, MSR_IA32_PERF_CTL, val); 542 } 543 544 #define BYT_BCLK_FREQS 5 545 static int byt_freq_table[BYT_BCLK_FREQS] = { 833, 1000, 1333, 1167, 800}; 546 547 static int byt_get_scaling(void) 548 { 549 u64 value; 550 int i; 551 552 rdmsrl(MSR_FSB_FREQ, value); 553 i = value & 0x3; 554 555 BUG_ON(i > BYT_BCLK_FREQS); 556 557 return byt_freq_table[i] * 100; 558 } 559 560 static void byt_get_vid(struct cpudata *cpudata) 561 { 562 u64 value; 563 564 rdmsrl(BYT_VIDS, value); 565 cpudata->vid.min = int_tofp((value >> 8) & 0x7f); 566 cpudata->vid.max = int_tofp((value >> 16) & 0x7f); 567 cpudata->vid.ratio = div_fp( 568 cpudata->vid.max - cpudata->vid.min, 569 int_tofp(cpudata->pstate.max_pstate - 570 cpudata->pstate.min_pstate)); 571 572 rdmsrl(BYT_TURBO_VIDS, value); 573 cpudata->vid.turbo = value & 0x7f; 574 } 575 576 static int core_get_min_pstate(void) 577 { 578 u64 value; 579 580 rdmsrl(MSR_PLATFORM_INFO, value); 581 return (value >> 40) & 0xFF; 582 } 583 584 static int core_get_max_pstate(void) 585 { 586 u64 value; 587 588 rdmsrl(MSR_PLATFORM_INFO, value); 589 return (value >> 8) & 0xFF; 590 } 591 592 static int core_get_turbo_pstate(void) 593 { 594 u64 value; 595 int nont, ret; 596 597 rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT, value); 598 nont = core_get_max_pstate(); 599 ret = (value) & 255; 600 if (ret <= nont) 601 ret = nont; 602 return ret; 603 } 604 605 static inline int core_get_scaling(void) 606 { 607 return 100000; 608 } 609 610 static void core_set_pstate(struct cpudata *cpudata, int pstate) 611 { 612 u64 val; 613 614 val = pstate << 8; 615 if (limits.no_turbo && !limits.turbo_disabled) 616 val |= (u64)1 << 32; 617 618 wrmsrl_on_cpu(cpudata->cpu, MSR_IA32_PERF_CTL, val); 619 } 620 621 static int knl_get_turbo_pstate(void) 622 { 623 u64 value; 624 int nont, ret; 625 626 rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT, value); 627 nont = core_get_max_pstate(); 628 ret = (((value) >> 8) & 0xFF); 629 if (ret <= nont) 630 ret = nont; 631 return ret; 632 } 633 634 static struct cpu_defaults core_params = { 635 .pid_policy = { 636 .sample_rate_ms = 10, 637 .deadband = 0, 638 .setpoint = 97, 639 .p_gain_pct = 20, 640 .d_gain_pct = 0, 641 .i_gain_pct = 0, 642 }, 643 .funcs = { 644 .get_max = core_get_max_pstate, 645 .get_min = core_get_min_pstate, 646 .get_turbo = core_get_turbo_pstate, 647 .get_scaling = core_get_scaling, 648 .set = core_set_pstate, 649 }, 650 }; 651 652 static struct cpu_defaults byt_params = { 653 .pid_policy = { 654 .sample_rate_ms = 10, 655 .deadband = 0, 656 .setpoint = 60, 657 .p_gain_pct = 14, 658 .d_gain_pct = 0, 659 .i_gain_pct = 4, 660 }, 661 .funcs = { 662 .get_max = byt_get_max_pstate, 663 .get_min = byt_get_min_pstate, 664 .get_turbo = byt_get_turbo_pstate, 665 .set = byt_set_pstate, 666 .get_scaling = byt_get_scaling, 667 .get_vid = byt_get_vid, 668 }, 669 }; 670 671 static struct cpu_defaults knl_params = { 672 .pid_policy = { 673 .sample_rate_ms = 10, 674 .deadband = 0, 675 .setpoint = 97, 676 .p_gain_pct = 20, 677 .d_gain_pct = 0, 678 .i_gain_pct = 0, 679 }, 680 .funcs = { 681 .get_max = core_get_max_pstate, 682 .get_min = core_get_min_pstate, 683 .get_turbo = knl_get_turbo_pstate, 684 .set = core_set_pstate, 685 }, 686 }; 687 688 static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max) 689 { 690 int max_perf = cpu->pstate.turbo_pstate; 691 int max_perf_adj; 692 int min_perf; 693 694 if (limits.no_turbo || limits.turbo_disabled) 695 max_perf = cpu->pstate.max_pstate; 696 697 /* 698 * performance can be limited by user through sysfs, by cpufreq 699 * policy, or by cpu specific default values determined through 700 * experimentation. 701 */ 702 max_perf_adj = fp_toint(mul_fp(int_tofp(max_perf), limits.max_perf)); 703 *max = clamp_t(int, max_perf_adj, 704 cpu->pstate.min_pstate, cpu->pstate.turbo_pstate); 705 706 min_perf = fp_toint(mul_fp(int_tofp(max_perf), limits.min_perf)); 707 *min = clamp_t(int, min_perf, cpu->pstate.min_pstate, max_perf); 708 } 709 710 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate, bool force) 711 { 712 int max_perf, min_perf; 713 714 if (force) { 715 update_turbo_state(); 716 717 intel_pstate_get_min_max(cpu, &min_perf, &max_perf); 718 719 pstate = clamp_t(int, pstate, min_perf, max_perf); 720 721 if (pstate == cpu->pstate.current_pstate) 722 return; 723 } 724 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu); 725 726 cpu->pstate.current_pstate = pstate; 727 728 pstate_funcs.set(cpu, pstate); 729 } 730 731 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu) 732 { 733 cpu->pstate.min_pstate = pstate_funcs.get_min(); 734 cpu->pstate.max_pstate = pstate_funcs.get_max(); 735 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(); 736 cpu->pstate.scaling = pstate_funcs.get_scaling(); 737 738 if (pstate_funcs.get_vid) 739 pstate_funcs.get_vid(cpu); 740 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate, false); 741 } 742 743 static inline void intel_pstate_calc_busy(struct cpudata *cpu) 744 { 745 struct sample *sample = &cpu->sample; 746 int64_t core_pct; 747 748 core_pct = int_tofp(sample->aperf) * int_tofp(100); 749 core_pct = div64_u64(core_pct, int_tofp(sample->mperf)); 750 751 sample->freq = fp_toint( 752 mul_fp(int_tofp( 753 cpu->pstate.max_pstate * cpu->pstate.scaling / 100), 754 core_pct)); 755 756 sample->core_pct_busy = (int32_t)core_pct; 757 } 758 759 static inline void intel_pstate_sample(struct cpudata *cpu) 760 { 761 u64 aperf, mperf; 762 unsigned long flags; 763 u64 tsc; 764 765 local_irq_save(flags); 766 rdmsrl(MSR_IA32_APERF, aperf); 767 rdmsrl(MSR_IA32_MPERF, mperf); 768 tsc = native_read_tsc(); 769 local_irq_restore(flags); 770 771 cpu->last_sample_time = cpu->sample.time; 772 cpu->sample.time = ktime_get(); 773 cpu->sample.aperf = aperf; 774 cpu->sample.mperf = mperf; 775 cpu->sample.tsc = tsc; 776 cpu->sample.aperf -= cpu->prev_aperf; 777 cpu->sample.mperf -= cpu->prev_mperf; 778 cpu->sample.tsc -= cpu->prev_tsc; 779 780 intel_pstate_calc_busy(cpu); 781 782 cpu->prev_aperf = aperf; 783 cpu->prev_mperf = mperf; 784 cpu->prev_tsc = tsc; 785 } 786 787 static inline void intel_hwp_set_sample_time(struct cpudata *cpu) 788 { 789 int delay; 790 791 delay = msecs_to_jiffies(50); 792 mod_timer_pinned(&cpu->timer, jiffies + delay); 793 } 794 795 static inline void intel_pstate_set_sample_time(struct cpudata *cpu) 796 { 797 int delay; 798 799 delay = msecs_to_jiffies(pid_params.sample_rate_ms); 800 mod_timer_pinned(&cpu->timer, jiffies + delay); 801 } 802 803 static inline int32_t intel_pstate_get_scaled_busy(struct cpudata *cpu) 804 { 805 int32_t core_busy, max_pstate, current_pstate, sample_ratio; 806 s64 duration_us; 807 u32 sample_time; 808 809 /* 810 * core_busy is the ratio of actual performance to max 811 * max_pstate is the max non turbo pstate available 812 * current_pstate was the pstate that was requested during 813 * the last sample period. 814 * 815 * We normalize core_busy, which was our actual percent 816 * performance to what we requested during the last sample 817 * period. The result will be a percentage of busy at a 818 * specified pstate. 819 */ 820 core_busy = cpu->sample.core_pct_busy; 821 max_pstate = int_tofp(cpu->pstate.max_pstate); 822 current_pstate = int_tofp(cpu->pstate.current_pstate); 823 core_busy = mul_fp(core_busy, div_fp(max_pstate, current_pstate)); 824 825 /* 826 * Since we have a deferred timer, it will not fire unless 827 * we are in C0. So, determine if the actual elapsed time 828 * is significantly greater (3x) than our sample interval. If it 829 * is, then we were idle for a long enough period of time 830 * to adjust our busyness. 831 */ 832 sample_time = pid_params.sample_rate_ms * USEC_PER_MSEC; 833 duration_us = ktime_us_delta(cpu->sample.time, 834 cpu->last_sample_time); 835 if (duration_us > sample_time * 3) { 836 sample_ratio = div_fp(int_tofp(sample_time), 837 int_tofp(duration_us)); 838 core_busy = mul_fp(core_busy, sample_ratio); 839 } 840 841 return core_busy; 842 } 843 844 static inline void intel_pstate_adjust_busy_pstate(struct cpudata *cpu) 845 { 846 int32_t busy_scaled; 847 struct _pid *pid; 848 signed int ctl; 849 int from; 850 struct sample *sample; 851 852 from = cpu->pstate.current_pstate; 853 854 pid = &cpu->pid; 855 busy_scaled = intel_pstate_get_scaled_busy(cpu); 856 857 ctl = pid_calc(pid, busy_scaled); 858 859 /* Negative values of ctl increase the pstate and vice versa */ 860 intel_pstate_set_pstate(cpu, cpu->pstate.current_pstate - ctl, true); 861 862 sample = &cpu->sample; 863 trace_pstate_sample(fp_toint(sample->core_pct_busy), 864 fp_toint(busy_scaled), 865 from, 866 cpu->pstate.current_pstate, 867 sample->mperf, 868 sample->aperf, 869 sample->tsc, 870 sample->freq); 871 } 872 873 static void intel_hwp_timer_func(unsigned long __data) 874 { 875 struct cpudata *cpu = (struct cpudata *) __data; 876 877 intel_pstate_sample(cpu); 878 intel_hwp_set_sample_time(cpu); 879 } 880 881 static void intel_pstate_timer_func(unsigned long __data) 882 { 883 struct cpudata *cpu = (struct cpudata *) __data; 884 885 intel_pstate_sample(cpu); 886 887 intel_pstate_adjust_busy_pstate(cpu); 888 889 intel_pstate_set_sample_time(cpu); 890 } 891 892 #define ICPU(model, policy) \ 893 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\ 894 (unsigned long)&policy } 895 896 static const struct x86_cpu_id intel_pstate_cpu_ids[] = { 897 ICPU(0x2a, core_params), 898 ICPU(0x2d, core_params), 899 ICPU(0x37, byt_params), 900 ICPU(0x3a, core_params), 901 ICPU(0x3c, core_params), 902 ICPU(0x3d, core_params), 903 ICPU(0x3e, core_params), 904 ICPU(0x3f, core_params), 905 ICPU(0x45, core_params), 906 ICPU(0x46, core_params), 907 ICPU(0x47, core_params), 908 ICPU(0x4c, byt_params), 909 ICPU(0x4e, core_params), 910 ICPU(0x4f, core_params), 911 ICPU(0x56, core_params), 912 ICPU(0x57, knl_params), 913 {} 914 }; 915 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids); 916 917 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] = { 918 ICPU(0x56, core_params), 919 {} 920 }; 921 922 static int intel_pstate_init_cpu(unsigned int cpunum) 923 { 924 struct cpudata *cpu; 925 926 if (!all_cpu_data[cpunum]) 927 all_cpu_data[cpunum] = kzalloc(sizeof(struct cpudata), 928 GFP_KERNEL); 929 if (!all_cpu_data[cpunum]) 930 return -ENOMEM; 931 932 cpu = all_cpu_data[cpunum]; 933 934 cpu->cpu = cpunum; 935 intel_pstate_get_cpu_pstates(cpu); 936 937 init_timer_deferrable(&cpu->timer); 938 cpu->timer.data = (unsigned long)cpu; 939 cpu->timer.expires = jiffies + HZ/100; 940 941 if (!hwp_active) 942 cpu->timer.function = intel_pstate_timer_func; 943 else 944 cpu->timer.function = intel_hwp_timer_func; 945 946 intel_pstate_busy_pid_reset(cpu); 947 intel_pstate_sample(cpu); 948 949 add_timer_on(&cpu->timer, cpunum); 950 951 pr_debug("intel_pstate: controlling: cpu %d\n", cpunum); 952 953 return 0; 954 } 955 956 static unsigned int intel_pstate_get(unsigned int cpu_num) 957 { 958 struct sample *sample; 959 struct cpudata *cpu; 960 961 cpu = all_cpu_data[cpu_num]; 962 if (!cpu) 963 return 0; 964 sample = &cpu->sample; 965 return sample->freq; 966 } 967 968 static int intel_pstate_set_policy(struct cpufreq_policy *policy) 969 { 970 if (!policy->cpuinfo.max_freq) 971 return -ENODEV; 972 973 if (policy->policy == CPUFREQ_POLICY_PERFORMANCE && 974 policy->max >= policy->cpuinfo.max_freq) { 975 limits.min_policy_pct = 100; 976 limits.min_perf_pct = 100; 977 limits.min_perf = int_tofp(1); 978 limits.max_policy_pct = 100; 979 limits.max_perf_pct = 100; 980 limits.max_perf = int_tofp(1); 981 limits.no_turbo = 0; 982 return 0; 983 } 984 985 limits.min_policy_pct = (policy->min * 100) / policy->cpuinfo.max_freq; 986 limits.min_policy_pct = clamp_t(int, limits.min_policy_pct, 0 , 100); 987 limits.min_perf_pct = max(limits.min_policy_pct, limits.min_sysfs_pct); 988 limits.min_perf = div_fp(int_tofp(limits.min_perf_pct), int_tofp(100)); 989 990 limits.max_policy_pct = (policy->max * 100) / policy->cpuinfo.max_freq; 991 limits.max_policy_pct = clamp_t(int, limits.max_policy_pct, 0 , 100); 992 limits.max_perf_pct = min(limits.max_policy_pct, limits.max_sysfs_pct); 993 limits.max_perf = div_fp(int_tofp(limits.max_perf_pct), int_tofp(100)); 994 995 if (hwp_active) 996 intel_pstate_hwp_set(); 997 998 return 0; 999 } 1000 1001 static int intel_pstate_verify_policy(struct cpufreq_policy *policy) 1002 { 1003 cpufreq_verify_within_cpu_limits(policy); 1004 1005 if (policy->policy != CPUFREQ_POLICY_POWERSAVE && 1006 policy->policy != CPUFREQ_POLICY_PERFORMANCE) 1007 return -EINVAL; 1008 1009 return 0; 1010 } 1011 1012 static void intel_pstate_stop_cpu(struct cpufreq_policy *policy) 1013 { 1014 int cpu_num = policy->cpu; 1015 struct cpudata *cpu = all_cpu_data[cpu_num]; 1016 1017 pr_debug("intel_pstate: CPU %d exiting\n", cpu_num); 1018 1019 del_timer_sync(&all_cpu_data[cpu_num]->timer); 1020 if (hwp_active) 1021 return; 1022 1023 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate, false); 1024 } 1025 1026 static int intel_pstate_cpu_init(struct cpufreq_policy *policy) 1027 { 1028 struct cpudata *cpu; 1029 int rc; 1030 1031 rc = intel_pstate_init_cpu(policy->cpu); 1032 if (rc) 1033 return rc; 1034 1035 cpu = all_cpu_data[policy->cpu]; 1036 1037 if (limits.min_perf_pct == 100 && limits.max_perf_pct == 100) 1038 policy->policy = CPUFREQ_POLICY_PERFORMANCE; 1039 else 1040 policy->policy = CPUFREQ_POLICY_POWERSAVE; 1041 1042 policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling; 1043 policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling; 1044 1045 /* cpuinfo and default policy values */ 1046 policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling; 1047 policy->cpuinfo.max_freq = 1048 cpu->pstate.turbo_pstate * cpu->pstate.scaling; 1049 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; 1050 cpumask_set_cpu(policy->cpu, policy->cpus); 1051 1052 return 0; 1053 } 1054 1055 static struct cpufreq_driver intel_pstate_driver = { 1056 .flags = CPUFREQ_CONST_LOOPS, 1057 .verify = intel_pstate_verify_policy, 1058 .setpolicy = intel_pstate_set_policy, 1059 .get = intel_pstate_get, 1060 .init = intel_pstate_cpu_init, 1061 .stop_cpu = intel_pstate_stop_cpu, 1062 .name = "intel_pstate", 1063 }; 1064 1065 static int __initdata no_load; 1066 static int __initdata no_hwp; 1067 static int __initdata hwp_only; 1068 static unsigned int force_load; 1069 1070 static int intel_pstate_msrs_not_valid(void) 1071 { 1072 if (!pstate_funcs.get_max() || 1073 !pstate_funcs.get_min() || 1074 !pstate_funcs.get_turbo()) 1075 return -ENODEV; 1076 1077 return 0; 1078 } 1079 1080 static void copy_pid_params(struct pstate_adjust_policy *policy) 1081 { 1082 pid_params.sample_rate_ms = policy->sample_rate_ms; 1083 pid_params.p_gain_pct = policy->p_gain_pct; 1084 pid_params.i_gain_pct = policy->i_gain_pct; 1085 pid_params.d_gain_pct = policy->d_gain_pct; 1086 pid_params.deadband = policy->deadband; 1087 pid_params.setpoint = policy->setpoint; 1088 } 1089 1090 static void copy_cpu_funcs(struct pstate_funcs *funcs) 1091 { 1092 pstate_funcs.get_max = funcs->get_max; 1093 pstate_funcs.get_min = funcs->get_min; 1094 pstate_funcs.get_turbo = funcs->get_turbo; 1095 pstate_funcs.get_scaling = funcs->get_scaling; 1096 pstate_funcs.set = funcs->set; 1097 pstate_funcs.get_vid = funcs->get_vid; 1098 } 1099 1100 #if IS_ENABLED(CONFIG_ACPI) 1101 #include <acpi/processor.h> 1102 1103 static bool intel_pstate_no_acpi_pss(void) 1104 { 1105 int i; 1106 1107 for_each_possible_cpu(i) { 1108 acpi_status status; 1109 union acpi_object *pss; 1110 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; 1111 struct acpi_processor *pr = per_cpu(processors, i); 1112 1113 if (!pr) 1114 continue; 1115 1116 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer); 1117 if (ACPI_FAILURE(status)) 1118 continue; 1119 1120 pss = buffer.pointer; 1121 if (pss && pss->type == ACPI_TYPE_PACKAGE) { 1122 kfree(pss); 1123 return false; 1124 } 1125 1126 kfree(pss); 1127 } 1128 1129 return true; 1130 } 1131 1132 static bool intel_pstate_has_acpi_ppc(void) 1133 { 1134 int i; 1135 1136 for_each_possible_cpu(i) { 1137 struct acpi_processor *pr = per_cpu(processors, i); 1138 1139 if (!pr) 1140 continue; 1141 if (acpi_has_method(pr->handle, "_PPC")) 1142 return true; 1143 } 1144 return false; 1145 } 1146 1147 enum { 1148 PSS, 1149 PPC, 1150 }; 1151 1152 struct hw_vendor_info { 1153 u16 valid; 1154 char oem_id[ACPI_OEM_ID_SIZE]; 1155 char oem_table_id[ACPI_OEM_TABLE_ID_SIZE]; 1156 int oem_pwr_table; 1157 }; 1158 1159 /* Hardware vendor-specific info that has its own power management modes */ 1160 static struct hw_vendor_info vendor_info[] = { 1161 {1, "HP ", "ProLiant", PSS}, 1162 {1, "ORACLE", "X4-2 ", PPC}, 1163 {1, "ORACLE", "X4-2L ", PPC}, 1164 {1, "ORACLE", "X4-2B ", PPC}, 1165 {1, "ORACLE", "X3-2 ", PPC}, 1166 {1, "ORACLE", "X3-2L ", PPC}, 1167 {1, "ORACLE", "X3-2B ", PPC}, 1168 {1, "ORACLE", "X4470M2 ", PPC}, 1169 {1, "ORACLE", "X4270M3 ", PPC}, 1170 {1, "ORACLE", "X4270M2 ", PPC}, 1171 {1, "ORACLE", "X4170M2 ", PPC}, 1172 {0, "", ""}, 1173 }; 1174 1175 static bool intel_pstate_platform_pwr_mgmt_exists(void) 1176 { 1177 struct acpi_table_header hdr; 1178 struct hw_vendor_info *v_info; 1179 const struct x86_cpu_id *id; 1180 u64 misc_pwr; 1181 1182 id = x86_match_cpu(intel_pstate_cpu_oob_ids); 1183 if (id) { 1184 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr); 1185 if ( misc_pwr & (1 << 8)) 1186 return true; 1187 } 1188 1189 if (acpi_disabled || 1190 ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr))) 1191 return false; 1192 1193 for (v_info = vendor_info; v_info->valid; v_info++) { 1194 if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE) && 1195 !strncmp(hdr.oem_table_id, v_info->oem_table_id, 1196 ACPI_OEM_TABLE_ID_SIZE)) 1197 switch (v_info->oem_pwr_table) { 1198 case PSS: 1199 return intel_pstate_no_acpi_pss(); 1200 case PPC: 1201 return intel_pstate_has_acpi_ppc() && 1202 (!force_load); 1203 } 1204 } 1205 1206 return false; 1207 } 1208 #else /* CONFIG_ACPI not enabled */ 1209 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; } 1210 static inline bool intel_pstate_has_acpi_ppc(void) { return false; } 1211 #endif /* CONFIG_ACPI */ 1212 1213 static int __init intel_pstate_init(void) 1214 { 1215 int cpu, rc = 0; 1216 const struct x86_cpu_id *id; 1217 struct cpu_defaults *cpu_def; 1218 1219 if (no_load) 1220 return -ENODEV; 1221 1222 id = x86_match_cpu(intel_pstate_cpu_ids); 1223 if (!id) 1224 return -ENODEV; 1225 1226 /* 1227 * The Intel pstate driver will be ignored if the platform 1228 * firmware has its own power management modes. 1229 */ 1230 if (intel_pstate_platform_pwr_mgmt_exists()) 1231 return -ENODEV; 1232 1233 cpu_def = (struct cpu_defaults *)id->driver_data; 1234 1235 copy_pid_params(&cpu_def->pid_policy); 1236 copy_cpu_funcs(&cpu_def->funcs); 1237 1238 if (intel_pstate_msrs_not_valid()) 1239 return -ENODEV; 1240 1241 pr_info("Intel P-state driver initializing.\n"); 1242 1243 all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus()); 1244 if (!all_cpu_data) 1245 return -ENOMEM; 1246 1247 if (static_cpu_has_safe(X86_FEATURE_HWP) && !no_hwp) 1248 intel_pstate_hwp_enable(); 1249 1250 if (!hwp_active && hwp_only) 1251 goto out; 1252 1253 rc = cpufreq_register_driver(&intel_pstate_driver); 1254 if (rc) 1255 goto out; 1256 1257 intel_pstate_debug_expose_params(); 1258 intel_pstate_sysfs_expose_params(); 1259 1260 return rc; 1261 out: 1262 get_online_cpus(); 1263 for_each_online_cpu(cpu) { 1264 if (all_cpu_data[cpu]) { 1265 del_timer_sync(&all_cpu_data[cpu]->timer); 1266 kfree(all_cpu_data[cpu]); 1267 } 1268 } 1269 1270 put_online_cpus(); 1271 vfree(all_cpu_data); 1272 return -ENODEV; 1273 } 1274 device_initcall(intel_pstate_init); 1275 1276 static int __init intel_pstate_setup(char *str) 1277 { 1278 if (!str) 1279 return -EINVAL; 1280 1281 if (!strcmp(str, "disable")) 1282 no_load = 1; 1283 if (!strcmp(str, "no_hwp")) 1284 no_hwp = 1; 1285 if (!strcmp(str, "force")) 1286 force_load = 1; 1287 if (!strcmp(str, "hwp_only")) 1288 hwp_only = 1; 1289 return 0; 1290 } 1291 early_param("intel_pstate", intel_pstate_setup); 1292 1293 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>"); 1294 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors"); 1295 MODULE_LICENSE("GPL"); 1296