1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * intel_pstate.c: Native P state management for Intel processors 4 * 5 * (C) Copyright 2012 Intel Corporation 6 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com> 7 */ 8 9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10 11 #include <linux/kernel.h> 12 #include <linux/kernel_stat.h> 13 #include <linux/module.h> 14 #include <linux/ktime.h> 15 #include <linux/hrtimer.h> 16 #include <linux/tick.h> 17 #include <linux/slab.h> 18 #include <linux/sched/cpufreq.h> 19 #include <linux/list.h> 20 #include <linux/cpu.h> 21 #include <linux/cpufreq.h> 22 #include <linux/sysfs.h> 23 #include <linux/types.h> 24 #include <linux/fs.h> 25 #include <linux/acpi.h> 26 #include <linux/vmalloc.h> 27 #include <linux/pm_qos.h> 28 #include <linux/bitfield.h> 29 #include <trace/events/power.h> 30 31 #include <asm/cpu.h> 32 #include <asm/div64.h> 33 #include <asm/msr.h> 34 #include <asm/cpu_device_id.h> 35 #include <asm/cpufeature.h> 36 #include <asm/intel-family.h> 37 #include "../drivers/thermal/intel/thermal_interrupt.h" 38 39 #define INTEL_PSTATE_SAMPLING_INTERVAL (10 * NSEC_PER_MSEC) 40 41 #define INTEL_CPUFREQ_TRANSITION_LATENCY 20000 42 #define INTEL_CPUFREQ_TRANSITION_DELAY_HWP 5000 43 #define INTEL_CPUFREQ_TRANSITION_DELAY 500 44 45 #ifdef CONFIG_ACPI 46 #include <acpi/processor.h> 47 #include <acpi/cppc_acpi.h> 48 #endif 49 50 #define FRAC_BITS 8 51 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS) 52 #define fp_toint(X) ((X) >> FRAC_BITS) 53 54 #define ONE_EIGHTH_FP ((int64_t)1 << (FRAC_BITS - 3)) 55 56 #define EXT_BITS 6 57 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS) 58 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS) 59 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS) 60 61 static inline int32_t mul_fp(int32_t x, int32_t y) 62 { 63 return ((int64_t)x * (int64_t)y) >> FRAC_BITS; 64 } 65 66 static inline int32_t div_fp(s64 x, s64 y) 67 { 68 return div64_s64((int64_t)x << FRAC_BITS, y); 69 } 70 71 static inline int ceiling_fp(int32_t x) 72 { 73 int mask, ret; 74 75 ret = fp_toint(x); 76 mask = (1 << FRAC_BITS) - 1; 77 if (x & mask) 78 ret += 1; 79 return ret; 80 } 81 82 static inline u64 mul_ext_fp(u64 x, u64 y) 83 { 84 return (x * y) >> EXT_FRAC_BITS; 85 } 86 87 static inline u64 div_ext_fp(u64 x, u64 y) 88 { 89 return div64_u64(x << EXT_FRAC_BITS, y); 90 } 91 92 /** 93 * struct sample - Store performance sample 94 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average 95 * performance during last sample period 96 * @busy_scaled: Scaled busy value which is used to calculate next 97 * P state. This can be different than core_avg_perf 98 * to account for cpu idle period 99 * @aperf: Difference of actual performance frequency clock count 100 * read from APERF MSR between last and current sample 101 * @mperf: Difference of maximum performance frequency clock count 102 * read from MPERF MSR between last and current sample 103 * @tsc: Difference of time stamp counter between last and 104 * current sample 105 * @time: Current time from scheduler 106 * 107 * This structure is used in the cpudata structure to store performance sample 108 * data for choosing next P State. 109 */ 110 struct sample { 111 int32_t core_avg_perf; 112 int32_t busy_scaled; 113 u64 aperf; 114 u64 mperf; 115 u64 tsc; 116 u64 time; 117 }; 118 119 /** 120 * struct pstate_data - Store P state data 121 * @current_pstate: Current requested P state 122 * @min_pstate: Min P state possible for this platform 123 * @max_pstate: Max P state possible for this platform 124 * @max_pstate_physical:This is physical Max P state for a processor 125 * This can be higher than the max_pstate which can 126 * be limited by platform thermal design power limits 127 * @perf_ctl_scaling: PERF_CTL P-state to frequency scaling factor 128 * @scaling: Scaling factor between performance and frequency 129 * @turbo_pstate: Max Turbo P state possible for this platform 130 * @min_freq: @min_pstate frequency in cpufreq units 131 * @max_freq: @max_pstate frequency in cpufreq units 132 * @turbo_freq: @turbo_pstate frequency in cpufreq units 133 * 134 * Stores the per cpu model P state limits and current P state. 135 */ 136 struct pstate_data { 137 int current_pstate; 138 int min_pstate; 139 int max_pstate; 140 int max_pstate_physical; 141 int perf_ctl_scaling; 142 int scaling; 143 int turbo_pstate; 144 unsigned int min_freq; 145 unsigned int max_freq; 146 unsigned int turbo_freq; 147 }; 148 149 /** 150 * struct vid_data - Stores voltage information data 151 * @min: VID data for this platform corresponding to 152 * the lowest P state 153 * @max: VID data corresponding to the highest P State. 154 * @turbo: VID data for turbo P state 155 * @ratio: Ratio of (vid max - vid min) / 156 * (max P state - Min P State) 157 * 158 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling) 159 * This data is used in Atom platforms, where in addition to target P state, 160 * the voltage data needs to be specified to select next P State. 161 */ 162 struct vid_data { 163 int min; 164 int max; 165 int turbo; 166 int32_t ratio; 167 }; 168 169 /** 170 * struct global_params - Global parameters, mostly tunable via sysfs. 171 * @no_turbo: Whether or not to use turbo P-states. 172 * @turbo_disabled: Whether or not turbo P-states are available at all, 173 * based on the MSR_IA32_MISC_ENABLE value and whether or 174 * not the maximum reported turbo P-state is different from 175 * the maximum reported non-turbo one. 176 * @min_perf_pct: Minimum capacity limit in percent of the maximum turbo 177 * P-state capacity. 178 * @max_perf_pct: Maximum capacity limit in percent of the maximum turbo 179 * P-state capacity. 180 */ 181 struct global_params { 182 bool no_turbo; 183 bool turbo_disabled; 184 int max_perf_pct; 185 int min_perf_pct; 186 }; 187 188 /** 189 * struct cpudata - Per CPU instance data storage 190 * @cpu: CPU number for this instance data 191 * @policy: CPUFreq policy value 192 * @update_util: CPUFreq utility callback information 193 * @update_util_set: CPUFreq utility callback is set 194 * @iowait_boost: iowait-related boost fraction 195 * @last_update: Time of the last update. 196 * @pstate: Stores P state limits for this CPU 197 * @vid: Stores VID limits for this CPU 198 * @last_sample_time: Last Sample time 199 * @aperf_mperf_shift: APERF vs MPERF counting frequency difference 200 * @prev_aperf: Last APERF value read from APERF MSR 201 * @prev_mperf: Last MPERF value read from MPERF MSR 202 * @prev_tsc: Last timestamp counter (TSC) value 203 * @sample: Storage for storing last Sample data 204 * @min_perf_ratio: Minimum capacity in terms of PERF or HWP ratios 205 * @max_perf_ratio: Maximum capacity in terms of PERF or HWP ratios 206 * @acpi_perf_data: Stores ACPI perf information read from _PSS 207 * @valid_pss_table: Set to true for valid ACPI _PSS entries found 208 * @epp_powersave: Last saved HWP energy performance preference 209 * (EPP) or energy performance bias (EPB), 210 * when policy switched to performance 211 * @epp_policy: Last saved policy used to set EPP/EPB 212 * @epp_default: Power on default HWP energy performance 213 * preference/bias 214 * @epp_cached: Cached HWP energy-performance preference value 215 * @hwp_req_cached: Cached value of the last HWP Request MSR 216 * @hwp_cap_cached: Cached value of the last HWP Capabilities MSR 217 * @last_io_update: Last time when IO wake flag was set 218 * @sched_flags: Store scheduler flags for possible cross CPU update 219 * @hwp_boost_min: Last HWP boosted min performance 220 * @suspended: Whether or not the driver has been suspended. 221 * @hwp_notify_work: workqueue for HWP notifications. 222 * 223 * This structure stores per CPU instance data for all CPUs. 224 */ 225 struct cpudata { 226 int cpu; 227 228 unsigned int policy; 229 struct update_util_data update_util; 230 bool update_util_set; 231 232 struct pstate_data pstate; 233 struct vid_data vid; 234 235 u64 last_update; 236 u64 last_sample_time; 237 u64 aperf_mperf_shift; 238 u64 prev_aperf; 239 u64 prev_mperf; 240 u64 prev_tsc; 241 struct sample sample; 242 int32_t min_perf_ratio; 243 int32_t max_perf_ratio; 244 #ifdef CONFIG_ACPI 245 struct acpi_processor_performance acpi_perf_data; 246 bool valid_pss_table; 247 #endif 248 unsigned int iowait_boost; 249 s16 epp_powersave; 250 s16 epp_policy; 251 s16 epp_default; 252 s16 epp_cached; 253 u64 hwp_req_cached; 254 u64 hwp_cap_cached; 255 u64 last_io_update; 256 unsigned int sched_flags; 257 u32 hwp_boost_min; 258 bool suspended; 259 struct delayed_work hwp_notify_work; 260 }; 261 262 static struct cpudata **all_cpu_data; 263 264 /** 265 * struct pstate_funcs - Per CPU model specific callbacks 266 * @get_max: Callback to get maximum non turbo effective P state 267 * @get_max_physical: Callback to get maximum non turbo physical P state 268 * @get_min: Callback to get minimum P state 269 * @get_turbo: Callback to get turbo P state 270 * @get_scaling: Callback to get frequency scaling factor 271 * @get_cpu_scaling: Get frequency scaling factor for a given cpu 272 * @get_aperf_mperf_shift: Callback to get the APERF vs MPERF frequency difference 273 * @get_val: Callback to convert P state to actual MSR write value 274 * @get_vid: Callback to get VID data for Atom platforms 275 * 276 * Core and Atom CPU models have different way to get P State limits. This 277 * structure is used to store those callbacks. 278 */ 279 struct pstate_funcs { 280 int (*get_max)(int cpu); 281 int (*get_max_physical)(int cpu); 282 int (*get_min)(int cpu); 283 int (*get_turbo)(int cpu); 284 int (*get_scaling)(void); 285 int (*get_cpu_scaling)(int cpu); 286 int (*get_aperf_mperf_shift)(void); 287 u64 (*get_val)(struct cpudata*, int pstate); 288 void (*get_vid)(struct cpudata *); 289 }; 290 291 static struct pstate_funcs pstate_funcs __read_mostly; 292 293 static bool hwp_active __ro_after_init; 294 static int hwp_mode_bdw __ro_after_init; 295 static bool per_cpu_limits __ro_after_init; 296 static bool hwp_forced __ro_after_init; 297 static bool hwp_boost __read_mostly; 298 299 static struct cpufreq_driver *intel_pstate_driver __read_mostly; 300 301 #define HYBRID_SCALING_FACTOR 78741 302 #define HYBRID_SCALING_FACTOR_MTL 80000 303 304 static int hybrid_scaling_factor = HYBRID_SCALING_FACTOR; 305 306 static inline int core_get_scaling(void) 307 { 308 return 100000; 309 } 310 311 #ifdef CONFIG_ACPI 312 static bool acpi_ppc; 313 #endif 314 315 static struct global_params global; 316 317 static DEFINE_MUTEX(intel_pstate_driver_lock); 318 static DEFINE_MUTEX(intel_pstate_limits_lock); 319 320 #ifdef CONFIG_ACPI 321 322 static bool intel_pstate_acpi_pm_profile_server(void) 323 { 324 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER || 325 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER) 326 return true; 327 328 return false; 329 } 330 331 static bool intel_pstate_get_ppc_enable_status(void) 332 { 333 if (intel_pstate_acpi_pm_profile_server()) 334 return true; 335 336 return acpi_ppc; 337 } 338 339 #ifdef CONFIG_ACPI_CPPC_LIB 340 341 /* The work item is needed to avoid CPU hotplug locking issues */ 342 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work) 343 { 344 sched_set_itmt_support(); 345 } 346 347 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn); 348 349 #define CPPC_MAX_PERF U8_MAX 350 351 static void intel_pstate_set_itmt_prio(int cpu) 352 { 353 struct cppc_perf_caps cppc_perf; 354 static u32 max_highest_perf = 0, min_highest_perf = U32_MAX; 355 int ret; 356 357 ret = cppc_get_perf_caps(cpu, &cppc_perf); 358 if (ret) 359 return; 360 361 /* 362 * On some systems with overclocking enabled, CPPC.highest_perf is hardcoded to 0xff. 363 * In this case we can't use CPPC.highest_perf to enable ITMT. 364 * In this case we can look at MSR_HWP_CAPABILITIES bits [8:0] to decide. 365 */ 366 if (cppc_perf.highest_perf == CPPC_MAX_PERF) 367 cppc_perf.highest_perf = HWP_HIGHEST_PERF(READ_ONCE(all_cpu_data[cpu]->hwp_cap_cached)); 368 369 /* 370 * The priorities can be set regardless of whether or not 371 * sched_set_itmt_support(true) has been called and it is valid to 372 * update them at any time after it has been called. 373 */ 374 sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu); 375 376 if (max_highest_perf <= min_highest_perf) { 377 if (cppc_perf.highest_perf > max_highest_perf) 378 max_highest_perf = cppc_perf.highest_perf; 379 380 if (cppc_perf.highest_perf < min_highest_perf) 381 min_highest_perf = cppc_perf.highest_perf; 382 383 if (max_highest_perf > min_highest_perf) { 384 /* 385 * This code can be run during CPU online under the 386 * CPU hotplug locks, so sched_set_itmt_support() 387 * cannot be called from here. Queue up a work item 388 * to invoke it. 389 */ 390 schedule_work(&sched_itmt_work); 391 } 392 } 393 } 394 395 static int intel_pstate_get_cppc_guaranteed(int cpu) 396 { 397 struct cppc_perf_caps cppc_perf; 398 int ret; 399 400 ret = cppc_get_perf_caps(cpu, &cppc_perf); 401 if (ret) 402 return ret; 403 404 if (cppc_perf.guaranteed_perf) 405 return cppc_perf.guaranteed_perf; 406 407 return cppc_perf.nominal_perf; 408 } 409 410 static int intel_pstate_cppc_get_scaling(int cpu) 411 { 412 struct cppc_perf_caps cppc_perf; 413 int ret; 414 415 ret = cppc_get_perf_caps(cpu, &cppc_perf); 416 417 /* 418 * If the nominal frequency and the nominal performance are not 419 * zero and the ratio between them is not 100, return the hybrid 420 * scaling factor. 421 */ 422 if (!ret && cppc_perf.nominal_perf && cppc_perf.nominal_freq && 423 cppc_perf.nominal_perf * 100 != cppc_perf.nominal_freq) 424 return hybrid_scaling_factor; 425 426 return core_get_scaling(); 427 } 428 429 #else /* CONFIG_ACPI_CPPC_LIB */ 430 static inline void intel_pstate_set_itmt_prio(int cpu) 431 { 432 } 433 #endif /* CONFIG_ACPI_CPPC_LIB */ 434 435 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) 436 { 437 struct cpudata *cpu; 438 int ret; 439 int i; 440 441 if (hwp_active) { 442 intel_pstate_set_itmt_prio(policy->cpu); 443 return; 444 } 445 446 if (!intel_pstate_get_ppc_enable_status()) 447 return; 448 449 cpu = all_cpu_data[policy->cpu]; 450 451 ret = acpi_processor_register_performance(&cpu->acpi_perf_data, 452 policy->cpu); 453 if (ret) 454 return; 455 456 /* 457 * Check if the control value in _PSS is for PERF_CTL MSR, which should 458 * guarantee that the states returned by it map to the states in our 459 * list directly. 460 */ 461 if (cpu->acpi_perf_data.control_register.space_id != 462 ACPI_ADR_SPACE_FIXED_HARDWARE) 463 goto err; 464 465 /* 466 * If there is only one entry _PSS, simply ignore _PSS and continue as 467 * usual without taking _PSS into account 468 */ 469 if (cpu->acpi_perf_data.state_count < 2) 470 goto err; 471 472 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu); 473 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) { 474 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n", 475 (i == cpu->acpi_perf_data.state ? '*' : ' '), i, 476 (u32) cpu->acpi_perf_data.states[i].core_frequency, 477 (u32) cpu->acpi_perf_data.states[i].power, 478 (u32) cpu->acpi_perf_data.states[i].control); 479 } 480 481 cpu->valid_pss_table = true; 482 pr_debug("_PPC limits will be enforced\n"); 483 484 return; 485 486 err: 487 cpu->valid_pss_table = false; 488 acpi_processor_unregister_performance(policy->cpu); 489 } 490 491 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) 492 { 493 struct cpudata *cpu; 494 495 cpu = all_cpu_data[policy->cpu]; 496 if (!cpu->valid_pss_table) 497 return; 498 499 acpi_processor_unregister_performance(policy->cpu); 500 } 501 #else /* CONFIG_ACPI */ 502 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) 503 { 504 } 505 506 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) 507 { 508 } 509 510 static inline bool intel_pstate_acpi_pm_profile_server(void) 511 { 512 return false; 513 } 514 #endif /* CONFIG_ACPI */ 515 516 #ifndef CONFIG_ACPI_CPPC_LIB 517 static inline int intel_pstate_get_cppc_guaranteed(int cpu) 518 { 519 return -ENOTSUPP; 520 } 521 522 static int intel_pstate_cppc_get_scaling(int cpu) 523 { 524 return core_get_scaling(); 525 } 526 #endif /* CONFIG_ACPI_CPPC_LIB */ 527 528 static int intel_pstate_freq_to_hwp_rel(struct cpudata *cpu, int freq, 529 unsigned int relation) 530 { 531 if (freq == cpu->pstate.turbo_freq) 532 return cpu->pstate.turbo_pstate; 533 534 if (freq == cpu->pstate.max_freq) 535 return cpu->pstate.max_pstate; 536 537 switch (relation) { 538 case CPUFREQ_RELATION_H: 539 return freq / cpu->pstate.scaling; 540 case CPUFREQ_RELATION_C: 541 return DIV_ROUND_CLOSEST(freq, cpu->pstate.scaling); 542 } 543 544 return DIV_ROUND_UP(freq, cpu->pstate.scaling); 545 } 546 547 static int intel_pstate_freq_to_hwp(struct cpudata *cpu, int freq) 548 { 549 return intel_pstate_freq_to_hwp_rel(cpu, freq, CPUFREQ_RELATION_L); 550 } 551 552 /** 553 * intel_pstate_hybrid_hwp_adjust - Calibrate HWP performance levels. 554 * @cpu: Target CPU. 555 * 556 * On hybrid processors, HWP may expose more performance levels than there are 557 * P-states accessible through the PERF_CTL interface. If that happens, the 558 * scaling factor between HWP performance levels and CPU frequency will be less 559 * than the scaling factor between P-state values and CPU frequency. 560 * 561 * In that case, adjust the CPU parameters used in computations accordingly. 562 */ 563 static void intel_pstate_hybrid_hwp_adjust(struct cpudata *cpu) 564 { 565 int perf_ctl_max_phys = cpu->pstate.max_pstate_physical; 566 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling; 567 int perf_ctl_turbo = pstate_funcs.get_turbo(cpu->cpu); 568 int scaling = cpu->pstate.scaling; 569 int freq; 570 571 pr_debug("CPU%d: perf_ctl_max_phys = %d\n", cpu->cpu, perf_ctl_max_phys); 572 pr_debug("CPU%d: perf_ctl_turbo = %d\n", cpu->cpu, perf_ctl_turbo); 573 pr_debug("CPU%d: perf_ctl_scaling = %d\n", cpu->cpu, perf_ctl_scaling); 574 pr_debug("CPU%d: HWP_CAP guaranteed = %d\n", cpu->cpu, cpu->pstate.max_pstate); 575 pr_debug("CPU%d: HWP_CAP highest = %d\n", cpu->cpu, cpu->pstate.turbo_pstate); 576 pr_debug("CPU%d: HWP-to-frequency scaling factor: %d\n", cpu->cpu, scaling); 577 578 cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_pstate * scaling, 579 perf_ctl_scaling); 580 cpu->pstate.max_freq = rounddown(cpu->pstate.max_pstate * scaling, 581 perf_ctl_scaling); 582 583 freq = perf_ctl_max_phys * perf_ctl_scaling; 584 cpu->pstate.max_pstate_physical = intel_pstate_freq_to_hwp(cpu, freq); 585 586 freq = cpu->pstate.min_pstate * perf_ctl_scaling; 587 cpu->pstate.min_freq = freq; 588 /* 589 * Cast the min P-state value retrieved via pstate_funcs.get_min() to 590 * the effective range of HWP performance levels. 591 */ 592 cpu->pstate.min_pstate = intel_pstate_freq_to_hwp(cpu, freq); 593 } 594 595 static bool turbo_is_disabled(void) 596 { 597 u64 misc_en; 598 599 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en); 600 601 return !!(misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE); 602 } 603 604 static int min_perf_pct_min(void) 605 { 606 struct cpudata *cpu = all_cpu_data[0]; 607 int turbo_pstate = cpu->pstate.turbo_pstate; 608 609 return turbo_pstate ? 610 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0; 611 } 612 613 static s16 intel_pstate_get_epb(struct cpudata *cpu_data) 614 { 615 u64 epb; 616 int ret; 617 618 if (!boot_cpu_has(X86_FEATURE_EPB)) 619 return -ENXIO; 620 621 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb); 622 if (ret) 623 return (s16)ret; 624 625 return (s16)(epb & 0x0f); 626 } 627 628 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data) 629 { 630 s16 epp; 631 632 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 633 /* 634 * When hwp_req_data is 0, means that caller didn't read 635 * MSR_HWP_REQUEST, so need to read and get EPP. 636 */ 637 if (!hwp_req_data) { 638 epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, 639 &hwp_req_data); 640 if (epp) 641 return epp; 642 } 643 epp = (hwp_req_data >> 24) & 0xff; 644 } else { 645 /* When there is no EPP present, HWP uses EPB settings */ 646 epp = intel_pstate_get_epb(cpu_data); 647 } 648 649 return epp; 650 } 651 652 static int intel_pstate_set_epb(int cpu, s16 pref) 653 { 654 u64 epb; 655 int ret; 656 657 if (!boot_cpu_has(X86_FEATURE_EPB)) 658 return -ENXIO; 659 660 ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb); 661 if (ret) 662 return ret; 663 664 epb = (epb & ~0x0f) | pref; 665 wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb); 666 667 return 0; 668 } 669 670 /* 671 * EPP/EPB display strings corresponding to EPP index in the 672 * energy_perf_strings[] 673 * index String 674 *------------------------------------- 675 * 0 default 676 * 1 performance 677 * 2 balance_performance 678 * 3 balance_power 679 * 4 power 680 */ 681 682 enum energy_perf_value_index { 683 EPP_INDEX_DEFAULT = 0, 684 EPP_INDEX_PERFORMANCE, 685 EPP_INDEX_BALANCE_PERFORMANCE, 686 EPP_INDEX_BALANCE_POWERSAVE, 687 EPP_INDEX_POWERSAVE, 688 }; 689 690 static const char * const energy_perf_strings[] = { 691 [EPP_INDEX_DEFAULT] = "default", 692 [EPP_INDEX_PERFORMANCE] = "performance", 693 [EPP_INDEX_BALANCE_PERFORMANCE] = "balance_performance", 694 [EPP_INDEX_BALANCE_POWERSAVE] = "balance_power", 695 [EPP_INDEX_POWERSAVE] = "power", 696 NULL 697 }; 698 static unsigned int epp_values[] = { 699 [EPP_INDEX_DEFAULT] = 0, /* Unused index */ 700 [EPP_INDEX_PERFORMANCE] = HWP_EPP_PERFORMANCE, 701 [EPP_INDEX_BALANCE_PERFORMANCE] = HWP_EPP_BALANCE_PERFORMANCE, 702 [EPP_INDEX_BALANCE_POWERSAVE] = HWP_EPP_BALANCE_POWERSAVE, 703 [EPP_INDEX_POWERSAVE] = HWP_EPP_POWERSAVE, 704 }; 705 706 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data, int *raw_epp) 707 { 708 s16 epp; 709 int index = -EINVAL; 710 711 *raw_epp = 0; 712 epp = intel_pstate_get_epp(cpu_data, 0); 713 if (epp < 0) 714 return epp; 715 716 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 717 if (epp == epp_values[EPP_INDEX_PERFORMANCE]) 718 return EPP_INDEX_PERFORMANCE; 719 if (epp == epp_values[EPP_INDEX_BALANCE_PERFORMANCE]) 720 return EPP_INDEX_BALANCE_PERFORMANCE; 721 if (epp == epp_values[EPP_INDEX_BALANCE_POWERSAVE]) 722 return EPP_INDEX_BALANCE_POWERSAVE; 723 if (epp == epp_values[EPP_INDEX_POWERSAVE]) 724 return EPP_INDEX_POWERSAVE; 725 *raw_epp = epp; 726 return 0; 727 } else if (boot_cpu_has(X86_FEATURE_EPB)) { 728 /* 729 * Range: 730 * 0x00-0x03 : Performance 731 * 0x04-0x07 : Balance performance 732 * 0x08-0x0B : Balance power 733 * 0x0C-0x0F : Power 734 * The EPB is a 4 bit value, but our ranges restrict the 735 * value which can be set. Here only using top two bits 736 * effectively. 737 */ 738 index = (epp >> 2) + 1; 739 } 740 741 return index; 742 } 743 744 static int intel_pstate_set_epp(struct cpudata *cpu, u32 epp) 745 { 746 int ret; 747 748 /* 749 * Use the cached HWP Request MSR value, because in the active mode the 750 * register itself may be updated by intel_pstate_hwp_boost_up() or 751 * intel_pstate_hwp_boost_down() at any time. 752 */ 753 u64 value = READ_ONCE(cpu->hwp_req_cached); 754 755 value &= ~GENMASK_ULL(31, 24); 756 value |= (u64)epp << 24; 757 /* 758 * The only other updater of hwp_req_cached in the active mode, 759 * intel_pstate_hwp_set(), is called under the same lock as this 760 * function, so it cannot run in parallel with the update below. 761 */ 762 WRITE_ONCE(cpu->hwp_req_cached, value); 763 ret = wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 764 if (!ret) 765 cpu->epp_cached = epp; 766 767 return ret; 768 } 769 770 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data, 771 int pref_index, bool use_raw, 772 u32 raw_epp) 773 { 774 int epp = -EINVAL; 775 int ret; 776 777 if (!pref_index) 778 epp = cpu_data->epp_default; 779 780 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 781 if (use_raw) 782 epp = raw_epp; 783 else if (epp == -EINVAL) 784 epp = epp_values[pref_index]; 785 786 /* 787 * To avoid confusion, refuse to set EPP to any values different 788 * from 0 (performance) if the current policy is "performance", 789 * because those values would be overridden. 790 */ 791 if (epp > 0 && cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) 792 return -EBUSY; 793 794 ret = intel_pstate_set_epp(cpu_data, epp); 795 } else { 796 if (epp == -EINVAL) 797 epp = (pref_index - 1) << 2; 798 ret = intel_pstate_set_epb(cpu_data->cpu, epp); 799 } 800 801 return ret; 802 } 803 804 static ssize_t show_energy_performance_available_preferences( 805 struct cpufreq_policy *policy, char *buf) 806 { 807 int i = 0; 808 int ret = 0; 809 810 while (energy_perf_strings[i] != NULL) 811 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]); 812 813 ret += sprintf(&buf[ret], "\n"); 814 815 return ret; 816 } 817 818 cpufreq_freq_attr_ro(energy_performance_available_preferences); 819 820 static struct cpufreq_driver intel_pstate; 821 822 static ssize_t store_energy_performance_preference( 823 struct cpufreq_policy *policy, const char *buf, size_t count) 824 { 825 struct cpudata *cpu = all_cpu_data[policy->cpu]; 826 char str_preference[21]; 827 bool raw = false; 828 ssize_t ret; 829 u32 epp = 0; 830 831 ret = sscanf(buf, "%20s", str_preference); 832 if (ret != 1) 833 return -EINVAL; 834 835 ret = match_string(energy_perf_strings, -1, str_preference); 836 if (ret < 0) { 837 if (!boot_cpu_has(X86_FEATURE_HWP_EPP)) 838 return ret; 839 840 ret = kstrtouint(buf, 10, &epp); 841 if (ret) 842 return ret; 843 844 if (epp > 255) 845 return -EINVAL; 846 847 raw = true; 848 } 849 850 /* 851 * This function runs with the policy R/W semaphore held, which 852 * guarantees that the driver pointer will not change while it is 853 * running. 854 */ 855 if (!intel_pstate_driver) 856 return -EAGAIN; 857 858 mutex_lock(&intel_pstate_limits_lock); 859 860 if (intel_pstate_driver == &intel_pstate) { 861 ret = intel_pstate_set_energy_pref_index(cpu, ret, raw, epp); 862 } else { 863 /* 864 * In the passive mode the governor needs to be stopped on the 865 * target CPU before the EPP update and restarted after it, 866 * which is super-heavy-weight, so make sure it is worth doing 867 * upfront. 868 */ 869 if (!raw) 870 epp = ret ? epp_values[ret] : cpu->epp_default; 871 872 if (cpu->epp_cached != epp) { 873 int err; 874 875 cpufreq_stop_governor(policy); 876 ret = intel_pstate_set_epp(cpu, epp); 877 err = cpufreq_start_governor(policy); 878 if (!ret) 879 ret = err; 880 } else { 881 ret = 0; 882 } 883 } 884 885 mutex_unlock(&intel_pstate_limits_lock); 886 887 return ret ?: count; 888 } 889 890 static ssize_t show_energy_performance_preference( 891 struct cpufreq_policy *policy, char *buf) 892 { 893 struct cpudata *cpu_data = all_cpu_data[policy->cpu]; 894 int preference, raw_epp; 895 896 preference = intel_pstate_get_energy_pref_index(cpu_data, &raw_epp); 897 if (preference < 0) 898 return preference; 899 900 if (raw_epp) 901 return sprintf(buf, "%d\n", raw_epp); 902 else 903 return sprintf(buf, "%s\n", energy_perf_strings[preference]); 904 } 905 906 cpufreq_freq_attr_rw(energy_performance_preference); 907 908 static ssize_t show_base_frequency(struct cpufreq_policy *policy, char *buf) 909 { 910 struct cpudata *cpu = all_cpu_data[policy->cpu]; 911 int ratio, freq; 912 913 ratio = intel_pstate_get_cppc_guaranteed(policy->cpu); 914 if (ratio <= 0) { 915 u64 cap; 916 917 rdmsrl_on_cpu(policy->cpu, MSR_HWP_CAPABILITIES, &cap); 918 ratio = HWP_GUARANTEED_PERF(cap); 919 } 920 921 freq = ratio * cpu->pstate.scaling; 922 if (cpu->pstate.scaling != cpu->pstate.perf_ctl_scaling) 923 freq = rounddown(freq, cpu->pstate.perf_ctl_scaling); 924 925 return sprintf(buf, "%d\n", freq); 926 } 927 928 cpufreq_freq_attr_ro(base_frequency); 929 930 static struct freq_attr *hwp_cpufreq_attrs[] = { 931 &energy_performance_preference, 932 &energy_performance_available_preferences, 933 &base_frequency, 934 NULL, 935 }; 936 937 static void __intel_pstate_get_hwp_cap(struct cpudata *cpu) 938 { 939 u64 cap; 940 941 rdmsrl_on_cpu(cpu->cpu, MSR_HWP_CAPABILITIES, &cap); 942 WRITE_ONCE(cpu->hwp_cap_cached, cap); 943 cpu->pstate.max_pstate = HWP_GUARANTEED_PERF(cap); 944 cpu->pstate.turbo_pstate = HWP_HIGHEST_PERF(cap); 945 } 946 947 static void intel_pstate_get_hwp_cap(struct cpudata *cpu) 948 { 949 int scaling = cpu->pstate.scaling; 950 951 __intel_pstate_get_hwp_cap(cpu); 952 953 cpu->pstate.max_freq = cpu->pstate.max_pstate * scaling; 954 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * scaling; 955 if (scaling != cpu->pstate.perf_ctl_scaling) { 956 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling; 957 958 cpu->pstate.max_freq = rounddown(cpu->pstate.max_freq, 959 perf_ctl_scaling); 960 cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_freq, 961 perf_ctl_scaling); 962 } 963 } 964 965 static void intel_pstate_hwp_set(unsigned int cpu) 966 { 967 struct cpudata *cpu_data = all_cpu_data[cpu]; 968 int max, min; 969 u64 value; 970 s16 epp; 971 972 max = cpu_data->max_perf_ratio; 973 min = cpu_data->min_perf_ratio; 974 975 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) 976 min = max; 977 978 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value); 979 980 value &= ~HWP_MIN_PERF(~0L); 981 value |= HWP_MIN_PERF(min); 982 983 value &= ~HWP_MAX_PERF(~0L); 984 value |= HWP_MAX_PERF(max); 985 986 if (cpu_data->epp_policy == cpu_data->policy) 987 goto skip_epp; 988 989 cpu_data->epp_policy = cpu_data->policy; 990 991 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) { 992 epp = intel_pstate_get_epp(cpu_data, value); 993 cpu_data->epp_powersave = epp; 994 /* If EPP read was failed, then don't try to write */ 995 if (epp < 0) 996 goto skip_epp; 997 998 epp = 0; 999 } else { 1000 /* skip setting EPP, when saved value is invalid */ 1001 if (cpu_data->epp_powersave < 0) 1002 goto skip_epp; 1003 1004 /* 1005 * No need to restore EPP when it is not zero. This 1006 * means: 1007 * - Policy is not changed 1008 * - user has manually changed 1009 * - Error reading EPB 1010 */ 1011 epp = intel_pstate_get_epp(cpu_data, value); 1012 if (epp) 1013 goto skip_epp; 1014 1015 epp = cpu_data->epp_powersave; 1016 } 1017 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 1018 value &= ~GENMASK_ULL(31, 24); 1019 value |= (u64)epp << 24; 1020 } else { 1021 intel_pstate_set_epb(cpu, epp); 1022 } 1023 skip_epp: 1024 WRITE_ONCE(cpu_data->hwp_req_cached, value); 1025 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value); 1026 } 1027 1028 static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata); 1029 1030 static void intel_pstate_hwp_offline(struct cpudata *cpu) 1031 { 1032 u64 value = READ_ONCE(cpu->hwp_req_cached); 1033 int min_perf; 1034 1035 intel_pstate_disable_hwp_interrupt(cpu); 1036 1037 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 1038 /* 1039 * In case the EPP has been set to "performance" by the 1040 * active mode "performance" scaling algorithm, replace that 1041 * temporary value with the cached EPP one. 1042 */ 1043 value &= ~GENMASK_ULL(31, 24); 1044 value |= HWP_ENERGY_PERF_PREFERENCE(cpu->epp_cached); 1045 /* 1046 * However, make sure that EPP will be set to "performance" when 1047 * the CPU is brought back online again and the "performance" 1048 * scaling algorithm is still in effect. 1049 */ 1050 cpu->epp_policy = CPUFREQ_POLICY_UNKNOWN; 1051 } 1052 1053 /* 1054 * Clear the desired perf field in the cached HWP request value to 1055 * prevent nonzero desired values from being leaked into the active 1056 * mode. 1057 */ 1058 value &= ~HWP_DESIRED_PERF(~0L); 1059 WRITE_ONCE(cpu->hwp_req_cached, value); 1060 1061 value &= ~GENMASK_ULL(31, 0); 1062 min_perf = HWP_LOWEST_PERF(READ_ONCE(cpu->hwp_cap_cached)); 1063 1064 /* Set hwp_max = hwp_min */ 1065 value |= HWP_MAX_PERF(min_perf); 1066 value |= HWP_MIN_PERF(min_perf); 1067 1068 /* Set EPP to min */ 1069 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) 1070 value |= HWP_ENERGY_PERF_PREFERENCE(HWP_EPP_POWERSAVE); 1071 1072 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 1073 } 1074 1075 #define POWER_CTL_EE_ENABLE 1 1076 #define POWER_CTL_EE_DISABLE 2 1077 1078 static int power_ctl_ee_state; 1079 1080 static void set_power_ctl_ee_state(bool input) 1081 { 1082 u64 power_ctl; 1083 1084 mutex_lock(&intel_pstate_driver_lock); 1085 rdmsrl(MSR_IA32_POWER_CTL, power_ctl); 1086 if (input) { 1087 power_ctl &= ~BIT(MSR_IA32_POWER_CTL_BIT_EE); 1088 power_ctl_ee_state = POWER_CTL_EE_ENABLE; 1089 } else { 1090 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE); 1091 power_ctl_ee_state = POWER_CTL_EE_DISABLE; 1092 } 1093 wrmsrl(MSR_IA32_POWER_CTL, power_ctl); 1094 mutex_unlock(&intel_pstate_driver_lock); 1095 } 1096 1097 static void intel_pstate_hwp_enable(struct cpudata *cpudata); 1098 1099 static void intel_pstate_hwp_reenable(struct cpudata *cpu) 1100 { 1101 intel_pstate_hwp_enable(cpu); 1102 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, READ_ONCE(cpu->hwp_req_cached)); 1103 } 1104 1105 static int intel_pstate_suspend(struct cpufreq_policy *policy) 1106 { 1107 struct cpudata *cpu = all_cpu_data[policy->cpu]; 1108 1109 pr_debug("CPU %d suspending\n", cpu->cpu); 1110 1111 cpu->suspended = true; 1112 1113 /* disable HWP interrupt and cancel any pending work */ 1114 intel_pstate_disable_hwp_interrupt(cpu); 1115 1116 return 0; 1117 } 1118 1119 static int intel_pstate_resume(struct cpufreq_policy *policy) 1120 { 1121 struct cpudata *cpu = all_cpu_data[policy->cpu]; 1122 1123 pr_debug("CPU %d resuming\n", cpu->cpu); 1124 1125 /* Only restore if the system default is changed */ 1126 if (power_ctl_ee_state == POWER_CTL_EE_ENABLE) 1127 set_power_ctl_ee_state(true); 1128 else if (power_ctl_ee_state == POWER_CTL_EE_DISABLE) 1129 set_power_ctl_ee_state(false); 1130 1131 if (cpu->suspended && hwp_active) { 1132 mutex_lock(&intel_pstate_limits_lock); 1133 1134 /* Re-enable HWP, because "online" has not done that. */ 1135 intel_pstate_hwp_reenable(cpu); 1136 1137 mutex_unlock(&intel_pstate_limits_lock); 1138 } 1139 1140 cpu->suspended = false; 1141 1142 return 0; 1143 } 1144 1145 static void intel_pstate_update_policies(void) 1146 { 1147 int cpu; 1148 1149 for_each_possible_cpu(cpu) 1150 cpufreq_update_policy(cpu); 1151 } 1152 1153 static void __intel_pstate_update_max_freq(struct cpudata *cpudata, 1154 struct cpufreq_policy *policy) 1155 { 1156 intel_pstate_get_hwp_cap(cpudata); 1157 1158 policy->cpuinfo.max_freq = READ_ONCE(global.no_turbo) ? 1159 cpudata->pstate.max_freq : cpudata->pstate.turbo_freq; 1160 1161 refresh_frequency_limits(policy); 1162 } 1163 1164 static void intel_pstate_update_limits(unsigned int cpu) 1165 { 1166 struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpu); 1167 1168 if (!policy) 1169 return; 1170 1171 __intel_pstate_update_max_freq(all_cpu_data[cpu], policy); 1172 1173 cpufreq_cpu_release(policy); 1174 } 1175 1176 static void intel_pstate_update_limits_for_all(void) 1177 { 1178 int cpu; 1179 1180 for_each_possible_cpu(cpu) 1181 intel_pstate_update_limits(cpu); 1182 } 1183 1184 /************************** sysfs begin ************************/ 1185 #define show_one(file_name, object) \ 1186 static ssize_t show_##file_name \ 1187 (struct kobject *kobj, struct kobj_attribute *attr, char *buf) \ 1188 { \ 1189 return sprintf(buf, "%u\n", global.object); \ 1190 } 1191 1192 static ssize_t intel_pstate_show_status(char *buf); 1193 static int intel_pstate_update_status(const char *buf, size_t size); 1194 1195 static ssize_t show_status(struct kobject *kobj, 1196 struct kobj_attribute *attr, char *buf) 1197 { 1198 ssize_t ret; 1199 1200 mutex_lock(&intel_pstate_driver_lock); 1201 ret = intel_pstate_show_status(buf); 1202 mutex_unlock(&intel_pstate_driver_lock); 1203 1204 return ret; 1205 } 1206 1207 static ssize_t store_status(struct kobject *a, struct kobj_attribute *b, 1208 const char *buf, size_t count) 1209 { 1210 char *p = memchr(buf, '\n', count); 1211 int ret; 1212 1213 mutex_lock(&intel_pstate_driver_lock); 1214 ret = intel_pstate_update_status(buf, p ? p - buf : count); 1215 mutex_unlock(&intel_pstate_driver_lock); 1216 1217 return ret < 0 ? ret : count; 1218 } 1219 1220 static ssize_t show_turbo_pct(struct kobject *kobj, 1221 struct kobj_attribute *attr, char *buf) 1222 { 1223 struct cpudata *cpu; 1224 int total, no_turbo, turbo_pct; 1225 uint32_t turbo_fp; 1226 1227 mutex_lock(&intel_pstate_driver_lock); 1228 1229 if (!intel_pstate_driver) { 1230 mutex_unlock(&intel_pstate_driver_lock); 1231 return -EAGAIN; 1232 } 1233 1234 cpu = all_cpu_data[0]; 1235 1236 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; 1237 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1; 1238 turbo_fp = div_fp(no_turbo, total); 1239 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100))); 1240 1241 mutex_unlock(&intel_pstate_driver_lock); 1242 1243 return sprintf(buf, "%u\n", turbo_pct); 1244 } 1245 1246 static ssize_t show_num_pstates(struct kobject *kobj, 1247 struct kobj_attribute *attr, char *buf) 1248 { 1249 struct cpudata *cpu; 1250 int total; 1251 1252 mutex_lock(&intel_pstate_driver_lock); 1253 1254 if (!intel_pstate_driver) { 1255 mutex_unlock(&intel_pstate_driver_lock); 1256 return -EAGAIN; 1257 } 1258 1259 cpu = all_cpu_data[0]; 1260 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; 1261 1262 mutex_unlock(&intel_pstate_driver_lock); 1263 1264 return sprintf(buf, "%u\n", total); 1265 } 1266 1267 static ssize_t show_no_turbo(struct kobject *kobj, 1268 struct kobj_attribute *attr, char *buf) 1269 { 1270 ssize_t ret; 1271 1272 mutex_lock(&intel_pstate_driver_lock); 1273 1274 if (!intel_pstate_driver) { 1275 mutex_unlock(&intel_pstate_driver_lock); 1276 return -EAGAIN; 1277 } 1278 1279 ret = sprintf(buf, "%u\n", global.no_turbo); 1280 1281 mutex_unlock(&intel_pstate_driver_lock); 1282 1283 return ret; 1284 } 1285 1286 static ssize_t store_no_turbo(struct kobject *a, struct kobj_attribute *b, 1287 const char *buf, size_t count) 1288 { 1289 unsigned int input; 1290 bool no_turbo; 1291 1292 if (sscanf(buf, "%u", &input) != 1) 1293 return -EINVAL; 1294 1295 mutex_lock(&intel_pstate_driver_lock); 1296 1297 if (!intel_pstate_driver) { 1298 count = -EAGAIN; 1299 goto unlock_driver; 1300 } 1301 1302 no_turbo = !!clamp_t(int, input, 0, 1); 1303 1304 if (no_turbo == global.no_turbo) 1305 goto unlock_driver; 1306 1307 if (global.turbo_disabled) { 1308 pr_notice_once("Turbo disabled by BIOS or unavailable on processor\n"); 1309 count = -EPERM; 1310 goto unlock_driver; 1311 } 1312 1313 WRITE_ONCE(global.no_turbo, no_turbo); 1314 1315 mutex_lock(&intel_pstate_limits_lock); 1316 1317 if (no_turbo) { 1318 struct cpudata *cpu = all_cpu_data[0]; 1319 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate; 1320 1321 /* Squash the global minimum into the permitted range. */ 1322 if (global.min_perf_pct > pct) 1323 global.min_perf_pct = pct; 1324 } 1325 1326 mutex_unlock(&intel_pstate_limits_lock); 1327 1328 intel_pstate_update_limits_for_all(); 1329 arch_set_max_freq_ratio(no_turbo); 1330 1331 unlock_driver: 1332 mutex_unlock(&intel_pstate_driver_lock); 1333 1334 return count; 1335 } 1336 1337 static void update_qos_request(enum freq_qos_req_type type) 1338 { 1339 struct freq_qos_request *req; 1340 struct cpufreq_policy *policy; 1341 int i; 1342 1343 for_each_possible_cpu(i) { 1344 struct cpudata *cpu = all_cpu_data[i]; 1345 unsigned int freq, perf_pct; 1346 1347 policy = cpufreq_cpu_get(i); 1348 if (!policy) 1349 continue; 1350 1351 req = policy->driver_data; 1352 cpufreq_cpu_put(policy); 1353 1354 if (!req) 1355 continue; 1356 1357 if (hwp_active) 1358 intel_pstate_get_hwp_cap(cpu); 1359 1360 if (type == FREQ_QOS_MIN) { 1361 perf_pct = global.min_perf_pct; 1362 } else { 1363 req++; 1364 perf_pct = global.max_perf_pct; 1365 } 1366 1367 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * perf_pct, 100); 1368 1369 if (freq_qos_update_request(req, freq) < 0) 1370 pr_warn("Failed to update freq constraint: CPU%d\n", i); 1371 } 1372 } 1373 1374 static ssize_t store_max_perf_pct(struct kobject *a, struct kobj_attribute *b, 1375 const char *buf, size_t count) 1376 { 1377 unsigned int input; 1378 int ret; 1379 1380 ret = sscanf(buf, "%u", &input); 1381 if (ret != 1) 1382 return -EINVAL; 1383 1384 mutex_lock(&intel_pstate_driver_lock); 1385 1386 if (!intel_pstate_driver) { 1387 mutex_unlock(&intel_pstate_driver_lock); 1388 return -EAGAIN; 1389 } 1390 1391 mutex_lock(&intel_pstate_limits_lock); 1392 1393 global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100); 1394 1395 mutex_unlock(&intel_pstate_limits_lock); 1396 1397 if (intel_pstate_driver == &intel_pstate) 1398 intel_pstate_update_policies(); 1399 else 1400 update_qos_request(FREQ_QOS_MAX); 1401 1402 mutex_unlock(&intel_pstate_driver_lock); 1403 1404 return count; 1405 } 1406 1407 static ssize_t store_min_perf_pct(struct kobject *a, struct kobj_attribute *b, 1408 const char *buf, size_t count) 1409 { 1410 unsigned int input; 1411 int ret; 1412 1413 ret = sscanf(buf, "%u", &input); 1414 if (ret != 1) 1415 return -EINVAL; 1416 1417 mutex_lock(&intel_pstate_driver_lock); 1418 1419 if (!intel_pstate_driver) { 1420 mutex_unlock(&intel_pstate_driver_lock); 1421 return -EAGAIN; 1422 } 1423 1424 mutex_lock(&intel_pstate_limits_lock); 1425 1426 global.min_perf_pct = clamp_t(int, input, 1427 min_perf_pct_min(), global.max_perf_pct); 1428 1429 mutex_unlock(&intel_pstate_limits_lock); 1430 1431 if (intel_pstate_driver == &intel_pstate) 1432 intel_pstate_update_policies(); 1433 else 1434 update_qos_request(FREQ_QOS_MIN); 1435 1436 mutex_unlock(&intel_pstate_driver_lock); 1437 1438 return count; 1439 } 1440 1441 static ssize_t show_hwp_dynamic_boost(struct kobject *kobj, 1442 struct kobj_attribute *attr, char *buf) 1443 { 1444 return sprintf(buf, "%u\n", hwp_boost); 1445 } 1446 1447 static ssize_t store_hwp_dynamic_boost(struct kobject *a, 1448 struct kobj_attribute *b, 1449 const char *buf, size_t count) 1450 { 1451 unsigned int input; 1452 int ret; 1453 1454 ret = kstrtouint(buf, 10, &input); 1455 if (ret) 1456 return ret; 1457 1458 mutex_lock(&intel_pstate_driver_lock); 1459 hwp_boost = !!input; 1460 intel_pstate_update_policies(); 1461 mutex_unlock(&intel_pstate_driver_lock); 1462 1463 return count; 1464 } 1465 1466 static ssize_t show_energy_efficiency(struct kobject *kobj, struct kobj_attribute *attr, 1467 char *buf) 1468 { 1469 u64 power_ctl; 1470 int enable; 1471 1472 rdmsrl(MSR_IA32_POWER_CTL, power_ctl); 1473 enable = !!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE)); 1474 return sprintf(buf, "%d\n", !enable); 1475 } 1476 1477 static ssize_t store_energy_efficiency(struct kobject *a, struct kobj_attribute *b, 1478 const char *buf, size_t count) 1479 { 1480 bool input; 1481 int ret; 1482 1483 ret = kstrtobool(buf, &input); 1484 if (ret) 1485 return ret; 1486 1487 set_power_ctl_ee_state(input); 1488 1489 return count; 1490 } 1491 1492 show_one(max_perf_pct, max_perf_pct); 1493 show_one(min_perf_pct, min_perf_pct); 1494 1495 define_one_global_rw(status); 1496 define_one_global_rw(no_turbo); 1497 define_one_global_rw(max_perf_pct); 1498 define_one_global_rw(min_perf_pct); 1499 define_one_global_ro(turbo_pct); 1500 define_one_global_ro(num_pstates); 1501 define_one_global_rw(hwp_dynamic_boost); 1502 define_one_global_rw(energy_efficiency); 1503 1504 static struct attribute *intel_pstate_attributes[] = { 1505 &status.attr, 1506 &no_turbo.attr, 1507 NULL 1508 }; 1509 1510 static const struct attribute_group intel_pstate_attr_group = { 1511 .attrs = intel_pstate_attributes, 1512 }; 1513 1514 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[]; 1515 1516 static struct kobject *intel_pstate_kobject; 1517 1518 static void __init intel_pstate_sysfs_expose_params(void) 1519 { 1520 struct device *dev_root = bus_get_dev_root(&cpu_subsys); 1521 int rc; 1522 1523 if (dev_root) { 1524 intel_pstate_kobject = kobject_create_and_add("intel_pstate", &dev_root->kobj); 1525 put_device(dev_root); 1526 } 1527 if (WARN_ON(!intel_pstate_kobject)) 1528 return; 1529 1530 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group); 1531 if (WARN_ON(rc)) 1532 return; 1533 1534 if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) { 1535 rc = sysfs_create_file(intel_pstate_kobject, &turbo_pct.attr); 1536 WARN_ON(rc); 1537 1538 rc = sysfs_create_file(intel_pstate_kobject, &num_pstates.attr); 1539 WARN_ON(rc); 1540 } 1541 1542 /* 1543 * If per cpu limits are enforced there are no global limits, so 1544 * return without creating max/min_perf_pct attributes 1545 */ 1546 if (per_cpu_limits) 1547 return; 1548 1549 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr); 1550 WARN_ON(rc); 1551 1552 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr); 1553 WARN_ON(rc); 1554 1555 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids)) { 1556 rc = sysfs_create_file(intel_pstate_kobject, &energy_efficiency.attr); 1557 WARN_ON(rc); 1558 } 1559 } 1560 1561 static void __init intel_pstate_sysfs_remove(void) 1562 { 1563 if (!intel_pstate_kobject) 1564 return; 1565 1566 sysfs_remove_group(intel_pstate_kobject, &intel_pstate_attr_group); 1567 1568 if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) { 1569 sysfs_remove_file(intel_pstate_kobject, &num_pstates.attr); 1570 sysfs_remove_file(intel_pstate_kobject, &turbo_pct.attr); 1571 } 1572 1573 if (!per_cpu_limits) { 1574 sysfs_remove_file(intel_pstate_kobject, &max_perf_pct.attr); 1575 sysfs_remove_file(intel_pstate_kobject, &min_perf_pct.attr); 1576 1577 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids)) 1578 sysfs_remove_file(intel_pstate_kobject, &energy_efficiency.attr); 1579 } 1580 1581 kobject_put(intel_pstate_kobject); 1582 } 1583 1584 static void intel_pstate_sysfs_expose_hwp_dynamic_boost(void) 1585 { 1586 int rc; 1587 1588 if (!hwp_active) 1589 return; 1590 1591 rc = sysfs_create_file(intel_pstate_kobject, &hwp_dynamic_boost.attr); 1592 WARN_ON_ONCE(rc); 1593 } 1594 1595 static void intel_pstate_sysfs_hide_hwp_dynamic_boost(void) 1596 { 1597 if (!hwp_active) 1598 return; 1599 1600 sysfs_remove_file(intel_pstate_kobject, &hwp_dynamic_boost.attr); 1601 } 1602 1603 /************************** sysfs end ************************/ 1604 1605 static void intel_pstate_notify_work(struct work_struct *work) 1606 { 1607 struct cpudata *cpudata = 1608 container_of(to_delayed_work(work), struct cpudata, hwp_notify_work); 1609 struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpudata->cpu); 1610 1611 if (policy) { 1612 __intel_pstate_update_max_freq(cpudata, policy); 1613 1614 cpufreq_cpu_release(policy); 1615 } 1616 1617 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0); 1618 } 1619 1620 static DEFINE_SPINLOCK(hwp_notify_lock); 1621 static cpumask_t hwp_intr_enable_mask; 1622 1623 void notify_hwp_interrupt(void) 1624 { 1625 unsigned int this_cpu = smp_processor_id(); 1626 unsigned long flags; 1627 u64 value; 1628 1629 if (!hwp_active || !boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) 1630 return; 1631 1632 rdmsrl_safe(MSR_HWP_STATUS, &value); 1633 if (!(value & 0x01)) 1634 return; 1635 1636 spin_lock_irqsave(&hwp_notify_lock, flags); 1637 1638 if (!cpumask_test_cpu(this_cpu, &hwp_intr_enable_mask)) 1639 goto ack_intr; 1640 1641 schedule_delayed_work(&all_cpu_data[this_cpu]->hwp_notify_work, 1642 msecs_to_jiffies(10)); 1643 1644 spin_unlock_irqrestore(&hwp_notify_lock, flags); 1645 1646 return; 1647 1648 ack_intr: 1649 wrmsrl_safe(MSR_HWP_STATUS, 0); 1650 spin_unlock_irqrestore(&hwp_notify_lock, flags); 1651 } 1652 1653 static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata) 1654 { 1655 bool cancel_work; 1656 1657 if (!boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) 1658 return; 1659 1660 /* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */ 1661 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00); 1662 1663 spin_lock_irq(&hwp_notify_lock); 1664 cancel_work = cpumask_test_and_clear_cpu(cpudata->cpu, &hwp_intr_enable_mask); 1665 spin_unlock_irq(&hwp_notify_lock); 1666 1667 if (cancel_work) 1668 cancel_delayed_work_sync(&cpudata->hwp_notify_work); 1669 } 1670 1671 static void intel_pstate_enable_hwp_interrupt(struct cpudata *cpudata) 1672 { 1673 /* Enable HWP notification interrupt for guaranteed performance change */ 1674 if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) { 1675 spin_lock_irq(&hwp_notify_lock); 1676 INIT_DELAYED_WORK(&cpudata->hwp_notify_work, intel_pstate_notify_work); 1677 cpumask_set_cpu(cpudata->cpu, &hwp_intr_enable_mask); 1678 spin_unlock_irq(&hwp_notify_lock); 1679 1680 /* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */ 1681 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x01); 1682 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0); 1683 } 1684 } 1685 1686 static void intel_pstate_update_epp_defaults(struct cpudata *cpudata) 1687 { 1688 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0); 1689 1690 /* 1691 * If the EPP is set by firmware, which means that firmware enabled HWP 1692 * - Is equal or less than 0x80 (default balance_perf EPP) 1693 * - But less performance oriented than performance EPP 1694 * then use this as new balance_perf EPP. 1695 */ 1696 if (hwp_forced && cpudata->epp_default <= HWP_EPP_BALANCE_PERFORMANCE && 1697 cpudata->epp_default > HWP_EPP_PERFORMANCE) { 1698 epp_values[EPP_INDEX_BALANCE_PERFORMANCE] = cpudata->epp_default; 1699 return; 1700 } 1701 1702 /* 1703 * If this CPU gen doesn't call for change in balance_perf 1704 * EPP return. 1705 */ 1706 if (epp_values[EPP_INDEX_BALANCE_PERFORMANCE] == HWP_EPP_BALANCE_PERFORMANCE) 1707 return; 1708 1709 /* 1710 * Use hard coded value per gen to update the balance_perf 1711 * and default EPP. 1712 */ 1713 cpudata->epp_default = epp_values[EPP_INDEX_BALANCE_PERFORMANCE]; 1714 intel_pstate_set_epp(cpudata, cpudata->epp_default); 1715 } 1716 1717 static void intel_pstate_hwp_enable(struct cpudata *cpudata) 1718 { 1719 /* First disable HWP notification interrupt till we activate again */ 1720 if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) 1721 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00); 1722 1723 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1); 1724 1725 intel_pstate_enable_hwp_interrupt(cpudata); 1726 1727 if (cpudata->epp_default >= 0) 1728 return; 1729 1730 intel_pstate_update_epp_defaults(cpudata); 1731 } 1732 1733 static int atom_get_min_pstate(int not_used) 1734 { 1735 u64 value; 1736 1737 rdmsrl(MSR_ATOM_CORE_RATIOS, value); 1738 return (value >> 8) & 0x7F; 1739 } 1740 1741 static int atom_get_max_pstate(int not_used) 1742 { 1743 u64 value; 1744 1745 rdmsrl(MSR_ATOM_CORE_RATIOS, value); 1746 return (value >> 16) & 0x7F; 1747 } 1748 1749 static int atom_get_turbo_pstate(int not_used) 1750 { 1751 u64 value; 1752 1753 rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value); 1754 return value & 0x7F; 1755 } 1756 1757 static u64 atom_get_val(struct cpudata *cpudata, int pstate) 1758 { 1759 u64 val; 1760 int32_t vid_fp; 1761 u32 vid; 1762 1763 val = (u64)pstate << 8; 1764 if (READ_ONCE(global.no_turbo) && !global.turbo_disabled) 1765 val |= (u64)1 << 32; 1766 1767 vid_fp = cpudata->vid.min + mul_fp( 1768 int_tofp(pstate - cpudata->pstate.min_pstate), 1769 cpudata->vid.ratio); 1770 1771 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max); 1772 vid = ceiling_fp(vid_fp); 1773 1774 if (pstate > cpudata->pstate.max_pstate) 1775 vid = cpudata->vid.turbo; 1776 1777 return val | vid; 1778 } 1779 1780 static int silvermont_get_scaling(void) 1781 { 1782 u64 value; 1783 int i; 1784 /* Defined in Table 35-6 from SDM (Sept 2015) */ 1785 static int silvermont_freq_table[] = { 1786 83300, 100000, 133300, 116700, 80000}; 1787 1788 rdmsrl(MSR_FSB_FREQ, value); 1789 i = value & 0x7; 1790 WARN_ON(i > 4); 1791 1792 return silvermont_freq_table[i]; 1793 } 1794 1795 static int airmont_get_scaling(void) 1796 { 1797 u64 value; 1798 int i; 1799 /* Defined in Table 35-10 from SDM (Sept 2015) */ 1800 static int airmont_freq_table[] = { 1801 83300, 100000, 133300, 116700, 80000, 1802 93300, 90000, 88900, 87500}; 1803 1804 rdmsrl(MSR_FSB_FREQ, value); 1805 i = value & 0xF; 1806 WARN_ON(i > 8); 1807 1808 return airmont_freq_table[i]; 1809 } 1810 1811 static void atom_get_vid(struct cpudata *cpudata) 1812 { 1813 u64 value; 1814 1815 rdmsrl(MSR_ATOM_CORE_VIDS, value); 1816 cpudata->vid.min = int_tofp((value >> 8) & 0x7f); 1817 cpudata->vid.max = int_tofp((value >> 16) & 0x7f); 1818 cpudata->vid.ratio = div_fp( 1819 cpudata->vid.max - cpudata->vid.min, 1820 int_tofp(cpudata->pstate.max_pstate - 1821 cpudata->pstate.min_pstate)); 1822 1823 rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value); 1824 cpudata->vid.turbo = value & 0x7f; 1825 } 1826 1827 static int core_get_min_pstate(int cpu) 1828 { 1829 u64 value; 1830 1831 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &value); 1832 return (value >> 40) & 0xFF; 1833 } 1834 1835 static int core_get_max_pstate_physical(int cpu) 1836 { 1837 u64 value; 1838 1839 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &value); 1840 return (value >> 8) & 0xFF; 1841 } 1842 1843 static int core_get_tdp_ratio(int cpu, u64 plat_info) 1844 { 1845 /* Check how many TDP levels present */ 1846 if (plat_info & 0x600000000) { 1847 u64 tdp_ctrl; 1848 u64 tdp_ratio; 1849 int tdp_msr; 1850 int err; 1851 1852 /* Get the TDP level (0, 1, 2) to get ratios */ 1853 err = rdmsrl_safe_on_cpu(cpu, MSR_CONFIG_TDP_CONTROL, &tdp_ctrl); 1854 if (err) 1855 return err; 1856 1857 /* TDP MSR are continuous starting at 0x648 */ 1858 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03); 1859 err = rdmsrl_safe_on_cpu(cpu, tdp_msr, &tdp_ratio); 1860 if (err) 1861 return err; 1862 1863 /* For level 1 and 2, bits[23:16] contain the ratio */ 1864 if (tdp_ctrl & 0x03) 1865 tdp_ratio >>= 16; 1866 1867 tdp_ratio &= 0xff; /* ratios are only 8 bits long */ 1868 pr_debug("tdp_ratio %x\n", (int)tdp_ratio); 1869 1870 return (int)tdp_ratio; 1871 } 1872 1873 return -ENXIO; 1874 } 1875 1876 static int core_get_max_pstate(int cpu) 1877 { 1878 u64 tar; 1879 u64 plat_info; 1880 int max_pstate; 1881 int tdp_ratio; 1882 int err; 1883 1884 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &plat_info); 1885 max_pstate = (plat_info >> 8) & 0xFF; 1886 1887 tdp_ratio = core_get_tdp_ratio(cpu, plat_info); 1888 if (tdp_ratio <= 0) 1889 return max_pstate; 1890 1891 if (hwp_active) { 1892 /* Turbo activation ratio is not used on HWP platforms */ 1893 return tdp_ratio; 1894 } 1895 1896 err = rdmsrl_safe_on_cpu(cpu, MSR_TURBO_ACTIVATION_RATIO, &tar); 1897 if (!err) { 1898 int tar_levels; 1899 1900 /* Do some sanity checking for safety */ 1901 tar_levels = tar & 0xff; 1902 if (tdp_ratio - 1 == tar_levels) { 1903 max_pstate = tar_levels; 1904 pr_debug("max_pstate=TAC %x\n", max_pstate); 1905 } 1906 } 1907 1908 return max_pstate; 1909 } 1910 1911 static int core_get_turbo_pstate(int cpu) 1912 { 1913 u64 value; 1914 int nont, ret; 1915 1916 rdmsrl_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value); 1917 nont = core_get_max_pstate(cpu); 1918 ret = (value) & 255; 1919 if (ret <= nont) 1920 ret = nont; 1921 return ret; 1922 } 1923 1924 static u64 core_get_val(struct cpudata *cpudata, int pstate) 1925 { 1926 u64 val; 1927 1928 val = (u64)pstate << 8; 1929 if (READ_ONCE(global.no_turbo) && !global.turbo_disabled) 1930 val |= (u64)1 << 32; 1931 1932 return val; 1933 } 1934 1935 static int knl_get_aperf_mperf_shift(void) 1936 { 1937 return 10; 1938 } 1939 1940 static int knl_get_turbo_pstate(int cpu) 1941 { 1942 u64 value; 1943 int nont, ret; 1944 1945 rdmsrl_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value); 1946 nont = core_get_max_pstate(cpu); 1947 ret = (((value) >> 8) & 0xFF); 1948 if (ret <= nont) 1949 ret = nont; 1950 return ret; 1951 } 1952 1953 static void hybrid_get_type(void *data) 1954 { 1955 u8 *cpu_type = data; 1956 1957 *cpu_type = get_this_hybrid_cpu_type(); 1958 } 1959 1960 static int hwp_get_cpu_scaling(int cpu) 1961 { 1962 u8 cpu_type = 0; 1963 1964 smp_call_function_single(cpu, hybrid_get_type, &cpu_type, 1); 1965 /* P-cores have a smaller perf level-to-freqency scaling factor. */ 1966 if (cpu_type == 0x40) 1967 return hybrid_scaling_factor; 1968 1969 /* Use default core scaling for E-cores */ 1970 if (cpu_type == 0x20) 1971 return core_get_scaling(); 1972 1973 /* 1974 * If reached here, this system is either non-hybrid (like Tiger 1975 * Lake) or hybrid-capable (like Alder Lake or Raptor Lake) with 1976 * no E cores (in which case CPUID for hybrid support is 0). 1977 * 1978 * The CPPC nominal_frequency field is 0 for non-hybrid systems, 1979 * so the default core scaling will be used for them. 1980 */ 1981 return intel_pstate_cppc_get_scaling(cpu); 1982 } 1983 1984 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate) 1985 { 1986 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu); 1987 cpu->pstate.current_pstate = pstate; 1988 /* 1989 * Generally, there is no guarantee that this code will always run on 1990 * the CPU being updated, so force the register update to run on the 1991 * right CPU. 1992 */ 1993 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL, 1994 pstate_funcs.get_val(cpu, pstate)); 1995 } 1996 1997 static void intel_pstate_set_min_pstate(struct cpudata *cpu) 1998 { 1999 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate); 2000 } 2001 2002 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu) 2003 { 2004 int perf_ctl_max_phys = pstate_funcs.get_max_physical(cpu->cpu); 2005 int perf_ctl_scaling = pstate_funcs.get_scaling(); 2006 2007 cpu->pstate.min_pstate = pstate_funcs.get_min(cpu->cpu); 2008 cpu->pstate.max_pstate_physical = perf_ctl_max_phys; 2009 cpu->pstate.perf_ctl_scaling = perf_ctl_scaling; 2010 2011 if (hwp_active && !hwp_mode_bdw) { 2012 __intel_pstate_get_hwp_cap(cpu); 2013 2014 if (pstate_funcs.get_cpu_scaling) { 2015 cpu->pstate.scaling = pstate_funcs.get_cpu_scaling(cpu->cpu); 2016 if (cpu->pstate.scaling != perf_ctl_scaling) 2017 intel_pstate_hybrid_hwp_adjust(cpu); 2018 } else { 2019 cpu->pstate.scaling = perf_ctl_scaling; 2020 } 2021 } else { 2022 cpu->pstate.scaling = perf_ctl_scaling; 2023 cpu->pstate.max_pstate = pstate_funcs.get_max(cpu->cpu); 2024 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(cpu->cpu); 2025 } 2026 2027 if (cpu->pstate.scaling == perf_ctl_scaling) { 2028 cpu->pstate.min_freq = cpu->pstate.min_pstate * perf_ctl_scaling; 2029 cpu->pstate.max_freq = cpu->pstate.max_pstate * perf_ctl_scaling; 2030 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * perf_ctl_scaling; 2031 } 2032 2033 if (pstate_funcs.get_aperf_mperf_shift) 2034 cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift(); 2035 2036 if (pstate_funcs.get_vid) 2037 pstate_funcs.get_vid(cpu); 2038 2039 intel_pstate_set_min_pstate(cpu); 2040 } 2041 2042 /* 2043 * Long hold time will keep high perf limits for long time, 2044 * which negatively impacts perf/watt for some workloads, 2045 * like specpower. 3ms is based on experiements on some 2046 * workoads. 2047 */ 2048 static int hwp_boost_hold_time_ns = 3 * NSEC_PER_MSEC; 2049 2050 static inline void intel_pstate_hwp_boost_up(struct cpudata *cpu) 2051 { 2052 u64 hwp_req = READ_ONCE(cpu->hwp_req_cached); 2053 u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached); 2054 u32 max_limit = (hwp_req & 0xff00) >> 8; 2055 u32 min_limit = (hwp_req & 0xff); 2056 u32 boost_level1; 2057 2058 /* 2059 * Cases to consider (User changes via sysfs or boot time): 2060 * If, P0 (Turbo max) = P1 (Guaranteed max) = min: 2061 * No boost, return. 2062 * If, P0 (Turbo max) > P1 (Guaranteed max) = min: 2063 * Should result in one level boost only for P0. 2064 * If, P0 (Turbo max) = P1 (Guaranteed max) > min: 2065 * Should result in two level boost: 2066 * (min + p1)/2 and P1. 2067 * If, P0 (Turbo max) > P1 (Guaranteed max) > min: 2068 * Should result in three level boost: 2069 * (min + p1)/2, P1 and P0. 2070 */ 2071 2072 /* If max and min are equal or already at max, nothing to boost */ 2073 if (max_limit == min_limit || cpu->hwp_boost_min >= max_limit) 2074 return; 2075 2076 if (!cpu->hwp_boost_min) 2077 cpu->hwp_boost_min = min_limit; 2078 2079 /* level at half way mark between min and guranteed */ 2080 boost_level1 = (HWP_GUARANTEED_PERF(hwp_cap) + min_limit) >> 1; 2081 2082 if (cpu->hwp_boost_min < boost_level1) 2083 cpu->hwp_boost_min = boost_level1; 2084 else if (cpu->hwp_boost_min < HWP_GUARANTEED_PERF(hwp_cap)) 2085 cpu->hwp_boost_min = HWP_GUARANTEED_PERF(hwp_cap); 2086 else if (cpu->hwp_boost_min == HWP_GUARANTEED_PERF(hwp_cap) && 2087 max_limit != HWP_GUARANTEED_PERF(hwp_cap)) 2088 cpu->hwp_boost_min = max_limit; 2089 else 2090 return; 2091 2092 hwp_req = (hwp_req & ~GENMASK_ULL(7, 0)) | cpu->hwp_boost_min; 2093 wrmsrl(MSR_HWP_REQUEST, hwp_req); 2094 cpu->last_update = cpu->sample.time; 2095 } 2096 2097 static inline void intel_pstate_hwp_boost_down(struct cpudata *cpu) 2098 { 2099 if (cpu->hwp_boost_min) { 2100 bool expired; 2101 2102 /* Check if we are idle for hold time to boost down */ 2103 expired = time_after64(cpu->sample.time, cpu->last_update + 2104 hwp_boost_hold_time_ns); 2105 if (expired) { 2106 wrmsrl(MSR_HWP_REQUEST, cpu->hwp_req_cached); 2107 cpu->hwp_boost_min = 0; 2108 } 2109 } 2110 cpu->last_update = cpu->sample.time; 2111 } 2112 2113 static inline void intel_pstate_update_util_hwp_local(struct cpudata *cpu, 2114 u64 time) 2115 { 2116 cpu->sample.time = time; 2117 2118 if (cpu->sched_flags & SCHED_CPUFREQ_IOWAIT) { 2119 bool do_io = false; 2120 2121 cpu->sched_flags = 0; 2122 /* 2123 * Set iowait_boost flag and update time. Since IO WAIT flag 2124 * is set all the time, we can't just conclude that there is 2125 * some IO bound activity is scheduled on this CPU with just 2126 * one occurrence. If we receive at least two in two 2127 * consecutive ticks, then we treat as boost candidate. 2128 */ 2129 if (time_before64(time, cpu->last_io_update + 2 * TICK_NSEC)) 2130 do_io = true; 2131 2132 cpu->last_io_update = time; 2133 2134 if (do_io) 2135 intel_pstate_hwp_boost_up(cpu); 2136 2137 } else { 2138 intel_pstate_hwp_boost_down(cpu); 2139 } 2140 } 2141 2142 static inline void intel_pstate_update_util_hwp(struct update_util_data *data, 2143 u64 time, unsigned int flags) 2144 { 2145 struct cpudata *cpu = container_of(data, struct cpudata, update_util); 2146 2147 cpu->sched_flags |= flags; 2148 2149 if (smp_processor_id() == cpu->cpu) 2150 intel_pstate_update_util_hwp_local(cpu, time); 2151 } 2152 2153 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu) 2154 { 2155 struct sample *sample = &cpu->sample; 2156 2157 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf); 2158 } 2159 2160 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time) 2161 { 2162 u64 aperf, mperf; 2163 unsigned long flags; 2164 u64 tsc; 2165 2166 local_irq_save(flags); 2167 rdmsrl(MSR_IA32_APERF, aperf); 2168 rdmsrl(MSR_IA32_MPERF, mperf); 2169 tsc = rdtsc(); 2170 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) { 2171 local_irq_restore(flags); 2172 return false; 2173 } 2174 local_irq_restore(flags); 2175 2176 cpu->last_sample_time = cpu->sample.time; 2177 cpu->sample.time = time; 2178 cpu->sample.aperf = aperf; 2179 cpu->sample.mperf = mperf; 2180 cpu->sample.tsc = tsc; 2181 cpu->sample.aperf -= cpu->prev_aperf; 2182 cpu->sample.mperf -= cpu->prev_mperf; 2183 cpu->sample.tsc -= cpu->prev_tsc; 2184 2185 cpu->prev_aperf = aperf; 2186 cpu->prev_mperf = mperf; 2187 cpu->prev_tsc = tsc; 2188 /* 2189 * First time this function is invoked in a given cycle, all of the 2190 * previous sample data fields are equal to zero or stale and they must 2191 * be populated with meaningful numbers for things to work, so assume 2192 * that sample.time will always be reset before setting the utilization 2193 * update hook and make the caller skip the sample then. 2194 */ 2195 if (cpu->last_sample_time) { 2196 intel_pstate_calc_avg_perf(cpu); 2197 return true; 2198 } 2199 return false; 2200 } 2201 2202 static inline int32_t get_avg_frequency(struct cpudata *cpu) 2203 { 2204 return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz); 2205 } 2206 2207 static inline int32_t get_avg_pstate(struct cpudata *cpu) 2208 { 2209 return mul_ext_fp(cpu->pstate.max_pstate_physical, 2210 cpu->sample.core_avg_perf); 2211 } 2212 2213 static inline int32_t get_target_pstate(struct cpudata *cpu) 2214 { 2215 struct sample *sample = &cpu->sample; 2216 int32_t busy_frac; 2217 int target, avg_pstate; 2218 2219 busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift, 2220 sample->tsc); 2221 2222 if (busy_frac < cpu->iowait_boost) 2223 busy_frac = cpu->iowait_boost; 2224 2225 sample->busy_scaled = busy_frac * 100; 2226 2227 target = READ_ONCE(global.no_turbo) ? 2228 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate; 2229 target += target >> 2; 2230 target = mul_fp(target, busy_frac); 2231 if (target < cpu->pstate.min_pstate) 2232 target = cpu->pstate.min_pstate; 2233 2234 /* 2235 * If the average P-state during the previous cycle was higher than the 2236 * current target, add 50% of the difference to the target to reduce 2237 * possible performance oscillations and offset possible performance 2238 * loss related to moving the workload from one CPU to another within 2239 * a package/module. 2240 */ 2241 avg_pstate = get_avg_pstate(cpu); 2242 if (avg_pstate > target) 2243 target += (avg_pstate - target) >> 1; 2244 2245 return target; 2246 } 2247 2248 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate) 2249 { 2250 int min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio); 2251 int max_pstate = max(min_pstate, cpu->max_perf_ratio); 2252 2253 return clamp_t(int, pstate, min_pstate, max_pstate); 2254 } 2255 2256 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate) 2257 { 2258 if (pstate == cpu->pstate.current_pstate) 2259 return; 2260 2261 cpu->pstate.current_pstate = pstate; 2262 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate)); 2263 } 2264 2265 static void intel_pstate_adjust_pstate(struct cpudata *cpu) 2266 { 2267 int from = cpu->pstate.current_pstate; 2268 struct sample *sample; 2269 int target_pstate; 2270 2271 target_pstate = get_target_pstate(cpu); 2272 target_pstate = intel_pstate_prepare_request(cpu, target_pstate); 2273 trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu); 2274 intel_pstate_update_pstate(cpu, target_pstate); 2275 2276 sample = &cpu->sample; 2277 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf), 2278 fp_toint(sample->busy_scaled), 2279 from, 2280 cpu->pstate.current_pstate, 2281 sample->mperf, 2282 sample->aperf, 2283 sample->tsc, 2284 get_avg_frequency(cpu), 2285 fp_toint(cpu->iowait_boost * 100)); 2286 } 2287 2288 static void intel_pstate_update_util(struct update_util_data *data, u64 time, 2289 unsigned int flags) 2290 { 2291 struct cpudata *cpu = container_of(data, struct cpudata, update_util); 2292 u64 delta_ns; 2293 2294 /* Don't allow remote callbacks */ 2295 if (smp_processor_id() != cpu->cpu) 2296 return; 2297 2298 delta_ns = time - cpu->last_update; 2299 if (flags & SCHED_CPUFREQ_IOWAIT) { 2300 /* Start over if the CPU may have been idle. */ 2301 if (delta_ns > TICK_NSEC) { 2302 cpu->iowait_boost = ONE_EIGHTH_FP; 2303 } else if (cpu->iowait_boost >= ONE_EIGHTH_FP) { 2304 cpu->iowait_boost <<= 1; 2305 if (cpu->iowait_boost > int_tofp(1)) 2306 cpu->iowait_boost = int_tofp(1); 2307 } else { 2308 cpu->iowait_boost = ONE_EIGHTH_FP; 2309 } 2310 } else if (cpu->iowait_boost) { 2311 /* Clear iowait_boost if the CPU may have been idle. */ 2312 if (delta_ns > TICK_NSEC) 2313 cpu->iowait_boost = 0; 2314 else 2315 cpu->iowait_boost >>= 1; 2316 } 2317 cpu->last_update = time; 2318 delta_ns = time - cpu->sample.time; 2319 if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL) 2320 return; 2321 2322 if (intel_pstate_sample(cpu, time)) 2323 intel_pstate_adjust_pstate(cpu); 2324 } 2325 2326 static struct pstate_funcs core_funcs = { 2327 .get_max = core_get_max_pstate, 2328 .get_max_physical = core_get_max_pstate_physical, 2329 .get_min = core_get_min_pstate, 2330 .get_turbo = core_get_turbo_pstate, 2331 .get_scaling = core_get_scaling, 2332 .get_val = core_get_val, 2333 }; 2334 2335 static const struct pstate_funcs silvermont_funcs = { 2336 .get_max = atom_get_max_pstate, 2337 .get_max_physical = atom_get_max_pstate, 2338 .get_min = atom_get_min_pstate, 2339 .get_turbo = atom_get_turbo_pstate, 2340 .get_val = atom_get_val, 2341 .get_scaling = silvermont_get_scaling, 2342 .get_vid = atom_get_vid, 2343 }; 2344 2345 static const struct pstate_funcs airmont_funcs = { 2346 .get_max = atom_get_max_pstate, 2347 .get_max_physical = atom_get_max_pstate, 2348 .get_min = atom_get_min_pstate, 2349 .get_turbo = atom_get_turbo_pstate, 2350 .get_val = atom_get_val, 2351 .get_scaling = airmont_get_scaling, 2352 .get_vid = atom_get_vid, 2353 }; 2354 2355 static const struct pstate_funcs knl_funcs = { 2356 .get_max = core_get_max_pstate, 2357 .get_max_physical = core_get_max_pstate_physical, 2358 .get_min = core_get_min_pstate, 2359 .get_turbo = knl_get_turbo_pstate, 2360 .get_aperf_mperf_shift = knl_get_aperf_mperf_shift, 2361 .get_scaling = core_get_scaling, 2362 .get_val = core_get_val, 2363 }; 2364 2365 #define X86_MATCH(model, policy) \ 2366 X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \ 2367 X86_FEATURE_APERFMPERF, &policy) 2368 2369 static const struct x86_cpu_id intel_pstate_cpu_ids[] = { 2370 X86_MATCH(SANDYBRIDGE, core_funcs), 2371 X86_MATCH(SANDYBRIDGE_X, core_funcs), 2372 X86_MATCH(ATOM_SILVERMONT, silvermont_funcs), 2373 X86_MATCH(IVYBRIDGE, core_funcs), 2374 X86_MATCH(HASWELL, core_funcs), 2375 X86_MATCH(BROADWELL, core_funcs), 2376 X86_MATCH(IVYBRIDGE_X, core_funcs), 2377 X86_MATCH(HASWELL_X, core_funcs), 2378 X86_MATCH(HASWELL_L, core_funcs), 2379 X86_MATCH(HASWELL_G, core_funcs), 2380 X86_MATCH(BROADWELL_G, core_funcs), 2381 X86_MATCH(ATOM_AIRMONT, airmont_funcs), 2382 X86_MATCH(SKYLAKE_L, core_funcs), 2383 X86_MATCH(BROADWELL_X, core_funcs), 2384 X86_MATCH(SKYLAKE, core_funcs), 2385 X86_MATCH(BROADWELL_D, core_funcs), 2386 X86_MATCH(XEON_PHI_KNL, knl_funcs), 2387 X86_MATCH(XEON_PHI_KNM, knl_funcs), 2388 X86_MATCH(ATOM_GOLDMONT, core_funcs), 2389 X86_MATCH(ATOM_GOLDMONT_PLUS, core_funcs), 2390 X86_MATCH(SKYLAKE_X, core_funcs), 2391 X86_MATCH(COMETLAKE, core_funcs), 2392 X86_MATCH(ICELAKE_X, core_funcs), 2393 X86_MATCH(TIGERLAKE, core_funcs), 2394 X86_MATCH(SAPPHIRERAPIDS_X, core_funcs), 2395 X86_MATCH(EMERALDRAPIDS_X, core_funcs), 2396 {} 2397 }; 2398 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids); 2399 2400 #ifdef CONFIG_ACPI 2401 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = { 2402 X86_MATCH(BROADWELL_D, core_funcs), 2403 X86_MATCH(BROADWELL_X, core_funcs), 2404 X86_MATCH(SKYLAKE_X, core_funcs), 2405 X86_MATCH(ICELAKE_X, core_funcs), 2406 X86_MATCH(SAPPHIRERAPIDS_X, core_funcs), 2407 {} 2408 }; 2409 #endif 2410 2411 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = { 2412 X86_MATCH(KABYLAKE, core_funcs), 2413 {} 2414 }; 2415 2416 static int intel_pstate_init_cpu(unsigned int cpunum) 2417 { 2418 struct cpudata *cpu; 2419 2420 cpu = all_cpu_data[cpunum]; 2421 2422 if (!cpu) { 2423 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL); 2424 if (!cpu) 2425 return -ENOMEM; 2426 2427 WRITE_ONCE(all_cpu_data[cpunum], cpu); 2428 2429 cpu->cpu = cpunum; 2430 2431 cpu->epp_default = -EINVAL; 2432 2433 if (hwp_active) { 2434 intel_pstate_hwp_enable(cpu); 2435 2436 if (intel_pstate_acpi_pm_profile_server()) 2437 hwp_boost = true; 2438 } 2439 } else if (hwp_active) { 2440 /* 2441 * Re-enable HWP in case this happens after a resume from ACPI 2442 * S3 if the CPU was offline during the whole system/resume 2443 * cycle. 2444 */ 2445 intel_pstate_hwp_reenable(cpu); 2446 } 2447 2448 cpu->epp_powersave = -EINVAL; 2449 cpu->epp_policy = 0; 2450 2451 intel_pstate_get_cpu_pstates(cpu); 2452 2453 pr_debug("controlling: cpu %d\n", cpunum); 2454 2455 return 0; 2456 } 2457 2458 static void intel_pstate_set_update_util_hook(unsigned int cpu_num) 2459 { 2460 struct cpudata *cpu = all_cpu_data[cpu_num]; 2461 2462 if (hwp_active && !hwp_boost) 2463 return; 2464 2465 if (cpu->update_util_set) 2466 return; 2467 2468 /* Prevent intel_pstate_update_util() from using stale data. */ 2469 cpu->sample.time = 0; 2470 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util, 2471 (hwp_active ? 2472 intel_pstate_update_util_hwp : 2473 intel_pstate_update_util)); 2474 cpu->update_util_set = true; 2475 } 2476 2477 static void intel_pstate_clear_update_util_hook(unsigned int cpu) 2478 { 2479 struct cpudata *cpu_data = all_cpu_data[cpu]; 2480 2481 if (!cpu_data->update_util_set) 2482 return; 2483 2484 cpufreq_remove_update_util_hook(cpu); 2485 cpu_data->update_util_set = false; 2486 synchronize_rcu(); 2487 } 2488 2489 static int intel_pstate_get_max_freq(struct cpudata *cpu) 2490 { 2491 return READ_ONCE(global.no_turbo) ? 2492 cpu->pstate.max_freq : cpu->pstate.turbo_freq; 2493 } 2494 2495 static void intel_pstate_update_perf_limits(struct cpudata *cpu, 2496 unsigned int policy_min, 2497 unsigned int policy_max) 2498 { 2499 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling; 2500 int32_t max_policy_perf, min_policy_perf; 2501 2502 max_policy_perf = policy_max / perf_ctl_scaling; 2503 if (policy_max == policy_min) { 2504 min_policy_perf = max_policy_perf; 2505 } else { 2506 min_policy_perf = policy_min / perf_ctl_scaling; 2507 min_policy_perf = clamp_t(int32_t, min_policy_perf, 2508 0, max_policy_perf); 2509 } 2510 2511 /* 2512 * HWP needs some special consideration, because HWP_REQUEST uses 2513 * abstract values to represent performance rather than pure ratios. 2514 */ 2515 if (hwp_active && cpu->pstate.scaling != perf_ctl_scaling) { 2516 int freq; 2517 2518 freq = max_policy_perf * perf_ctl_scaling; 2519 max_policy_perf = intel_pstate_freq_to_hwp(cpu, freq); 2520 freq = min_policy_perf * perf_ctl_scaling; 2521 min_policy_perf = intel_pstate_freq_to_hwp(cpu, freq); 2522 } 2523 2524 pr_debug("cpu:%d min_policy_perf:%d max_policy_perf:%d\n", 2525 cpu->cpu, min_policy_perf, max_policy_perf); 2526 2527 /* Normalize user input to [min_perf, max_perf] */ 2528 if (per_cpu_limits) { 2529 cpu->min_perf_ratio = min_policy_perf; 2530 cpu->max_perf_ratio = max_policy_perf; 2531 } else { 2532 int turbo_max = cpu->pstate.turbo_pstate; 2533 int32_t global_min, global_max; 2534 2535 /* Global limits are in percent of the maximum turbo P-state. */ 2536 global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100); 2537 global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100); 2538 global_min = clamp_t(int32_t, global_min, 0, global_max); 2539 2540 pr_debug("cpu:%d global_min:%d global_max:%d\n", cpu->cpu, 2541 global_min, global_max); 2542 2543 cpu->min_perf_ratio = max(min_policy_perf, global_min); 2544 cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf); 2545 cpu->max_perf_ratio = min(max_policy_perf, global_max); 2546 cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio); 2547 2548 /* Make sure min_perf <= max_perf */ 2549 cpu->min_perf_ratio = min(cpu->min_perf_ratio, 2550 cpu->max_perf_ratio); 2551 2552 } 2553 pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", cpu->cpu, 2554 cpu->max_perf_ratio, 2555 cpu->min_perf_ratio); 2556 } 2557 2558 static int intel_pstate_set_policy(struct cpufreq_policy *policy) 2559 { 2560 struct cpudata *cpu; 2561 2562 if (!policy->cpuinfo.max_freq) 2563 return -ENODEV; 2564 2565 pr_debug("set_policy cpuinfo.max %u policy->max %u\n", 2566 policy->cpuinfo.max_freq, policy->max); 2567 2568 cpu = all_cpu_data[policy->cpu]; 2569 cpu->policy = policy->policy; 2570 2571 mutex_lock(&intel_pstate_limits_lock); 2572 2573 intel_pstate_update_perf_limits(cpu, policy->min, policy->max); 2574 2575 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) { 2576 int pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio); 2577 2578 /* 2579 * NOHZ_FULL CPUs need this as the governor callback may not 2580 * be invoked on them. 2581 */ 2582 intel_pstate_clear_update_util_hook(policy->cpu); 2583 intel_pstate_set_pstate(cpu, pstate); 2584 } else { 2585 intel_pstate_set_update_util_hook(policy->cpu); 2586 } 2587 2588 if (hwp_active) { 2589 /* 2590 * When hwp_boost was active before and dynamically it 2591 * was turned off, in that case we need to clear the 2592 * update util hook. 2593 */ 2594 if (!hwp_boost) 2595 intel_pstate_clear_update_util_hook(policy->cpu); 2596 intel_pstate_hwp_set(policy->cpu); 2597 } 2598 /* 2599 * policy->cur is never updated with the intel_pstate driver, but it 2600 * is used as a stale frequency value. So, keep it within limits. 2601 */ 2602 policy->cur = policy->min; 2603 2604 mutex_unlock(&intel_pstate_limits_lock); 2605 2606 return 0; 2607 } 2608 2609 static void intel_pstate_adjust_policy_max(struct cpudata *cpu, 2610 struct cpufreq_policy_data *policy) 2611 { 2612 if (!hwp_active && 2613 cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate && 2614 policy->max < policy->cpuinfo.max_freq && 2615 policy->max > cpu->pstate.max_freq) { 2616 pr_debug("policy->max > max non turbo frequency\n"); 2617 policy->max = policy->cpuinfo.max_freq; 2618 } 2619 } 2620 2621 static void intel_pstate_verify_cpu_policy(struct cpudata *cpu, 2622 struct cpufreq_policy_data *policy) 2623 { 2624 int max_freq; 2625 2626 if (hwp_active) { 2627 intel_pstate_get_hwp_cap(cpu); 2628 max_freq = READ_ONCE(global.no_turbo) ? 2629 cpu->pstate.max_freq : cpu->pstate.turbo_freq; 2630 } else { 2631 max_freq = intel_pstate_get_max_freq(cpu); 2632 } 2633 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, max_freq); 2634 2635 intel_pstate_adjust_policy_max(cpu, policy); 2636 } 2637 2638 static int intel_pstate_verify_policy(struct cpufreq_policy_data *policy) 2639 { 2640 intel_pstate_verify_cpu_policy(all_cpu_data[policy->cpu], policy); 2641 2642 return 0; 2643 } 2644 2645 static int intel_cpufreq_cpu_offline(struct cpufreq_policy *policy) 2646 { 2647 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2648 2649 pr_debug("CPU %d going offline\n", cpu->cpu); 2650 2651 if (cpu->suspended) 2652 return 0; 2653 2654 /* 2655 * If the CPU is an SMT thread and it goes offline with the performance 2656 * settings different from the minimum, it will prevent its sibling 2657 * from getting to lower performance levels, so force the minimum 2658 * performance on CPU offline to prevent that from happening. 2659 */ 2660 if (hwp_active) 2661 intel_pstate_hwp_offline(cpu); 2662 else 2663 intel_pstate_set_min_pstate(cpu); 2664 2665 intel_pstate_exit_perf_limits(policy); 2666 2667 return 0; 2668 } 2669 2670 static int intel_pstate_cpu_online(struct cpufreq_policy *policy) 2671 { 2672 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2673 2674 pr_debug("CPU %d going online\n", cpu->cpu); 2675 2676 intel_pstate_init_acpi_perf_limits(policy); 2677 2678 if (hwp_active) { 2679 /* 2680 * Re-enable HWP and clear the "suspended" flag to let "resume" 2681 * know that it need not do that. 2682 */ 2683 intel_pstate_hwp_reenable(cpu); 2684 cpu->suspended = false; 2685 } 2686 2687 return 0; 2688 } 2689 2690 static int intel_pstate_cpu_offline(struct cpufreq_policy *policy) 2691 { 2692 intel_pstate_clear_update_util_hook(policy->cpu); 2693 2694 return intel_cpufreq_cpu_offline(policy); 2695 } 2696 2697 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy) 2698 { 2699 pr_debug("CPU %d exiting\n", policy->cpu); 2700 2701 policy->fast_switch_possible = false; 2702 2703 return 0; 2704 } 2705 2706 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy) 2707 { 2708 struct cpudata *cpu; 2709 int rc; 2710 2711 rc = intel_pstate_init_cpu(policy->cpu); 2712 if (rc) 2713 return rc; 2714 2715 cpu = all_cpu_data[policy->cpu]; 2716 2717 cpu->max_perf_ratio = 0xFF; 2718 cpu->min_perf_ratio = 0; 2719 2720 /* cpuinfo and default policy values */ 2721 policy->cpuinfo.min_freq = cpu->pstate.min_freq; 2722 policy->cpuinfo.max_freq = READ_ONCE(global.no_turbo) ? 2723 cpu->pstate.max_freq : cpu->pstate.turbo_freq; 2724 2725 policy->min = policy->cpuinfo.min_freq; 2726 policy->max = policy->cpuinfo.max_freq; 2727 2728 intel_pstate_init_acpi_perf_limits(policy); 2729 2730 policy->fast_switch_possible = true; 2731 2732 return 0; 2733 } 2734 2735 static int intel_pstate_cpu_init(struct cpufreq_policy *policy) 2736 { 2737 int ret = __intel_pstate_cpu_init(policy); 2738 2739 if (ret) 2740 return ret; 2741 2742 /* 2743 * Set the policy to powersave to provide a valid fallback value in case 2744 * the default cpufreq governor is neither powersave nor performance. 2745 */ 2746 policy->policy = CPUFREQ_POLICY_POWERSAVE; 2747 2748 if (hwp_active) { 2749 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2750 2751 cpu->epp_cached = intel_pstate_get_epp(cpu, 0); 2752 } 2753 2754 return 0; 2755 } 2756 2757 static struct cpufreq_driver intel_pstate = { 2758 .flags = CPUFREQ_CONST_LOOPS, 2759 .verify = intel_pstate_verify_policy, 2760 .setpolicy = intel_pstate_set_policy, 2761 .suspend = intel_pstate_suspend, 2762 .resume = intel_pstate_resume, 2763 .init = intel_pstate_cpu_init, 2764 .exit = intel_pstate_cpu_exit, 2765 .offline = intel_pstate_cpu_offline, 2766 .online = intel_pstate_cpu_online, 2767 .update_limits = intel_pstate_update_limits, 2768 .name = "intel_pstate", 2769 }; 2770 2771 static int intel_cpufreq_verify_policy(struct cpufreq_policy_data *policy) 2772 { 2773 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2774 2775 intel_pstate_verify_cpu_policy(cpu, policy); 2776 intel_pstate_update_perf_limits(cpu, policy->min, policy->max); 2777 2778 return 0; 2779 } 2780 2781 /* Use of trace in passive mode: 2782 * 2783 * In passive mode the trace core_busy field (also known as the 2784 * performance field, and lablelled as such on the graphs; also known as 2785 * core_avg_perf) is not needed and so is re-assigned to indicate if the 2786 * driver call was via the normal or fast switch path. Various graphs 2787 * output from the intel_pstate_tracer.py utility that include core_busy 2788 * (or performance or core_avg_perf) have a fixed y-axis from 0 to 100%, 2789 * so we use 10 to indicate the normal path through the driver, and 2790 * 90 to indicate the fast switch path through the driver. 2791 * The scaled_busy field is not used, and is set to 0. 2792 */ 2793 2794 #define INTEL_PSTATE_TRACE_TARGET 10 2795 #define INTEL_PSTATE_TRACE_FAST_SWITCH 90 2796 2797 static void intel_cpufreq_trace(struct cpudata *cpu, unsigned int trace_type, int old_pstate) 2798 { 2799 struct sample *sample; 2800 2801 if (!trace_pstate_sample_enabled()) 2802 return; 2803 2804 if (!intel_pstate_sample(cpu, ktime_get())) 2805 return; 2806 2807 sample = &cpu->sample; 2808 trace_pstate_sample(trace_type, 2809 0, 2810 old_pstate, 2811 cpu->pstate.current_pstate, 2812 sample->mperf, 2813 sample->aperf, 2814 sample->tsc, 2815 get_avg_frequency(cpu), 2816 fp_toint(cpu->iowait_boost * 100)); 2817 } 2818 2819 static void intel_cpufreq_hwp_update(struct cpudata *cpu, u32 min, u32 max, 2820 u32 desired, bool fast_switch) 2821 { 2822 u64 prev = READ_ONCE(cpu->hwp_req_cached), value = prev; 2823 2824 value &= ~HWP_MIN_PERF(~0L); 2825 value |= HWP_MIN_PERF(min); 2826 2827 value &= ~HWP_MAX_PERF(~0L); 2828 value |= HWP_MAX_PERF(max); 2829 2830 value &= ~HWP_DESIRED_PERF(~0L); 2831 value |= HWP_DESIRED_PERF(desired); 2832 2833 if (value == prev) 2834 return; 2835 2836 WRITE_ONCE(cpu->hwp_req_cached, value); 2837 if (fast_switch) 2838 wrmsrl(MSR_HWP_REQUEST, value); 2839 else 2840 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 2841 } 2842 2843 static void intel_cpufreq_perf_ctl_update(struct cpudata *cpu, 2844 u32 target_pstate, bool fast_switch) 2845 { 2846 if (fast_switch) 2847 wrmsrl(MSR_IA32_PERF_CTL, 2848 pstate_funcs.get_val(cpu, target_pstate)); 2849 else 2850 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL, 2851 pstate_funcs.get_val(cpu, target_pstate)); 2852 } 2853 2854 static int intel_cpufreq_update_pstate(struct cpufreq_policy *policy, 2855 int target_pstate, bool fast_switch) 2856 { 2857 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2858 int old_pstate = cpu->pstate.current_pstate; 2859 2860 target_pstate = intel_pstate_prepare_request(cpu, target_pstate); 2861 if (hwp_active) { 2862 int max_pstate = policy->strict_target ? 2863 target_pstate : cpu->max_perf_ratio; 2864 2865 intel_cpufreq_hwp_update(cpu, target_pstate, max_pstate, 0, 2866 fast_switch); 2867 } else if (target_pstate != old_pstate) { 2868 intel_cpufreq_perf_ctl_update(cpu, target_pstate, fast_switch); 2869 } 2870 2871 cpu->pstate.current_pstate = target_pstate; 2872 2873 intel_cpufreq_trace(cpu, fast_switch ? INTEL_PSTATE_TRACE_FAST_SWITCH : 2874 INTEL_PSTATE_TRACE_TARGET, old_pstate); 2875 2876 return target_pstate; 2877 } 2878 2879 static int intel_cpufreq_target(struct cpufreq_policy *policy, 2880 unsigned int target_freq, 2881 unsigned int relation) 2882 { 2883 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2884 struct cpufreq_freqs freqs; 2885 int target_pstate; 2886 2887 freqs.old = policy->cur; 2888 freqs.new = target_freq; 2889 2890 cpufreq_freq_transition_begin(policy, &freqs); 2891 2892 target_pstate = intel_pstate_freq_to_hwp_rel(cpu, freqs.new, relation); 2893 target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, false); 2894 2895 freqs.new = target_pstate * cpu->pstate.scaling; 2896 2897 cpufreq_freq_transition_end(policy, &freqs, false); 2898 2899 return 0; 2900 } 2901 2902 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy, 2903 unsigned int target_freq) 2904 { 2905 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2906 int target_pstate; 2907 2908 target_pstate = intel_pstate_freq_to_hwp(cpu, target_freq); 2909 2910 target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, true); 2911 2912 return target_pstate * cpu->pstate.scaling; 2913 } 2914 2915 static void intel_cpufreq_adjust_perf(unsigned int cpunum, 2916 unsigned long min_perf, 2917 unsigned long target_perf, 2918 unsigned long capacity) 2919 { 2920 struct cpudata *cpu = all_cpu_data[cpunum]; 2921 u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached); 2922 int old_pstate = cpu->pstate.current_pstate; 2923 int cap_pstate, min_pstate, max_pstate, target_pstate; 2924 2925 cap_pstate = READ_ONCE(global.no_turbo) ? 2926 HWP_GUARANTEED_PERF(hwp_cap) : 2927 HWP_HIGHEST_PERF(hwp_cap); 2928 2929 /* Optimization: Avoid unnecessary divisions. */ 2930 2931 target_pstate = cap_pstate; 2932 if (target_perf < capacity) 2933 target_pstate = DIV_ROUND_UP(cap_pstate * target_perf, capacity); 2934 2935 min_pstate = cap_pstate; 2936 if (min_perf < capacity) 2937 min_pstate = DIV_ROUND_UP(cap_pstate * min_perf, capacity); 2938 2939 if (min_pstate < cpu->pstate.min_pstate) 2940 min_pstate = cpu->pstate.min_pstate; 2941 2942 if (min_pstate < cpu->min_perf_ratio) 2943 min_pstate = cpu->min_perf_ratio; 2944 2945 if (min_pstate > cpu->max_perf_ratio) 2946 min_pstate = cpu->max_perf_ratio; 2947 2948 max_pstate = min(cap_pstate, cpu->max_perf_ratio); 2949 if (max_pstate < min_pstate) 2950 max_pstate = min_pstate; 2951 2952 target_pstate = clamp_t(int, target_pstate, min_pstate, max_pstate); 2953 2954 intel_cpufreq_hwp_update(cpu, min_pstate, max_pstate, target_pstate, true); 2955 2956 cpu->pstate.current_pstate = target_pstate; 2957 intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_FAST_SWITCH, old_pstate); 2958 } 2959 2960 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy) 2961 { 2962 struct freq_qos_request *req; 2963 struct cpudata *cpu; 2964 struct device *dev; 2965 int ret, freq; 2966 2967 dev = get_cpu_device(policy->cpu); 2968 if (!dev) 2969 return -ENODEV; 2970 2971 ret = __intel_pstate_cpu_init(policy); 2972 if (ret) 2973 return ret; 2974 2975 policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY; 2976 /* This reflects the intel_pstate_get_cpu_pstates() setting. */ 2977 policy->cur = policy->cpuinfo.min_freq; 2978 2979 req = kcalloc(2, sizeof(*req), GFP_KERNEL); 2980 if (!req) { 2981 ret = -ENOMEM; 2982 goto pstate_exit; 2983 } 2984 2985 cpu = all_cpu_data[policy->cpu]; 2986 2987 if (hwp_active) { 2988 u64 value; 2989 2990 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY_HWP; 2991 2992 intel_pstate_get_hwp_cap(cpu); 2993 2994 rdmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, &value); 2995 WRITE_ONCE(cpu->hwp_req_cached, value); 2996 2997 cpu->epp_cached = intel_pstate_get_epp(cpu, value); 2998 } else { 2999 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY; 3000 } 3001 3002 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.min_perf_pct, 100); 3003 3004 ret = freq_qos_add_request(&policy->constraints, req, FREQ_QOS_MIN, 3005 freq); 3006 if (ret < 0) { 3007 dev_err(dev, "Failed to add min-freq constraint (%d)\n", ret); 3008 goto free_req; 3009 } 3010 3011 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.max_perf_pct, 100); 3012 3013 ret = freq_qos_add_request(&policy->constraints, req + 1, FREQ_QOS_MAX, 3014 freq); 3015 if (ret < 0) { 3016 dev_err(dev, "Failed to add max-freq constraint (%d)\n", ret); 3017 goto remove_min_req; 3018 } 3019 3020 policy->driver_data = req; 3021 3022 return 0; 3023 3024 remove_min_req: 3025 freq_qos_remove_request(req); 3026 free_req: 3027 kfree(req); 3028 pstate_exit: 3029 intel_pstate_exit_perf_limits(policy); 3030 3031 return ret; 3032 } 3033 3034 static int intel_cpufreq_cpu_exit(struct cpufreq_policy *policy) 3035 { 3036 struct freq_qos_request *req; 3037 3038 req = policy->driver_data; 3039 3040 freq_qos_remove_request(req + 1); 3041 freq_qos_remove_request(req); 3042 kfree(req); 3043 3044 return intel_pstate_cpu_exit(policy); 3045 } 3046 3047 static int intel_cpufreq_suspend(struct cpufreq_policy *policy) 3048 { 3049 intel_pstate_suspend(policy); 3050 3051 if (hwp_active) { 3052 struct cpudata *cpu = all_cpu_data[policy->cpu]; 3053 u64 value = READ_ONCE(cpu->hwp_req_cached); 3054 3055 /* 3056 * Clear the desired perf field in MSR_HWP_REQUEST in case 3057 * intel_cpufreq_adjust_perf() is in use and the last value 3058 * written by it may not be suitable. 3059 */ 3060 value &= ~HWP_DESIRED_PERF(~0L); 3061 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 3062 WRITE_ONCE(cpu->hwp_req_cached, value); 3063 } 3064 3065 return 0; 3066 } 3067 3068 static struct cpufreq_driver intel_cpufreq = { 3069 .flags = CPUFREQ_CONST_LOOPS, 3070 .verify = intel_cpufreq_verify_policy, 3071 .target = intel_cpufreq_target, 3072 .fast_switch = intel_cpufreq_fast_switch, 3073 .init = intel_cpufreq_cpu_init, 3074 .exit = intel_cpufreq_cpu_exit, 3075 .offline = intel_cpufreq_cpu_offline, 3076 .online = intel_pstate_cpu_online, 3077 .suspend = intel_cpufreq_suspend, 3078 .resume = intel_pstate_resume, 3079 .update_limits = intel_pstate_update_limits, 3080 .name = "intel_cpufreq", 3081 }; 3082 3083 static struct cpufreq_driver *default_driver; 3084 3085 static void intel_pstate_driver_cleanup(void) 3086 { 3087 unsigned int cpu; 3088 3089 cpus_read_lock(); 3090 for_each_online_cpu(cpu) { 3091 if (all_cpu_data[cpu]) { 3092 if (intel_pstate_driver == &intel_pstate) 3093 intel_pstate_clear_update_util_hook(cpu); 3094 3095 kfree(all_cpu_data[cpu]); 3096 WRITE_ONCE(all_cpu_data[cpu], NULL); 3097 } 3098 } 3099 cpus_read_unlock(); 3100 3101 intel_pstate_driver = NULL; 3102 } 3103 3104 static int intel_pstate_register_driver(struct cpufreq_driver *driver) 3105 { 3106 int ret; 3107 3108 if (driver == &intel_pstate) 3109 intel_pstate_sysfs_expose_hwp_dynamic_boost(); 3110 3111 memset(&global, 0, sizeof(global)); 3112 global.max_perf_pct = 100; 3113 global.turbo_disabled = turbo_is_disabled(); 3114 global.no_turbo = global.turbo_disabled; 3115 3116 arch_set_max_freq_ratio(global.turbo_disabled); 3117 3118 intel_pstate_driver = driver; 3119 ret = cpufreq_register_driver(intel_pstate_driver); 3120 if (ret) { 3121 intel_pstate_driver_cleanup(); 3122 return ret; 3123 } 3124 3125 global.min_perf_pct = min_perf_pct_min(); 3126 3127 return 0; 3128 } 3129 3130 static ssize_t intel_pstate_show_status(char *buf) 3131 { 3132 if (!intel_pstate_driver) 3133 return sprintf(buf, "off\n"); 3134 3135 return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ? 3136 "active" : "passive"); 3137 } 3138 3139 static int intel_pstate_update_status(const char *buf, size_t size) 3140 { 3141 if (size == 3 && !strncmp(buf, "off", size)) { 3142 if (!intel_pstate_driver) 3143 return -EINVAL; 3144 3145 if (hwp_active) 3146 return -EBUSY; 3147 3148 cpufreq_unregister_driver(intel_pstate_driver); 3149 intel_pstate_driver_cleanup(); 3150 return 0; 3151 } 3152 3153 if (size == 6 && !strncmp(buf, "active", size)) { 3154 if (intel_pstate_driver) { 3155 if (intel_pstate_driver == &intel_pstate) 3156 return 0; 3157 3158 cpufreq_unregister_driver(intel_pstate_driver); 3159 } 3160 3161 return intel_pstate_register_driver(&intel_pstate); 3162 } 3163 3164 if (size == 7 && !strncmp(buf, "passive", size)) { 3165 if (intel_pstate_driver) { 3166 if (intel_pstate_driver == &intel_cpufreq) 3167 return 0; 3168 3169 cpufreq_unregister_driver(intel_pstate_driver); 3170 intel_pstate_sysfs_hide_hwp_dynamic_boost(); 3171 } 3172 3173 return intel_pstate_register_driver(&intel_cpufreq); 3174 } 3175 3176 return -EINVAL; 3177 } 3178 3179 static int no_load __initdata; 3180 static int no_hwp __initdata; 3181 static int hwp_only __initdata; 3182 static unsigned int force_load __initdata; 3183 3184 static int __init intel_pstate_msrs_not_valid(void) 3185 { 3186 if (!pstate_funcs.get_max(0) || 3187 !pstate_funcs.get_min(0) || 3188 !pstate_funcs.get_turbo(0)) 3189 return -ENODEV; 3190 3191 return 0; 3192 } 3193 3194 static void __init copy_cpu_funcs(struct pstate_funcs *funcs) 3195 { 3196 pstate_funcs.get_max = funcs->get_max; 3197 pstate_funcs.get_max_physical = funcs->get_max_physical; 3198 pstate_funcs.get_min = funcs->get_min; 3199 pstate_funcs.get_turbo = funcs->get_turbo; 3200 pstate_funcs.get_scaling = funcs->get_scaling; 3201 pstate_funcs.get_val = funcs->get_val; 3202 pstate_funcs.get_vid = funcs->get_vid; 3203 pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift; 3204 } 3205 3206 #ifdef CONFIG_ACPI 3207 3208 static bool __init intel_pstate_no_acpi_pss(void) 3209 { 3210 int i; 3211 3212 for_each_possible_cpu(i) { 3213 acpi_status status; 3214 union acpi_object *pss; 3215 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; 3216 struct acpi_processor *pr = per_cpu(processors, i); 3217 3218 if (!pr) 3219 continue; 3220 3221 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer); 3222 if (ACPI_FAILURE(status)) 3223 continue; 3224 3225 pss = buffer.pointer; 3226 if (pss && pss->type == ACPI_TYPE_PACKAGE) { 3227 kfree(pss); 3228 return false; 3229 } 3230 3231 kfree(pss); 3232 } 3233 3234 pr_debug("ACPI _PSS not found\n"); 3235 return true; 3236 } 3237 3238 static bool __init intel_pstate_no_acpi_pcch(void) 3239 { 3240 acpi_status status; 3241 acpi_handle handle; 3242 3243 status = acpi_get_handle(NULL, "\\_SB", &handle); 3244 if (ACPI_FAILURE(status)) 3245 goto not_found; 3246 3247 if (acpi_has_method(handle, "PCCH")) 3248 return false; 3249 3250 not_found: 3251 pr_debug("ACPI PCCH not found\n"); 3252 return true; 3253 } 3254 3255 static bool __init intel_pstate_has_acpi_ppc(void) 3256 { 3257 int i; 3258 3259 for_each_possible_cpu(i) { 3260 struct acpi_processor *pr = per_cpu(processors, i); 3261 3262 if (!pr) 3263 continue; 3264 if (acpi_has_method(pr->handle, "_PPC")) 3265 return true; 3266 } 3267 pr_debug("ACPI _PPC not found\n"); 3268 return false; 3269 } 3270 3271 enum { 3272 PSS, 3273 PPC, 3274 }; 3275 3276 /* Hardware vendor-specific info that has its own power management modes */ 3277 static struct acpi_platform_list plat_info[] __initdata = { 3278 {"HP ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, NULL, PSS}, 3279 {"ORACLE", "X4-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3280 {"ORACLE", "X4-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3281 {"ORACLE", "X4-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3282 {"ORACLE", "X3-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3283 {"ORACLE", "X3-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3284 {"ORACLE", "X3-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3285 {"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3286 {"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3287 {"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3288 {"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3289 {"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3290 {"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3291 {"ORACLE", "X6-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3292 {"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3293 { } /* End */ 3294 }; 3295 3296 #define BITMASK_OOB (BIT(8) | BIT(18)) 3297 3298 static bool __init intel_pstate_platform_pwr_mgmt_exists(void) 3299 { 3300 const struct x86_cpu_id *id; 3301 u64 misc_pwr; 3302 int idx; 3303 3304 id = x86_match_cpu(intel_pstate_cpu_oob_ids); 3305 if (id) { 3306 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr); 3307 if (misc_pwr & BITMASK_OOB) { 3308 pr_debug("Bit 8 or 18 in the MISC_PWR_MGMT MSR set\n"); 3309 pr_debug("P states are controlled in Out of Band mode by the firmware/hardware\n"); 3310 return true; 3311 } 3312 } 3313 3314 idx = acpi_match_platform_list(plat_info); 3315 if (idx < 0) 3316 return false; 3317 3318 switch (plat_info[idx].data) { 3319 case PSS: 3320 if (!intel_pstate_no_acpi_pss()) 3321 return false; 3322 3323 return intel_pstate_no_acpi_pcch(); 3324 case PPC: 3325 return intel_pstate_has_acpi_ppc() && !force_load; 3326 } 3327 3328 return false; 3329 } 3330 3331 static void intel_pstate_request_control_from_smm(void) 3332 { 3333 /* 3334 * It may be unsafe to request P-states control from SMM if _PPC support 3335 * has not been enabled. 3336 */ 3337 if (acpi_ppc) 3338 acpi_processor_pstate_control(); 3339 } 3340 #else /* CONFIG_ACPI not enabled */ 3341 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; } 3342 static inline bool intel_pstate_has_acpi_ppc(void) { return false; } 3343 static inline void intel_pstate_request_control_from_smm(void) {} 3344 #endif /* CONFIG_ACPI */ 3345 3346 #define INTEL_PSTATE_HWP_BROADWELL 0x01 3347 3348 #define X86_MATCH_HWP(model, hwp_mode) \ 3349 X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \ 3350 X86_FEATURE_HWP, hwp_mode) 3351 3352 static const struct x86_cpu_id hwp_support_ids[] __initconst = { 3353 X86_MATCH_HWP(BROADWELL_X, INTEL_PSTATE_HWP_BROADWELL), 3354 X86_MATCH_HWP(BROADWELL_D, INTEL_PSTATE_HWP_BROADWELL), 3355 X86_MATCH_HWP(ANY, 0), 3356 {} 3357 }; 3358 3359 static bool intel_pstate_hwp_is_enabled(void) 3360 { 3361 u64 value; 3362 3363 rdmsrl(MSR_PM_ENABLE, value); 3364 return !!(value & 0x1); 3365 } 3366 3367 #define POWERSAVE_MASK GENMASK(7, 0) 3368 #define BALANCE_POWER_MASK GENMASK(15, 8) 3369 #define BALANCE_PERFORMANCE_MASK GENMASK(23, 16) 3370 #define PERFORMANCE_MASK GENMASK(31, 24) 3371 3372 #define HWP_SET_EPP_VALUES(powersave, balance_power, balance_perf, performance) \ 3373 (FIELD_PREP_CONST(POWERSAVE_MASK, powersave) |\ 3374 FIELD_PREP_CONST(BALANCE_POWER_MASK, balance_power) |\ 3375 FIELD_PREP_CONST(BALANCE_PERFORMANCE_MASK, balance_perf) |\ 3376 FIELD_PREP_CONST(PERFORMANCE_MASK, performance)) 3377 3378 #define HWP_SET_DEF_BALANCE_PERF_EPP(balance_perf) \ 3379 (HWP_SET_EPP_VALUES(HWP_EPP_POWERSAVE, HWP_EPP_BALANCE_POWERSAVE,\ 3380 balance_perf, HWP_EPP_PERFORMANCE)) 3381 3382 static const struct x86_cpu_id intel_epp_default[] = { 3383 /* 3384 * Set EPP value as 102, this is the max suggested EPP 3385 * which can result in one core turbo frequency for 3386 * AlderLake Mobile CPUs. 3387 */ 3388 X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, HWP_SET_DEF_BALANCE_PERF_EPP(102)), 3389 X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, HWP_SET_DEF_BALANCE_PERF_EPP(32)), 3390 X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE_L, HWP_SET_EPP_VALUES(HWP_EPP_POWERSAVE, 3391 HWP_EPP_BALANCE_POWERSAVE, 115, 16)), 3392 {} 3393 }; 3394 3395 static const struct x86_cpu_id intel_hybrid_scaling_factor[] = { 3396 X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE_L, HYBRID_SCALING_FACTOR_MTL), 3397 {} 3398 }; 3399 3400 static int __init intel_pstate_init(void) 3401 { 3402 static struct cpudata **_all_cpu_data; 3403 const struct x86_cpu_id *id; 3404 int rc; 3405 3406 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) 3407 return -ENODEV; 3408 3409 id = x86_match_cpu(hwp_support_ids); 3410 if (id) { 3411 hwp_forced = intel_pstate_hwp_is_enabled(); 3412 3413 if (hwp_forced) 3414 pr_info("HWP enabled by BIOS\n"); 3415 else if (no_load) 3416 return -ENODEV; 3417 3418 copy_cpu_funcs(&core_funcs); 3419 /* 3420 * Avoid enabling HWP for processors without EPP support, 3421 * because that means incomplete HWP implementation which is a 3422 * corner case and supporting it is generally problematic. 3423 * 3424 * If HWP is enabled already, though, there is no choice but to 3425 * deal with it. 3426 */ 3427 if ((!no_hwp && boot_cpu_has(X86_FEATURE_HWP_EPP)) || hwp_forced) { 3428 hwp_active = true; 3429 hwp_mode_bdw = id->driver_data; 3430 intel_pstate.attr = hwp_cpufreq_attrs; 3431 intel_cpufreq.attr = hwp_cpufreq_attrs; 3432 intel_cpufreq.flags |= CPUFREQ_NEED_UPDATE_LIMITS; 3433 intel_cpufreq.adjust_perf = intel_cpufreq_adjust_perf; 3434 if (!default_driver) 3435 default_driver = &intel_pstate; 3436 3437 pstate_funcs.get_cpu_scaling = hwp_get_cpu_scaling; 3438 3439 goto hwp_cpu_matched; 3440 } 3441 pr_info("HWP not enabled\n"); 3442 } else { 3443 if (no_load) 3444 return -ENODEV; 3445 3446 id = x86_match_cpu(intel_pstate_cpu_ids); 3447 if (!id) { 3448 pr_info("CPU model not supported\n"); 3449 return -ENODEV; 3450 } 3451 3452 copy_cpu_funcs((struct pstate_funcs *)id->driver_data); 3453 } 3454 3455 if (intel_pstate_msrs_not_valid()) { 3456 pr_info("Invalid MSRs\n"); 3457 return -ENODEV; 3458 } 3459 /* Without HWP start in the passive mode. */ 3460 if (!default_driver) 3461 default_driver = &intel_cpufreq; 3462 3463 hwp_cpu_matched: 3464 /* 3465 * The Intel pstate driver will be ignored if the platform 3466 * firmware has its own power management modes. 3467 */ 3468 if (intel_pstate_platform_pwr_mgmt_exists()) { 3469 pr_info("P-states controlled by the platform\n"); 3470 return -ENODEV; 3471 } 3472 3473 if (!hwp_active && hwp_only) 3474 return -ENOTSUPP; 3475 3476 pr_info("Intel P-state driver initializing\n"); 3477 3478 _all_cpu_data = vzalloc(array_size(sizeof(void *), num_possible_cpus())); 3479 if (!_all_cpu_data) 3480 return -ENOMEM; 3481 3482 WRITE_ONCE(all_cpu_data, _all_cpu_data); 3483 3484 intel_pstate_request_control_from_smm(); 3485 3486 intel_pstate_sysfs_expose_params(); 3487 3488 if (hwp_active) { 3489 const struct x86_cpu_id *id = x86_match_cpu(intel_epp_default); 3490 const struct x86_cpu_id *hybrid_id = x86_match_cpu(intel_hybrid_scaling_factor); 3491 3492 if (id) { 3493 epp_values[EPP_INDEX_POWERSAVE] = 3494 FIELD_GET(POWERSAVE_MASK, id->driver_data); 3495 epp_values[EPP_INDEX_BALANCE_POWERSAVE] = 3496 FIELD_GET(BALANCE_POWER_MASK, id->driver_data); 3497 epp_values[EPP_INDEX_BALANCE_PERFORMANCE] = 3498 FIELD_GET(BALANCE_PERFORMANCE_MASK, id->driver_data); 3499 epp_values[EPP_INDEX_PERFORMANCE] = 3500 FIELD_GET(PERFORMANCE_MASK, id->driver_data); 3501 pr_debug("Updated EPPs powersave:%x balanced power:%x balanced perf:%x performance:%x\n", 3502 epp_values[EPP_INDEX_POWERSAVE], 3503 epp_values[EPP_INDEX_BALANCE_POWERSAVE], 3504 epp_values[EPP_INDEX_BALANCE_PERFORMANCE], 3505 epp_values[EPP_INDEX_PERFORMANCE]); 3506 } 3507 3508 if (hybrid_id) { 3509 hybrid_scaling_factor = hybrid_id->driver_data; 3510 pr_debug("hybrid scaling factor: %d\n", hybrid_scaling_factor); 3511 } 3512 3513 } 3514 3515 mutex_lock(&intel_pstate_driver_lock); 3516 rc = intel_pstate_register_driver(default_driver); 3517 mutex_unlock(&intel_pstate_driver_lock); 3518 if (rc) { 3519 intel_pstate_sysfs_remove(); 3520 return rc; 3521 } 3522 3523 if (hwp_active) { 3524 const struct x86_cpu_id *id; 3525 3526 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids); 3527 if (id) { 3528 set_power_ctl_ee_state(false); 3529 pr_info("Disabling energy efficiency optimization\n"); 3530 } 3531 3532 pr_info("HWP enabled\n"); 3533 } else if (boot_cpu_has(X86_FEATURE_HYBRID_CPU)) { 3534 pr_warn("Problematic setup: Hybrid processor with disabled HWP\n"); 3535 } 3536 3537 return 0; 3538 } 3539 device_initcall(intel_pstate_init); 3540 3541 static int __init intel_pstate_setup(char *str) 3542 { 3543 if (!str) 3544 return -EINVAL; 3545 3546 if (!strcmp(str, "disable")) 3547 no_load = 1; 3548 else if (!strcmp(str, "active")) 3549 default_driver = &intel_pstate; 3550 else if (!strcmp(str, "passive")) 3551 default_driver = &intel_cpufreq; 3552 3553 if (!strcmp(str, "no_hwp")) 3554 no_hwp = 1; 3555 3556 if (!strcmp(str, "force")) 3557 force_load = 1; 3558 if (!strcmp(str, "hwp_only")) 3559 hwp_only = 1; 3560 if (!strcmp(str, "per_cpu_perf_limits")) 3561 per_cpu_limits = true; 3562 3563 #ifdef CONFIG_ACPI 3564 if (!strcmp(str, "support_acpi_ppc")) 3565 acpi_ppc = true; 3566 #endif 3567 3568 return 0; 3569 } 3570 early_param("intel_pstate", intel_pstate_setup); 3571 3572 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>"); 3573 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors"); 3574