1 /* 2 * Copyright (C) 2013 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/cpu.h> 11 #include <linux/cpufreq.h> 12 #include <linux/cpu_cooling.h> 13 #include <linux/err.h> 14 #include <linux/module.h> 15 #include <linux/nvmem-consumer.h> 16 #include <linux/of.h> 17 #include <linux/of_address.h> 18 #include <linux/pm_opp.h> 19 #include <linux/platform_device.h> 20 #include <linux/regulator/consumer.h> 21 22 #define PU_SOC_VOLTAGE_NORMAL 1250000 23 #define PU_SOC_VOLTAGE_HIGH 1275000 24 #define FREQ_1P2_GHZ 1200000000 25 26 static struct regulator *arm_reg; 27 static struct regulator *pu_reg; 28 static struct regulator *soc_reg; 29 30 enum IMX6_CPUFREQ_CLKS { 31 ARM, 32 PLL1_SYS, 33 STEP, 34 PLL1_SW, 35 PLL2_PFD2_396M, 36 /* MX6UL requires two more clks */ 37 PLL2_BUS, 38 SECONDARY_SEL, 39 }; 40 #define IMX6Q_CPUFREQ_CLK_NUM 5 41 #define IMX6UL_CPUFREQ_CLK_NUM 7 42 43 static int num_clks; 44 static struct clk_bulk_data clks[] = { 45 { .id = "arm" }, 46 { .id = "pll1_sys" }, 47 { .id = "step" }, 48 { .id = "pll1_sw" }, 49 { .id = "pll2_pfd2_396m" }, 50 { .id = "pll2_bus" }, 51 { .id = "secondary_sel" }, 52 }; 53 54 static struct device *cpu_dev; 55 static struct thermal_cooling_device *cdev; 56 static bool free_opp; 57 static struct cpufreq_frequency_table *freq_table; 58 static unsigned int max_freq; 59 static unsigned int transition_latency; 60 61 static u32 *imx6_soc_volt; 62 static u32 soc_opp_count; 63 64 static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index) 65 { 66 struct dev_pm_opp *opp; 67 unsigned long freq_hz, volt, volt_old; 68 unsigned int old_freq, new_freq; 69 bool pll1_sys_temp_enabled = false; 70 int ret; 71 72 new_freq = freq_table[index].frequency; 73 freq_hz = new_freq * 1000; 74 old_freq = clk_get_rate(clks[ARM].clk) / 1000; 75 76 opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz); 77 if (IS_ERR(opp)) { 78 dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz); 79 return PTR_ERR(opp); 80 } 81 82 volt = dev_pm_opp_get_voltage(opp); 83 dev_pm_opp_put(opp); 84 85 volt_old = regulator_get_voltage(arm_reg); 86 87 dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n", 88 old_freq / 1000, volt_old / 1000, 89 new_freq / 1000, volt / 1000); 90 91 /* scaling up? scale voltage before frequency */ 92 if (new_freq > old_freq) { 93 if (!IS_ERR(pu_reg)) { 94 ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0); 95 if (ret) { 96 dev_err(cpu_dev, "failed to scale vddpu up: %d\n", ret); 97 return ret; 98 } 99 } 100 ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0); 101 if (ret) { 102 dev_err(cpu_dev, "failed to scale vddsoc up: %d\n", ret); 103 return ret; 104 } 105 ret = regulator_set_voltage_tol(arm_reg, volt, 0); 106 if (ret) { 107 dev_err(cpu_dev, 108 "failed to scale vddarm up: %d\n", ret); 109 return ret; 110 } 111 } 112 113 /* 114 * The setpoints are selected per PLL/PDF frequencies, so we need to 115 * reprogram PLL for frequency scaling. The procedure of reprogramming 116 * PLL1 is as below. 117 * For i.MX6UL, it has a secondary clk mux, the cpu frequency change 118 * flow is slightly different from other i.MX6 OSC. 119 * The cpu frequeny change flow for i.MX6(except i.MX6UL) is as below: 120 * - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it 121 * - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it 122 * - Disable pll2_pfd2_396m_clk 123 */ 124 if (of_machine_is_compatible("fsl,imx6ul") || 125 of_machine_is_compatible("fsl,imx6ull")) { 126 /* 127 * When changing pll1_sw_clk's parent to pll1_sys_clk, 128 * CPU may run at higher than 528MHz, this will lead to 129 * the system unstable if the voltage is lower than the 130 * voltage of 528MHz, so lower the CPU frequency to one 131 * half before changing CPU frequency. 132 */ 133 clk_set_rate(clks[ARM].clk, (old_freq >> 1) * 1000); 134 clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk); 135 if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk)) 136 clk_set_parent(clks[SECONDARY_SEL].clk, 137 clks[PLL2_BUS].clk); 138 else 139 clk_set_parent(clks[SECONDARY_SEL].clk, 140 clks[PLL2_PFD2_396M].clk); 141 clk_set_parent(clks[STEP].clk, clks[SECONDARY_SEL].clk); 142 clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk); 143 if (freq_hz > clk_get_rate(clks[PLL2_BUS].clk)) { 144 clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000); 145 clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk); 146 } 147 } else { 148 clk_set_parent(clks[STEP].clk, clks[PLL2_PFD2_396M].clk); 149 clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk); 150 if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk)) { 151 clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000); 152 clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk); 153 } else { 154 /* pll1_sys needs to be enabled for divider rate change to work. */ 155 pll1_sys_temp_enabled = true; 156 clk_prepare_enable(clks[PLL1_SYS].clk); 157 } 158 } 159 160 /* Ensure the arm clock divider is what we expect */ 161 ret = clk_set_rate(clks[ARM].clk, new_freq * 1000); 162 if (ret) { 163 int ret1; 164 165 dev_err(cpu_dev, "failed to set clock rate: %d\n", ret); 166 ret1 = regulator_set_voltage_tol(arm_reg, volt_old, 0); 167 if (ret1) 168 dev_warn(cpu_dev, 169 "failed to restore vddarm voltage: %d\n", ret1); 170 return ret; 171 } 172 173 /* PLL1 is only needed until after ARM-PODF is set. */ 174 if (pll1_sys_temp_enabled) 175 clk_disable_unprepare(clks[PLL1_SYS].clk); 176 177 /* scaling down? scale voltage after frequency */ 178 if (new_freq < old_freq) { 179 ret = regulator_set_voltage_tol(arm_reg, volt, 0); 180 if (ret) { 181 dev_warn(cpu_dev, 182 "failed to scale vddarm down: %d\n", ret); 183 ret = 0; 184 } 185 ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0); 186 if (ret) { 187 dev_warn(cpu_dev, "failed to scale vddsoc down: %d\n", ret); 188 ret = 0; 189 } 190 if (!IS_ERR(pu_reg)) { 191 ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0); 192 if (ret) { 193 dev_warn(cpu_dev, "failed to scale vddpu down: %d\n", ret); 194 ret = 0; 195 } 196 } 197 } 198 199 return 0; 200 } 201 202 static void imx6q_cpufreq_ready(struct cpufreq_policy *policy) 203 { 204 cdev = of_cpufreq_cooling_register(policy); 205 206 if (!cdev) 207 dev_err(cpu_dev, 208 "running cpufreq without cooling device: %ld\n", 209 PTR_ERR(cdev)); 210 } 211 212 static int imx6q_cpufreq_init(struct cpufreq_policy *policy) 213 { 214 int ret; 215 216 policy->clk = clks[ARM].clk; 217 ret = cpufreq_generic_init(policy, freq_table, transition_latency); 218 policy->suspend_freq = max_freq; 219 220 return ret; 221 } 222 223 static int imx6q_cpufreq_exit(struct cpufreq_policy *policy) 224 { 225 cpufreq_cooling_unregister(cdev); 226 227 return 0; 228 } 229 230 static struct cpufreq_driver imx6q_cpufreq_driver = { 231 .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK, 232 .verify = cpufreq_generic_frequency_table_verify, 233 .target_index = imx6q_set_target, 234 .get = cpufreq_generic_get, 235 .init = imx6q_cpufreq_init, 236 .exit = imx6q_cpufreq_exit, 237 .name = "imx6q-cpufreq", 238 .ready = imx6q_cpufreq_ready, 239 .attr = cpufreq_generic_attr, 240 .suspend = cpufreq_generic_suspend, 241 }; 242 243 #define OCOTP_CFG3 0x440 244 #define OCOTP_CFG3_SPEED_SHIFT 16 245 #define OCOTP_CFG3_SPEED_1P2GHZ 0x3 246 #define OCOTP_CFG3_SPEED_996MHZ 0x2 247 #define OCOTP_CFG3_SPEED_852MHZ 0x1 248 249 static void imx6q_opp_check_speed_grading(struct device *dev) 250 { 251 struct device_node *np; 252 void __iomem *base; 253 u32 val; 254 255 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp"); 256 if (!np) 257 return; 258 259 base = of_iomap(np, 0); 260 if (!base) { 261 dev_err(dev, "failed to map ocotp\n"); 262 goto put_node; 263 } 264 265 /* 266 * SPEED_GRADING[1:0] defines the max speed of ARM: 267 * 2b'11: 1200000000Hz; 268 * 2b'10: 996000000Hz; 269 * 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz. 270 * 2b'00: 792000000Hz; 271 * We need to set the max speed of ARM according to fuse map. 272 */ 273 val = readl_relaxed(base + OCOTP_CFG3); 274 val >>= OCOTP_CFG3_SPEED_SHIFT; 275 val &= 0x3; 276 277 if (val < OCOTP_CFG3_SPEED_996MHZ) 278 if (dev_pm_opp_disable(dev, 996000000)) 279 dev_warn(dev, "failed to disable 996MHz OPP\n"); 280 281 if (of_machine_is_compatible("fsl,imx6q") || 282 of_machine_is_compatible("fsl,imx6qp")) { 283 if (val != OCOTP_CFG3_SPEED_852MHZ) 284 if (dev_pm_opp_disable(dev, 852000000)) 285 dev_warn(dev, "failed to disable 852MHz OPP\n"); 286 if (val != OCOTP_CFG3_SPEED_1P2GHZ) 287 if (dev_pm_opp_disable(dev, 1200000000)) 288 dev_warn(dev, "failed to disable 1.2GHz OPP\n"); 289 } 290 iounmap(base); 291 put_node: 292 of_node_put(np); 293 } 294 295 #define OCOTP_CFG3_6UL_SPEED_696MHZ 0x2 296 #define OCOTP_CFG3_6ULL_SPEED_792MHZ 0x2 297 #define OCOTP_CFG3_6ULL_SPEED_900MHZ 0x3 298 299 static int imx6ul_opp_check_speed_grading(struct device *dev) 300 { 301 u32 val; 302 int ret = 0; 303 304 if (of_find_property(dev->of_node, "nvmem-cells", NULL)) { 305 ret = nvmem_cell_read_u32(dev, "speed_grade", &val); 306 if (ret) 307 return ret; 308 } else { 309 struct device_node *np; 310 void __iomem *base; 311 312 np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-ocotp"); 313 if (!np) 314 return -ENOENT; 315 316 base = of_iomap(np, 0); 317 of_node_put(np); 318 if (!base) { 319 dev_err(dev, "failed to map ocotp\n"); 320 return -EFAULT; 321 } 322 323 val = readl_relaxed(base + OCOTP_CFG3); 324 iounmap(base); 325 } 326 327 /* 328 * Speed GRADING[1:0] defines the max speed of ARM: 329 * 2b'00: Reserved; 330 * 2b'01: 528000000Hz; 331 * 2b'10: 696000000Hz on i.MX6UL, 792000000Hz on i.MX6ULL; 332 * 2b'11: 900000000Hz on i.MX6ULL only; 333 * We need to set the max speed of ARM according to fuse map. 334 */ 335 val >>= OCOTP_CFG3_SPEED_SHIFT; 336 val &= 0x3; 337 338 if (of_machine_is_compatible("fsl,imx6ul")) { 339 if (val != OCOTP_CFG3_6UL_SPEED_696MHZ) 340 if (dev_pm_opp_disable(dev, 696000000)) 341 dev_warn(dev, "failed to disable 696MHz OPP\n"); 342 } 343 344 if (of_machine_is_compatible("fsl,imx6ull")) { 345 if (val != OCOTP_CFG3_6ULL_SPEED_792MHZ) 346 if (dev_pm_opp_disable(dev, 792000000)) 347 dev_warn(dev, "failed to disable 792MHz OPP\n"); 348 349 if (val != OCOTP_CFG3_6ULL_SPEED_900MHZ) 350 if (dev_pm_opp_disable(dev, 900000000)) 351 dev_warn(dev, "failed to disable 900MHz OPP\n"); 352 } 353 354 return ret; 355 } 356 357 static int imx6q_cpufreq_probe(struct platform_device *pdev) 358 { 359 struct device_node *np; 360 struct dev_pm_opp *opp; 361 unsigned long min_volt, max_volt; 362 int num, ret; 363 const struct property *prop; 364 const __be32 *val; 365 u32 nr, i, j; 366 367 cpu_dev = get_cpu_device(0); 368 if (!cpu_dev) { 369 pr_err("failed to get cpu0 device\n"); 370 return -ENODEV; 371 } 372 373 np = of_node_get(cpu_dev->of_node); 374 if (!np) { 375 dev_err(cpu_dev, "failed to find cpu0 node\n"); 376 return -ENOENT; 377 } 378 379 if (of_machine_is_compatible("fsl,imx6ul") || 380 of_machine_is_compatible("fsl,imx6ull")) 381 num_clks = IMX6UL_CPUFREQ_CLK_NUM; 382 else 383 num_clks = IMX6Q_CPUFREQ_CLK_NUM; 384 385 ret = clk_bulk_get(cpu_dev, num_clks, clks); 386 if (ret) 387 goto put_node; 388 389 arm_reg = regulator_get(cpu_dev, "arm"); 390 pu_reg = regulator_get_optional(cpu_dev, "pu"); 391 soc_reg = regulator_get(cpu_dev, "soc"); 392 if (PTR_ERR(arm_reg) == -EPROBE_DEFER || 393 PTR_ERR(soc_reg) == -EPROBE_DEFER || 394 PTR_ERR(pu_reg) == -EPROBE_DEFER) { 395 ret = -EPROBE_DEFER; 396 dev_dbg(cpu_dev, "regulators not ready, defer\n"); 397 goto put_reg; 398 } 399 if (IS_ERR(arm_reg) || IS_ERR(soc_reg)) { 400 dev_err(cpu_dev, "failed to get regulators\n"); 401 ret = -ENOENT; 402 goto put_reg; 403 } 404 405 ret = dev_pm_opp_of_add_table(cpu_dev); 406 if (ret < 0) { 407 dev_err(cpu_dev, "failed to init OPP table: %d\n", ret); 408 goto put_reg; 409 } 410 411 if (of_machine_is_compatible("fsl,imx6ul") || 412 of_machine_is_compatible("fsl,imx6ull")) { 413 ret = imx6ul_opp_check_speed_grading(cpu_dev); 414 if (ret == -EPROBE_DEFER) 415 return ret; 416 if (ret) { 417 dev_err(cpu_dev, "failed to read ocotp: %d\n", 418 ret); 419 return ret; 420 } 421 } else { 422 imx6q_opp_check_speed_grading(cpu_dev); 423 } 424 425 /* Because we have added the OPPs here, we must free them */ 426 free_opp = true; 427 num = dev_pm_opp_get_opp_count(cpu_dev); 428 if (num < 0) { 429 ret = num; 430 dev_err(cpu_dev, "no OPP table is found: %d\n", ret); 431 goto out_free_opp; 432 } 433 434 ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table); 435 if (ret) { 436 dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret); 437 goto out_free_opp; 438 } 439 440 /* Make imx6_soc_volt array's size same as arm opp number */ 441 imx6_soc_volt = devm_kcalloc(cpu_dev, num, sizeof(*imx6_soc_volt), 442 GFP_KERNEL); 443 if (imx6_soc_volt == NULL) { 444 ret = -ENOMEM; 445 goto free_freq_table; 446 } 447 448 prop = of_find_property(np, "fsl,soc-operating-points", NULL); 449 if (!prop || !prop->value) 450 goto soc_opp_out; 451 452 /* 453 * Each OPP is a set of tuples consisting of frequency and 454 * voltage like <freq-kHz vol-uV>. 455 */ 456 nr = prop->length / sizeof(u32); 457 if (nr % 2 || (nr / 2) < num) 458 goto soc_opp_out; 459 460 for (j = 0; j < num; j++) { 461 val = prop->value; 462 for (i = 0; i < nr / 2; i++) { 463 unsigned long freq = be32_to_cpup(val++); 464 unsigned long volt = be32_to_cpup(val++); 465 if (freq_table[j].frequency == freq) { 466 imx6_soc_volt[soc_opp_count++] = volt; 467 break; 468 } 469 } 470 } 471 472 soc_opp_out: 473 /* use fixed soc opp volt if no valid soc opp info found in dtb */ 474 if (soc_opp_count != num) { 475 dev_warn(cpu_dev, "can NOT find valid fsl,soc-operating-points property in dtb, use default value!\n"); 476 for (j = 0; j < num; j++) 477 imx6_soc_volt[j] = PU_SOC_VOLTAGE_NORMAL; 478 if (freq_table[num - 1].frequency * 1000 == FREQ_1P2_GHZ) 479 imx6_soc_volt[num - 1] = PU_SOC_VOLTAGE_HIGH; 480 } 481 482 if (of_property_read_u32(np, "clock-latency", &transition_latency)) 483 transition_latency = CPUFREQ_ETERNAL; 484 485 /* 486 * Calculate the ramp time for max voltage change in the 487 * VDDSOC and VDDPU regulators. 488 */ 489 ret = regulator_set_voltage_time(soc_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]); 490 if (ret > 0) 491 transition_latency += ret * 1000; 492 if (!IS_ERR(pu_reg)) { 493 ret = regulator_set_voltage_time(pu_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]); 494 if (ret > 0) 495 transition_latency += ret * 1000; 496 } 497 498 /* 499 * OPP is maintained in order of increasing frequency, and 500 * freq_table initialised from OPP is therefore sorted in the 501 * same order. 502 */ 503 max_freq = freq_table[--num].frequency; 504 opp = dev_pm_opp_find_freq_exact(cpu_dev, 505 freq_table[0].frequency * 1000, true); 506 min_volt = dev_pm_opp_get_voltage(opp); 507 dev_pm_opp_put(opp); 508 opp = dev_pm_opp_find_freq_exact(cpu_dev, max_freq * 1000, true); 509 max_volt = dev_pm_opp_get_voltage(opp); 510 dev_pm_opp_put(opp); 511 512 ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt); 513 if (ret > 0) 514 transition_latency += ret * 1000; 515 516 ret = cpufreq_register_driver(&imx6q_cpufreq_driver); 517 if (ret) { 518 dev_err(cpu_dev, "failed register driver: %d\n", ret); 519 goto free_freq_table; 520 } 521 522 of_node_put(np); 523 return 0; 524 525 free_freq_table: 526 dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table); 527 out_free_opp: 528 if (free_opp) 529 dev_pm_opp_of_remove_table(cpu_dev); 530 put_reg: 531 if (!IS_ERR(arm_reg)) 532 regulator_put(arm_reg); 533 if (!IS_ERR(pu_reg)) 534 regulator_put(pu_reg); 535 if (!IS_ERR(soc_reg)) 536 regulator_put(soc_reg); 537 538 clk_bulk_put(num_clks, clks); 539 put_node: 540 of_node_put(np); 541 542 return ret; 543 } 544 545 static int imx6q_cpufreq_remove(struct platform_device *pdev) 546 { 547 cpufreq_unregister_driver(&imx6q_cpufreq_driver); 548 dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table); 549 if (free_opp) 550 dev_pm_opp_of_remove_table(cpu_dev); 551 regulator_put(arm_reg); 552 if (!IS_ERR(pu_reg)) 553 regulator_put(pu_reg); 554 regulator_put(soc_reg); 555 556 clk_bulk_put(num_clks, clks); 557 558 return 0; 559 } 560 561 static struct platform_driver imx6q_cpufreq_platdrv = { 562 .driver = { 563 .name = "imx6q-cpufreq", 564 }, 565 .probe = imx6q_cpufreq_probe, 566 .remove = imx6q_cpufreq_remove, 567 }; 568 module_platform_driver(imx6q_cpufreq_platdrv); 569 570 MODULE_ALIAS("platform:imx6q-cpufreq"); 571 MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>"); 572 MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver"); 573 MODULE_LICENSE("GPL"); 574